CN102696106B - 用于高效功率电路的电子器件和部件 - Google Patents
用于高效功率电路的电子器件和部件 Download PDFInfo
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- CN102696106B CN102696106B CN201180005676.4A CN201180005676A CN102696106B CN 102696106 B CN102696106 B CN 102696106B CN 201180005676 A CN201180005676 A CN 201180005676A CN 102696106 B CN102696106 B CN 102696106B
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Abstract
一种电子部件包括:封装在单个封装体中的III-N晶体管以及III-N整流器件。III-N晶体管的栅极电极电连接到单个封装体的第一引脚或电连接到单个封装体的导电结构部分,III-N晶体管的漏极电极电连接到单个封装体的第二引脚并且电连接到III-N整流器件的第一电极,并且III-N整流器件的第二电极电连接到单个封装体的第三引脚。
Description
技术领域
描述了在功率切换电路应用中使用以实现具有非常高效率的功率电路的功率切换电路和部件。
背景技术
随着全球范围内的电力消耗量不断增加,电源和功率转换器在我们的社会中变得越来越重要。图1中示出了升压模式DC到DC功率转换器(本文称为“升压转换器”)的主要元件的电路示意图。升压转换器电路包括电感器10和14、切换器件(即晶体管11)、整流器件(即,二极管12)以及电荷存储器件(即,电容器13和15)。在晶体管11导通的时间期间,电感器10保持整个输入电压,并且输入电流流过电感器10和晶体管11,同时在电感器10中将电能存储为磁能。同时,二极管12防止电容器13通过晶体管11进行放电。当晶体管11截止时,跨电感器10的电势被反向,并且流过电感器10的输入电流也流过二极管12,由此以比输入线路处的更高的电压电势来向电容器输出负载供应能量并且对电容器13进行充电。
迄今为止,在诸如图1的升压转换器电路的功率电路中使用的二极管和晶体管通常以硅(Si)半导体材料来制造。用于功率应用的常用二极管和晶体管器件包括硅(Si)肖特基二极管、诸如CoolMOS的Si功率MOSFET以及Si绝缘栅双极晶体管(IGBT)。虽然Si功率器件比较廉价,但是它们具有许多缺点,包括相对低的切换速度以及高水平的电气噪声,通常被称为电磁干扰或EMI。对于更紧凑的电源来说,始终倾向于提高切换频率,这就需要在电源中使用的器件具有更高切换速度,并且电路架构被改进为充分地抑制由于高频操作而导致的增加的电气噪声。最近,由于与Si器件相比碳化硅(SiC)功率器件优越的电气和热特性而导致已经开始研究碳化硅(SiC)功率器件。基于III族氮化物(III-N)的半导体器件现在也呈现为对于功率电路应用的吸引人的候选。
虽然在功率应用中使用III-N器件是有益的,但是需要进一步的改进以在电路切换频率和切换速度进一步增加时,在保持高效率的同时充分地抑制EMI。
发明内容
一方面,描述了一种具有III-N晶体管以及III-N整流器件的电子部件。单个封装体包封III-N晶体管以及III-N整流器件。将III-N晶体管的栅极电极电连接到单个封装体的第一引脚或者电连接到单个封装体的导电结构部分,将III-N晶体管的漏极电极电连接到单个封装体的第二引脚以及III-N整流器件的第一电极,并且将III-N整流器件的第二电极电连接到单个封装体的第三引脚。
另一方面,描述了一种电压转换器,该电压转换器在以至少100kHz的频率以及1:2的转换比进行操作时具有大于97.8%的效率并且峰值输出电压噪声小于1伏特。
又一方面,描述了一种用于操作功率切换电路中的开关晶体管的方法。该方法包括:相对于开关晶体管的源极,将开关晶体管的栅极上的电压从晶体管阈值电压以上的值切换为晶体管阈值电压以下的值,或者从晶体管阈值电压以下的值切换为晶体管阈值电压以上的值。以约150伏特/纳秒或更高的速率切换该电压。
在实现中,包括或支持以下特征。III-N晶体管可以是场效应晶体管。III-N晶体管可以是高电压开关晶体管。III-N晶体管可以是增强型器件。III-N整流器件可以是III-N二极管,第一电极可以是阳极电极,而第二电极可以是阴极电极。III-N晶体管或III-N二极管可以是包括绝缘或半绝缘部分的横向器件,并且绝缘或半绝缘部分可以被直接安装到单个封装体的导电结构部分,而无需在单个封装体的导电结构部分和III-N晶体管之间或者在单个封装体的导电结构部分和III-N二极管之间的绝缘间隔物。绝缘或半绝缘部分可以是绝缘或半绝缘衬底。III-N晶体管或III-N二极管可以是包括导电或半导电衬底的横向器件,并且绝缘或半绝缘III-N层可以位于导电或半导电衬底与III-N晶体管或III-N二极管的沟道之间,其中导电或半导电衬底可以被直接安装到单个封装体的导电结构部分,而无需在单个封装体的导电结构部分和III-N晶体管之间或者在单个封装体的导电结构部分和III-N二极管之间的绝缘间隔物。导电或半导电衬底可以是硅衬底。III-N晶体管和III-N二极管可以位于公共衬底上。III-N晶体管可以是第一III-N晶体管,并且III-N整流器件可以是第二III-N晶体管。第一III-N晶体管或第二III-N晶体管可以是包括绝缘或半绝缘部分的横向器件,并且绝缘或半绝缘部分可以被直接安装到单个封装体的导电结构部分,而无需在单个封装体的导电结构部分和第一III-N晶体管之间或者在单个封装体的导电结构部分和第二III-N晶体管之间的绝缘间隔物。绝缘或半绝缘部分可以是绝缘或半绝缘衬底。第一III-N晶体管或第二III-N晶体管可以是包括导电或半导电衬底的横向器件、以及在导电或半导电衬底和第一III-N晶体管或第二III-N晶体管的沟道之间的绝缘或半绝缘III-N层,其中导电或半导电衬底可以被直接安装到单个封装体的导电结构部分,而无需在单个封装体的导电结构部分和III-N晶体管之间或在单个封装体的导电结构部分和III-N二极管之间的绝缘间隔物。第一III-N晶体管和第二III-N晶体管可以在公共衬底上形成。III-N晶体管的源极电极可以电连接到单个封装体的导电结构部分或者电连接到单个封装体的源极引脚。III-N晶体管可以是III-N耗尽型晶体管,并且电子部件还可以包括封装在单个封装体中的增强型晶体管,增强型晶体管包括增强型晶体管源极电极、增强型晶体管栅极电极以及增强型晶体管漏极电极,其中增强型晶体管源极电极可以电连接到单个封装体的导电结构部分或者电连接到单个封装体的源极引脚,增强型晶体管漏极电极可以电连接到III-N耗尽型晶体管的源极电极,并且增强型晶体管栅极电极可以电连接到单个封装体的第一引脚。III-N耗尽型晶体管可以是高电压开关晶体管,并且增强型晶体管可以是低电压晶体管。增强型晶体管可以是Si MOS器件。电压转换器可以包括本文描述的电子部件中的一个。当电压转换器以至少1MHz的频率进行操作时,电压转换器效率可以具有大于97.8%的效率并且峰值输出电压噪声小于1伏特。电压转换器可以包括能够作为常关开关进行操作的器件。电压转换器的器件可以是增强型III-N晶体管。电压转换器的器件可以是包括低电压增强型晶体管以及高电压耗尽型晶体管的组件。低电压增强型晶体管可以是Si MOS晶体管,并且高电压耗尽型晶体管可以是III-N晶体管。功率切换电路的峰值输出电压噪声可以小于1V。
附图说明
图1是现有技术的电压转换器电路的电路示意图。
图2是图1的电路中的晶体管的晶体管源-漏电流相对于时间以及源-漏电压相对于时间的代表性曲线。
图3是在图1的电压转换器电路的输出节点处的瞬时电压噪声相对于时间的曲线图。
图4和图5分别是电子部件的立体图和暴露的平面剖视图。
图6是电子部件的立体图。
图7是III-N HEMT器件的示意性截面图。
图8是III-N二极管的示意性截面图。
图9和图10是电子部件的暴露的平面剖视图。
图11和图12是电压转换器电路的电路示意图。
图13是在图12的电压转换器电路的输出节点处的瞬时电压噪声相对于时间的曲线图。
图14和图15是图12的升压转换器电路的效率和功率损失相对于输出功率的曲线图。
各个附图中的相同附图标记指示相同的元件。
具体实施方式
在高功率切换电路中,例如在图1中的升压转换器中,每当晶体管11从截止切换为导通或者从导通切换为截止时,切换损失都会发生。切换损失包括RC充电损失和跨接损失。如图2中示出的晶体管源-漏电流相对于时间以及源-漏电压相对于时间的代表性曲线所示,在晶体管从导通切换为截止的时间tswitch期间,跨晶体管上的电压17增加,而通过晶体管的电流16减小(相反,在晶体管从截止切换为导通的时间期间,跨晶体管上的电压减小,而通过晶体管的电流增加)。在切换期间的瞬时跨接功率损失由通过晶体管的电流与跨晶体管上的电压的乘积来给出,并且在切换期间的总的能量损失由功率损失对整个切换时间的时间积分来给出。减少晶体管开关时间tswitch(即,提高切换速度)降低了在切换期间的总的跨接能量损失,并且由此可以减小功率损失并且提高电路的效率。因此,有利的是,在电路操作期间,以较高的切换速度开关晶体管,因为这可以提高电路的效率。
在电路的操作期间开关晶体管可以被切换的最大速度在很大程度上受到晶体管的物理性质的限制,诸如沟道电荷密度、沟道电荷迁移率和沟道电荷饱和速度以及晶体管中的任何固有或寄生电容或电阻。晶体管在以超过该晶体管被设计成或额定的最大值的切换速度进行操作可能导致可靠性的问题和/或电磁干扰(EMI)。当前在诸如升压转换器电路的常规功率切换电路中使用的开关晶体管(例如Si基CoolMOS晶体管)通常额定用于以50伏特/纳秒的最大切换速度进行操作。与设计为以类似的电压和电流进行操作的Si基晶体管相比,III族氮化物(即,III-N)晶体管,例如III-N HEMT或HFET,通常具有优越的固有电子性质和较低的电容,并且因此能够以较高的切换速度进行操作,例如约150伏特/纳秒或更高、约200伏特/纳秒或更高或约250伏特/纳秒或更高。如本文中所使用的,术语III族氮化物或III-N材料、层、器件等是指根据化学式的AlxInyGazN化合物半导体材料构成的材料或器件,其中x+y+z约为1。
图3示出了在电路操作期间由申请人在图1的升压转换器电路的输出节点5处测量到的输出电压噪声相对于时间的曲线图,其中,III-NHEMT用于晶体管11,并且III-N二极管用作二极管12,并且晶体管11以200伏特/纳秒的切换速度进行切换。如图所示,指示EMI的大量电压波动,即“鸣震”6,在每次III-N HEMT晶体管进行切换之后立即在节点5处被观察到。如图3中所示,峰值输出电压噪声大于10V。因此,需要进行进一步改进来抑制EMI以在较高开关速度下进行操作。
虽然申请人***图1的升压转换器电路中的III-N HEMT以及III-N二极管本身固有地能够在不生成大量EMI的情况下以较高的电路切换速度进行操作,但是其他电路寄生效应仍然在电路内生成EMI或促进EMI产生。因此,可能需要降低或消除这些寄生效应的布局构造,以便于使电路在不生成大量EMI的情况下以较高的切换速度进行操作。
图4和图5分别示出了可以替代图1的升压转换器电路中的晶体管11和二极管12二者使用的单个电子部件20的立体图和暴露的平面剖视图。在升压转换器电路中替代晶体管11和二极管12(其中晶体管11和二极管12中的每一个被独立封装)来使用电子部件20,即使在操作期间晶体管切换速度增加时,可能产生由电路产生的降低或消除的EMI。图4的立体图仅示出了电子部件的封装体,而图5的平面图图示了封装体的多个部分以及封装或密封在封装体中的电子器件。电子部件20包括都封装、包封或密封在单个封装体中的III-N晶体管21和III-N整流器件22。
单个封装体包括多个密封结构部分,例如壳体24和封装体基座23,以及非结构部分,例如引脚91-95。如本文所使用的封装体的“结构部分”是形成封装体的基本形状或成型并且提供保护所包封的器件所需要的封装体的结构刚性的部分。在多数情况下,当在分立电路中使用包括了封装体的电子部件时,封装体的结构部分被直接安装到电路或电路板。在图4的单个封装体中,封装体基座23由导电材料形成,即封装体基座23是封装体的导电结构部分,并且壳体24由绝缘材料形成。单个封装体包括至少三个引脚,栅极引脚91、漏极引脚94以及阴极引脚95,并且可选地包括至少两个其他引脚,例如开路引脚92和源极引脚93。引脚91-95都由导电材料形成。当包括源极引脚93时,其可以电连接到封装体基座23或与封装体基座23电绝缘,并且所有其他引脚都与封装体基座电绝缘。如本文所用,如果两个或多个触点或其他项由能充分导电以确保触点或其他项中的每一个处的电势在任何偏置条件下总是相同,即近似相同的材料来连接,则两个或多个触点或其他项被称为“电连接”。
如本文所使用的,“单个封装体”是包含、包封、密封或封装一个或多个电子器件或部件(即,III-N晶体管21和III-N整流器件22)的封装体,该一个或多个电子器件或部件彼此不单独密封或封装在彼此分开的封装体中。即,单个封装体可以具有边界,一个或多个电子器件位于该边界内,并且在单个封装体内的电子器件中的一个和另一个电子器件之间没有封装分隔或没有间隔。单个封装体包括结构部分,诸如图4中的封装体基座23和壳体24,其可以形成单个腔,在该腔内包封了电子器件或部件。或者,包含在封装体中的电子器件或部件可以由封装体基座来支撑,并且单个壳体24可以在密封的电子器件或部件周围成型,使得单个封装体不包含任何腔(即,单个封装体不具有任何腔),并且壳体材料接触所包封的电子器件或部件。壳体24的占地面积(footprint),即,平行于封装体基座23的主表面的所测量的壳体的面积,可以小于900平方毫米、小于400平方毫米或小于100平方毫米。包封的电子器件或部件由封装体基座23来支撑。在任何电子器件之间可能不存在封装体基材或壳体材料,即,如果壳体24形成腔,则该腔可以是连续的腔。在单个封装体中包封的各个电子器件或部件之间的连接可以是线键合或者可以由线键合形成。各个包封的电子器件或部件彼此的连接或与部分封装体的连接不由电路板上的电路迹线形成。即,单个封装体中的腔内部可以不存在电路迹线,即沉积在电路板上的导电迹线。单个封装体在不包括任何额外的外壳的情况下具有机械完整性。
如图6中所示,在一些实施方式中,封装体基座23以及壳体24由导电壳体123(即导电结构部分)替代,其完整地围绕所包封的晶体管,在该情况下,当包括源极引脚93时,源极引脚93与导电壳体电连接或与之电绝缘,并且所有其他引脚都与导电壳体电绝缘。
III-N晶体管21可以是场效应晶体管(FET),诸如高电子迁移率晶体管(HEMT)、异质结场效应晶体管(HFET)、POLFET、JFET、MESFET、CAVET或适用于功率切换应用的任何其他III-N晶体管结构。可以适用于功率切换应用的III-N晶体管的示例可以在2009年3月19日公开的美国公开号2009-0072272、2009年3月19日公开的美国公开号2009-0072240、2009年6月11日公开的美国公开号2009-0146185、2008年4月23日提交的美国专利申请号12/108,449、2008年12月10日提交的美国专利申请号12/332,284、2009年2月9日提交的美国专利申请号12/368,248以及2009年3月19日公开的美国公开号2009-0072269中找到,其全部通过引用并入这里。
在一些实施方式中,III-N晶体管21是增强型(E型)器件,即常关器件,使得阈值电压大于0V,例如约1.5V-2V或大于2V。在其他实施方式中,III-N晶体管是耗尽型(D型)器件,即常开器件,使得阈值电压小于0V。为了防止在器件或电路故障的情况下器件意外开启,在功率切换应用中优选增强型器件。在一些实施方式中,III-N晶体管21是高电压开关晶体管。如本文所用,高电压开关晶体管是优化用于高电压切换应用的晶体管。即,当晶体管截止时,能够阻断高电压,诸如约300V或更高、约600V或更高或约1200V或更高,并且当晶体管导通时,其具有用于上述应用的足够低的导通电阻(RON),即,当大量电流通过该器件时,实现足够低的导电损失。
III-N晶体管21可以是横向器件,相对于所有电极在半导体主体的相对侧上具有绝缘或半绝缘部分,如图7中所示的III-N HEMT。在一些实施方式中,通过对半导体层进行掺杂以提供电绝缘层来形成半绝缘层,但是上述绝缘层不像一些绝缘材料那样的绝缘性。图7的III-NHEMT包括绝缘或半绝缘部分61;半导体主体62,半导体主体62包括诸如GaN层的III-N缓冲层63以及诸如AlGa层的III-N势垒层64、二维电子气(2DEG)沟道65;源极25;栅极26以及漏极27。III-N HEMT可以可选地包括导电或半导电部分66,例如硅衬底。
在一些实施方式中,不包括导电或半导电部分66,并且绝缘或半绝缘部分61是绝缘或半绝缘衬底或承载晶圆。在其他实施方式中,包括导电或半导电部分66,并且导电或半导电部分66是硅衬底或导电承载晶圆,并且绝缘或半绝缘部分61是绝缘或半绝缘III-N层。如本文所使用的,“衬底”是下述材料层,在该材料层上外延生长半导体器件的半导体材料层,使得接触或邻近衬底的半导体材料的一部分的晶体结构至少部分地与衬底相适应或者至少部分地由衬底的晶体结构来确定。在一些实施方式中,衬底不促进通过半导体器件的电流的导通。使III-N晶体管21成为相对于所有电极在半导体主体的相对侧上具有绝缘或半绝缘部分的横向器件是有利的,因为当将III-N晶体管21安装在封装体内时,在电极的相对侧上的器件表面,即表面68,可以被直接安装到封装体基座23,而不需要在III-N晶体管21和封装体基座23之间的绝缘间隔物,例如“垫片(shim)”。例如,当不包括导电或半导电部分66时,绝缘或半绝缘部分61可以被直接安装到封装体基座23上,而不需要在III-N晶体管21和封装体基座23之间的绝缘间隔物,并且当包括导电或半导电部分66时,导电或半导电部分66可以被直接安装到封装体基座23,而不需要在III-N晶体管21和封装体基座23之间的绝缘间隔物。当前在常规功率切换电路中使用的晶体管,例如Si CoolMOS晶体管,通常是在半导体主体两侧具有电极的垂直器件,并且因此在晶体管和封装体基座之间需要绝缘间隔物,这可能导致在晶体管的操作期间生成的热量的较差耗散,并且在一些情况下可能导致在电路操作期间产生更多EMI。
III-N晶体管21还可以包括用于功率切换应用的其他特征。可以包括但不限于栅极和半导体主体之间的绝缘层、表面钝化层、场板、在栅极下方的半导体主体的凹槽以及其他半导体层,诸如在III-N缓冲层63和III-N势垒层64之间的AlN层或者在2DEG 65和绝缘或半绝缘部分61之间或在2DEG 65和导电或半导电部分66之间的III-N背势垒层。
III-N整流器件22可以是III-N二极管。可以使用的III-N二极管的示例可以在2008年12月10日提交的美国专利申请号12/332,284、2009年3月19日公开的美国公开号2009-0072269中找到,其全部内容通过引用并入这里。III-N整流器件22可以是横向III-N二极管,其相对于所有电极在半导体主体的相对侧上具有绝缘或半绝缘部分,诸如图8中所示的III-N二极管。图8的III-N二极管包括绝缘或半绝缘部分61、包括III-N缓冲层63(诸如GaN)以及III-N势垒层64(诸如AlGaN)、二维电子气(2DEG)沟道65的半导体主体62、在绝缘或半绝缘部分61的相对侧上接触半导体主体62并且形成与半导体主体62的半导体材料的肖特基接触的阳极触点28以及形成与2DEG沟道65的欧姆接触的阴极触点29。III-N二极管可选地可以包括导电或半导电部分66,例如硅衬底。
在一些实施方式中,不包括导电或半导电部分66,并且绝缘或半绝缘部分61是绝缘或半绝缘衬底或承载晶圆。在其他实施方式中,包括导电或半导电部分66,并且导电或半导电部分66是硅衬底或导电承载晶圆,并且绝缘或半绝缘部分是绝缘或半绝缘III-N层。使III-N整流器件22成为相对于所有电极在半导体主体62的相对侧上具有绝缘或半绝缘部分的横向二极管可能是有利的。当将III-N二极管安装在封装体内部时,电极的相对侧上的器件表面,即表面69,可以被直接安装到封装体基座23,而不需要在III-N二极管22和封装体基座23之间的绝缘间隔物,诸如“垫片”。例如,当不包括导电或半导电部分66时,绝缘或半绝缘部分61可以被直接安装到封装体基座23,而不需要在III-N二极管22和封装体基座23之间的绝缘间隔物,并且当包括导电或半导电部分66时,导电或半导电部分66可以被直接安装到封装体基座23,而不需要在III-N二极管22和封装体基座23之间的绝缘间隔物。当前用于常规功率切换电路的二极管,例如SiC二极管,通常是在半导体主体的两侧上具有电极的垂直器件,并且因此需要在二极管和封装体基座之间的绝缘间隔物,这可能导致在二极管的操作期间中生成的热量的较差耗散,并且在一些情况下可能导致在电路操作期间产生更多EMI。
用作III-N整流器件22的III-N二极管还可以包括用于功率切换应用的其他特征。可以包括但不限于表面钝化层、场板、在阳极下方的半导体主体中的凹槽、以及其他半导体层,诸如在III-N缓冲层63和III-N势垒层64之间的AlN层或者在2DEG65和绝缘或半绝缘部分61之间的III-N背势垒层。
在一些实施方式中,III-N晶体管21由与III-N整流器件22相同的III-N材料层结构形成或者包括与III-N整流器件22相同的III-N材料层结构(参见图7和图8)。在一些实施方式中,III-N晶体管21和III-N整流器件22共享或形成在公共衬底上。在公共衬底上形成该器件可能是有利的,因为两种器件可以被集成在单个芯片上,并且电极之间的电触点可以光刻地限定,而不是由线键来形成,由此简化了电路并且降低了生产成本。可以由相同III-N材料层结构形成或包括相同III-N材料层结构和/或可以共享公共衬底的III-N晶体管和二极管的示例可以在2008年12月10日提交的美国专利申请号12/332,284中找到。
在一些实施方式中,III-N整流器件是第二III-N晶体管,如图9中所示。由此,当III-N整流器件由第二III-N晶体管形成时,III-N整流器件被称为III-N整流器件22’或第二III-N晶体管22’。例如,III-N整流器件22’可以由与III-N晶体管21类似或相同结构的III-N晶体管来形成。III-N晶体管22’可以是高电压开关晶体管。可以用作诸如升压转换器的电路中的整流器件的III-N晶体管的方法的描述可以在2009年9月9日提交的美国专利申请号12/556,438中找到,其内容通过引用并入这里。
当III-N二极管用于III-N整流器件22时,III-N晶体管21和III-N二极管被安装在单个封装体内部并且如下进行连接。返回参考图6,可以是单个或多个线键合的电连接器35-39用于将封装体的多个部分、III-N晶体管以及III-N二极管彼此电连接。III-N晶体管21和III-N二极管22都安装在封装体内部,其中其相应的绝缘或半绝缘衬底都与封装体基座23接触。III-N晶体管21的源极电极25电连接到封装体的导电结构部分,诸如封装体基座23,或者另外可以诸如通过导电连接器35电连接到封装体的源极引脚93。III-N晶体管21的栅极电极26诸如通过导电连接器36电连接到封装体的栅极引脚91。III-N晶体管21的漏极电极27诸如通过导电连接器38电连接III-N二极管的阳极触点28。漏极电极27和阳极触点28诸如通过将一个或全部这些触点/电极线键合到漏极引脚94,如示通过导电连接器37,来电连接到封装体的漏极引脚94。III-N二极管的阴极触点29诸如通过导电连接器39来电连接到封装体的阴极引脚95。
当第二III-N晶体管用于III-N整流器件22’时,第一III-N晶体管21和第二III-N晶体管22’都被安装在单个封装体内部,并且如下进行连接。参考图9,III-N晶体管21和第二III-N晶体管22’都安装在封装体内,其中其各自的绝缘或半绝缘衬底都与封装体基座23接触。III-N晶体管21的源极电极25电连接到封装体的导电结构部分,诸如封装体基座23,或者还可以替代地诸如通过导电连接器35电连接到封装体的源极引脚93。III-N晶体管21的栅极26例如通过导电连接器91电连接到封装体的栅极引脚91。III-N晶体管21的漏极电极27诸如通过导电连接器38电连接到第二III-N晶体管22’的源极电极28’。第一晶体管的漏极电极27和第二晶体管的源极电极28’都诸如通过将这些电极中的一个或两个线键合到漏极引脚,例如通过导电连接器37,来电连接到封装体的漏极引脚94。第二III-N晶体管22’的漏极电极29’诸如通过导电连接器39来电连接到封装体的阴极引脚95。第二III-N晶体管22’的栅极电极58’可以诸如通过导电连接器59来电连接到封装体的引脚92。
当图6的电子部件用于升压转换器电路或多种其他电路时,III-N晶体管21的源极电极25电连接到DC接地、AC接地或电路接地。如本文所使用的,如果在操作期间总是保持处于固定的DC电势,则认为节点、器件、层或部件是“AC接地的”。AC和DC接地统称为“电路接地”。当源极电极25电连接到封装体基座23时,可以通过将封装体基座23安装到电路的接地平面来使源极电极25DC或AC接地。在该情况下,可以省略封装体引脚92和93,使得封装体仅具有3个引脚,其中一个引脚,例如栅极引脚91,连接到晶体管栅极电极26;一个引脚,例如漏极引脚94,连接到晶体管漏极电极27;并且一个引脚,例如阴极引脚95,连接到二极管阴极触点29。形成仅具有三个引脚的器件是有利的,因为许多标准商业可提供的封装体都仅适用于3个引脚。当封装体包括源极引脚93并且源极电极25电连接到源极引脚93时,可以通过将源极引脚93连接到电路接地或者将源极引脚93以其他方式电连接到封装体基座23并且将封装体基座连接到电路接地来使源极电极25可以DC或AC接地。无论封装体上引脚数目如何,这些引脚都可以任何期望的顺序从封装体的一侧排到另一侧,并且该顺序不限于图6中所示的顺序。理想地,引脚被排序为使得所有电连接器的总长度和/或晶体管、二极管的总占地面积以及封装体引脚网络被最小化,由此降低寄生效应以及可能降低电路操作过程中产生的EMI。
虽然期望图6和图9中的III-N晶体管21是增强型器件,但是实际上难以制造远大于0V的阈值电压的III-N晶体管,其对在高功率切换应用中使用也具有期望的特性。可以通过用高电压III-N耗尽型(D型)晶体管21’(这里的III-N D型晶体管21’)和低电压增强型晶体管41(E型晶体管41)替换图6中的III-N晶体管21来解决该问题,如图10中所示方式进行连接。
图10示出了可以替代图1中的升压转换器电路中的晶体管11和二极管12使用的另一单个电子部件40的平面图。使用电子部件40替代升压转换器电路中的晶体管11和二极管12(其中晶体管11和二极管12分别是独立封装的)可以导致即使在电路操作期间晶体管以较高的切换速度进行操作时也降低或消除由电路产生的EMI。图10的暴露的平面图图示了封装体的多个部分以及封装在该封装体中的电子部件(没有全部示出)。电子部件40包括都封装在单个封装体中的高电压III-N耗尽型晶体管21’、低电压增强型晶体管41以及III-N整流器件22。用于图10中的单个电子部件40的封装体可以分别与用于图6和图9中的单个电子部件20和20’的相同,即用于单个电子部件40的封装体可以与图4中所示的相同。III-N整流器件22可以是如图6中的III-N二极管,或者替代地可以是如图9中所示的第二III-N晶体管,并且具有与图6或图9的单个电子部件中的III-N整流器件22相同的需求和结构。
III-N D型晶体管21’是高电压器件,并且因此至少能阻断图1的常规升压转换器电路中的跨晶体管11下降的最大电压,其对于高电压应用来说可以是300V、600V、1200V或应用所需要的其他适当的阻断电压。换言之,III-N D型晶体管21’可以阻断在0V和至少Vmax之间的任何电压,其中Vmax是跨晶体管11下降的最大电压。在一些实施方式中,III-N D型晶体管21’可以阻断在0V和至少2Vmax之间的任何电压。用于高电压器件的典型III-N D型晶体管阈值电压Vth约为-5至-10V(D型=负Vth)。E型晶体管41可以阻断在0V和至少|Vth|之间的任何电压,其中|Vth|是III-N D型晶体管21’的阈值电压的幅值(绝对值)。在一些实施方式中,E型晶体管41可以阻断在0V和至少约2*|Vth|之间的任何电压。因此,E型晶体管41是低电压器件,其必须能够阻断的电压基本上小于电路的高电压。在一些实施方式中,III-N D型晶体管21’可以阻断在0V和至少约1200V之间的任何电压,并且具有约-5V的阈值电压,并且E型晶体管41可以阻断在0V和至少约5V之间的任何电压,诸如至少约10V。在一些实施方式中,III-N D型晶体管21’是高电压III-N HEMT器件,并且E型晶体管41是Si MOS器件或III-NHEMT器件。在其他实施方式中,E型晶体管41是氮面III-N器件,并且III-N D型晶体管21’是III面III-N器件。
当III-N二极管用于III-N整流器件22并且Si MOS器件用于E型晶体管41时,III-N D型晶体管21’、E型晶体管41以及III-N二极管22都安装在单个封装体内部,并且如下进行连接。参考图10,可以是单个或多个线键合的电连接器37’、38’、39以及52-55用于将封装体的多个部分、III-N D型晶体管21’、E型晶体管41以及III-N二极管22彼此电连接。III-N D型晶体管21’和III-N二极管22都安装在封装体内部,其中其各自的绝缘或半绝缘衬底或其各自的导电或半导电衬底都与封装体基座23接触,而E型晶体管41被安装在绝缘间隔物上,并且相对于E型晶体管41的间隔物的一侧接触封装体基座23。因为常规Si MOS器件往往是垂直器件,其中其漏极触点位于半导体主体的与其源极电极42相对侧上,所以常规Si MOS器件可能需要在Si MOS器件和封装体基座23之间***绝缘间隔物。III-N D型晶体管21’的栅极电极26’以及E型晶体管源极电极42(Si MOS器件的源极电极)都电连接诸如封装体基座23的封装体的导电结构部分,或者可以替代地电连接到封装体的源极引脚93。导电连接器55可以用于将E型晶体管源极电极42电连接到封装体基座23或源极引脚93。E型晶体管栅极电极43(Si-MOS器件的栅极电极)诸如通过导电连接器54电连接到封装体的栅极引脚91。E型晶体管漏极电极44(Si-MOS器件的漏极电极)诸如通过导电连接器52电连接到III-N D型晶体管21’的源极触点25’。III-N D型晶体管21’的漏极电极27’诸如通过导电连接器53电连接到III-N二极管的阳极触点28。漏极电极27’和阳极触点28诸如通过将这些触点/电极中的一个或两个线键合到漏极引脚94来电连接到封装体的漏极引脚94。III-N二极管的阴极触点29诸如通过导电连接器39来电连接到封装体的阴极引脚95。
当低电压III-N增强型器件用于E型晶体管41时,电连接与图10中所示的相同。然而,低电压III-N增强型器件可以包括绝缘或半绝缘部分,诸如绝缘或半绝缘衬底,在该情况下,III-N增强型器件可以被直接安装到封装体基座23,其中其绝缘或半绝缘部分接触封装体基座或者处于封装体基座23和器件沟道之间。
图10中的组件60(其包括如图所示进行连接的高电压III-N D型晶体管21’以及低电压E型晶体管41)可以与单个高电压III-N E型晶体管类似地进行操作或者可以操作为单个高电压III-N E型晶体管,即常关开关,其中其阈值电压与E型晶体管41的阈值电压相同,并且其击穿电压与III-N D型晶体管21’的击穿电压类似。即,相对于封装体基座23或源极引脚93施加到栅极引脚91的输入电压信号可能在漏极引脚94处产生输出信号,该输出信号与在单个高电压III-N E型晶体管取代组件60并如图6和图9所示方式进行连接时所产生的输出信号相同。与高电压III-N E型器件相比,高电压III-N D型晶体管和低电压E型晶体管更易于制造并且可大批量生产,因此分别与图6和图9中所示的电子部件20和20’相比,图10中的电子部件40更易于制造。
图11中示出了利用图6的电子部件20的升压转换器电路的电路示意图,而图12示出了利用图10的电子部件40的升压转换器电路的电路示意图。在图11和图12中,节点191电连接到电子部件20或40的封装体引脚91,节点194电连接到电子部件20或40的封装体引脚94,节点195电连接到电子部件20或40的封装体引脚95,并且节点193电连接到电子部件20或40的封装体引脚93或封装体基座23。
图13示出了由申请人在电路操作期间在图12的升压转换器电路的输出节点5处测量到的输出电压噪声相对于时间的曲线图。对于该测量,高电压III-N D型异质结场效应晶体管(HFET)用于III-N D型晶体管21’,低电压Si MOS E型器件用于E型晶体管41,III-N二极管用于二极管22,并且电路操作情况与图3中所示的相同。晶体管以200伏特/纳秒的切换速度进行切换。如图所示,在输出节点5处测量到的鸣震9基本上小于在图3中的输出节点处测量到的鸣震。峰值输出电压噪声小于1V,其比在图3中测量的峰值输出电压噪声小了的10倍以上。EMI也被进一步降低,和/或如果替代图11中的电路中的电子部件40分别使用在图6和图9中的电子部件20或20’,则在不生成较高水平的EMI的情况下甚至可以使用较高的切换速度。
与图3中对于包括较小数目的分立器件但是其中晶体管和二极管是独立封装体的升压转换器电路相比,图12中的电路所观察到的EMI的降低归因于寄生电阻、电容和/或电感的降低,能够通过使用封装了所有二极管和晶体管的单个封装体来实现这些降低。在图1的电路中,其中晶体管11和二极管12被独立封装,电路占地面积以及电连接的长度受到独立封装体的限制并且可能过大,因此即使在III-N器件用于晶体管11和二极管12时导致难以忍受的寄生效应以及大量的EMI生成。使用封装或密封图12中的电路中的整流器件和晶体管的单个封装体可以支持更小的电路占地面积以及在电极和部件之间更短的电连接器,即线键合),由此降低寄生电阻、电容和/或电感。因此,图6、图9和图10中的电子部件20,20'和40应当分别被配置为使得寄生电阻、电容和电感被最小化,即,应当被配置为使得占地面积以及电连接器的长度被最小化。对于图10的电子部件40来说,当Si MOS器件用于E型晶体管41时,还优选Si MOS器件具有尽可能小的漏极面积(平行于封装体基座23的主表面所测量到的),因为从仅通过绝缘间隔物使漏极与封装体基座23分离所得到的大的漏极对地电容可能进一步促进电路中的EMI。此外,因为与图10中的电子部件40相比,图6和图9的电子部件20和20’分别包括较少数目的分立器件,并且电子部件20和20’中的所有二极管和晶体管都可以在不需要绝缘垫片的情况下被安装到封装体基座23,所以由使用电子部件20或20’的电路产生的EMI甚至小于由其中电子部件20或20’由电子部件40替代的相同电路产生的EMI,和/或在不生成较高水平的EMI的情况下可以使用更高的切换速度。
图14和图15示出了图12的升压转换器的效率121和功率损失122相对于输出功率的曲线图,该升压转换器包括图10的电子部件40。电子部件40包括高电压III-N耗尽型HEMT、低电压增强型Si MOS晶体管以及III-N二极管。对于图14和图15的测量,电压从200V转换为400V,即,转换比率是1:2。对于图14的测量,电路以100kHz的频率进行操作,而对于图15的测量,电路以1MHz的频率进行操作。如图14中所示,在100kHz下,升压转换器在约50W至700W之间的所有输出功率下呈现出大于97.8%的效率,其中峰值效率大于约99%。如图15中所示,在1MHz下,升压转换器在约50W至700W的所有输出功率下都呈现出大于91.8%的效率,其中峰值效率大于约97.8%。
已经描述了多个实施方式。然而,应当理解,在不脱离本文描述的技术和器件的精神和范围的情况下,可以进行各种改进。因此,其他实施方式都在下述权利要求的范围内。
Claims (18)
1.一种电子部件,包括:
III-N耗尽型晶体管;
增强型晶体管;
III-N整流器件;以及
单个封装体,所述单个封装体包封所述III-N耗尽型晶体管、所述增强型晶体管和所述III-N整流器件,其中
所述III-N耗尽型晶体管的栅极电极电连接到所述单个封装体的导电结构部分,
所述III-N耗尽型晶体管的漏极电极电连接到所述单个封装体的第二引脚并且电连接到所述III-N整流器件的第一电极,
所述III-N整流器件的第二电极电连接到所述单个封装体的第三引脚,并且
所述增强型晶体管的源极电极电连接到所述单个封装体的所述导电结构部分、或者电连接到所述单个封装体的源极引脚,所述增强型晶体管的漏极电极电连接到所述III-N耗尽型晶体管的源极电极,并且所述增强型晶体管的栅极电极电连接到所述单个封装体的第一引脚。
2.根据权利要求1所述的电子部件,其中,所述III-N耗尽型晶体管是场效应晶体管。
3.根据权利要求1所述的电子部件,其中,所述III-N耗尽型晶体管是高电压开关晶体管。
4.根据权利要求1所述的电子部件,其中,所述III-N整流器件是III-N二极管,所述第一电极是阳极电极,并且所述第二电极是阴极电极。
5.根据权利要求4所述的电子部件,其中,所述III-N耗尽型晶体管是横向器件,所述横向器件包括绝缘或半绝缘部分,并且所述绝缘或半绝缘部分被直接安装到所述单个封装体的所述导电结构部分,而无需在所述III-N耗尽型晶体管和所述单个封装体的所述导电结构部分之间的绝缘间隔物。
6.根据权利要求5所述的电子部件,其中,所述绝缘或半绝缘部分是绝缘或半绝缘衬底。
7.根据权利要求4所述的电子部件,其中,所述III-N耗尽型晶体管是横向器件,所述横向器件包括导电或半导电衬底,并且绝缘或半绝缘III-N层位于所述导电或半导电衬底和所述III-N耗尽型晶体管的沟道之间,其中,所述导电或半导电衬底被直接安装到所述单个封装体的所述导电结构部分,而无需在所述III-N耗尽型晶体管和所述单个封装体的所述导电结构部分之间的绝缘间隔物。
8.根据权利要求7所述的电子部件,其中,所述导电或半导电衬底是硅衬底。
9.根据权利要求4所述的电子部件,其中,所述III-N耗尽型晶体管和所述III-N二极管位于公共衬底上。
10.根据权利要求1所述的电子部件,其中,所述III-N耗尽型晶体管是第一III-N晶体管,并且所述III-N整流器件是第二III-N晶体管。
11.根据权利要求10所述的电子部件,其中,所述第一III-N晶体管或所述第二III-N晶体管是横向器件,所述横向器件包括绝缘或半绝缘部分,并且所述绝缘或半绝缘部分被直接安装到所述单个封装体的所述导电结构部分,而无需在所述第一III-N晶体管和所述单个封装体的所述导电结构部分之间或者在所述第二III-N晶体管和所述单个封装体的所述导电结构部分之间的绝缘间隔物。
12.根据权利要求11所述的电子部件,其中,所述绝缘或半绝缘部分是绝缘或半绝缘衬底。
13.根据权利要求10所述的电子部件,其中,所述第一III-N晶体管或所述第二III-N晶体管是横向器件,所述横向器件包括导电或半导电衬底,并且绝缘或半绝缘III-N层位于所述导电或半导电衬底和所述第一III-N晶体管或所述第二III-N晶体管的沟道之间,其中,所述导电或半导电衬底被直接安装到所述单个封装体的所述导电结构部分,而无需在所述III-N晶体管和所述单个封装体的所述导电结构部分之间或者在所述III-N二极管和所述单个封装体的所述导电结构部分之间的绝缘间隔物。
14.根据权利要求13所述的电子部件,其中,所述导电或半导电衬底是硅衬底。
15.根据权利要求10所述的电子部件,其中,所述第一III-N晶体管和所述第二III-N晶体管位于公共衬底上。
16.根据权利要求1所述的电子部件,其中,所述III-N耗尽型晶体管是高电压开关晶体管,并且所述增强型晶体管是低电压晶体管。
17.根据权利要求16所述的电子部件,其中,所述增强型晶体管是Si MOS器件。
18.根据权利要求1所述的电子部件,其中,所述电子部件是电压转换器的一部分。
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JP2013516795A (ja) | 2013-05-13 |
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EP2522030A4 (en) | 2015-03-18 |
WO2011085260A2 (en) | 2011-07-14 |
EP2522030A2 (en) | 2012-11-14 |
US20110169549A1 (en) | 2011-07-14 |
US9401341B2 (en) | 2016-07-26 |
JP5883799B2 (ja) | 2016-03-15 |
TWI545721B (zh) | 2016-08-11 |
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WO2011085260A3 (en) | 2011-11-10 |
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