CN102412239A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN102412239A
CN102412239A CN2011102547404A CN201110254740A CN102412239A CN 102412239 A CN102412239 A CN 102412239A CN 2011102547404 A CN2011102547404 A CN 2011102547404A CN 201110254740 A CN201110254740 A CN 201110254740A CN 102412239 A CN102412239 A CN 102412239A
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semiconductor
chip
semiconductor chip
semiconductor device
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CN102412239B (zh
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井上谕
神田和重
清水有威
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Japanese Businessman Panjaya Co ltd
Kioxia Corp
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Toshiba Corp
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Abstract

本发明涉及半导体器件及其制造方法，半导体器件具备：将多个半导体芯片层叠而构成的层叠芯片；和在上述多个半导体芯片上分别设置并且使不良的半导体芯片不激活的多个不激活电路，上述多个半导体芯片分别具有多个半导体基板和在上述多个半导体基板内形成的多个贯通电极，上述多个贯通电极被电连接。

Description

半导体器件及其制造方法
技术领域
本发明涉及半导体器件及其制造方法。
背景技术
作为半导体存储器件的一种，已知有例如NAND型闪速存储器。NAND型闪速存储器在便携信息终端和/或存储卡等各种领域中使用。
另一方面，作为实现***LSI的高集成化和/或大容量化的方法，可使用例如多芯片封装体(MCP：Multi Chip Package)。通过由MCP构成NAND型闪速存储器等半导体存储器件，可实现高集成化和/或大容量化。
发明内容
本发明的实施方式提供在降低制造成本的同时可使层叠芯片所包括的不良半导体芯片不激活的半导体器件及其制造方法。
本发明的实施方式的半导体器件，具备将多个半导体芯片层叠而构成的层叠芯片和在上述多个半导体芯片分别设置且使不良的半导体芯片不激活的多个不激活电路，上述多个半导体芯片分别具有多个半导体基板和在上述多个半导体基板内形成的多个贯通电极，上述多个贯通电极电连接。
根据本发明的实施方式，可提供在降低制造成本的同时可使层叠芯片所包括的不良半导体芯片不激活的半导体器件及其制造方法。
附图说明
图1是表示多芯片封装体的结构的剖视图。
图2是表示多芯片封装体的构成的俯视图。
图3是表示半导体芯片的构成的剖视图。
图4是表示NAND型闪速存储器的构成的方框图。
图5是表示不激活电路的一个实例的电路图。
图6是表示多芯片封装体的制造方法的流程图。
图7是表示多芯片封装体的制造工序的立体图。
图8是表示多芯片封装体的制造工序的剖视图。
图9是表示多芯片封装体的制造工序的剖视图。
图10是表示多芯片封装体的制造工序的剖视图。
图11是表示多芯片封装体的制造工序的剖视图。
图12是表示多芯片封装体的制造工序的立体图。
图13是表示多芯片封装体的制造工序的立体图。
具体实施方式
(第一实施方式)
(1)多芯片封装体(MCP)10的结构
图1是表示本实施方式涉及的多芯片封装体10的结构的剖视图。图2是表示多芯片封装体10的构成的俯视图。
多芯片封装体10具备将多个半导体芯片21在纵向上层叠的层叠芯片(多芯片)20。再有，在图1中，作为一个实例而图示将四个半导体芯片21-1～21-4层叠的层叠芯片20，但是，对于半导体芯片21的数量没有特别限制。
已层叠的半导体芯片21-1～21-4通过后述的贯通电极(贯通过孔插塞)31和凸部30而电连接。层叠芯片20经多个焊盘36而与多个键合线12的一端电连接。多个键合线12的另一端与多个输入输出销11电连接。层叠芯片20、输入输出销11的一部分以及键合线12通过例如包含模制树脂的密封材料13来密封。
图3是表示半导体芯片21的构成的剖视图。半导体芯片21具备包括例如硅(Si)基板的半导体基板33、在半导体基板33上形成的半导体元件以及布线层等。在半导体元件中，包括MOS(金属氧化物半导体)晶体管、二极管、逻辑电路、存储元件等。在图3中，示出MOS晶体管Tr来作为半导体元件的一个实例。
在半导体基板33内，设有将相邻的半导体元件电分离的元件分离绝缘层38。MOS晶体管Tr设置在半导体基板33的表面区域中的没有设置元件分离绝缘层38的元件区域(有源区域)。MOS晶体管Tr具备在半导体基板33内互相离开地形成的源区域S和漏区域D以及在源区域S和漏区域D间的半导体基板33上隔着栅绝缘膜而形成的栅电极G。
在半导体基板33内，设有将其贯通的贯通电极(贯通过孔插塞)31。在贯通电极(thorough electrode)31和半导体基板33之间，设有绝缘膜32。在贯通电极31之上，设有第一级布线层34。在第一级布线层34的上方，设有第二级布线层35。第一级布线层34和第二级布线层35通过过孔插塞而电连接。在第二级布线层35的上方，设有构成为第三级布线层的焊盘36。第二级布线层35和焊盘36通过过孔插塞而电连接。再有，对于布线层的层叠数没有特别限定，可以是三层以上，也可以是少于三层。
半导体芯片21-1的贯通电极31和半导体芯片21-2的焊盘36通过凸部(突起状电极)30电连接。凸部30包括例如焊料球。在半导体基板33和焊盘36之间，由层间绝缘层37填满。在如此构成的层叠芯片20中，通过贯通半导体基板33地形成的贯通电极31，而可将半导体芯片21间以最短距离电连接。作为使用贯通电极31连接的布线，可以是电源线，也可以是信号线。
其次，对装载于半导体芯片21的电路构成进行说明。在本实施方式中，作为在半导体芯片21上装载的电路，以NAND型闪速存储器为例进行说明。图4是表示NAND型闪速存储器的构成的方框图。
半导体芯片21具备被施加电源电压Vcc的焊盘40、被施加接地电压Vss的焊盘41和被输入各种控制信号以及数据并且输出数据的多个焊盘42。焊盘40经切断用布线43而与电路部50连接。对切断用布线43在后面描述。焊盘41和42与电路部50连接。
在电路部50，包括构成NAND型闪速存储器的各种电路51～59。存储单元阵列51通过将例如多个浮置栅型存储单元矩阵状地排列而构成。行译码器(包括字线驱动电路)52驱动在存储单元阵列51配置的字线和选择栅线。读出放大器电路53具备例如一页大小的读出放大器和数据保持电路，构成对存储单元阵列51以页为单位进行数据写入和数据读出的页缓冲器。
由读出放大器电路53读出的一页大小的读出数据被列译码器(列选通器)54选择，向I/O缓冲器55输送。向I/O缓冲器55输送的读出数据从焊盘42所包括的I/O端子向外部输出。向I/O端子输入的写入数据由列译码器54选择，向读出放大器电路53载入。在读出放大器电路53载入一页大小的写入数据，其保持到写入循环结束为止。
地址信号经焊盘42向I/O缓冲器55输入，然后，由地址保持电路56保持。由地址保持电路56保持的地址信号被输送到行译码器52和列译码器54。
控制电路57根据芯片使能信号/CE、写入使能信号/WE、读出使能信号/RE、地址锁存器使能信号ALE、指令锁存器使能信号CLE等控制信号，来生成数据读出、写入及删除的定时控制用的各种内部定时信号。上述标记“/”意指低态有效(low active)。控制电路57根据这些内部定时信号来进行数据写入和删除的时序控制、数据读出的工作控制。此外，控制电路57具备不激活电路44。不激活电路44是用于使装载自身的半导体芯片21不激活的电路。
电压产生电路58由控制电路57控制，产生用于数据写入和/或删除的各种高电压Vgen。通电复位电路59为了防止半导体芯片21内的电路的误工作而在电源接通时将半导体芯片21内的电路复位。因此，通电复位电路59生成复位信号/RST。通电复位电路59监视电源电压Vcc，在电源电压Vcc为阈值以上的情况下，输出包括低电平的脉冲的复位信号/RST。半导体芯片21内的电路通过复位信号/RST而复位。
半导体芯片21-1～21-4的每个包括图4所示的NAND型闪速存储器。即，在本实施方式中，以构成层叠芯片20的多个半导体芯片21-1～21-4分别具有相同电路构成的情况为例进行说明。但是，不限于此类构成，也可使半导体芯片21-2～21-4承担从属芯片的作用、使半导体芯片21-1承担控制从属芯片的主芯片的作用，使得层叠芯片20作为整体而构成一个NAND型闪速存储器。在此类构成的情况下，在从属芯片主要装载存储单元阵列，在主芯片装载控制存储单元阵列的控制电路和/或电源电路。
其次，对不激活电路44的构成进行说明。在本实施方式中，各半导体芯片21具备图4所示的不激活电路44。图5是表示不激活电路44的一个实例的电路图。
不激活电路44具备保险丝60、P沟道MOS晶体管(PMOS晶体管)61和62、反相(inverter)电路63～65以及NOR电路66。
保险丝60的一端与节点N1连接，另一端接地。作为保险丝60，使用可由激光切断的激光保险丝或可电切断的电保险丝(e保险丝)。
PMOS晶体管61的源与电源电压端子Vcc连接，漏与节点N1连接，从通电复位电路59向栅输入复位信号/RST。PMOS晶体管62的源与电源电压端子Vcc连接，漏与节点N1连接。
反相电路63的输入端子与节点N1连接，输出端子与PMOS晶体管62的栅和反相电路64的输入端子连接。反相电路64的输出端子与NOR电路66的第一输入端子连接。
从外部向NOR电路66的第二输入端子输入芯片使能信号/CE，输出端子与反相电路65的输入端子连接。反相电路65输出新的芯片使能信号/CE，将该芯片使能信号/CE送至控制电路57。
(2)制造方法
其次，对多芯片封装体10的制造方法进行说明。图6是表示多芯片封装体10的制造方法的流程图。
首先，如图7所示，形成包括多个半导体芯片21的半导体晶片70。再有，形成多个图7所示的半导体晶片70(步骤S100)。
接着，在各半导体晶片70形成贯通电极31(步骤S101)。具体地，如图8所示，通过采用光刻技术，而在半导体基板33的背面形成设有与贯通孔71的平面形状对应的开口部的抗蚀剂图形。而且，通过将该抗蚀剂图形作为掩模来对半导体基板33进行干蚀刻，从而在半导体基板33形成贯通孔71。然后，通过灰化(ashing)工序来除去抗蚀剂图形。
接着，如图9所示，通过例如CVD(化学气相淀积)法，覆盖贯通孔71的侧壁地在半导体基板33的背面形成绝缘膜32。作为绝缘膜32，例如，采用硅氧化物。接着，通过使用光刻技术和干蚀刻工序，而在绝缘膜32和层间绝缘层37内形成到达第一级布线层34的开口部72。
接着，如图10所示，通过例如镀Cu，而形成埋入开口部72且覆盖贯通孔71的侧壁的贯通电极31。接着，如图11所示，使用例如焊料球来形成与贯通电极31接触且从半导体基板33突起的凸部30。这样，在半导体基板33内形成贯通电极31。
接着，对晶片状态的半导体芯片21进行管芯分类测试(步骤S102)。管芯分类测试是对晶片状态下的芯片的不良状况进行筛选的测试，包括电特性的测试工序。在该晶片状态下的管芯分类测试中，识别产生DC不良的半导体芯片(步骤S103)。DC不良意指电源线引起的不良情况，包括电源线间短路的不良情况和电源线的一部分成为开路的不良情况。在半导体芯片21上，设有用于将从芯片外部施加的电源电压Vcc送至芯片内的电路的电源线Vcc、用于将从芯片外部施加的接地电压Vss送至芯片内的电路的电源线(接地线)Vss和用于将在芯片内部产生的电源电压Vgen送至芯片内的电路的电源线Vgen。
根据管芯分类测试的结果，而将DC不良分为(1)电源线Vgen和电源线Vss间的短路、(2)电源线Vcc和电源线Vgen间的短路以及(3)电源线Vcc和电源线Vss间的短路这三种。由于是贯通电极，因此存在一个DC不良芯片对其他全部层叠芯片都产生影响的问题。因此，在发生DC不良(1)或DC不良(2)的半导体芯片中，使该半导体芯片不激活。这样，即使是包括发生DC不良的半导体芯片的层叠芯片，也可避免不良芯片对合格品的半导体芯片产生影响。另一方面，在发生DC不良(3)的半导体芯片中，将该半导体芯片的电源线Vcc或电源线Vss在焊盘附近切断。这样，即使是包括发生DC不良的半导体芯片的层叠芯片，也可避免不良芯片对合格品的半导体芯片产生影响。
下面说明对于DC不良的具体处理方法。
(1)电源线Vgen和电源线Vss间的短路或(2)电源线Vcc和电源线Vgen间的短路
在发生DC不良(1)或DC不良(2)的情况下(步骤S104)，该半导体芯片不能工作。因此，使该不良芯片不激活(步骤S105)。为此，由不激活电路44使得向不良芯片输入的芯片使能信号/CE总是成为高电平(不激活状态)。
即，在装载于不良芯片的不激活电路44中，切断图5所示的保险丝60。在切断保险丝60的状态下，在电源接通时通电复位信号/RST成为低电平时，节点N1成为高电平。该节点N1经两个反相电路63、64而与NOR电路66连接。因此，与从外部输入的芯片使能信号/CE的逻辑无关，不激活电路44总是输出高电平的芯片使能信号/CE。这样，该不良芯片不会激活。
另一方面，在没有切断保险丝60的情况下，不激活电路44将从外部输入的芯片使能信号/CE按原来的逻辑状态输出。这样，可通过从外部输入的芯片使能信号/CE来控制合格品的半导体芯片的选通/不选通。
(3)电源线Vcc和电源线Vss间的短路
在被施加来自半导体芯片的外部的电源电压的外部电源线和接地线短路时，在半导体芯片整体流过大电流，因此不能用上述方法补救层叠芯片。再有，在外部电源线和/或接地线通过贯通电极电连接的情况下，在层叠芯片整体流过大电流。
在DC不良(3)的情况下，需要使用激光等将短路部位物理性地切断。此时，将短路部位分别切断时，生产率变差，成本增加。因此，在本实施方式中，如图4所示，在焊盘40的附近即焊盘40和电路部50之间预先配置切断用布线43。优选的是，切断用布线43由易于因激光的热而熔化的材料构成，形成得比其他布线粗，再有，在其周围不配置其他布线以易于切断。通过将该切断用布线43物理性地切断而使不良芯片不激活(步骤S107)。
再有，在本实施方式中，对电源线Vcc添加切断用布线43，但是，也可对电源线Vss添加切断用布线43。在该实例中，通过将切断用布线43切断，也可防止电源线Vcc和电源线Vss间的短路。
接着，如图12所示，将上侧的半导体晶片的凸部和下侧的半导体晶片的焊盘连接而层叠多个半导体晶片70-1～70-4(步骤S108)。
接着，如图13所示，将层叠晶片切割(步骤S109)。这样，形成多个层叠芯片20。然后，将层叠芯片20封装，而完成多芯片封装体10的制造。
再有，在上述两个方法中，使不良芯片不激活的多芯片封装体10可通过将新的合格品的半导体芯片按不良芯片的数量层叠来补充存储容量。
(3)效果
如上所述，在本实施方式中，在制造多芯片封装体10时，进行多个半导体晶片70的管芯分类测试，根据管芯分类测试的结果，将DC不良分为(1)电源线Vgen和电源线Vss间的短路、(2)电源线Vcc和电源线Vgen间的短路以及(3)电源线Vcc和电源线Vss间的短路这三种。而且，对于发生DC不良(1)或DC不良(2)的不良芯片，通过不激活电路44而使不良芯片不激活。在发生DC不良(3)的情况下，通过将在焊盘40附近设置的切断用布线43物理性地切断而使不良芯片不激活。然后，将多个半导体晶片70层叠，通过将该层叠晶片切割而形成层叠芯片20。再有，使用贯通电极31而将层叠芯片20以最短距离电连接。
因此，根据本实施方式，在具备使用贯通电极31来电连接的层叠芯片20的多芯片封装体10中，可使发生DC不良的不良芯片不激活。这样，可避免不良芯片对其他芯片造成影响。
此外，即使在外部电源Vcc和Vss间短路的情况下，也可将不良芯片的电源线从其他芯片切断。这样，即使在外部电源Vcc和Vss使用贯通电极31来将半导体芯片之间电连接的情况下，也可将不良品补救为合格品。
另外，在多芯片封装体中，在将半导体晶片切割后将半导体芯片层叠时，制造工序复杂，制造成本增加。但是，在本实施方式中，在半导体晶片的状态下将半导体芯片层叠，因此可简化制造工序，降低制造成本。
再有，在本实施方式中，以将NAND型闪速存储器作为在多芯片封装体10上装载的电路为例进行说明。但是，并不限于此，本实施方式当然也可适用于NAND型闪速存储器以外的其他半导体存储器。

Claims (16)

1.一种半导体器件，其特征在于，
具备：
将多个半导体芯片层叠而构成的层叠芯片；和
在上述多个半导体芯片上分别设置并且使不良的半导体芯片不激活的多个不激活电路，
上述多个半导体芯片分别具有多个半导体基板和在上述多个半导体基板内形成的多个贯通电极，上述多个贯通电极被电连接。
2.根据权利要求1所述的半导体器件，其特征在于，
上述多个半导体芯片的各个包括：被施加外部电源的第一电源线；被施加在上述半导体芯片内生成的内部电源的第二电源线；和被施加接地电压的接地线，
上述多个半导体芯片所包括的多个第一电源线由贯通电极电连接，
上述多个半导体芯片所包括的多个第二电源线由贯通电极电连接，
上述多个半导体芯片所包括的多个接地线由贯通电极电连接。
3.根据权利要求2所述的半导体器件，其特征在于，
上述多个不激活电路的各个在发生上述第二电源线及上述接地线之间的短路时或发生上述第一电源线及上述第二电源线之间的短路时，使芯片使能信号总是不激活。
4.根据权利要求3所述的半导体器件，其特征在于，
上述不激活电路包括保险丝，相应于上述保险丝的状态来控制上述芯片使能信号。
5.根据权利要求3所述的半导体器件，其特征在于，
上述芯片使能信号控制上述半导体芯片的激活和不激活。
6.根据权利要求3所述的半导体器件，其特征在于，
上述半导体芯片从外部接收上述芯片使能信号。
7.根据权利要求2所述的半导体器件，其特征在于，
上述半导体芯片包括使用上述外部电源来生成上述内部电源的电压产生电路。
8.根据权利要求2所述的半导体器件，其特征在于，
上述半导体芯片包括在焊盘和上述第一电源线之间或焊盘和上述接地线之间设置的布线，
上述布线在发生上述第一电源线及上述接地线之间的短路时被切断。
9.根据权利要求8所述的半导体器件，其特征在于，
上述布线包含通过激光的热而熔化的材料。
10.根据权利要求1所述的半导体器件，其特征在于，
上述半导体芯片是半导体存储器。
11.一种半导体器件的制造方法，其特征在于，
包括：
准备分别具有多个半导体基板和在上述多个半导体基板内形成的多个贯通电极的多个晶片的工序；
测试各晶片所包括的多个半导体芯片的电特性的工序；
根据上述测试结果来使不良的半导体芯片不激活的工序；
以使上述贯通电极电连接的方式层叠上述多个晶片的工序；和
将上述层叠的晶片分离为多个层叠芯片的工序。
12.根据权利要求11所述的半导体器件的制造方法，其特征在于，
上述多个半导体芯片的各个包括：被施加外部电源的第一电源线；被施加在该半导体芯片内产生的内部电源的第二电源线；和被施加接地电压的接地线，
上述多个半导体芯片所包括的多个第一电源线由贯通电极电连接，
上述多个半导体芯片所包括的多个第二电源线由贯通电极电连接，
上述多个半导体芯片所包括的多个接地线由贯通电极电连接。
13.根据权利要求12所述的半导体器件的制造方法，其特征在于，
上述不激活的工序包括：在发生上述第二电源线及上述接地线之间的短路时或发生上述第一电源线及上述第二电源线之间的短路时，使芯片使能信号总是不激活的工序。
14.根据权利要求12所述的半导体器件的制造方法，其特征在于，
上述半导体芯片包括使用上述外部电源来生成上述内部电源的电压产生电路。
15.根据权利要求12所述的半导体器件的制造方法，其特征在于，
上述不激活的工序包括：在发生上述第一电源线及上述接地线之间的短路时，从焊盘将上述第一电源线或上述接地线切断的工序。
16.根据权利要求11所述的半导体器件的制造方法，其特征在于，
上述半导体芯片是半导体存储器。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106847726A (zh) * 2017-02-08 2017-06-13 上海华虹宏力半导体制造有限公司 晶圆测试方法
CN108630596A (zh) * 2017-03-22 2018-10-09 东芝存储器株式会社 半导体装置的制造方法及半导体装置

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101690487B1 (ko) * 2010-11-08 2016-12-28 삼성전자주식회사 반도체 장치 및 제조 방법
KR102190382B1 (ko) 2012-12-20 2020-12-11 삼성전자주식회사 반도체 패키지
US20160005816A1 (en) * 2014-07-02 2016-01-07 International Rectifier Corporation Group III-V Transistor with Voltage Controlled Substrate
TWI699761B (zh) 2015-03-04 2020-07-21 日商東芝記憶體股份有限公司 半導體裝置
KR102410992B1 (ko) * 2015-11-26 2022-06-20 삼성전자주식회사 적층형 메모리 장치, 이를 포함하는 메모리 패키지 및 메모리 시스템
WO2017126014A1 (ja) * 2016-01-18 2017-07-27 ウルトラメモリ株式会社 積層型半導体装置及びその製造方法
CN110246799B (zh) * 2018-03-07 2021-06-25 长鑫存储技术有限公司 连接结构及其制造方法、半导体器件

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5946545A (en) * 1994-03-30 1999-08-31 Internatinal Business Machines Corporation Semiconductor stack structures and fabrication/sparing methods utilizing programmable spare circuit
CN2629223Y (zh) * 2003-05-30 2004-07-28 威盛电子股份有限公司 芯片模块
CN1540665A (zh) * 2003-04-21 2004-10-27 ���ش�洢����ʽ���� 存储器模块和存储器***
CN1551344A (zh) * 2003-05-19 2004-12-01 精工爱普生株式会社 半导体装置和层叠型半导体装置以及它们的制造方法
US20080081457A1 (en) * 2006-09-29 2008-04-03 Megica Corporation Integrated circuit chips with fine-line metal and over-passivation metal
US20090207663A1 (en) * 2008-02-14 2009-08-20 Sang-Gu Kang Flash Memory Devices Including Ready/Busy Control Circuits and Methods of Testing the Same
US20100193903A1 (en) * 2008-07-23 2010-08-05 Epworks Co., Ltd. Three dimensional semiconductor device, method of manufacturing the same and electrical cutoff method for using fuse pattern of the same

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6292422B1 (en) * 1999-12-22 2001-09-18 Texas Instruments Incorporated Read/write protected electrical fuse
US6404660B1 (en) * 1999-12-23 2002-06-11 Rambus, Inc. Semiconductor package with a controlled impedance bus and method of forming same
JP4483136B2 (ja) * 2001-06-20 2010-06-16 ソニー株式会社 半導体デバイスの実装方法及び半導体装置の製造方法
JP2003185710A (ja) * 2001-10-03 2003-07-03 Matsushita Electric Ind Co Ltd マルチチップモジュール、半導体チップ及びマルチチップモジュールのチップ間接続テスト方法
US6762918B2 (en) * 2002-05-20 2004-07-13 International Business Machines Corporation Fault free fuse network
JP2003338193A (ja) * 2002-05-21 2003-11-28 Mitsubishi Electric Corp 半導体メモリモジュール
US7071547B2 (en) * 2002-09-11 2006-07-04 Tessera, Inc. Assemblies having stacked semiconductor chips and methods of making same
US7112895B2 (en) * 2003-08-15 2006-09-26 Infineon Technologies Ag Reduced power consumption in integrated circuits with fuse controlled redundant circuits
US20050088794A1 (en) * 2003-10-23 2005-04-28 International Business Machines Corporation Removeable ESD for improving I/O pin bandwidth
JP4340517B2 (ja) * 2003-10-30 2009-10-07 Ｏｋｉセミコンダクタ株式会社 半導体装置及びその製造方法
US7061304B2 (en) * 2004-01-28 2006-06-13 International Business Machines Corporation Fuse latch with compensated programmable resistive trip point
US7271988B2 (en) * 2004-08-04 2007-09-18 Taiwan Semiconductor Manufacturing Company Method and system to protect electrical fuses
DE102006016345A1 (de) * 2006-04-05 2007-10-18 Infineon Technologies Ag Halbleitermodul mit diskreten Bauelementen und Verfahren zur Herstellung desselben
JP4886434B2 (ja) * 2006-09-04 2012-02-29 株式会社東芝 不揮発性半導体記憶装置
JP4791924B2 (ja) * 2006-09-22 2011-10-12 株式会社東芝 半導体記憶装置
JP4937842B2 (ja) * 2007-06-06 2012-05-23 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
KR100881198B1 (ko) * 2007-06-20 2009-02-05 삼성전자주식회사 반도체 패키지 및 이를 실장한 반도체 패키지 모듈
US7816934B2 (en) * 2007-10-16 2010-10-19 Micron Technology, Inc. Reconfigurable connections for stacked semiconductor devices
JP2009129498A (ja) * 2007-11-22 2009-06-11 Toshiba Corp 半導体記憶装置
KR101307490B1 (ko) * 2009-03-30 2013-12-11 메기가 코포레이션 상부 포스트-패시베이션 기술 및 하부 구조물 기술을 이용한 집적 회로 칩
JP2011082449A (ja) * 2009-10-09 2011-04-21 Elpida Memory Inc 半導体装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5946545A (en) * 1994-03-30 1999-08-31 Internatinal Business Machines Corporation Semiconductor stack structures and fabrication/sparing methods utilizing programmable spare circuit
CN1540665A (zh) * 2003-04-21 2004-10-27 ���ش�洢����ʽ���� 存储器模块和存储器***
CN1551344A (zh) * 2003-05-19 2004-12-01 精工爱普生株式会社 半导体装置和层叠型半导体装置以及它们的制造方法
CN2629223Y (zh) * 2003-05-30 2004-07-28 威盛电子股份有限公司 芯片模块
US20080081457A1 (en) * 2006-09-29 2008-04-03 Megica Corporation Integrated circuit chips with fine-line metal and over-passivation metal
US20090207663A1 (en) * 2008-02-14 2009-08-20 Sang-Gu Kang Flash Memory Devices Including Ready/Busy Control Circuits and Methods of Testing the Same
US20100193903A1 (en) * 2008-07-23 2010-08-05 Epworks Co., Ltd. Three dimensional semiconductor device, method of manufacturing the same and electrical cutoff method for using fuse pattern of the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106847726A (zh) * 2017-02-08 2017-06-13 上海华虹宏力半导体制造有限公司 晶圆测试方法
CN108630596A (zh) * 2017-03-22 2018-10-09 东芝存储器株式会社 半导体装置的制造方法及半导体装置
CN108630596B (zh) * 2017-03-22 2022-01-11 东芝存储器株式会社 半导体装置的制造方法及半导体装置

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