CN102237409A - 功率半导体器件 - Google Patents

功率半导体器件 Download PDF

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CN102237409A
CN102237409A CN2011101055652A CN201110105565A CN102237409A CN 102237409 A CN102237409 A CN 102237409A CN 2011101055652 A CN2011101055652 A CN 2011101055652A CN 201110105565 A CN201110105565 A CN 201110105565A CN 102237409 A CN102237409 A CN 102237409A
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semiconductor layer
film
power semiconductor
dielectric film
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斋藤涉
小野升太郎
薮崎宗久
谷内俊治
渡边美穗
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Toshiba Corp
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Abstract

一种功率半导体器件，具备：第一导电类型的第一半导体层；上述第一导电类型的第二半导体层和第二导电类型的第三半导体层，横向上周期性地设置在第一半导体层之上；上述第二导电类型的第四半导体层，设置在上述第三半导体层之上；上述第一导电类型的第五半导体层，选择性地设置在上述第四半导体层的表面；第一主电极，与上述第一半导体层连接；第二主电极，与上述第四半导体层和上述第五半导体层连接；第一绝缘膜，设置在从上述第五半导体层的表面直至上述第二半导体层的沟槽的侧壁；第二绝缘膜，设置在比上述第一绝缘膜靠近上述沟槽的底部侧，介电常数高于上述第一绝缘膜；控制电极，隔着上述第一绝缘膜和上述第二绝缘膜填充在上述沟槽中。

Description

功率半导体器件
本申请基于并要求申请日为2010年4月27日的日本专利申请No.2010-102340的优先权，其全部内容作为参考被包含在本文中。
技术领域
本发明的实施方式涉及功率半导体器件。
背景技术
纵式功率MOSFET的通态电阻很大程度依存于传导层(漂移层)部分的电阻。而且，决定该漂移层电阻的掺杂浓度根据基极层和漂移层所形成的pn结的耐压而不能提高到极限以上。因此，在器件耐压与通态电阻之间存在折衷选择的关系。改善该折衷选择对低消耗功率器件很重要。该折衷选择具有取决于器件材料的极限，超过该极限是实现超过现有功率器件的低通态电阻的办法。
另外，作为解决该问题的MOSFET的一例，已知有一种在漂移层中填充了被称作超级结(SJ)结构的周期性的p柱状层和n柱状层的结构。在SJ结构中，使p柱状层和n柱状层中所含的填充量(杂质量)同量做出模拟的非掺杂层以保持高耐压。同时，通过使电流流过高掺杂的n柱状层来实现超过材料极限的低通态电阻。此外，通过缩窄SJ结构的横向周期，提高p柱状层和n柱状层的杂质浓度，能够进一步实现低通态电阻。
但是，在SJ结构中，除了基极层和漂移层所形成的pn结之外，还在漂移层内的p柱状层和n柱状层之间形成pn结。从而，pn结面积变大，漏-源极间电容Cds变大。因此，通常难以依靠Cds和栅-漏极间电容Cgd来把由流经Cgd的变位电流所控制的漏极电压的变化率(dV/dt)抑制在规定范围内。其结果，存在开关噪声增大的问题。因此，要求有一种维持SJ结构的低通态电阻并且能够降低开关噪声的功率半导体器件。
发明内容
本发明的实施方式提供一种能降低通态电阻和开关噪声的功率半导体器件。
本发明的实施方式的功率半导体器件一般具备：第一导电类型的第一半导体层；上述第一导电类型的第二半导体层和第二导电类型的第三半导体层，横向上周期性地设置在上述第一半导体层之上。在上述第三半导体层之上设置上述第二导电类型的第四半导体层，在上述第四半导体层的表面上选择性地设置上述第一导电类型的第五半导体层。具备：第一主电极，与上述第一半导体层连接；第二主电极，与上述第四半导体层和上述第五半导体层连接。具备：第一绝缘膜，设置在从上述第五半导体层的表面直至上述第二半导体层的沟槽的侧壁上；第二绝缘膜，设置在比上述第一绝缘膜往上述沟槽的底部侧，介电常数高于上述第一绝缘膜；控制电极，通过上述第一绝缘膜和上述第二绝缘膜填充在上述沟槽中。
根据本发明的实施方式，提供一种能兼顾低通态电阻和低开关噪声的功率半导体器件。
附图说明
图1是模式性地示出第一实施方式的功率半导体器件的剖视图。
图2是模式性地示出第一实施方式的变形例的功率半导体器件的剖视图。
图3是模式性地示出第二实施方式的功率半导体器件的剖视图。
图4是模式性地示出第二实施方式的变形例的功率半导体器件的剖视图。
图5是模式性地示出第三实施方式的变形例的功率半导体器件的剖视图。
图6是模式性地示出第四实施方式的功率半导体器件的剖视图。
具体实施方式
以下，参照附图对本发明的实施方式进行说明。另外，在以下的实施方式中，对附图中的同一部分标记同一符号并适当省略其详细说明，对不同部分适当进行说明。假设第一导电类型为n型，第二导电类型为p型进行说明，但也可以假设第一导电类型为p型，第二导电类型为n型。
(第一实施方式)
参照图1，对第一实施方式的功率半导体器件进行说明。
图1(a)是示出第一实施方式的功率半导体器件MOSFET100的单位单元的截面的模式图。图1(b)是示出第一实施方式的变形例的功率半导体器件MOSFET110的单位单元的截面的模式图。
图1(a)所示的MOSFET100具备：作为第一半导体层的n型漏极层2；设置在n型漏极层2之上的作为第二半导体层的n型柱状层3和作为第三半导体层的p型柱状层4。在沿n型漏极层2的主面20的横向上周期性配置n型柱状层3和p型柱状层4。n型柱状层3中掺杂的n型杂质的量和p型柱状层4中掺杂的p型杂质的量设置成大致同量，在n型漏极层2上形成SJ结构。
另一方面，将n型漏极层2的杂质浓度设置得高于n型柱状层3的杂质浓度。然后，在n型漏极层2的另一个主面30上设置作为第一主电极的漏电极1，与n型漏极层2电连接。
在p型柱状层4之上设置作为第四半导体层的p型基极层5，在p型基极层5的表面上选择性地设置作为第五半导体层的n型源极层6。然后设置有从n型源极层6的表面直至n型柱状层3的沟槽12。在沟槽12的侧壁上设置作为第一绝缘膜的栅极绝缘膜8。另外，在比栅极绝缘膜8靠近底部侧的沟槽12的内面上设置介电常数高于栅极绝缘膜8的作为第二绝缘膜的高介质膜7。
另一方面，在沟槽12内部，隔着栅极绝缘膜8和高介质膜7填充着作为控制电极的栅电极9。
在MOSFET100中，栅电极9隔着栅极绝缘膜8与n型源极层6、p型基极层5和n型柱状层3对置，隔着高介质膜7与n型柱状层3对置。
另外，作为第二主电极的源电极10隔着层间绝缘膜13覆盖栅电极9之上，在相邻2个栅电极9之间设置成与p型基极层5和n型源极层6电连接。
上述的槽栅结构可以如下地形成。
例如，在使用溅射法在沟槽12内部形成了高介质膜之后进行刻蚀，将高介质膜7留在底部。接着，在高介质膜7上方的侧壁上形成由例如氧化硅膜(SiO2)构成的栅极绝缘膜8。另外，可以通过将成为栅电极9的导电性多晶硅填充到沟槽12内部来形成上述槽栅。
通过成为这样的结构，能够兼顾低通态电阻和低开关噪声。以下说明本实施方式的功率半导体的作用效果。
例如，通过缩短SJ结构的横向周期(n型柱状层3和p型柱状层4的横向的宽度)，能够提高n型柱状层3和p型柱状层4的杂质浓度。这样，流过漏极电流的n型柱状层3的电阻下降，得到低通态电阻。
但是，同时n型柱状层3与p型柱状层4之间的pn结的面积变大，漏-源极间电容Cds变大。因此，开关工作时的漏极电压的时间变化(dV/dt)受Cds的充放电支配，栅-漏极间电容Cgd的贡献相对变小。从而，通过适当选择外带栅极电阻，即使改变流到Cgd中的变位电流，也不能够控制dV/dt，从而容易产生开关噪声。因此，为了提高利用外带栅极电阻的控制性，考虑增大栅-漏极间电容Cgd。
为了增大Cgd，例如可以增大栅电极9与漏电极1之间的对置面积。对此，从p型基极层5向n型柱状层3侧突出很多地设置沟槽12是有效的。但是，如果使沟槽12的底部向漏电极1靠近，就在沟槽12的底部电场聚焦，具有耐压和雪崩容量下降的问题。
因此，在本实施方式的功率半导体器件中，在沟槽12的底部设置有高介质膜7。这样就能够增大Cgd，提高外带栅极电阻的控制性并且能够实现开关噪声的降低。然后，由于也可以减小沟槽12向n型柱状层3的突出，因此耐压和雪崩容量不会下降。
通常，沟槽12的突出量(从p型基极层5与n型柱状层3的边界到沟槽12底部的距离：UT)是p型基极层5厚度的25％～50％，在沟槽12底部处于容易引起电场聚焦的状态。对此，若使沟槽12的底部的突出量UT成为p型基极层5的厚度的10％以下，就能够抑制沟槽12底部的电场聚焦。另外，因为设置在沟槽12底部的绝缘膜(高介质膜7)引起绝缘击穿的临界电场比半导体层(n型柱状层3)的临界电场大一位，所以可以忽视沟槽12底部的电场，能够消除耐压和雪崩容量的下降。
在本实施方式的功率半导体器件中，仅在沟槽12底部形成高介质膜7，在沟槽12的侧壁上形成介电常数较低的栅极绝缘膜8。这样，不增加栅-源极间电容Cgs而开关时的栅极驱动变为高速，通过缩短延迟时间而能够降低驱动损耗。
栅极绝缘膜8可以使用例如SiO2和SiN、SiO2和SiN的复合膜等。另一方面，高介质膜7可以使用例如AlOx、HfOx、ZrOx、TaOx和它们的复合膜等。
此外，可以如图1(b)中示出的MOSFET110这样地使设置于沟槽22底部的高介质膜27成为层叠了由相互不同材料构成的多个层的叠层膜。例如，可以成为在n型柱状层3与高介质膜25之间形成SiO2膜24和在高介质膜25与栅电极9之间形成SiO2膜26的叠层膜。
图1(b)中示出的槽栅结构可以如下地设置。
首先，将沟槽12的内面热氧化形成SiO2膜24。接着，在沟槽22内部形成成为高介质膜25的高介质，另外，将该高介质刻蚀成规定的膜厚，在沟槽22底部留有高介质膜25。
然后，在高介质膜25之上使用例如CVD法形成SiO2膜26。之后，在沟槽22的侧壁上形成栅极绝缘膜8，用导电性的多晶硅填充沟槽22的内部而形成栅电极9。栅极绝缘膜8可以包括在形成SiO2膜24和SiO2膜26时形成在沟槽22侧壁上的SiO2膜。
通过将沟槽22的内面热氧化形成SiO2膜，能够实现在n型柱状层3与SiO2膜24的界面中降低界面电平并且抑制栅极阈值电压的变动从而稳定的工作。
另外，通过在栅电极9与高介质膜25之间形成SiO2膜26，能够掩盖高介质膜25中产生的针孔和晶界等，抑制栅-源极间的耐压的下降。
此外，在高介质膜25与栅电极9的紧密性较低的情况下，通过把由溶于双方的材料构成的介质膜夹在中间，能够提高紧密性。
在高介质膜25的上下形成的膜并不限于上述例子示出的SiO2膜，例如也可以使用SiN膜等与高介质膜25不同的异种膜。
图2是示出第一实施方式的其他的变形例的功率半导体器件的截面的模式图。
在图2(a)中示出的MOSFET120中，设置在沟槽32底部的高介质膜37例如是由高介质膜35和SiO2膜36构成的双层膜。在与n型柱状层3相连的底部设置高介质膜35，在与栅电极9相连的上侧设置SiO2膜36。
也可以取代SiO2膜36而使用SiN膜等与高介质膜35不同的异种材料。如前所述地覆盖高介质膜35的针孔和晶界可以提高高介质膜37的绝缘耐压。
在图2(b)中示出的MOSFET130中，设置在沟槽42底部的高介质膜47例如是由SiO2膜44和高介质膜45构成的双层膜。可以如前所述地在与n型柱状层3相连的一侧形成热氧化了沟槽42内面的SiO2膜44，在它之上形成高介质膜45。
如上所述，在本实施方式的功率半导体器件中，在从n型源极层6的表面贯通p型基极层5直至n型柱状层3的沟槽12、22、32、42的底部设置着高介质膜7、27、37、47。高介质膜可以是层叠了由相互不同材料构成的多个层的叠层膜，除上述例子以外，例如也可以使用层叠了种类不同的高介质的膜。
(第二实施方式)
关于第二实施方式的功率半导体器件，参照图3进行说明。
图3(a)是示出本实施方式的MOSFET200的截面的模式图。与上述第一实施方式的MOSFET100的不同点在于，在沟槽52侧壁的一部分中也形成有高介质膜57。
在MOSFET200中，在沟槽52侧壁的一部分中也形成高介质膜57，栅电极9隔着高介质膜57与n型柱状层3和p型基极层5的一部分对置。
当对栅电极9施加正的栅极电压时，在与p型基极层5相连的侧壁中形成电子的累积层即反转沟道。另外，在隔着高介质膜7与栅电极对置的沟槽52的侧壁的一部分和底面的与n型柱状层3相连的部分中也形成电子的累积沟道。该累积沟道与反转沟道连在一起形成并降低通态电阻。由于沟槽52底部的绝缘膜是高介质膜57，因此与使用介电常数较低的绝缘膜的情况相比，能够增多累积的电子的量。从而，通过设置高介质膜57，能够进一步降低通态电阻。
图3(b)是示出本实施方式的变形例的MOSFET210的截面的模式图。设置在沟槽62底部的高介质膜67是层叠了由相互不同材料构成的多个层的叠层膜，在这一点上与MOSFET200不同。
例如，高介质膜67可以做成包含对沟槽62的内面进行热氧化而形成的SiO2膜64、高介质膜65和SiO2膜66的三层膜。
MOSFET210的槽栅结构例如可以如下地形成。
首先，在沟槽62的内面上形成包含SiO2膜64的热氧化膜。接着，例如使用溅射法，在沟槽62内部形成高介质膜。之后，对高介质膜进行刻蚀，仅留在沟槽62底部上，作为高介质膜65。
然后，在高介质膜65之上例如使用CVD法形成SiO2膜66。另外，在沟槽62的侧壁上形成栅极绝缘膜8，接着，用导电性多晶硅填充沟槽62内部而形成栅电极9。栅极绝缘膜8可以包括在形成SiO2膜64和SiO2膜66时形成在沟槽62侧壁上的SiO2膜。
图4是示出本实施方式的另外的变形例的功率半导体器件的截面的模式图。
在图4(a)中示出的MOSFET220中，以覆盖沟槽72的底面和侧壁的一部分的方式形成高介质膜77，但在不与p型基极层5相连这一点上与MOSFET200不同。
即，栅电极9把高介质膜77夹在中间而与n型柱状层3对置，另一方面，隔着栅极绝缘膜8与n型源极层6、p型基极层5和n型柱状层3对置。
通过这样地仅在与n型柱状层3相连的部分上形成高介质膜77，而不形成在与p型基极层5相连的部分上，能够比MOSFET200减小Cgs。另一方面，由于在沟槽72的侧壁的底部形成高介质膜77，因此能够维持由形成在与n型柱状层3之间的界面上的累积沟道所产生的通态电阻的降低效果。即，能够在高速维持开关时的栅极驱动的状态下实现通态电阻的降低。
另外，也可以如图4(b)所示的MOSFET230那样地在沟槽82的底部设置的高介质膜87中使用层叠了由相互不同材料构成的多个层的叠层膜。与上述的MOSFET210相同，例如作为高介质膜87，可以使用包含由热氧化形成的SiO2膜84、高介质膜85和SiO2膜86的三层膜。
(第三实施方式)
关于第三实施方式的功率半导体器件，参照图5进行说明。
图5(a)是示出本实施方式的MOSFET240的截面的模式图。具有与上述第一实施方式的MOSFET100相同的槽栅结构。另一方面，沟槽12的底部位于n型杂质的浓度比n型柱状层3高的n型区域19中间，在这一点上与MOSFET100不同。
通过如前所述地在沟槽12的底部设置高介质膜7，能够增大Cgd。另外，通过使沟槽12底部的突出量UT成为p型基极层5厚度的10％以下，能够抑制沟槽12底部中的电场聚焦。
这样就在n型柱状层3与p型基极层5之间多出设置提高n型杂质浓度的n型区域19的富余空间。在n型区域19中，在相邻2个p型柱状层4之间设置有沟槽12，漏极电流的流路变窄。从而，通过提高n型区域19的杂质浓度，能够降低通态电阻。
可以通过在n型漏极层2之上形成SJ结构时增加n型杂质的掺杂量来形成n型区域19。此外，也可以向沟槽12的底部离子注入n型杂质。n型区域19的杂质浓度例如可以设为n型柱状层3的n型杂质的2～4倍的浓度。
n型区域19可以设置在第一实施方式和第二实施方式中示出的所有的MOSFET中。例如，图5(b)中示出的MOSFET250具有与第二实施方式中示出的MOSFET200相同的槽栅结构，而且进一步具有n型区域19。
(第四实施方式)
关于第四实施方式的功率半导体器件，参照图6进行说明。
图6是示出本实施方式的MOSFET300的器件部和终端部的截面的模式图。
在MOSFET300的器件部中，在沟槽12a的底部形成有高介质膜7，具有与第一实施方式中示出的MOSFET100相同结构的单位单元。
另一方面，在MOSFET300的终端部中，在位于器件部外周的p型柱状层4之上设置有p型护圈层91。另外，在p型护圈层91的表面和n型柱状层3b的表面上设置有场绝缘膜94。在场绝缘膜94之上设置有栅极引出电极93。
栅极引出电极93经由栅极配线与栅电极9电连接。在图6中示出的MOSFET300中，经由栅极配线92与位于器件部与终端部的边界上的沟槽12b之中所设置的栅电极9连接。此外，形成在器件部中的沟槽12a之中所设置的栅电极9和沟槽12b之中所设置的栅电极9，用未图示的部分电连接。
另外，在MOSFET300中，在栅极引出电极93下的场绝缘膜94中设置有作为第三绝缘膜的高介质膜95。由于栅极引出电极93和栅电极9电连接，因此，栅极引出电极93与漏电极之间的寄生电容也包含在Cgd中。从而，通过在栅极引出电极93下设置高介质膜95，也能够增加Cgd。这样就提高了由流经Cgd的变位电流控制的漏极电压的变化率(dV/dt)的控制性，能够实现开关噪声的降低。
在MOSFET300中，在终端部中设置了栅极引出电极93，但做成栅极引出电极设置在器件部中的结构，也能够在引出电极下设置高介质膜来增大Cgd。
设置在栅极引出电极93之下的高介质膜95可以设为与设置在沟槽12a和12b底部的高介质膜7相同的材料。此外，也可以同时设置高介质膜7和高介质膜95。
作为配线压焊区来设置的栅极引出电极的尺寸即使芯片尺寸改变也不大变化，寄生电容的变化也少。从而，当MOSFET300的芯片面积变小时，栅极引出电极93的寄生电容相对变大，设置高介质膜95而导致的Cgd的增加率变大。即，在栅极引出电极之下设置高介质膜的效果还是芯片尺寸小的功率半导体器件较大。
另外，在芯片尺寸小的功率半导体器件中，为了提高静电容量(ESD容量)而构成为增大输入电容Cgs。在该情况下，在栅极引出电极之下设置高介质膜也是有效的。
在图6中示出的MOSFET300中，为了增大Cgd，将高介质膜95形成在n型柱状层3b的表面上，但是，也可以为了增大Cgs而使高介质膜95在p型护圈层91或p型基极层5之上延伸。
此外，通过在栅极引出电极93下设置高介质膜95来产生大的寄生电容的方法，不限定于上述实施方式中记载的槽栅结构，在平面栅结构中也可实施。
以上，参照本发明的第一～第四实施方式说明了本发明，但本发明不限定于这些实施方式。例如，业内人员基于申请时的技术水平所能完成的设计变更和材料的变更等、与本发明技术思想相同的实施方式，也包含在本发明的技术范围中。
例如，MOS栅极部和超级结结构的平面图形形成为条纹形，还可以形成为格子形和锯齿形。
此外，作为半导体，除了硅(Si)以外，例如还可以使用碳化硅(SiC)和氮化镓(GaN)等的化合物半导体和金刚石等的宽带隙半导体。
另外，已经以具有超级结结构的MOSFET为例进行了说明，但如果本发明的结构是具有槽栅结构和超级结结构两者的器件，也可以适用在MOSFET与SBD的结合器件、IGBT等的器件中。

Claims (20)

1.一种功率半导体器件，其特征在于，具备：
第一导电类型的第一半导体层；
上述第一导电类型的第二半导体层和第二导电类型的第三半导体层，横向上周期性地设置在上述第一半导体层之上；
上述第二导电类型的第四半导体层，设置在上述第三半导体层之上；
上述第一导电类型的第五半导体层，选择性地设置在上述第四半导体层的表面上；
第一主电极，与上述第一半导体层连接；
第二主电极，与上述第四半导体层和上述第五半导体层连接；
第一绝缘膜，设置在从上述第五半导体层的表面直至上述第二半导体层的沟槽的侧壁上；
第二绝缘膜，设置在比上述第一绝缘膜靠近上述沟槽的底部侧，介电常数高于上述第一绝缘膜；以及
控制电极，隔着上述第一绝缘膜和上述第二绝缘膜填充在上述沟槽中。
2.根据权利要求1所述的功率半导体器件，其特征在于，
从上述第二半导体层与上述第四半导体层的边界向上述第二半导体层突出的上述沟槽的突出量是上述第四半导体层的层厚的10％以下。
3.根据权利要求1所述的功率半导体器件，其特征在于，
上述第二半导体层中掺杂的第一导电类型的杂质的量，与上述第三半导体层中掺杂的第二导电类型的杂质的量相同。
4.根据权利要求1所述的功率半导体器件，其特征在于，
上述第一绝缘膜包含氧化硅(SiO2)膜和氮化硅(SiN)膜的至少某一种。
5.根据权利要求4所述的功率半导体器件，其特征在于，
上述第一绝缘膜包含对上述沟槽的内面进行热氧化而设置的SiO2膜。
6.根据权利要求1所述的功率半导体器件，其特征在于，
上述第二绝缘膜包含氧化铝(AlOx)、氧化铪(HfOx)、氧化锆(ZrOx)和氧化钽(TaOx)中的至少一种。
7.根据权利要求1所述的功率半导体器件，其特征在于，
上述第二绝缘膜是层叠了由相互不同材料构成的多个层的叠层膜。
8.根据权利要求7所述的功率半导体器件，其特征在于，
上述第二绝缘膜包含：SiO2膜和SiN膜的某一种；以及包含氧化铝(AlOx)、氧化铪(HfOx)、氧化锆(ZrOx)和氧化钽(TaOx)中的至少一种的膜。
9.根据权利要求7所述的功率半导体器件，其特征在于，
上述第二绝缘膜层叠有：对上述沟槽的内面进行热氧化而设置的SiO2膜；以及包含氧化铝(AlOx)、氧化铪(HfOx)、氧化锆(ZrOx)和氧化钽(TaOx)中的至少一种的膜。
10.根据权利要求7所述的功率半导体器件，其特征在于，
上述第二绝缘膜在2个SiO2膜之间层叠有包含氧化铝(AlOx)、氧化铪(HfOx)、氧化锆(ZrOx)和氧化钽(TaOx)中的至少一种的膜。
11.根据权利要求10所述的功率半导体器件，其特征在于，
上述2个SiO2膜中的一个是对上述沟槽的内面进行热氧化而设置的SiO2膜。
12.根据权利要求7所述的功率半导体器件，其特征在于，
上述第二绝缘膜在2个SiN膜之间层叠有包含氧化铝(AlOx)、氧化铪(HfOx)、氧化锆(ZrOx)和氧化钽(TaOx)中的至少一种的膜。
13.根据权利要求1所述的功率半导体器件，其特征在于，
在上述沟槽的侧壁的一部分上也形成有上述第二绝缘膜。
14.根据权利要求13所述的功率半导体器件，其特征在于，
上述第二绝缘膜不与上述第四半导体层相连。
15.根据权利要求1所述的功率半导体器件，其特征在于，
在上述第二半导体层与上述第四半导体层之间还具备第一导电类型杂质的浓度高于上述第二半导体层的半导体区域。
16.根据权利要求15所述的功率半导体器件，其特征在于，
在上述沟槽的底部设置有上述半导体区域。
17.根据权利要求1所述的功率半导体器件，其特征在于，
上述控制电极具有引出电极，
在上述引出电极之下设置介电常数高于上述第一绝缘膜的第三绝缘膜。
18.根据权利要求17所述的功率半导体器件，其特征在于，
在上述引出电极与上述第二半导体层的表面之间设置上述第三绝缘膜。
19.根据权利要求17所述的功率半导体器件，其特征在于，
上述第三绝缘膜是包含氧化铝(AlOx)、氧化铪(HfOx)、氧化锆(ZrOx)和氧化钽(TaOx)中的至少一种的膜。
20.根据权利要求17所述的功率半导体器件，其特征在于，具备：
器件部，包括上述第四半导体层和上述第五半导体层；以及
终端部，沿着上述器件部的外周设置，
上述引出电极设置在上述终端部中。
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104779289A (zh) * 2014-01-10 2015-07-15 株式会社东芝 半导体装置
CN105070757A (zh) * 2015-08-18 2015-11-18 上海华虹宏力半导体制造有限公司 改善超级结器件的开关特性的结构
CN111933711A (zh) * 2020-08-18 2020-11-13 电子科技大学 一种集成sbd的超结mosfet
CN112582397A (zh) * 2019-09-27 2021-03-30 南亚科技股份有限公司 半导体装置及其制造方法

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011233701A (ja) * 2010-04-27 2011-11-17 Toshiba Corp 電力用半導体素子
JP5920970B2 (ja) * 2011-11-30 2016-05-24 ローム株式会社 半導体装置
US8829562B2 (en) * 2012-07-24 2014-09-09 Infineon Technologies Ag Semiconductor device including a dielectric structure in a trench
JP2016054181A (ja) * 2014-09-03 2016-04-14 トヨタ自動車株式会社 絶縁ゲート型スイッチング素子
JP6400548B2 (ja) 2015-09-14 2018-10-03 株式会社東芝 半導体装置
JP6860522B2 (ja) 2018-04-17 2021-04-14 株式会社東芝 半導体装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070145479A1 (en) * 2005-12-27 2007-06-28 Denso Corporation Semiconductor device having super junction structure
US20070181975A1 (en) * 2004-03-10 2007-08-09 Koninklijke Philips Electronics N.V. Trench-gate transistors and their manufacture
US20080258211A1 (en) * 2007-01-31 2008-10-23 Fuji Electric Holdings Co., Ltd. Semiconductor device and method for manufacturing the same

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2309336B (en) 1996-01-22 2001-05-23 Fuji Electric Co Ltd Semiconductor device
JP3938964B2 (ja) 1997-02-10 2007-06-27 三菱電機株式会社 高耐圧半導体装置およびその製造方法
JP4764987B2 (ja) * 2000-09-05 2011-09-07 富士電機株式会社 超接合半導体素子
JP4393144B2 (ja) 2003-09-09 2010-01-06 株式会社東芝 電力用半導体装置
US7368777B2 (en) * 2003-12-30 2008-05-06 Fairchild Semiconductor Corporation Accumulation device with charge balance structure and method of forming the same
DE102004007197B4 (de) * 2004-02-13 2012-11-08 Infineon Technologies Ag Hochsperrendes Halbleiterbauelement mit niedriger Durchlassspannung
JP5002148B2 (ja) 2005-11-24 2012-08-15 株式会社東芝 半導体装置
JP5132123B2 (ja) 2006-11-01 2013-01-30 株式会社東芝 電力用半導体素子
US8659074B2 (en) * 2007-01-09 2014-02-25 Maxpower Semiconductor, Inc. Semiconductor device
US8203181B2 (en) * 2008-09-30 2012-06-19 Infineon Technologies Austria Ag Trench MOSFET semiconductor device and manufacturing method therefor
US8022474B2 (en) * 2008-09-30 2011-09-20 Infineon Technologies Austria Ag Semiconductor device
JP2011233701A (ja) * 2010-04-27 2011-11-17 Toshiba Corp 電力用半導体素子
JP5639926B2 (ja) * 2011-02-28 2014-12-10 株式会社日立製作所 炭化珪素半導体装置及びその製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070181975A1 (en) * 2004-03-10 2007-08-09 Koninklijke Philips Electronics N.V. Trench-gate transistors and their manufacture
US20070145479A1 (en) * 2005-12-27 2007-06-28 Denso Corporation Semiconductor device having super junction structure
US20080258211A1 (en) * 2007-01-31 2008-10-23 Fuji Electric Holdings Co., Ltd. Semiconductor device and method for manufacturing the same

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104779289A (zh) * 2014-01-10 2015-07-15 株式会社东芝 半导体装置
CN105070757A (zh) * 2015-08-18 2015-11-18 上海华虹宏力半导体制造有限公司 改善超级结器件的开关特性的结构
CN112582397A (zh) * 2019-09-27 2021-03-30 南亚科技股份有限公司 半导体装置及其制造方法
CN112582397B (zh) * 2019-09-27 2024-03-19 南亚科技股份有限公司 半导体装置及其制造方法
CN111933711A (zh) * 2020-08-18 2020-11-13 电子科技大学 一种集成sbd的超结mosfet

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