CN102916049B - 包括结型场效应晶体管的半导体器件及其制造方法 - Google Patents

包括结型场效应晶体管的半导体器件及其制造方法 Download PDF

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CN102916049B
CN102916049B CN201210422691.5A CN201210422691A CN102916049B CN 102916049 B CN102916049 B CN 102916049B CN 201210422691 A CN201210422691 A CN 201210422691A CN 102916049 B CN102916049 B CN 102916049B
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tagma
epitaxial loayer
doping type
effect transistor
field effect
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CN102916049A (zh
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马荣耀
李铁生
张磊
傅达平
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Chengdu Monolithic Power Systems Co Ltd
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Chengdu Monolithic Power Systems Co Ltd
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    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
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    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
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Abstract

公开了一种包括结型场效应晶体管的半导体器件及其制造方法。该半导体器件包括结型场效应晶体管，所述结型场效应晶体管包括：半导体衬底，具有第一掺杂类型并作为结型场效应晶体管的漏极区；外延层，位于半导体衬底上，具有第一掺杂类型；体区，位于外延层中，具有第二掺杂类型，第二掺杂类型与第一掺杂类型是相反的掺杂类型；源极区，位于外延层中，具有第一掺杂类型；以及栅极区，位于体区中，具有第二掺杂类型，其中，所述结型场效应晶体管还包括屏蔽层，屏蔽层具有第二掺杂类型，位于外延层的内部，并且位于源极区和漏极区之间的导电路径中。由于采用屏蔽层，在结型场效应晶体管中产生新的夹断区，从而可以减小夹断电压。

Description

包括结型场效应晶体管的半导体器件及其制造方法
技术领域
本发明涉及半导体器件及其制造方法，更具体地涉及包括结型场效应晶体管的半导体器件及其制造方法。
背景技术
图1所示为现有的N沟道结型场效应晶体管(JFET)100的剖视图。该JFET 100包括N+型漏极区101(一般为衬底)、位于N+型漏极区101上的N-型外延层102、位于N-型外延层102中的P型体区103、位于N-型外延层102中以及P型体区103之间的N+型源极区104、以及位于P型体区103中的P+型栅极区105。该JFET100还包括层间介电层(ILDL)106，以及穿过ILDL106与N+型源极区104电连接的源极接触107和穿过ILDL106与P+型栅极区105电连接的栅极接触108。，P型体区103围绕N-型外延层102的一部分。N+型源极区104位于N-型外延层102的该部分中。并且，N-型外延层102的该部分从N+型源极区104延伸至N+型漏极区101，从而形成导电路径。在图1中示出的JFET 100为垂直器件。
在栅极接触108上施加偏置电压时，体区103产生夹断效应，从而控制导电路径中的电流。在图1中附图标记“A”表示体区103在N-型外延层102中产生的夹断区。为了获得增强的夹断效应，必须将夹断区A的尺寸设置为尽可能小，从而有利地获得减小的夹断电压。然而，夹断区A的尺寸减小导致沟道宽度的减小，从而不利地增加导通电阻Ron。并且，夹断区A的尺寸减小使得源极区104靠近栅极区105，从而不利地减小源漏击穿电压。夹断区A的尺寸减小还提高光刻工艺的分辨率要求，从而不利地增加了工艺复杂性。
因此，仍然希望在源极区104与栅极区105距离足够远的情形下获 得减小的夹断电压。
发明内容
为了解决前面描述的问题，本发明提出一种改进的包括JFET的半导体器件及其制造方法，其中JFET的源极区与栅极区可以保持足够的距离，同时可以减小JFET的夹断电压。
根据本发明的一方面，提供一种半导体器件，包括结型场效应晶体管，所述结型场效应晶体管包括：半导体衬底，具有第一掺杂类型并作为结型场效应晶体管的漏极区；外延层，位于半导体衬底上，具有第一掺杂类型；体区，位于外延层中，具有第二掺杂类型，第二掺杂类型与第一掺杂类型是相反的掺杂类型；源极区，位于外延层中，具有第一掺杂类型；以及栅极区，位于体区中，具有第二掺杂类型，其中，所述结型场效应晶体管还包括屏蔽层，屏蔽层具有第二掺杂类型，位于外延层的内部，并且位于源极区和漏极区之间的导电路径中。
优选地，该半导体器件还包括沟槽MOSFET，该沟槽MOSFET包括：所述半导体衬底，作为漏极区；所述外延层；所述体区；源极区，位于外延层中，具有第一掺杂类型；沟槽栅极，穿过所述体区进入所述外延层中；以及栅介质层，将沟槽栅极与所述体区和所述外延层隔开。
优选地，该半导体器件还包括平面MOSFET，该平面MOSFET包括：所述半导体衬底；所述外延层；所述体区；源极区和漏极区，位于所述体区中，具有第一掺杂类型；栅极导体，位于源极区和漏极区之间的体区上；以及栅介质层，位于栅极导体和体区之间，将栅极导体与所述体区隔开。
根据本发明的另一方面，提供一种制造半导体器件的方法，包括：在半导体衬底上形成外延层，半导体衬底具有第一掺杂类型，并且半导体衬底作为结型场效应晶体管的漏极区，外延层具有第一掺杂类型；在外延层中形成体区，体区具有第二掺杂类型，第二掺杂类型与第一掺杂类型是相反的掺杂类型；在外延层的内部形成屏蔽层，屏蔽层具有第二掺杂类型；在外延层中形成结型场效应晶体管的源极区，结型场效应晶体管的源极区具有第一掺杂类型；以及在体区中形成结型场效应晶体管 的栅极区，结型场效应晶体管的栅极区具有第二掺杂类型，其中，屏蔽层位于源极区和漏极区之间的导电路径中。
优选地，该方法还包括制造沟槽MOSFET，其中制造沟槽MOSFET的至少一部分步骤在与制造结型场效应晶体管的一部分步骤相同。
优选地，该方法还包括制造平面MOSFET，其中制造平面MOSFET的至少一部分步骤在与制造结型场效应晶体管的一部分步骤相同。
在根据本发明的半导体器件中，由于采用屏蔽层，在JFET中产生新的夹断区。即使在JFET的源极区与栅极区之间的足够距离的情形下也可以增强夹断效应，从而可以降低夹断电压。另一方面，该JFET可以通过保持源极区与栅极区之间的足够距离而获得高击穿电压。由于可以相应地增加沟道宽度，因此可以获得低导通电阻。因此，根据本发明的半导体器件不必在设计JFET时进行性能上的折衷。此外，制造JFET的至少一部分步骤可以与制造沟槽MOSFET或平面MOSFET的一部分步骤相同，从而可以减小将JFET与沟槽MOSFET或平面MOSFET集成在一个芯片上的复杂度，降低生产成本。
附图说明
为了更好地理解本发明，将根据以下附图对本发明进行详细描述：
图1是现有的结型场效应晶体管的剖视图；
图2是根据本发明一个实施例的结型场效应晶体管的剖视图。
图3是根据本发明一个实施例的结型场效应晶体管的剖视图。
图4是根据本发明一个实施例的包括结型场效应晶体管和沟槽MOSFET的半导体器件的剖视图。
图5是根据本发明一个实施例的包括结型场效应晶体管和平面MOSFET的半导体器件的剖视图。
图6是根据本发明一个实施例的制造结型场效应晶体管的方法的流程图。
具体实施方式
下面参照附图充分描述本发明的示范实施例。在各个附图中，相同 的元件采用类似的附图标记来表示。为了清楚起见，附图中的各个部分没有按比例绘制，并且简化了一些具体结构和功能的详细描述。此外，在一些实施例中已经详细描述过的类似的结构和功能，在其它实施例中不再赘述。尽管本发明的各项术语是结合具体的示范实施例来一一描述的，但这些术语适用于本领域的任何合理场合，不应理解为局限于这里阐述的示范实施方式。
图2是根据本发明一个实施例的结型场效应晶体管(JFET)200的剖视图。在图2中，采用与图1类似的附图标记表示相同的元件，其中附图标记是三位数字，第一位是“2”，第二位和第三位与图1中的相应元件的相应数字相同。
该JFET 200包括N+型漏极区201(一般为衬底)、位于N+型漏极区201上的N-型外延层202、位于N-型外延层202中的P型体区203、位于N-型外延层202中以及P型体区203之间的N+型源极区204、以及位于P型体区203中的P+型栅极区205。该JFET 200还包括层间介电层(ILDL)206，以及穿过ILDL206与N+型源极区204电连接的源极接触207和穿过ILDL206与P+型栅极区205电连接的栅极接触208。P型体区203围绕N-型外延层202的一部分。N+型源极区204位于N-型外延层202的该部分中。并且，N-型外延层202的该部分从N+型源极区204延伸至N+型漏极区201，从而形成导电路径。在图2中示出的JFET 200为垂直器件。
图2中示出的JFET 200与图1示出的JFET 100的不同之处在于JFET 200还包括位于N+型源极区204下方的N-型外延层202中的P型屏蔽层209。该P型屏蔽层209位于源极区和漏极区之间的导电路径中。
在栅极接触208上施加偏置电压时，体区203产生夹断效应，在N-型外延层202中产生夹断区A。屏蔽层209作为电场屏蔽层，至少部分地减小夹断区A中的电场。不仅如此，屏蔽层209还在外延层202中位于屏蔽层209和体区203之间的部分产生新的夹断区B。结果，体区203和屏蔽层209共同产生夹断效应。即使源极区204和栅极区205的距离较大，屏蔽层209的存在也可以使得夹断区的有效尺寸较小，从而增强夹断效应。
屏蔽层209例如是在外延层202中形成的高能注入区。屏蔽层209的深度由屏蔽层209与体区203之间的距离决定。屏蔽层209与体区203之间的最小距离应当足够小使得可以形成夹断区B。优选地，屏蔽层209的至少一部分位于体区203的底部之上。屏蔽层209的横向尺寸也由屏蔽层209与体区203之间的距离决定。屏蔽层209与体区203之间的最小距离应当足够大使得屏蔽层209与体区203不相互接触，否则将不利地阻断导电路径。优选地，屏蔽层209的横向尺寸与导电路径的顶部尺寸一致。如图2所示，体区203在外延区202中限定导电路径。由于体区203的掺杂分布，导电路径的顶部尺寸最小。屏蔽层209的横向截面的形状取决于制造工艺中使用的掩模。优选地，屏蔽层209的横向截面的形状与导电路径的顶部截面的形状一致，也即与体区203的顶部截面的形状互补。优选地，在有源区为方形的JFET 200中，屏蔽层209的横向截面的形状为方形，在有源区为圆形的JFET 200中，屏蔽层209的横向截面的形状为圆形。在屏蔽层209的横向截面的形状与有源区的形状一致的情形下，可以有利地控制屏蔽层209与体区203之间的最小距离。
在一个实施例中，JFET 200的N+型漏极区201由高掺杂浓度的半导体衬底形成。在一个实施例中，N-型外延层202是半导体衬底上的外延半导体层。半导体衬底或半导体层由半导体材料组成，半导体材料例如包括III-V族半导体，如GaAs、InP、GaN、SiC，以及IV族半导体，如Si、Ge。在优选的实施例中，半导体衬底或半导体层可采用例如锗化硅(二元化合物)，碳化硅(尤其是用于高压场合)、氮化锗等不同的化合物。
在一个实施例中，P型体区203是在N-型外延层202中形成的注入区，例如在N-型外延层202中注入P型掺杂元素(例如硼)而形成。在一个实施例中，通过离子轰击来注入掺杂元素。
在一个实施例中，N+型源极区204是在N-型外延层202中形成的注入区，例如在N-型外延层202中进一步注入N型掺杂元素(例如砷、磷或锑)而形成。
在一个实施例中，P+型栅极区205是在P型体区203中形成的注入区，例如在P型体区203中进一步注入P型掺杂元素(例如硼)而形成。
在一个实施例中，层间介电层206包括二氧化硅。可采用任何已知的方法来制造氧化层，例如热生长、淀积等。
在一个实施例中，源极接触207和栅极接触208包括钨。可采用任何已知的方法来制造金属接触，例如采用金属填充层间介电层206中的穿透孔。
在一个实施例中，P型体区203围绕N-型外延层202的一部分，形成封闭的环形，从而N-型外延层202的该部分形成源极区和漏极区之间的导电路径的至少一部分。
在一些实施例中，可采用如下描述中的结构尺寸，但这些结构尺寸并不意味着限制本发明的范围，而仅是作为示例。
层间介电层206的厚度与JFET 200的电压等级有关，可以根据不同的电压需求作相应的调整。在一个实施例中，层间介电层206的厚度选用能够实现JFET 200所需电压的最小厚度。随着所需电压的增大，层间介电层206的厚度也随之增加。在一个实施例中，层间介电层206为氧化层。
在一个实施例中，N+型源极区204的厚度大约为0.1μm～2μm。N+型源极区204的厚度不仅与JFET所需的击穿电压有关，而且与其构成材料有关。在一个实施例中，N+型源极区204的厚度大约是0.25μm。
图3是根据本发明一个实施例的结型场效应晶体管(JFET)300的剖视图。在图3中，采用与图2类似的附图标记表示相同的元件，其中附图标记是三位数字，第一位是“3”，第二位和第三位与图2中的相应元件的相应数字相同。对两个实施例中相同的元件将不再详述。
图3中示出的JFET 300与图2示出的JFET 200的不同之处在于JFET 300还包括在N-型外延层302中形成的沟槽。沟槽的内壁衬有例如HfO2的栅介质层310，并且在沟槽内填充例如掺杂多晶硅的栅极导体311。该JFET 300还包括穿过层间介电层(ILDL)306与栅极导体311电连接的另一个栅极接触312。栅极导体311也称为沟槽栅极。
在栅极接触308和另一个栅极接触312上施加相同或不同的偏置电压时，在体区303和栅极导体311之间产生夹断区A。屏蔽层309作为电场屏蔽层，至少部分地减小夹断区A中的电场。不仅如此，屏蔽层309 还在外延层302中位于屏蔽层309和体区303之间的部分产生新的夹断区B，以及在外延层302中位于屏蔽层309和栅极导体311之间的部分产生新的夹断区C。结果，体区303、栅极导体311和屏蔽层309共同产生夹断效应。
与图2所示的JFET 200类似，根据屏蔽区309与体区303、栅极导体311的最小距离确定屏蔽区309的深度和横向尺寸，使得既可以形成夹断区B、C，又不会阻断导电路径。
在一个实施例中，栅极导体311位于有源区的中间，P型体区303与栅极导体311同心地设置，围绕N-型外延层302的一部分，形成封闭的环形，从而N-型外延层302的该部分在P型体区303和栅极导体311之间形成源极区和漏极区之间的导电路径的至少一部分。
图4是根据本发明一个实施例的包括结型场效应晶体管(JFET)的半导体器件400的剖视图。在图4中，采用与图2类似的附图标记表示相同的元件，其中附图标记是三位数字，第一位是“4”，第二位和第三位与图2中的相应元件的相应数字相同。对两个实施例中相同的元件将不再详述。
该半导体器件400包括集成在同一个半导体芯片上的JFET 400a和沟槽MOSFET(金属氧化物半导体场效应晶体管)400b。JFET 400a和沟槽MOSFET 400b均为垂直型器件。优选地，JFET 400a和沟槽MOSFET400b之间由未施加偏置电压的沟槽栅极电隔离，从而可以省去形成附加的浅沟槽隔离结构的步骤。JFET 400a和沟槽MOSFET 400b共用N+型漏极区401(一般为衬底)、N-型外延层402和层间介电层(ILDL)406。
JFET 400a与图2中示出的JFET 200相同。沟槽MOSFET 400b则可以是任何常规的类型。在图4中示出的沟槽MOSFET 400b包括在N-型外延层402中形成的P型体区403b，在P型体区403b中形成的N+型源极区404b，以及在P型体区403b中形成的位于N+型源极区404b下方的P+掺杂区405b。N+型源极区404b与P+掺杂区405b未直接接触。源极接触408b穿过ILDL 406和N+型源极区404b并延伸到P+掺杂区405b，并且与N+型源极区404b和P+掺杂区405b电接触。
沟槽MOSFET 400b还包括穿过N+型源极区404b和P型体区403b 延伸到N-型外延层中的沟槽。沟槽的内壁衬有例如HfO2的栅介质层410，并且在沟槽内填充例如掺杂多晶硅的栅极导体411。栅极接触412穿过层间介电层(ILDL)406与栅极导体411电连接。栅极导体411也称为沟槽栅极。
在栅极接触412上施加偏置电压时，可以控制在源极区404b和漏极区401之间流经P型体区403b中的导电路径的电流。
在该实施例的半导体器件400中，JFET 400a的P型体区403a、P+型掺杂区405a、N+源极区404a和源极接触408a可以与沟槽MOSFET400b的P型体区403b、P+掺杂区405b、N+源极区404b和源极接触408b分别在相同的步骤中利用相同的掩模形成。沟槽MOSFET 400b的沟槽栅极可以与用于将JFET 400a和沟槽MOSFET 400b相互隔开的沟槽栅极在相同的步骤中利用相同的掩模形成。沟槽MOSFET 400b的沟槽栅极与用于隔离的沟槽栅极的区别仅在于在工作中前者施加有偏置电压，而后者通常浮置。
在图4中还示出了与JFET 400a相邻的终止结构。该终止结构包括至少一个用于隔离的沟槽栅极。然而，正如本领域的技术人员可以理解的那样，该终止结构不限于沟槽栅极的形式，还可以采用已知的结构，例如浅沟槽隔离。
图5是根据本发明一个实施例的包括结型场效应晶体管(JFET)的半导体器件500的剖视图。在图5中，采用与图2类似的附图标记表示相同的元件，其中附图标记是三位数字，第一位是“5”，第二位和第三位与图2中的相应元件的相应数字相同。对两个实施例中相同的元件将不再详述。
该半导体器件500包括集成在同一个半导体芯片上的JFET 500a和平面MOSFET 500b。JFET 500a为垂直型器件，平面MOSFET500b为平面型器件。JFET 500a和平面MOSFET 500b之间根据设计要求可以直接连接(如图5所示)。替代地，JFET 500a和平面MOSFET 500b之间可以由浅沟槽隔离隔开。在图5中示出JFET 500a的栅极和平面MOSFET500b的源极或漏极直接连接的情形。JFET 500a和平面MOSFET 500b共用半导体衬底501(即JFET的N+型漏极区)、N-型外延层502、P型 体区503、层间介电层(ILDL)506以及栅极接触508。
JFET 500a与图2中示出的JFET 200相同。平面MOSFET 500b则可以是任何常规的类型。应当注意，为简便起见，在图5中示出平面MOSFET 500b的一部分，包括源/漏极区中的一个和沟道区的一部分，以描述JFET 500a和平面MOSFET 500b彼此的关联。如图5所示，平面MOSFET 500b包括在P型体区503中形成的一个N+型源/漏极区504b。平面MOSFET 500b的N+型源/漏极区504b与JFET 500a的栅极区505邻近，并且JFET 500a的一个栅极接触提供电连接，从而直接将平面MOSFET 500b的一个N+型源/漏极区504b与JFET 500a的栅极区505直接连接。平面MOSFET 500b还包括在P体区503上形成的栅介质层513和栅极导体514，其中栅介质层513将栅极导体514与P体区503中的沟道区隔开。尽管在图5中未示出，平面MOSFET 500b还包括在P体区503中形成的另一个N+型源/漏极区504b。
在栅极导体514上施加偏置电压时，可以控制在一个N+型源/漏极区504b和另一个N+型源/漏极区504b之间流经P型体区503中的沟道区的电流。
在该实施例的半导体器件500中，JFET 500a的N+源极区504a可以与平面MOSFET 500b的一个N+型源/漏极区504b在相同的步骤中利用相同的掩模形成。
在图5中还示出了与JFET 500a相邻的终止结构。该终止结构可以采用已知的结构，例如浅沟槽隔离。
图6是根据本发明一个实施例的制造结型场效应晶体管(例如图2所示的结型场效应晶体管200)的方法的流程图。该制造方法包括步骤S01～S07。这里需要说明的是，该实施例仅仅是优选的，其中的步骤、工艺、参数可以根据实际需要改变。例如，根据本发明的其他实施例，可以采用更多或更少的步骤来制造本发明的结型场效应晶体管。
该实施例的方法开始于N+型半导体衬底，例如掺杂为N+型的单晶硅衬底。该N+型半导体衬底将形成JFET 200的N+型漏极区201。通过已知的沉积工艺，例如脉冲激光沉积(PLD)、分子束外延(MBE)、化学气相沉积(CVD)等，在N+型半导体衬底上形成N-型外延层202(步 骤S01)。该N-型外延层202可以是原位掺杂的，也可以是在形成外延层之后采用附加的步骤掺杂的。
然后，通过其中包含曝光和显影的光刻工艺，在N-型外延层202上形成含有图案的第一光抗蚀剂掩模。采用该第一光抗蚀剂掩模作为遮挡掩模，在N-型外延层202中注入P型掺杂元素(例如硼)，从而形成P型体区203(步骤S02)。例如，第一光抗蚀剂掩模遮挡有源区的中间部分，从而P型体区203形成围绕N-型外延层202的相应部分的环形。正如本领域的技术人员已知的那样，可以通过控制离子注入的参数，控制注入区的深度、分布和掺杂浓度。在该实施例中，P型体区203从N-型外延层202表面向下延伸一定深度，但未到达N+型漏极区201。通过灰化或溶解去除第一光抗蚀剂掩模。
然后，通过上述的光刻工艺，在N-型外延层202上形成含有图案的第二光抗蚀剂掩模。在优选的实施例中，第二光抗蚀剂掩模与第一光抗蚀剂掩模的图案互补。例如，第二光抗蚀剂掩模遮挡先前形成的P型体区203，并暴露有源区的中间部分。采用该第二光抗蚀剂掩模作为遮挡掩模，在N-型外延层202中注入P型掺杂元素(例如硼)，从而形成P型屏蔽层209(步骤S03)。通过控制离子注入的参数，在N-型外延层202的一定深度处形成P型屏蔽层209。然而，P型屏蔽层209未到达N+型漏极区201。通过灰化或溶解去除第二光抗蚀剂掩模。
然后，按照本领域已知的方法(例如上述使用掩模的注入方法)，在N-型外延层202中形成从表面向下延伸一定深度的N+型源极区204(步骤S04)。N+型源极区204位于P型屏蔽层209的上方。
然后，按照本领域已知的方法(例如上述使用掩模的注入方法)，在P型体区203中形成从表面向下延伸一定深度的P+型栅极区205(步骤S05)。
然后，通过上述的沉积工艺，在半导体结构的表面上形成覆盖的层间介电层(ILDL)206(步骤S06)。在一个实施例中，层间介电层206是二氧化硅或者其它衬底材料的氧化物。层间介电层206可能被淀积太多，从而部分淀积于外延层的上表面，因此可以进一步例如通化学机械研磨去除外延层上表面的层间介电层206。
然后，对层间介电层206进行图案化，形成穿过层间介电层分别到达N+型源极区204和P+型栅极区205的穿透孔。该图案化可以包括以下步骤：通过上述的光刻工艺，在层间介电层206上形成含有图案的光抗蚀剂掩模；通过干法蚀刻，如离子铣蚀刻、等离子蚀刻、反应离子蚀刻、激光烧蚀，或者通过其中使用蚀刻剂溶液的湿法蚀刻，去除层间介电层206的暴露部分，从而形成穿透孔。
进一步地，沉积金属材料(例如钨)以填充穿透孔，再利用金属剥离技术即可获得源极接触207和栅极接触208(步骤S07)。如果有必要的话，可通过化学机械平面化(CMP)或其他方法平整半导体结构的表面。
上述实施例均涉及N沟道的JFET，由于P沟道JFET的各个掺杂区域的类型与N沟道的JFET相反，因此本发明的实施例仅仅需要稍作改变就可以应用于P沟道JFET。
上述本发明的说明书和实施仅仅以示例性的方式对本发明进行了说明，这些实施例不是完全详尽的，并不用于限定本发明的范围。对于公开的实施例进行变化和修改都是可能的，其他可行的选择性实施例和对实施例中元件的等同变化可以被本技术领域的普通技术人员所了解。本发明所公开的实施例的其他变化和修改并不超出本发明的精神和保护范围。因此，本发明旨在包括所有落入本发明和所述权利要求范围及主旨内的替代例、改进例和变化例等。

Claims (10)

1.一种半导体器件，包括结型场效应晶体管，所述结型场效应晶体管包括：
半导体衬底，具有第一掺杂类型并作为结型场效应晶体管的漏极区；
外延层，位于半导体衬底上，具有第一掺杂类型；
体区，位于外延层中，具有第二掺杂类型，第二掺杂类型与第一掺杂类型是相反的掺杂类型；
源极区，位于外延层中，具有第一掺杂类型；以及
栅极区，位于体区中，具有第二掺杂类型，
其中，所述结型场效应晶体管还包括屏蔽层，屏蔽层具有第二掺杂类型，位于外延层的内部，并且位于源极区和漏极区之间的导电路径中，所述屏蔽层的横向截面的形状与体区的顶部截面的形状互补。
2.根据权利要求1所述的半导体器件，其中外延层的位于体区和屏蔽层之间的一部分为夹断区。
3.根据权利要求1所述的半导体器件，其中体区是围绕外延层的一部分的环形，并且源极区位于该部分的外延层中。
4.根据权利要求1所述的半导体器件，其中屏蔽层的横向截面的形状与有源区的形状一致。
5.根据权利要求1所述的半导体器件，其中结型场效应晶体管还包括沟槽栅极和栅介质层，该沟槽栅极位于外延层中，并且由栅介质层与外延层隔开。
6.根据权利要求5所述的半导体器件，其中外延层的位于沟槽栅极和屏蔽层之间的一部分为夹断区。
7.根据权利要求1至6中任一项所述的半导体器件，还包括沟槽MOSFET，该沟槽MOSFET包括：
所述半导体衬底，作为漏极区；
所述外延层；
所述体区；
源极区，位于外延层中，具有第一掺杂类型；
沟槽栅极，穿过所述体区进入所述外延层中；以及
栅介质层，将沟槽栅极与所述体区和所述外延层隔开。
8.根据权利要求1至6中任一项所述的半导体器件，还包括平面MOSFET，该平面MOSFET包括：
所述半导体衬底；
所述外延层；
所述体区；
源极区和漏极区，位于所述体区中，具有第一掺杂类型；
栅极导体，位于源极区和漏极区之间的体区上；以及
栅介质层，位于栅极导体和体区之间，将栅极导体与所述体区隔开。
9.一种制造半导体器件的方法，包括：
在半导体衬底上形成外延层，半导体衬底具有第一掺杂类型，并且半导体衬底作为结型场效应晶体管的漏极区，外延层具有第一掺杂类型；
在外延层中形成体区，体区具有第二掺杂类型，第二掺杂类型与第一掺杂类型是相反的掺杂类型；
在外延层的内部形成屏蔽层，屏蔽层具有第二掺杂类型；
在外延层中形成结型场效应晶体管的源极区，结型场效应晶体管的源极区具有第一掺杂类型；以及
在体区中形成结型场效应晶体管的栅极区，结型场效应晶体管的栅极区具有第二掺杂类型，
其中，屏蔽层位于源极区和漏极区之间的导电路径中，所述屏蔽层的横向截面的形状与体区的顶部截面的形状互补。
10.根据权利要求9所述的方法，在形成结型场效应晶体管的栅极区之后，还包括：
在外延层中形成沟槽；
在沟槽内壁形成栅介质层；以及
采用栅极导体填充沟槽以形成结型场效应晶体管的沟槽栅极。
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