CN111081759B - 一种增强型碳化硅mosfet器件及其制造方法 - Google Patents

一种增强型碳化硅mosfet器件及其制造方法 Download PDF

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CN111081759B
CN111081759B CN201911258411.XA CN201911258411A CN111081759B CN 111081759 B CN111081759 B CN 111081759B CN 201911258411 A CN201911258411 A CN 201911258411A CN 111081759 B CN111081759 B CN 111081759B
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吴苏州
李晓云
杨高洁
叶怀宇
张国旗
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Southern University of Science and Technology
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Shenzhen Third Generation Semiconductor Research Institute
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Abstract

本发明公开了一种增强型碳化硅MOSFET器件，自下而上依次为：背面金属，N+型重掺杂SiC衬底，N‑外延层，绝缘介质层以及正面金属。本发明将肖特基二极管集成到MOSFET器件当中通过灵活增减肖特基势垒金属层的面积来调整和适配MOSFET及肖特基二极管的电流和规格，从而起到增加MOSFET开关速度，降低开关损耗等作用，可以大幅提升器件性能和可靠性，并降低器件应用成本。采用沟槽型SiC MOSFET设计，将导电沟道从传统的水平方向变更为垂直方向，从而消除了传统MOSFET的原胞之间的JFET效应，提升器件的电流能力。沟槽底部的栅底P区可以保护减弱沟槽底部电场，对槽底栅氧起到一定的静电屏蔽的作用，提升器件的可靠性。同时对器件耐压也有一定的帮助。

Description

一种增强型碳化硅MOSFET器件及其制造方法
技术领域
本发明属于半导体芯片制造工艺技术领域,具体涉及一种增强型碳化硅MOSFET器件及其制造方法。
背景技术
第三代半导体材料碳化硅(SiC)具有不同于传统硅半导体材料的诸多特点，其能带间隙为硅的2.8倍,达到3.09电子伏特；其绝缘击穿场强为硅的5.3倍,高达3.2MV/cm，其导热率是硅的3.3倍,为49w/cm·K。从而使其在高温、高频、大功率、抗辐射应用场合下成为十分理想的半导体材料。由于碳化硅功率器件可显著降低电子设备的能耗，故碳化硅功率器件在新能源领域内得到了广泛的应用。
金属氧化物半导体场效应晶体管(Metal-Oxide-Semiconductor Field-EffectTransistor，MOSFET)是下一代高效电力电子器件技术的核心器件。SiC MOSFET相比于Si-MOSFET导通电阻更小、开关电压更高、应用频率更高、温度性能更好，特别适用于功率开关应用。SiC MOSFET经过领域内多年的研究，已经有一些现有技术能够制备出SiC MOSFET器件。在很多的实际应用场景中存在着SiC MOSFET器件的开关速度较慢以及开关损耗过大的问题，另外，器件的电流能力也不够可靠。因此，现有技术中提出一种解决方案，即在SiCMOSFET器件中反并联一个二极管一起工作。这样可以提升开关器件的开关速度，降低开关损耗，提升器件的电流能力及可靠性。
然而，现有技术中存在以下问题：
1.现有技术中往往将源极与p阱进行了电连接短路，这种器件设计方式实际上等同于并联了一个源极及沟道之间的反偏二极管。由于SiC材料禁带宽度高，反并联的PN二极管的开启电压非常高，相应的损耗也大。
2.现有技术中反并联的PN二极管的降低器件电流驱动能力同时也会增大损耗。
因此，目前需要一种解决方案能够使得器件的开关速度加快，开关损耗降低，提升器件电流驱动能力。提升器件整体可靠性。
发明内容
针对现有技术中所存在的问题，本发明公开了一种增强型碳化硅MOSFET及其制造方法。该增强型碳化硅MOSFET器件采用沟槽型结构，相比较传统的平面型结构，其导电沟道从水平方向变为垂直沟道，原胞与原胞之间的寄生JFET电阻变更肖特基器件，对碳化硅MOSFET器件起到增加开关速度，降低开关损耗等正面作用。并且因为结构的差异，传统结构中的寄生JFET电阻不再存在，从而可以起到降低MOSFET导通电阻的作用，从而提升MOSFET的电流能力。
根据本发明的一个发明一种增强型碳化硅MOSFET器件，其特征在于，自下而上依次为：背面金属，所述背面金属由金属Ti、金属Ni以及金属Ag组合形成；N+型重掺杂SiC衬底；N-外延层，所述N-外延层上表面包括在水平方向上平行间隔排列的若干个P型体区，所述P型体区在所述N-外延层上表面向下形成，所述P型体区包括第一离子，所述若干个P型体区之间通过肖特基势垒金属层相连接；所述至少三个P型体区上表面的中央区域包括N+源极，所述N+源极在P型体区上表面中央区域向下形成，所述N+源极包括第二离子；所述N+源极的中央区域下方设有槽，所述槽的深度深于所述P型体区但不予N+型重掺杂SiC衬底接触；所述槽包括栅底P区，所述栅底P区设置在所述槽底部，所述栅底P区包括第三离子；所述槽还包括多晶硅栅极，所述多晶硅栅极充满整个槽；所述N-外延层和所述槽还包括栅氧化层，所述栅氧化层生长在所述槽内壁；所述P型体区上表面所述N+源极外侧还包括P型体区接触层，所述P型体区接触层在P型体区上表面向下设置形成，所述P型体区接触层包括第四离子；所述P型体区还包括P+埋层，所述P+埋层设置在所述P型体区的中央位置并在所述槽外侧，所述P+埋层包括第五离子；所述N+源极、所述P型体区接触层和所述肖特基势垒金属层上方设置有欧姆接触金属层；绝缘介质层，所述绝缘介质层是由SiO2组成；所述绝缘介质层设置在所述多晶硅栅极上方和所述P型体区接触层上方；正面金属，所述正面金属由Al组成，厚度为1-5μm。
优选地，所述碳化硅衬底所用碳化硅单晶体材料可以是2H-SiC单晶体、4H-SiC单晶体的其中一种，所述N+型重掺杂SiC衬底的掺杂浓度为3×1019-3×1020个离子/CM3。
优选地，所述N-外延层的掺杂浓度在1×1015-1×1016个离子/CM3之间，厚度为10-30μm，掺杂杂质为氮元素。
优选地，所述P型体区的深度为1-3μm，所述第一离子为硼离子，所述N+源极的深度为0.2-0.8μm，所述第二离子为磷离子。
优选地，所述第三离子、第四离子、第五离子为硼离子。
优选地，所述多晶硅的掺杂浓度大于1×1020个离子/CM3。
优选地，所述栅氧化层的厚度为0.04-0.1μm。
优选地，所述绝缘介质层的厚度为
Figure BDA0002310926030000031
所述肖特基势垒金属层为TiMo或TiW，所述肖特基势垒金属层的厚度为
Figure BDA0002310926030000032
所述欧姆接触金属层的厚度为
Figure BDA0002310926030000033
根据本发明的一个方面，一种增强型碳化硅MOSFET器件的制造方法，包括：步骤1：选用N+型重掺杂SiC衬底，在其上表面生长N-外延层；步骤2：在所述N-外延层上表面通过光刻和离子注入方式向下注入第一离子形成水平方向上平行间隔排列的至少三个P型体区，在所述至少三个P型体区上表面的中央区域通过离子注入方式向下注入第二离子形成N+源极；步骤3：在所述N+源极的中央区域通过槽光刻和槽刻蚀的方式向下刻蚀形成槽，所述槽的深度为所述P型体区的深度的1.2-1.5倍；步骤4：在所述槽的底部通过离子注入方式向下注入第三离子形成栅底P区；步骤5：通过5-10次快速热氧化方式在所述N-外延层上表面以及槽内壁生长第一栅氧化层，然后通过湿法腐蚀方式剥除第一栅氧化层，再通过炉管热氧氧化方式在所述N-外延层上表面以及槽内壁第二栅氧化层；步骤6：在所述N-外延层上表面以及槽内淀积多晶硅，通过CMP工艺对N-外延层上表面的多晶硅进行刻蚀；步骤7：在所述第二栅氧化层下方所述N-外延层上表面注入第四离子形成P型体区接触层；步骤8：在所述第二栅氧化层上表面生长绝缘介质层，所述绝缘介质层由SiO2组成；步骤9：通过光刻、刻蚀方式，刻蚀所述绝缘介质层形成至少六个通道，所述通道通向所述P型体区上表面和所述N+源极上表面，所述至少六个通道所形成的区域为第一区域；步骤10：通过离子注入方式在所述通道通向的所述P型体区上表面注入第五离子形成P+埋层，所述第五离子的注入深度为所述P型体区的深度的0.4-0.6倍；步骤11：通过干法刻蚀方式将P型体区之间的区域上方的所述P型体区接触层、第二栅氧化层和绝缘介质层刻穿形成第二区域，在所述第二区域上淀积势垒金属形成肖特基势垒金属层，所述淀积结束后在N2气氛下进行高温退火；步骤12：在所述第一区域与所述第二区域上淀积金属钛形成欧姆接触金属层；步骤13：在所述欧姆接触金属层与所述绝缘介质层上方生长Al，形成正面金属。
优选地，所述第一离子为硼离子，所述第一离子的注入次数为多次，单次注入剂量为2×1013-1×1014个离子/CM2，累计注入剂量为1×1014-5×1014个离子/CM2，注入能量为50Kev-1.5Mev，注入深度为1μm-2.5μm。
优选地，所述第二离子为磷离子，所述第二离子的注入剂量在3×1015-2×1016个离子/CM2之间，注入能量为150Kev-500Kev，注入深度为0.3μm-0.5μm。
优选地，对所述P+源极和所述P型体区进行高温推进，所述高温推进的温度为1700-1900℃，所述高温推进的时间为60min-300min。
优选地，所述槽的深度为1-4μm，宽度为0.4-1μm，在所述槽光刻和槽刻蚀后需对所述槽底部进行圆滑处理。
优选地，所述第三离子为硼离子，所述注入剂量为1×1013-1×1014个离子/CM2，注入能量为30-80Kev。
优选地，所述快速热氧化方式时间为30S-2min，单次快速热氧化的厚度小于
Figure BDA0002310926030000051
累积快速热氧化厚度大于
Figure BDA0002310926030000052
优选地，所述炉管热氧氧化方式采用CL基气体，所述炉管热氧氧化方式所形成的所述第二氧化层的厚度为0.04-0.1μm。
优选地，所述多晶硅的杂质浓度为1×1020个离子/CM3以上，所述多晶硅的厚度为
Figure BDA0002310926030000053
优选地，所述第四离子的注入能量为50-150Kev，注入剂量为1×1013-5×1013个离子/CM2。
优选地，所述绝缘介质层的厚度为
Figure BDA0002310926030000054
优选地，所述第五离子的注入能量为300-800Kev，注入剂量为2×1013-2×1014个离子/CM2。
优选地，在所述欧姆接触金属层积淀完成后进行高温退火，退火温度为900-1100℃。
有益效果：
本发明与现有技术相比，主要的优点有：
(1)通过独特的设计，将肖特基二极管集成到MOSFET器件当中。并且可以通过灵活增减肖特基势垒金属层的面积来调整和适配MOSFET及肖特基二极管的电流和规格。从而起到增加MOSFET开关速度，降低开关损耗等作用，可以大幅提升器件性能和可靠性，并降低器件应用成本。
(2)采用沟槽型SiC MOSFET设计，将导电沟道从传统的水平方向变更为垂直方向，从而消除了传统MOSFET的原胞之间的JFET效应，提升器件的电流能力。传统MOS的JFET区域巧妙转化为肖特基区域，对器件起到保护及性能提升的作用。
(3)通过Lift-off工艺分开制作欧姆接触和肖特基接触，在不额外增加光刻版的前提下可以分别调试两种接触(欧姆接触和肖特基接触)的最佳特性。
(4)沟槽底部的栅底P区可以保护减弱沟槽底部电场，对槽底栅氧起到一定的静电屏蔽的作用，提升器件的可靠性。同时对器件耐压也有一定的帮助。
(5)肖特基势垒金属层采用化学性主导的ICP等离子耦合刻蚀，可以减少界面损伤。并且干法刻蚀可以通过刻蚀去除表面SiO2材料、栅氧化层以及P型体区接触层，从而去除因为氧化步骤和离子注入步骤带来的界面态，最终提升肖特基器件的性能。
(6)N+源极及P型体区接触孔下方的P型杂质注入可以降低Pbase电阻(P基电阻)，可以有效提升器件的抗浪涌能力。此步注入也无需增加额外的光罩。
附图说明
图1为本发明实施例中增强型碳化硅MOSFET器件的结构示意图；
图2为本发明实施例中增强型碳化硅MOSFET器件的原理示意图；
图3为本发明实施例中包括N+型重掺杂SiC衬底和N-外延层的器件结构示意图；
图4为本发明实施例中包括P型体区的器件结构示意图；
图5为本发明实施例中包括N+源极所形成的器件结构示意图；
图6为本发明实施例中包括槽的器件结构示意图；
图7为本发明实施例中包括栅底P区的器件结构示意图；
图8为本发明实施例中包括栅氧化层的器件结构示意图；
图9为本发明实施例中包括多晶硅栅极的器件结构示意图；
图10为本发明实施例中刻蚀掉表面多晶硅的器件结构示意图；
图11为本发明实施例中包括P型体区接触层的器件结构示意图；
图12为本发明实施例中包括绝缘介质层的器件结构示意图；
图13为本发明实施例中包括通道的器件结构示意图；
图14为本发明实施例中包括P+埋层的器件结构示意图；
图15为本发明实施例中经过干法刻蚀方式刻蚀后的器件结构示意图；
图16为本发明实施例中包括肖特基势垒金属层的器件结构示意图；
图17为本发明实施例中包括欧姆接触金属层和正面金属的器件结构示意图。
背面金属1，N+型重掺杂SiC衬底2，N-外延层3，P型体区4，N+源极5，槽6，栅氧化层7，多晶硅栅极8，P型体区接触层9，P+埋层10，绝缘介质层11，肖特基势垒金属层12，欧姆接触金属层13，正面金属14，栅底P区15。
具体实施方式
现在将参照若干示例性实施例来论述本发明的内容。应当理解，论述了这些实施例仅是为了使得本领域普通技术人员能够更好地理解且因此实现本发明的内容，而不是暗示对本发明的范围的任何限制。
如本文中所使用的，术语“包括”及其变体要被解读为意味着“包括但不限于”的开放式术语。术语“基于”要被解读为“至少部分地基于”。术语“一个实施例”和“一种实施例”要被解读为“至少一个实施例”。术语“另一个实施例”要被解读为“至少一个其他实施例”。
本发明针对现有技术中在源极与沟道之间并联反偏二极管会提高器件的开启电压并且降低器件电流驱动能力，提供了一种增强型碳化硅MOSFET器件及制造方法。该器件为沟槽型MOSFET器件，如图2所示，本发明同时在该器件中内置了并联了SiC肖特基器件，从而使得器件的开关速度加快，开关损耗降低，提升器件电流驱动能力，提升器件整体可靠性。一种增强型碳化硅MOSFET器件，自下而上依次包括：
背面金属1，该金属由金属Ti、金属Ni以及金属Ag组合形成，在SiC衬底背面淀积金属之前，需要对SiC衬底背面进行研磨减薄；在背面金属1淀积之后需要对器件整体进行退火处理。
如图3所示，N+型重掺杂SiC衬底2，该SiC衬底可以选用2H SiC衬底或者4H SiC衬底，N+型重掺杂衬底的掺杂浓度约为3×1019-3×1020个离子/CM3。
N-外延层3，该外延层的掺杂浓度在1×1015-1×1016个离子/CM3之间，厚度为10-30μm，掺杂杂质为氮元素。如图4所示，N-外延层3上表面包括在水平方向上平行间隔排列的多个P型体区，P型体区的数量没有限制，可根据器件的尺寸大小进行排布。P型体区4通过光刻和离子注入方式在N-外延层3上表面向下注入第一离子形成，所述第一离子优选为硼离子，P型体区4的深度为1-3μm。
如图5所示，至少三个P型体区4上表面的中央区域包括N+源极5，该N+源极5通过光刻、离子注入的方式在P型体区4上表面中央区域向下刻蚀并注入第二离子形成，第二离子优选为磷离子，N+源极5的深度为0.2-0.8μm。
如图6所示，N+源极5的中央区域包括槽6，该槽6通过槽光刻和槽刻蚀的方式在N+源极5上表面中央区域向下刻蚀形成，槽6的深度为所述P型体区的1.2-1.5倍，深度在1-4μm之间，宽度在0.4-1μm之间。
如图7所示，槽6包括栅底P区15，栅底P区15在所述槽6底部通过离子注入方式向下注入第三离子形成，该第三离子优选为硼离子；槽6还包括多晶硅栅极8，多晶硅栅极8通过注入方式充满整个槽，多晶硅的掺杂浓度大于1×1020个离子/CM3；如图8所示，所述槽6和N-外延层还包括栅氧化层7，栅氧化层7通过炉管热氧氧化方式生长在所述N-外延层3上表面以及所述槽6内壁，栅氧化层7的厚度为0.04-0.1μm。
如图11所示，N-外延层3上表面还包括P型体区接触层9，P型体区接触层9通过离子注入方式在所述栅氧化层7下方注入第四离子形成，所述第四离子优选为硼离子；
如图14所示，P型体区4还包括P+埋层10，P+埋层10在P型体区4的上表面通过离子注入的方式向下注入第五离子形成，该第五离子优选为硼离子，所述P+埋层10的注入深度为P型体区4深度的0.4-0.6倍；
如图12所示，绝缘介质层11，绝缘介质层11是由SiO2所组成的；绝缘介质层11包括肖特基势垒金属层12以及欧姆接触金属层13；如图16所示，肖特基势垒金属层12通过光刻和刻蚀的方式淀积于N-外延层3上表面上方并与N-外延层3接触，肖特基势垒金属层12设置于P型体区4之间；如图17所示，欧姆接触金属层13布置在绝缘介质层11中无SiO2处；绝缘介质层11的厚度为
Figure BDA0002310926030000091
肖特基势垒金属层12为TiMo或TiW，肖特基势垒金属层12的厚度为
Figure BDA0002310926030000092
欧姆接触金属层13为Ti的厚度为
Figure BDA0002310926030000093
如图17所示，正面金属14，正面金属14由Al组成，厚度为1-5μm。
本发明中所公开的一种增强型碳化硅MOSFET器件的制备方法，包括：
步骤1：选用N+型重掺杂SiC衬底2，在其上表面生长N-外延层3；N+型重掺杂SiC衬底2可以选用2H SiC衬底或者4H SiC衬底。N+型重掺杂SiC衬底2的掺杂浓度约为3×1019-3×1020个离子/CM3，N-外延层3的掺杂浓度在1×1015-1×1016个离子/CM3之间，厚度为10-30μm，掺杂杂质为氮元素。根据掺杂浓度及N-外延层3的厚度，可以实现1000-3000V左右的耐压。
步骤2：在N-外延层3上表面通过光刻和离子注入方式向下注入第一离子，该第一离子优选为硼离子，形成水平方向上平行间隔排列的至少三个P型体区4，注入方式为多次注入，每次的注入深度不同，从而形成垂直方向上各处的杂质均匀分布。优选地，注入次数为3-5次。单次注入剂量在2×1013-1×1014个离子/cm2之间。累计注入剂量在1×1014-5×1014个离子/cm2之间。注入能量为50Kev-1.5Mev之间，各级能量梯度一致。注入深度从表面到底部在1um-2.5um之间。在P型体区4上表面的中央区域通过离子注入方式向下注入第二离子形成N+源极5，该第二离子为磷离子，第二离子优选注入剂量在3×1015-2×1016个离子/CM2之间。注入结深在0.3μm-0.5μm之间，注入能量在150-500kev之间。接着对N+源极5及P型体区4进行高温推进，推进温度在1700-1900℃之间，推进时间在60min-300min之间。推进完成后P型体区结深在1-3μm，N型源区在0.2-0.8μm之间。
步骤3：在N-外延层3上表面除N+源极5中央区域外的其他区域涂抹光刻胶，在中央区域通过槽光刻和槽刻蚀的方式向下刻蚀形成槽6，槽6的深度为P型体区4的深度的1.2-1.5倍，刻蚀气体优选为F基气体，如CF4，C2F6，CHF3等。刻蚀完成后对槽6底部进行圆滑处理，从而可以使得槽6底部更平滑，可以削弱槽6底部电场，减少底部的SiC与氧化物表面态。
步骤4：在槽6的底部通过离子注入方式向下注入第三离子形成栅底P区，第三离子优选为硼离子；注入剂量为1×1013-1×1014个离子/CM2，注入能量为30-80Kev。注入完成后，去除光刻胶。步骤4中注入的第三离子在器件反偏时候可以参与耗尽，起到削弱栅氧底部电场的作用，从而可以提升器件的耐压及可靠性。
步骤5：如图8所示，通过多次快速热氧化方式在N-外延层4上表面以及槽6内壁生长第一栅氧化层。该多次快速热氧化方式优选为5-10次，次数过多会增加器件的制造成本。然后通过湿法腐蚀方式剥除第一栅氧化层，再通过炉管热氧氧化方式在所述N-外延层上表面以及槽内壁第二栅氧化层7；快速热氧化方式的时间通常在30s-2min，单次热氧化的厚度在
Figure BDA0002310926030000111
以内。累计热氧化厚度在
Figure BDA0002310926030000112
以上。最终得以将槽6内壁变的更加光滑，界面态更少。接着采用炉管热氧氧化的方法生长栅氧化层7，为进一步提升栅氧质量，可以通入CL基气体进行氧化。最终氧化层厚度在0.04-0.1μm之间。在氧化过程中，底部的第三离子被激活。
步骤6：如图9所示，在N-外延层3上表面以及槽内淀积多晶硅以形成多晶硅栅极7，多晶硅的杂质浓度在1×1020个离子/CM3以上，多晶硅的厚度在
Figure BDA0002310926030000113
之间，如图10所示，通过CMP工艺对N-外延层上表面的多晶硅进行刻蚀；
步骤7：如图11所示，在第二栅氧化层7下方所述N-外延层3上表面注入第四离子形成P型体区接触层9，该第四离子优选为硼离子，注入能量以恰好穿透栅氧薄膜为准，优化能量为50-150Kev左右；注入剂量在1×1013-5×1013个离子/CM2之间。第四离子可以让P型体区4表面浓度更浓，在后续的工艺过程中更容易形成欧姆接触。而在N+源极5及多晶硅栅极8的N型杂质浓度远高于P型杂质浓度，所以依然为N型。
步骤8：如图12所示，在栅氧化层7上表面生长绝缘介质层10，绝缘介质层10由SiO2组成；生长方式采用LPCVD(低压化学气相淀积)，介质层的厚度在
Figure BDA0002310926030000114
之间。
步骤9：如图13所示，通过光刻、刻蚀方式，刻蚀绝缘介质层10形成至少六个通道，所述通道通向所述P型体区4上表面和N+源极5上表面，六个通道所形成的区域为第一区域。
步骤10：如图14所示，通过离子注入方式在通道通向的P型体区4上表面注入第五离子形成P+埋层；优选地，第五离子为硼离子；第五离子的注入深度为P型体区4的深度的0.4-0.6倍，深于N+源极5；注入能量在300-800Kev之间，注入的杂质剂量在2×1013-2×1014个离子/CM2之间。此步注入的第五离子可以降低基区内部电阻，从而阻止寄生NPN三极管的开启，提升器件的抗EAS能力，提升器件的可靠性，且由于P+埋层10距离垂直的导电沟道存在一定的距离，不会影响MOSFET的电压能力和电流能力。
步骤11：如图15所示，通过干法刻蚀方式将P型体区4之间的区域上方的P型体区接触层9、第二栅氧化层和绝缘介质层10刻穿形成第二区域。干法刻蚀方式包括：通过EOP方式刻蚀绝缘介质层10，EOP方式是在干法等离子体刻蚀的时候，会产生气态的副产物，刻蚀不同材料时，产生的副产物也是不同的，当一种材料刻蚀完成时候，通过传感器探测副产物的信号强弱，可以得知刻蚀完成。在EOP方式刻蚀完成之后，采用等离子耦合的ICP机刻蚀所述氧化层7和P型体区接触层9，一般的刻蚀深度为0.5um以内。如图16所示，在第二区域上淀积势垒金属形成肖特基势垒金属层12，淀积结束后在N2气氛下进行高温退火。
步骤12：如图17所示，在所述第一区域与所述第二区域上淀积金属钛形成欧姆接触金属层13。
步骤13：如图17所示，在所述欧姆接触金属层与所述绝缘介质层上方生长Al，形成正面金属。
尽管已经示出和描述了本发明的实施例，对于本领域的普通技术人员而言，可以理解在不脱离本发明的原理和精神的情况下可以对这些实施例进行多种变化、修改、替换和变型，本发明的范围由所附权利要求及其等同物限定。

Claims (22)

1.一种增强型碳化硅MOSFET器件，其特征在于，包括：
N-外延层，所述N-外延层上表面包括在水平方向上平行间隔排列的若干个P型体区，所述P型体区在所述N-外延层上表面向下形成，所述P型体区包括第一离子，所述若干个P型体区之间通过肖特基势垒金属层相连接；
至少三个所述P型体区上表面的中央区域包括N+源极，所述N+源极在P型体区上表面中央区域向下形成，所述N+源极包括第二离子；
所述N+源极的中央区域下方设有槽，所述槽的深度深于所述P型体区但不与N+型重掺杂SiC衬底接触；所述槽包括栅底P区，所述栅底P区设置在所述槽底部，所述栅底P区包括第三离子；
所述槽还包括多晶硅栅极，所述多晶硅栅极充满整个槽；所述N-外延层和所述槽还包括栅氧化层，所述栅氧化层生长在所述槽内壁；
所述P型体区上表面所述N+源极外侧还包括P型体区接触层，所述P型体区接触层在P型体区上表面向下设置形成，所述P型体区接触层包括第四离子；
所述P型体区还包括P+埋层，所述P+埋层设置在所述P型体区的中央位置并在所述槽外侧，所述P+埋层包括第五离子；所述N+源极、所述P型体区接触层和所述肖特基势垒金属层上方设置有欧姆接触金属层。
2.如权利要求1所述的器件，其特征在于，所述器件自上而下依次为：
背面金属，所述背面金属由金属Ti、金属Ni以及金属Ag组合形成；N+型重掺杂SiC衬底；所述N-外延层；绝缘介质层，所述绝缘介质层是由SiO2组成；所述绝缘介质层设置在所述多晶硅栅极上方和所述P型体区接触层上方；
正面金属，所述正面金属由Al组成，厚度为1-5μm。
3.如权利要求2所述的器件，其特征在于，所述碳化硅衬底所用碳化硅单晶体材料可以是2H-SiC单晶体、4H-SiC单晶体的其中一种，所述N+型重掺杂SiC衬底的掺杂浓度为3×1019-3×1020个离子/CM3。
4.如权利要求1所述的器件，其特征在于，所述N-外延层的掺杂浓度在1×1015-1×1016个离子/CM3之间，厚度为10-30μm，掺杂杂质为氮元素。
5.如权利要求1所述的器件，其特征在于，所述P型体区的深度为1-3μm，所述第一离子为硼离子，所述N+源极的深度为0.2-0.8μm，所述第二离子为磷离子。
6.如权利要求1所述的器件，其特征在于，所述第三离子、第四离子、第五离子为硼离子。
7.如权利要求1所述的器件，其特征在于，所述多晶硅的掺杂浓度大于1×1020个离子/CM3。
8.如权利要求1所述的器件，其特征在于，所述栅氧化层的厚度为0.04-0.1μm。
9.如权利要求2所述的器件，其特征在于，所述绝缘介质层的厚度为
Figure FDA0003645908830000021
所述肖特基势垒金属层为TiMo或TiW，所述肖特基势垒金属层的厚度为
Figure FDA0003645908830000022
所述欧姆接触金属层的厚度为
Figure FDA0003645908830000023
10.一种增强型碳化硅MOSFET器件的制造方法，其特征在于，包括：
步骤1：选用N+型重掺杂SiC衬底，在其上表面生长N-外延层；
步骤2：在所述N-外延层上表面通过光刻和离子注入方式向下注入第一离子形成水平方向上平行间隔排列的至少三个P型体区，在所述至少三个P型体区上表面的中央区域通过离子注入方式向下注入第二离子形成N+源极；
步骤3：在所述N+源极的中央区域通过槽光刻和槽刻蚀的方式向下刻蚀形成槽，所述槽的深度深于所述P型体区但不与N+型重掺杂SiC衬底接触；
步骤4：在所述槽的底部通过离子注入方式向下注入第三离子形成栅底P区；
步骤5：通过5-10次快速热氧化方式在所述N-外延层上表面以及槽内壁生长第一栅氧化层，然后通过湿法腐蚀方式剥除第一栅氧化层，再通过炉管热氧氧化方式在所述N-外延层上表面以及槽内壁第二栅氧化层；
步骤6：在所述N-外延层上表面以及槽内淀积多晶硅，通过CMP工艺对N-外延层上表面的多晶硅进行刻蚀；
步骤7：在所述第二栅氧化层下方所述N-外延层上表面注入第四离子形成P型体区接触层；
步骤8：在所述第二栅氧化层上表面生长绝缘介质层，所述绝缘介质层由SiO2组成；
步骤9：通过光刻、刻蚀方式，刻蚀所述绝缘介质层形成至少六个通道，所述通道通向所述P型体区上表面和所述N+源极上表面，所述至少六个通道所形成的区域为第一区域；
步骤10：通过离子注入方式在所述通道通向的所述P型体区上表面注入第五离子形成P+埋层，所述第五离子的注入深度为所述P型体区的深度的0.4-0.6倍；
步骤11：通过干法刻蚀方式将P型体区之间的区域上方的所述P型体区接触层、第二栅氧化层和绝缘介质层刻穿形成第二区域，在所述第二区域上淀积势垒金属形成肖特基势垒金属层，所述淀积结束后在N2气氛下进行高温退火；
步骤12：在所述第一区域与所述第二区域上淀积金属钛形成欧姆接触金属层；
步骤13：在所述欧姆接触金属层与所述绝缘介质层上方生长Al，形成正面金属。
11.如权利要求10所述的制造方法，其特征在于，所述第一离子为硼离子，所述第一离子的注入次数为3-5次，单次注入剂量为2×1013-1×1014个离子/CM2，累计注入剂量为1×1014-5×1014个离子/CM2，注入能量为50Kev-1.5Mev，注入深度为1μm-2.5μm。
12.如权利要求10所述的制造方法，其特征在于，所述第二离子为磷离子，所述第二离子的注入剂量在3×1015-2×1016个离子/CM2之间，注入能量为150Kev-500Kev，注入深度为0.3μm-0.5μm。
13.如权利要求10所述的制造方法，其特征在于，对所述N+源极和所述P型体区进行高温推进，所述高温推进的温度为1700-1900℃，所述高温推进的时间为60min-300min。
14.如权利要求10所述的制造方法，其特征在于，所述槽的深度为1-4μm，宽度为0.4-1μm，在所述槽光刻和槽刻蚀后需对所述槽底部进行圆滑处理。
15.如权利要求10所述的制造方法，其特征在于，所述第三离子为硼离子，所述第三离子的注入剂量为1×1013-1×1014个离子/CM2，注入能量为30-80Kev。
16.如权利要求10所述的制造方法，其特征在于，所述快速热氧化方式时间为30S-2min，单次快速热氧化的厚度小于
Figure FDA0003645908830000044
累积快速热氧化厚度大于
Figure FDA0003645908830000041
17.如权利要求10所述的制造方法，其特征在于，所述炉管热氧氧化方式采用CL基气体，所述炉管热氧氧化方式所形成的所述第二栅氧化层的厚度为0.04-0.1μm。
18.如权利要求10所述的制造方法，其特征在于，所述多晶硅的杂质浓度为1×1020个离子/CM3以上，所述多晶硅的厚度为
Figure FDA0003645908830000042
19.如权利要求10所述的制造方法，其特征在于，所述第四离子的注入能量为50-150Kev，注入剂量为1×1013-5×1013个离子/CM2。
20.如权利要求10所述的制造方法，其特征在于，所述绝缘介质层的厚度为
Figure FDA0003645908830000043
21.如权利要求10所述的制造方法，其特征在于，所述第五离子的注入能量为300-800Kev，注入剂量为2×1013-2×1014个离子/CM2。
22.如权利要求10所述的制造方法，其特征在于，在所述欧姆接触金属层积淀完成后进行高温退火，退火温度为900-1100℃。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102364688A (zh) * 2011-11-09 2012-02-29 电子科技大学 一种垂直双扩散金属氧化物半导体场效应晶体管
CN104425246A (zh) * 2013-08-27 2015-03-18 无锡华润上华半导体有限公司 绝缘栅双极型晶体管及其制备方法
CN109065540A (zh) * 2018-08-06 2018-12-21 中国科学院半导体研究所 一种集成SBD的SiC UMOSFET的结构及制备方法
CN110534559A (zh) * 2019-09-03 2019-12-03 深圳第三代半导体研究院 一种碳化硅半导体器件终端及其制造方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8110869B2 (en) * 2005-02-11 2012-02-07 Alpha & Omega Semiconductor, Ltd Planar SRFET using no additional masks and layout method
US8779510B2 (en) * 2010-06-01 2014-07-15 Alpha And Omega Semiconductor Incorporated Semiconductor power devices manufactured with self-aligned processes and more reliable electrical contacts
US8674439B2 (en) * 2010-08-02 2014-03-18 Microsemi Corporation Low loss SiC MOSFET
CN105047721A (zh) * 2015-08-26 2015-11-11 国网智能电网研究院 一种碳化硅沟槽栅功率MOSFETs器件及其制备方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102364688A (zh) * 2011-11-09 2012-02-29 电子科技大学 一种垂直双扩散金属氧化物半导体场效应晶体管
CN104425246A (zh) * 2013-08-27 2015-03-18 无锡华润上华半导体有限公司 绝缘栅双极型晶体管及其制备方法
CN109065540A (zh) * 2018-08-06 2018-12-21 中国科学院半导体研究所 一种集成SBD的SiC UMOSFET的结构及制备方法
CN110534559A (zh) * 2019-09-03 2019-12-03 深圳第三代半导体研究院 一种碳化硅半导体器件终端及其制造方法

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