CN102005441A - 混合封装栅极可控的半导体开关器件及制备方法 - Google Patents

混合封装栅极可控的半导体开关器件及制备方法 Download PDF

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CN102005441A
CN102005441A CN201010270033XA CN201010270033A CN102005441A CN 102005441 A CN102005441 A CN 102005441A CN 201010270033X A CN201010270033X A CN 201010270033XA CN 201010270033 A CN201010270033 A CN 201010270033A CN 102005441 A CN102005441 A CN 102005441A
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wafer
semiconductor
switch device
gate transistor
insulated gate
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雷燮光
安荷·叭剌
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Alpha and Omega Semiconductor Ltd
Alpha and Omega Semiconductor Inc
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Abstract

本发明涉及一种混合封装的栅极可控的半导体开关器件(HPSD)，具有一个互联的由第一半导体晶片制成的绝缘栅极晶体管(IGT)，以及一个由第二半导体晶片制成的整流栅极晶体管(RGT)。RGT栅极和源极分别电连接到IGT源极和漏极上。HPSD含有一个具有多个封装端，用于将HPSD与其外部器件互联的封装基座。IGT晶片焊接在封装基座上方。第二半导体晶片形成在混合半导体外延层上方，混合半导体外延层覆盖在电绝缘衬底(EIS)上方，从而构成一个RGT晶片。RGT晶片通过EIS，堆积并焊接在IGT晶片上方。IGT、RGT晶片以及封装端通过接合引线互联。因此，HPSD是IGT晶片和RGT晶片的堆积式封装，减少了封装引脚，同时允许在IGT上灵活地放置器件的端电极。

Description

混合封装栅极可控的半导体开关器件及制备方法
技术领域
本发明主要涉及电路领域。更确切地说，本发明是关于电子开关电路的物理级封装及制备方法。
背景技术
除了技术上可靠的原理电路设计之外，当今的电子学还需要高品质、高效率的物理级封装。尤其是在便携式产品应用中，紧密封装尺寸、低电磁干扰/射频干扰(EMI/RFI)以及***结构的灵活性等都是极其重要的考量指标。
Baliga等人发明的美国专利号US5396085的名为“带有整流栅极的碳化硅开关器件”的专利，以下引用为US5396085，提出了一种碳化硅开关器件，在硅和碳化硅的混合衬底中，包括一种三端互联的硅MOSFET以及碳化硅MESFET(或JFET)。为了简便，US5396085的图5A、图5B、图6和图7特此引用为本发明申请文件的图1A、图1B、图2A和图2B。
因此，图1A是一个带有整流栅极10的三端碳化硅开关器件的电路图。三端开关器件10是由一个带有第一源级区14、第一漏极区16和绝缘栅极电极18的绝缘栅极场效应管12(如图所示的硅MOSFET)构成的。绝缘栅极场效应管12最好选用一种增强型器件，在零势能栅极偏压下(如图中虚线所示)不导电。因此，要在晶体管12中传导通常需要，在晶体管的有源区中形成一个反转层沟道。晶体管12也可选用一种ACCU-FET，最好设计成在零势能偏压下不导电的。如图所示，还可以选用一个带有第二源级区24、第二漏极区26和整流栅极电极28的整流栅极场效应管22(如图所示的碳化硅MESFET)，连接到绝缘栅极场效应管12上。还分别制备了源级接头20和漏极接头30。因此，通过绝缘栅极电极18、源级接头20和漏极接头30，电连接到三端器件上。图1B表示带有整流栅极10’的三端碳化硅开关器件的电路图。三端开关器件10’是由一个带有第二源级区24’、第二漏极区26’和整流栅极电极28’的整流栅极场效应管22’(如图所示的碳化硅JFET)构成的，整流栅极场效应管22’连接到绝缘栅极场效应管12上。
为了便于形成如图1A和图1B所示的三端开关器件10和10’，可以使用一个具有SiC和Si区域的混合半导体衬底48。图2A和图2B分别表示利用混合半导体衬底48制备的图1A和图1B所示的开关器件的剖面图。
值得注意的是，凭借硅和碳化硅的混合衬底，可以通过在硅-碳化硅交界面处的材料和工艺的兼容性，来限制开关器件10和10’的器件结构灵活性。开关器件10和10’的整体紧密封装尺寸，更加剧了这种限制作用。关于硅-碳化硅衬底的另一需要注意的问题是，由于在硅-碳化硅交界面处的分子级结构缺陷，引起器件漏电流的电势增长。因此，为了避免这些限制作用及问题，并保持整体的封装紧密，必须提出另一种三端开关器件的封装结构。
此外，本申请涉及以下专利申请案，特此引用，作为用于任何及全部意图的参考：
由弗朗索瓦赫伯特等人发明的，申请日期为2007年7月31日，申请号为US11/830951、名为“带有有效封装的多晶片直流-直流增强功率转换器”的美国专利申请，以下引用为US11/830951。
由弗朗索瓦赫伯特等人发明的，申请日期为2007年7月31日，申请号为US11/830996、名为“带有有效封装的多晶片直流-直流升压功率转换器”的美国专利申请，以下引用为US11/830996。
由冯涛等人发明的，申请日期为2009年2月23日，申请号为US12/391251、名为“带有堆积式电感和集成电路晶片的紧密功率半导体封装及方法”的美国专利申请，以下引用为US12/391251。
以及由冯涛等人发明的，申请日期为2009年3月4日，申请号为US12/397473、名为“紧密电感功率电子封装”的美国专利申请，以下引用为US12/397473。
发明内容
提出了一种混合封装的3-端栅极可控的半导体开关器件(HPSD)。HPSD具有一个互联的由第一半导体晶片制成的绝缘栅极晶体管(IGT)，以及一个由带有混合半导体层的第二半导体晶片制成的整流栅极晶体管(RGT)。RGT器件端电极位于第二半导体晶片的前表面上，RGT栅极电极和源极电极分别电连接到IGT源极电极和漏极电极上。HPSD包括：
一个具有多个封装终端的封装基座，用于将HPSD与其外部器件互联；
焊接在封装基座上方的IGT晶片；
一个位于电绝缘衬底(EIS)上方的RGT晶片，在电绝缘衬底上形成一个混合半导体外延层，用于制备RGT器件。通过EIS，依次将RGT晶片堆积并连接在IGT晶片上方；
各种互联线路，用于互联IGT晶片、RGT晶片以及封装终端；
因此，HPSD是IGT晶片和RGT晶片的堆积式封装，减少了封装引脚，并且允许更大的晶片尺寸，以及在IGT晶片上灵活地放置器件的端电极。
在一个较典型的实施例中，IGT是一个增强型金属氧化物半导体场效应管(MOSFET)。
在一种典型的器件结构中，增强型MOSFET是一个底部漏极的MOSFET，其漏极电极位于其底面上，其源极和栅极电极位于其顶面上。
更确切地说，封装基地可以由一个引线框、一个多层电路层压板或一个引线上芯片封装制成，底部漏极MOSFET晶片可以是焊接在引线上芯片封装的倒装晶片。
在另一个典型器件的结构中，增强型MOSFET是一个底部源极的MOSFET，其源极电极位于其底面上，其栅极和漏极电极位于其顶面上。
在一个较典型的实施例中，RGT是一种耗尽型的金属半导体场效应管(MESFET)。
在一个较典型的实施例中，第一半导体晶片是由硅(Si)、锗(Ge)、砷化镓(GaAs)或锗化硅(SiGe)制成的，第二半导体晶片是由氮化镓(GaN)制成的。
在一个较典型的实施例中，EIS为蓝宝石、金刚石、氧化锌(ZnO)、氮化铝(AIN)或半绝缘的SiC。如果EIS为蓝宝石的话，那么GaN就可以生长在EIS上。
在一个更加详细的实施例中，利用绝缘环氧树脂或不绝缘的环氧树脂，通过晶片固着，可以将RGT晶片焊接在IGT晶片上方。
在一个更加详细的实施例中，RGT晶片还包括蒸发的背部金属，可以利用焊料，通过晶片固着，将RGT晶片焊接在IGT晶片上方。
本发明提供的一种用于制备混合封装的3-端栅极可控的半导体开关器件的方法，半导体开关器件具有一个互联的由第一半导体晶片制成的绝缘栅极晶体管，以及一个由带有混合半导体层的第二半导体晶片制成的整流栅极晶体管，整流栅极晶体管的器件端电极位于第二半导体晶片的前表面上，整流栅极晶体管的栅极电极和源极电极分别电连接到绝缘栅极晶体管的源极电极和漏极电极上，该方法包括：
制备一个具有多个封装终端的封装基座，用于将半导体开关器件与其外部器件互联；
将绝缘栅极晶体管晶片固定在封装基座上方；
制备一个电绝缘衬底，并在衬底上方形成混合半导体层，以制成整流栅极晶体管晶片；
通过电绝缘衬底，将整流栅极晶体管晶片堆积固定在绝缘栅极晶体管晶片上方；并且
互联绝缘栅极晶体管晶片、整流栅极晶体管晶片以及封装终端。
上述的方法，所述的封装基座为引线上芯片封装，所述的绝缘栅极晶体管为底部漏极金属氧化物半导体场效应管，焊接绝缘栅极晶体管晶片还包括在引线上芯片封装上方，倒装晶片焊接底部漏极金属氧化物半导体场效应管晶片。
上述的方法，制成整流栅极晶体管晶片还包括在电绝缘衬底上镀背部金属，焊接整流栅极晶体管晶片还包括利用焊锡，焊接整流栅极晶体管晶片。
上述的方法，第二半导体晶片为由氮化镓制成的耗尽型器件，制备混合半导体层是由在蓝宝石上生长氮化镓制成的，第一半导体晶片为增强型器件。
对于本领域的技术人员，在本发明的以下内容中，还将详细说明本发明的这些方面及其各种实施例。
附图说明
为了更加完整地说明本发明的各种实施例，请参考以下附图。但是，这些附图仅用于解释说明，不应据此局限本发明的范围。
图1A表示原有技术的US5396085中，带有整流栅极的第一种三端碳化硅开关器件的电路图；
图2A表示利用混合半导体衬底，图1A所示的开关器件的剖面图；
图1B表示原有技术的US5396085中，带有整流栅极的第二种三端碳化硅开关器件的电路图；
图2B表示利用混合半导体衬底，图1B所示的开关器件的剖面图；
图3表示本发明所述的整流栅极晶体管晶片的透视图；
图4A表示本发明所述的混合封装的3-端栅极可控的半导体开关器件的第一种器件结构的透视图；以及
图4B表示本发明所述的混合封装的3-端栅极可控的半导体开关器件的第二种器件结构的透视图。
具体实施方式
本文中的说明以及附图仅用于说明本发明现有的一个或多个较佳实施例，以及一些附加器件和/或可选实施例。这些说明和附图仅用于解释说明，并不作为本发明的局限。因此，本领域的技术人员应掌握各种变化、修正和可选方案。这些变化、修正和可选方案也应认为仍在本发明的范围内。
图3与图4A表示本发明所述的带有整流栅极晶体管(RGT)晶片10，混合封装的3-端栅极可控的半导体开关器件(HPSD)50的第一种器件结构的透视图。
HPSD50具有一个封装基座，在此基座中含有各种引线框部分30a、30b、30c和30d。每个引线框部分30b、30c和30d都具有多个封装终端，用于将HPSD50与其外部器件互联。由硅半导体晶片22与硅半导体衬底22a制成的硅金属氧化物半导体场效应管(MOSFET)，焊接在封装基座(引线框部分30a)上方。因此，引线框部分30a也作为HPSD50主要的散热片。尤其是硅MOSFET可以是一种增强型垂直MOSFET。由独立的半导体晶片2制成的氮化镓(GaN)金属半导体场效应管(MESFET)，具有一个形成在例如蓝宝石衬底1之类的电绝缘衬底(EIS)上的GaN半导体外延层2a，以构成GaN整流栅极晶体管(RGT)晶片10(图3)。由于材料和工艺的兼容性，可以在蓝宝石衬底1上生长GaN外延层2a。尤其是GaN MESFET可以是一种耗尽型水平MESFET。GaN MESFET的器件端电极MESFET漏极电极2d、MESFET源极电极2s以及MESFET栅极电极2g都位于其前表面上。在这种情况下，硅垂直MOSFET为底部漏极MOSFET，其MOSFET漏极电极22d位于其底面上，其MOSFET源极电极22s和MOSFET栅极电极22g位于其顶面上。
RGT晶片10通过蓝宝石衬底1，依次堆积并焊接在硅半导体晶片22上方。由于蓝宝石是电绝缘材料，因此，可以利用绝缘的环氧树脂或不绝缘的环氧树脂，通过晶片固着，将RGT晶片10焊接在硅半导体晶片22上方。在另一个实施例中，在RGT晶片10的背部镀上一层金属，然后利用焊锡材料，将晶片固着在硅半导体晶片22上方。如果使用的是碳化硅(SiC)等半绝缘材料作为生长GaN外延层的衬底，那么需要在RGT衬底和MOSFET晶片之间保持适当的绝缘。HPSD50还带有各种接合引线32、34、36、38和40，用于互联硅MOSFET、RGT晶片10以及封装终端。因此，MESFET栅极电极2g通过接合引线38，连接到MOSFET源极电极22s上。MESFET源极电极2s通过接合引线32，连接到MOSFET漏极电极22d上。MOSFET源极电极22s通过接合引线34，连接到引线框部分30b上。MOSFET栅极电极22g通过接合引线36，连接到引线框部分30c上。MESFET漏极电极2d通过接合引线40，连接到引线框部分30d上。所形成的HPSD50构成了一个3-端增强型器件(与耗尽型器件相反)。增强型器件这一点很重要，因在其应用过程中，与最普通的MOSFET兼容，最普通的MOSFET是增强型器件，在通常情况保持断路，仅在施加栅极电压下才导通。如果需要的话，HPSD50也可以与最普通的MOSFET的标准引脚兼容。
硅半导体晶片22和GaN半导体晶片2的堆积式封装的好处在于，减少了HPSD50封装尺寸，并允许使用较大的独立晶片尺寸，从而相应地降低漏极-源极电阻RDS。作为一个特例，Si MOSFET可以获得1豪欧至2豪欧的RDS，GaN MESFET可以获得5豪欧至10豪欧的RDS。另外，需要说明的是，在RGT晶片10上使用电绝缘的蓝宝石衬底1，使得在硅半导体晶片22上可以灵活地放置器件端电极。
图3与图4B表示本发明所述的带有整流栅极晶体管(RGT)晶片10，半导体开关器件(HPSD)70的第二种器件结构的透视图。HPSD70具有一个封装基座，在此基座中含有各种引线框部分44a、44b和44c，每个引线框部分都具有多个封装终端，用于将HPSD70与其外部器件互联。由硅半导体晶片42与硅半导体衬底42a制成的硅垂直MOSFET，焊接在封装基座(引线框部分44a)上方。因此，引线框部分44a不仅起到封装的电接头作用，还作为HPSD70主要的散热片。
除了硅半导体晶片42是一种底部源极器件，其MOSFET源极电极42s位于其底面上，其栅极和漏极电极42g和42d位于其顶面上，与封装基座绝缘之外，HPSD70的其余部分都与HPSD50类似。因此，MESFET栅极电极2g通过接合引线56，连接到MOSFET源极电极42s上。MESFET源极电极2s通过接合引线52，连接到MOSFET漏极电极42d上。MOSFET源极电极42s连接到引线框部分44a上。MOSFET栅极电极42g通过接合引线54，连接到引线框部分44b上。MESFET漏极电极2d通过接合引线58，连接到引线框部分44c上。
尽管HPSD50的主开关节点(MOSFET漏极22d)短接到其主散热片(引线框部分30a)上，但HPSD70的主开关节点(MOSFET漏极42d)却与其主散热片(引线框部分44a)电绝缘。因此，与HPSD50相比，HPSD70的器件结构具有降低电磁干扰/射频干扰(EMI/RFI)辐射的优势。
本发明提出了一种HPSD。尽管所述的这种HPSD，利用电绝缘衬底为蓝宝石衬底1的RGT晶片10，但也可以使用其他电绝缘材料例如金刚石、氧化锌(ZnO)、氮化铝(AIN)或半绝缘的碳化硅(SiC)等作为衬底。参考US11/830951、US11/830996、US12/391251以及US12/397473，本领域的技术人员应理解，本发明也可以利用以下可选方案实施：
由印刷电路板(PCB)制成的封装基座。
由引线上芯片封装制成的封装基座，底部漏极硅半导体晶片22倒装晶片，通过焊锡球，焊接在引线上芯片封装上方。
用三维方向上制成的互联平板代替接合引线。
另外，一般来说，可以用由硅(Si)、锗(Ge)、砷化镓(GaAs)或锗化硅(SiGe)等制成的不同的绝缘栅极晶体管(IGT)，来代替硅MOSFET。
尽管上述说明涵盖了多种特殊示例，但这些特殊示例仅用于解释说明本发明的多个现有的较佳实施例，并不应据此局限本发明的范围。本领域的技术人员应理解，本发明还可以应用在各种其他特殊器件中，而且本领域的技术人员无需过多实验，就可以实施这些其他实施例。鉴于本专利文件，本发明的范围不应由上述说明中的特殊典型实施例限定，而应由以下权利要求书限定。权利要求书范围内的意图和等价的范围内的任何和全部修正，都应认为仍属本发明的意图和范围。

Claims (13)

1.一种混合封装的3-端栅极可控的半导体开关器件，其特征在于，具有一个互联的由第一半导体晶片制成的绝缘栅极晶体管，以及一个由带有混合半导体层的第二半导体晶片制成的整流栅极晶体管，整流栅极晶体管的器件端电极位于第二半导体晶片的前表面上，整流栅极晶体管的栅极电极和源极电极分别电连接到绝缘栅极晶体管的源极电极和漏极电极上，半导体开关器件包括：
一个具有多个封装终端的封装基座，用于将半导体开关器件与其外部器件互联；
固定在封装基座上方的绝缘栅极晶体管晶片；
一个电绝缘衬底及其上方所形成的混合半导体层，构成整流栅极晶体管晶片，整流栅极晶体管晶片通过电绝缘衬底堆积并固定在绝缘栅极晶体管晶片上方；以及
用于互联绝缘栅极晶体管晶片、整流栅极晶体管晶片以及封装终端的互联线路。
2.如权利要求1所述的半导体开关器件，其特征在于，所述的绝缘栅极晶体管为金属氧化物半导体场效应管。
3.如权利要求2所述的半导体开关器件，其特征在于，所述的金属氧化物半导体场效应管为底部漏极金属氧化物半导体场效应管，其漏极电极位于其底面上，其源极和栅极电极位于其顶面上。
4.如权利要求2所述的半导体开关器件，其特征在于，所述的金属氧化物半导体场效应管为底部源极金属氧化物半导体场效应管，其源极电极位于其底面上，其栅极和漏极电极位于其顶面上，从而与封装基座绝缘。
5.如权利要求1所述的半导体开关器件，其特征在于，所述的整流栅极晶体管为金属半导体场效应管。
6.如权利要求5所述的半导体开关器件，其特征在于，所述的金属半导体场效应管为耗尽型金属半导体场效应管。
7.如权利要求1所述的半导体开关器件，其特征在于，所述的第一半导体晶片是由硅、锗、砷化镓或锗化硅制成的。
8.如权利要求1所述的半导体开关器件，其特征在于，所述的混合半导体层是由氮化镓制成的。
9.如权利要求8所述的半导体开关器件，其特征在于，所述的电绝缘衬底为蓝宝石、金刚石、氧化锌、氮化铝或半绝缘的碳化硅。
10.一种用于制备混合封装的3-端栅极可控的半导体开关器件的方法，其特征在于，半导体开关器件具有一个互联的由第一半导体晶片制成的绝缘栅极晶体管，以及一个由带有混合半导体层的第二半导体晶片制成的整流栅极晶体管，整流栅极晶体管的器件端电极位于第二半导体晶片的前表面上，整流栅极晶体管的栅极电极和源极电极分别电连接到绝缘栅极晶体管的源极电极和漏极电极上，该方法包括：
制备一个具有多个封装终端的封装基座，用于将半导体开关器件与其外部器件互联；
将绝缘栅极晶体管晶片固定在封装基座上方；
制备一个电绝缘衬底，并在电绝缘衬底上方形成混合半导体层，以制成整流栅极晶体管晶片；
通过电绝缘衬底，将整流栅极晶体管晶片堆积固定在绝缘栅极晶体管晶片上方；并且
互联绝缘栅极晶体管晶片、整流栅极晶体管晶片以及封装终端。
11.如权利要求10所述的方法，其特征在于，所述的封装基座为引线上芯片封装，所述的绝缘栅极晶体管为底部漏极金属氧化物半导体场效应管，焊接绝缘栅极晶体管晶片还包括在引线上芯片封装上方，倒装晶片焊接底部漏极金属氧化物半导体场效应管晶片。
12.如权利要求10所述的方法，其特征在于，制成整流栅极晶体管晶片还包括在电绝缘衬底上镀背部金属，焊接整流栅极晶体管晶片还包括利用焊锡，焊接整流栅极晶体管晶片。
13.如权利要求10所述的方法，其特征在于，第二半导体晶片为由氮化镓制成的耗尽型器件，制备混合半导体层是由在蓝宝石上生长氮化镓制成的，第一半导体晶片为增强型器件。
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