CN101986429A - 芯片封装体及其形成方法 - Google Patents

芯片封装体及其形成方法 Download PDF

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CN101986429A
CN101986429A CN2010101444336A CN201010144433A CN101986429A CN 101986429 A CN101986429 A CN 101986429A CN 2010101444336 A CN2010101444336 A CN 2010101444336A CN 201010144433 A CN201010144433 A CN 201010144433A CN 101986429 A CN101986429 A CN 101986429A
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chip
insulating layer
metal level
flexible insulating
substrate
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CN101986429B (zh
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彭宝庆
黄俊龙
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XinTec Inc
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XinTec Inc
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Abstract

本发明提供一种芯片封装体及其形成方法，该芯片封装体包括基底；凹槽，自基底的上表面向下延伸；金属层，位于基底之上，且顺应性覆盖于此凹槽的侧壁与底部上；芯片，具有上表面，设置于凹槽中的金属层上，此芯片的上表面不低于凹槽外的金属层的上表面；以及保护层，覆盖于芯片之上。

Description

芯片封装体及其形成方法
技术领域
本发明涉及芯片封装体，且特别是涉及芯片下包覆有金属层的芯片封装体。
背景技术
随着半导体工艺技术的不断进步，可在更小的芯片中形成更多的半导体元件。除了使芯片的效能更为提升外，还能节省晶片面积而降低成本。然而，随着芯片尺寸缩小化与元件密度的增加，其输出/输入连接(I/O)的数目与密度也增加，造成芯片与外界间的导电通路形成不易。此外，缩小化芯片中的高密度元件于运作时，容易产生过多的热能而影响芯片的效能。
发明内容
本发明的目的在于提供一种芯片封装体及其形成方法，以解决上述问题。
为达上述目的，本发明实施例提供一种芯片封装体，包括基底；凹槽，自基底的上表面向下延伸；金属层，位于基底之上，且顺应性覆盖于此凹槽的侧壁与底部上；芯片，具有上表面，设置于凹槽中的金属层上，此芯片的上表面不低于凹槽外的金属层的上表面；以及保护层，覆盖于芯片之上。
本发明实施例提供一种芯片封装体的形成方法，包括提供暂时基底；在暂时基底上形成柔性绝缘层；在柔性绝缘层上接合芯片；将柔性绝缘层硬化为绝缘层；在暂时基底上形成金属层，金属层顺应性覆盖于绝缘层与芯片之上；在金属层上形成介电层；移除暂时基底；移除绝缘层；以及在芯片上形成保护层。
本发明另一实施例提供一种芯片封装体的形成方法，包括提供暂时基底；在暂时基底上形成绝缘层；在绝缘层上形成柔性绝缘层；在柔性绝缘层上接合至少一芯片；在暂时基底上形成金属层，金属层顺应性覆盖于柔性绝缘层与芯片之上；在金属层上形成介电层；移除暂时基底；移除柔性绝缘层；以及在芯片上形成保护层。
附图说明
图1A-图1G为本发明实施例的芯片封装体的一系列工艺剖视图；
图2A-图2G为本发明另一实施例的芯片封装体的一系列工艺剖视图；
图3A-图3E为本发明数个实施例中的芯片封装体的示意图；
图4A-图4C为本发明实施例的芯片接合步骤的一系列工艺剖视图。
附图标记说明
100～暂时基底；
102、201、202～柔性绝缘层；
102a、101a、201a、202a～绝缘层；
104、104a、104b～芯片；
106～金属层；
106a、106b～金属图案；
108～介电层；
110～保护层；
112、112a、112b～导电结构；
302a、302b～凹槽；
105a、105b、107、108a～表面。
具体实施方式
以下将详细说明本发明实施例的制作与使用方式。然而应注意的是，本发明提供许多可供应用的发明概念，其可以多种特定型式实施。文中所举例讨论的特定实施例仅为制造与使用本发明的特定方式，非用以限制本发明的范围。此外，在不同实施例中可能使用重复的标号或标示。这些重复仅为了简单清楚地叙述本发明，不代表所讨论的不同实施例及/或结构之间具有任何关连性。再者，当述及第一材料层位于第二材料层上或之上时，包括第一材料层与第二材料层直接接触或间隔有一或更多其他材料层的情形。
图1A-图1G显示本发明实施例的芯片封装体的一系列工艺剖面图。如图1A所示，提供暂时基底100。暂时基底100包括半导体材料、绝缘材料、金属材料、或前述的组合。在实施例中，暂时基底100例如为硅晶片或硅基底等。
接着，在暂时基底100上形成柔性绝缘层102。在后续工艺中，柔性绝缘层102将用以固定设置于其上的芯片，因此柔性绝缘层优选能使芯片陷入于其中而固定。柔性绝缘层102的材料例如为蜡、高分子材料、或前述的组合。柔性绝缘层102的形成方式例如包括网印涂布(screen printing)、胶膜涂布(1amination printing)、或旋转涂布(spin coating)。
如图1B所示，接着在柔性绝缘层102上接合芯片104。此外，在其他实施例中，可在柔性绝缘层102上接合一个以上的其他芯片104。芯片与芯片之间可为不同种类的芯片，而各有其运作效能。例如，在实施例中，芯片104可包括逻辑运算芯片、微机电***芯片、微流体***芯片、或利用热、光线及压力等物理变化量来测量的物理传感器芯片、射频元件芯片、加速计芯片、陀螺仪芯片、微制动器芯片、表面声波元件芯片、压力传感器芯片、喷墨头芯片、发光元件芯片、或太阳能电池芯片等。此外，芯片与芯片之间的尺寸或形状可彼此不同。此外，虽然图1B中的芯片104的侧壁大致垂直于暂时基底100的上表面，然在其他实施例中，可选用或形成侧壁倾斜于暂时基底100的上表面的芯片，可使后续形成的材料层(例如，金属层)较容易顺应性沉积。
在实施例中，芯片104的接合步骤包括将芯片104压入柔性绝缘层102中。如图1B所示，芯片104被部分压入柔性绝缘层102中而固定。
如图1C所示，接着将柔性绝缘层102硬化为绝缘层102a。硬化后的绝缘层102a除了可进一步固定芯片104外，还可使暂时基底100较易于后续工艺中移除。在实施例中，柔性绝缘层102的硬化步骤包括以紫外线照射或是对柔性绝缘层102加热而使之硬化为绝缘层102a。加热温度可视所采用的柔性绝缘层102的材料而定，例如可介于约120℃至约350℃之间。
接着，如图1C所示，在暂时基底100上形成金属层106。金属层106顺应性覆盖于绝缘层102a及芯片104上。在此实施例中，金属层106与芯片104直接接触。在其他实施例中，可视情况于芯片104与金属层106之间形成其他材料层，例如可为介电层或其他导电层等。金属层106的形成方式例如可为物理气相沉积、溅镀、化学气相沉积、电镀、或无电镀等。在实施例中，金属层106整面地顺应性形成于芯片104上。在另一实施例中，可进一步视需求而将金属层106图案化。例如，图案化后金属层106可作为芯片104下方的无源元件(被动元件)的一部分。此外，金属层106的形成有助于芯片104的散热，或者可用作接地。
接着，如图1D所示，在金属层106上形成介电层108。介电层108的材料可例如为环氧树脂、防焊材料、或其他适合的绝缘物质，例如无机材料的氧化硅层、氮化硅层、氮氧化硅层、金属氧化物、或前述的组合；或也可为有机高分子材料的聚酰亚胺树脂(polyimide)、苯环丁烯(butylcyclobutene，BCB，道氏化学公司)、聚对二甲苯(parylene)、萘聚合物(polynaphthalenes)、氟碳化物(fluorocarbons)、丙烯酸酯(acrylates)等。介电层108的形成方式可包含涂布方式，例如旋转涂布(spin coating)、喷涂(spray coating)、或淋幕涂布(curtain coating)，或其他适合的沉积方式，例如，液相沉积、物理气相沉积、化学气相沉积、低压化学气相沉积、等离子体增强式化学气相沉积、快速热化学气相沉积、或常压化学气相沉积等工艺。在后续工艺中，将改以介电层108作为承载芯片104的基底，因此介电层108优选具有大致平坦的上表面。
如图1E所示，将暂时基底100自已硬化的绝缘层102a的表面移除。接着，如图1F所示，移除绝缘层102a。在实施例中，硬化后的绝缘层102a的材料为蜡，因此可轻易地移除。绝缘层102a的移除方式例如包括加热到蜡融化的温度如100℃再通过外力移除。在此实施例中，芯片104的上表面高于两旁的金属层106的上表面。在另一实施例中，当芯片104仅接合于柔性绝缘层102上而不陷入其中时，芯片104将整个位于介电层108中，因此芯片的上表面将与两旁的金属层106的上表面大致等高而共平面。
如图1G所示，改以介电层108为基底，在芯片104上形成保护层110。保护层110的材料与形成方式可类似于介电层108。保护层110可保护芯片104免于受到外力冲击或外界污染。
在图1G所示实施例中，进一步在保护层110上形成导电结构112。导电结构112进一步例如通过导通孔(未显示)而电性连接至芯片104。在实施例中，每一导电结构112个别电性连接至芯片104。在另一实施例中，其中一导电结构112可同时电性连接至两个(或以上)不同的芯片104，形成两不同芯片间的信号传递桥梁。应注意的是，同一芯片104可能与数个导电结构112相连，但不代表这些导电结构112彼此间电性连接。这些导电结构112可能电性连接至芯片104中的不同接垫或元件区而彼此电性绝缘。在又一实施例中，导电结构112可电性连接至金属层106，此时例如可作为接地电极。
在实施例中，导电结构112例如是焊球。随着芯片104尺寸缩小化与元件密度的增加，其输出/输入连接(I/O)的数目与密度亦增加，此时在有限的芯片面积上形成导电结构(例如，植球工艺)是很困难的。本发明实施例通过形成保护层110，可使导电结构112(如焊球)分布在较大面积的保护层110上，有助于舒缓植球密度过密的问题。本发明实施例优选整合多芯片，使众多芯片的对应焊球共同分布在保护层110之上，可在舒缓导电结构的分布密度之余，还能有效利用保护层110上的面积，使整体芯片***封装体的尺寸缩小。
图2A-图2G显示本发明另一实施例的芯片封装体的一系列工艺剖视图，其中相似的元件将采用相似或相同的标号，且相似或相同的材料层的材料与其形成方式将不重复叙述。
如图2A所示，提供暂时基底100。接着，在暂时基底100上形成绝缘层101a。绝缘层101a的材料例如为蜡、高分子材料、或前述的组合。在实施例中，可先于暂时基底上形成柔性绝缘层，并接着将之硬化为绝缘层101a。例如，可通过加热或照射光线(如紫外光)的方式将柔性绝缘层硬化为绝缘层101a。接着，在绝缘层101a上形成柔性绝缘层102。
如图2B所示，接着在柔性绝缘层102上接合至少一芯片104。在实施例中，芯片104的接合步骤包括将芯片104压入柔性绝缘层102中。如图2B所示，在此实施例中，芯片104被部分压入柔性绝缘层102中而固定，且与绝缘层101a直接接触。
接着，如图2C所示，在暂时基底100上形成金属层106。金属层106顺应性覆盖于柔性绝缘层102及芯片104上。在此实施例中，金属层106与芯片104直接接触。在其他实施例中，可视情况在芯片104与金属层106之间形成其他材料层，例如可为介电层或其他导电层等。金属层106的形成方式例如可为物理气相沉积、溅镀、化学气相沉积、电镀、或无电镀等。其中，当以溅镀法形成金属层106时，由于在绝缘层101a上形成了柔性绝缘层102，可保护其下的绝缘层101a免于离子轰击而变质，有利于后续的移除步骤。
接着，如图2D所示，在金属层106上形成介电层108。在后续工艺中，将改以介电层108作为承载芯片104的基底，因此介电层108优选具有大致平坦的上表面。
如图2E所示，将暂时基底100自绝缘层101a的表面移除。接着，如图2F所示，移除绝缘层101a。在实施例中，绝缘层101a的材料为蜡，且受到柔性绝缘层102的保护而免于变质，因此可轻易地移除。在图2F的实施例中，柔性绝缘层102仍保留，其上表面大致与芯片104的上表面共平面。在另一实施例中，可完全或部分移除柔性绝缘层102。在又一实施例中，可将柔性绝缘层102硬化。
如图2G所示，改以介电层108为基底，在芯片104上形成保护层110。保护层110可保护芯片104免于受到外力冲击或外界污染。在图2G所示实施例中，进一步于保护层110上形成多个导电结构112。导电结构112进一步例如通过导通孔(未显示)而电性连接至芯片104。
在图2G所示实施例中，绝缘层(柔性绝缘层102或其硬化后的绝缘层)位于金属层106与保护层110之间，且其上表面不高于芯片104的上表面。例如，图2F的实施例中，绝缘层的上表面与芯片104的上表面大致等高而共平面。或者，在其他实施例中，可移除部分的绝缘层而使绝缘层102的上表面低于芯片104的上表面。
本发明实施例的芯片104的接合步骤不限于上述型式。例如，图4A-图4C显示本发明实施例的芯片接合步骤的一系列工艺剖面图。如图4A所示，在暂时基底100上依次形成柔性绝缘层201与柔性绝缘层202。接着，如图4B所示，在柔性绝缘层202上接合至少一芯片104。在此实施例中，芯片104的接合步骤包括将芯片104压入柔性绝缘层202中。如图4B所示，芯片104被部分压入柔性绝缘层202中而固定，且与柔性绝缘层201直接接触。在另一实施例中，芯片104仅陷入柔性绝缘层202中，但不与柔性绝缘层201直接接触。在又一实施例中，芯片104穿过柔性绝缘层201与柔性绝缘层202之间的界面而部分陷于柔性绝缘层201之中。芯片104陷于柔性绝缘层202及/或柔性绝缘层201之中的深度可视情况及需求而调整。
接着，如图4C所示，将柔性绝缘层201硬化为绝缘层201a以利于后续的暂时基底100移除步骤。在此实施例中，在硬化柔性绝缘层201的同时，也将柔性绝缘层202硬化为绝缘层202a。例如，可采用加热的方式使柔性绝缘层201与202的硬化同时进行。
或者，在其他实施例中，先在暂时基底100上形成已硬化的绝缘层201a，之后才在绝缘层201a上形成柔性绝缘层202。并接着接合芯片104与将柔性绝缘层202硬化为绝缘层202a。芯片104的接合例如可将部分的芯片104压入柔性绝缘层202中，并使与绝缘层201a直接接触。接着，可形成金属层106与后续的封装工艺。
图3A-图3F显示本发明数个实施例中的芯片封装体的示意图。图3A显示实施例的芯片封装体的剖面图。芯片封装体包括基底(即用作基底的介电层108)；第一凹槽302a，自基底(介电层108)的上表面108a向下延伸；金属层106，位于基底上，且顺应性覆盖在第一凹槽302a的侧壁与底部上；第一芯片104a，具有第一上表面105a，设置于第一凹槽302a中的金属层106上；以及保护层110，覆盖于第一芯片104a之上。本发明实施例的第一芯片104a的第一上表面105a不低于第一凹槽302a外的金属层106的上表面107。例如，第一芯片104a的第一上表面105a可高于第一凹槽302a外的金属层106的上表面107，或也可能大致与第一凹槽302a外的金属层106的上表面107共平面。在此实施例中，金属层106与第一芯片104a直接接触。当金属层106整面顺应性形成于芯片上时，第一芯片104a与第一凹槽302a中的全部的金属层106直接接触。此外，本发明实施例的芯片封装体还可包括设置于保护层上的导电结构112，其与第一芯片104a电性连接。此外，第一芯片104a的侧壁大致平行于第一凹槽302a的侧壁。
图3C显示实施例的芯片封装体的剖面图，其与图3A的结构相似。主要区别在于第一凹槽302a的侧壁倾斜于基底(即介电层108)的上表面108a，且第一芯片104a的侧壁也倾斜于基底，并大致平行于第一凹槽302a的侧壁。
请继续参照图3B，本发明实施例的芯片封装体可包括第二芯片104b(及/或其他更多芯片)，设置于第二凹槽302b中的金属层106上。第二凹槽302b自基底(即介电层108)的上表面108a向下延伸。与第一芯片104a相似，第二芯片104b的第二上表面105b也不低于第二凹槽302b外的金属层106的上表面107。第一凹槽302a与第二凹槽302b之间可具有不同的尺寸或形状。在此实施例中，金属层106与第二芯片104b直接接触。当金属层106整面顺应性形成于芯片上时，第二芯片104b与第二凹槽302b中的全部的金属层106直接接触。
在图3B的实施例中，第一芯片104a与第二芯片104b彼此间具有不同的尺寸及形状，且各自的功能也可不同。此实施例的芯片封装体也包括保护层110及设置于其上的第一导电结构112a及第二导电结构112b，分别电性连接至第一芯片104a及第二芯片104b。这些导电结构之一可同时电性连接至第一芯片104a及第二芯片104b，可作为两芯片间的信号传递桥梁。或者，两芯片可透过下方的金属层106而彼此传递信号。在其他实施例中，可进一步将金属层106图案化，使得第一凹槽302a中的金属层106不与第二凹槽302b中的金属层106电性连接。再者，第一导电结构112a及/或第二导电结构112b可视情况而与金属层106电性连接，例如可透过穿过保护层110的导电插塞。
此外，在实施例中，也可进一步将金属层106图案化，图案化后的金属层与基底(即介电层108)可共同组成无源元件，例如是电容、电感、或电阻等。例如图3D与图3E所示，金属层106经图案化后可包括第一金属图案106a与第二金属图案106b(如图3E所示)，其与基底可共同形成电容。形成于芯片底部的无源元件(电容)可例如透过金属层106与导电结构112而与芯片104内的特定元件电性连接。或者，形成于芯片底部的无源元件可直接透过芯片内部的导电通路而与芯片104内的特定元件电性连接。
本发明实施例的芯片封装体由于在芯片下形成有金属层，可使芯片运作时所产生的热能可顺利导出。芯片下的金属层还可有许多用途，例如可用作无源元件或接地。芯片封装体的导电结构(例如，焊球)分布于较大面积的保护层之上，可在舒缓导电结构的分布密度之余，还能有效利用保护层110上的面积，使整体***芯片封装体的尺寸缩小。由于本发明实施例的芯片封装体采用可硬化的柔性绝缘层来接合固定芯片，可便于控制芯片的高低位置，且柔性绝缘层于硬化后可轻易地移除，利于芯片封装体工艺的进行。
虽然本发明已以数个优选实施例披露如上，然其并非用以限定本发明，任何所属技术领域中普通技术人员，在不脱离本发明的精神和范围内，当可作任意的更动与润饰，因此本发明的保护范围当视后附的权利要求所界定为准。

Claims (20)

1.一种芯片封装体，包括：
基底；
第一凹槽，自该基底的上表面向下延伸；
金属层，位于该基底之上，且顺应性覆盖于该第一凹槽的侧壁与底部上；
第一芯片，具有第一上表面，设置于该第一凹槽中的该金属层上，该第一上表面不低于该第一凹槽外的该金属层的上表面；以及
保护层，覆盖于该第一芯片之上。
2.如权利要求1所述的芯片封装体，还包括至少一第一导电结构，设置于该保护层之上，该第一导电结构与该第一芯片或该金属层电性连接。
3.如权利要求1所述的芯片封装体，其中该第一凹槽的侧壁倾斜于该基底的该上表面。
4.如权利要求1所述的芯片封装体，还包括第一绝缘层，位于该金属层与该保护层之间，且该第一绝缘层的上表面不高于该第一芯片的该第一上表面。
5.如权利要求1所述的芯片封装体，还包括：
第二凹槽，自该基底的该上表面向下延伸，其中该金属层顺应性覆盖于该第二凹槽的侧壁与底部上；以及
第二芯片，具有第二上表面，设置于该第二凹槽中的该金属层上，该第二上表面不低于该第二凹槽外的该金属层的该上表面。
6.如权利要求5所述的芯片封装体，还包括至少一第二导电结构，设置于该保护层之上，该第二导电结构与该第二芯片或该金属层电性连接。
7.一种芯片封装体的形成方法，包括：
提供暂时基底；
在该暂时基底上形成第一柔性绝缘层；
在该第一柔性绝缘层上接合至少一芯片；
将该第一柔性绝缘层硬化为第一绝缘层；
在该暂时基底上形成金属层，该金属层顺应性覆盖于该第一绝缘层与该芯片之上；
在该金属层上形成介电层；
移除该暂时基底；
移除该第一绝缘层；以及
在该芯片上形成保护层。
8.如权利要求7所述的芯片封装体的形成方法，其中接合该芯片的步骤包括将部分的该芯片压入该第一柔性绝缘层中。
9.如权利要求7所述的芯片封装体的形成方法，其中该芯片的侧壁倾斜于该暂时基底的上表面。
10.如权利要求7所述的芯片封装体的形成方法，还包括于形成该第一柔性绝缘层之前，在该暂时基底上形成第二柔性绝缘层。
11.如权利要求10所述的芯片封装体的形成方法，其中于该第一柔性绝缘层上接合该芯片的步骤包括将部分的该芯片压入该第一柔性绝缘层中，并使该芯片与该第二柔性绝缘层直接接触。
12.如权利要求11所述的芯片封装体的形成方法，还包括将该第二柔性绝缘层硬化为第二绝缘层。
13.如权利要求12所述的芯片封装体的形成方法，其中该第二柔性绝缘层的硬化步骤与该第一柔性绝缘层的硬化步骤同时进行。
14.如权利要求10所述的芯片封装体的形成方法，还包括在形成该第一柔性绝缘层之前，将该第二柔性绝缘层硬化为第二绝缘层。
15.如权利要求14所述的芯片封装体的形成方法，其中接合该芯片的步骤包括将部分的该芯片压入该第一柔性绝缘层中，并使该芯片与该第二绝缘层直接接触。
16.一种芯片封装体的形成方法，包括：
提供暂时基底；
在该暂时基底上形成绝缘层；
在该绝缘层上形成柔性绝缘层；
在该柔性绝缘层上接合至少一芯片；
在该暂时基底上形成金属层，该金属层顺应性覆盖于该柔性绝缘层与该芯片之上；
在该金属层上形成介电层；
移除该暂时基底；
移除该柔性绝缘层；以及
在该芯片上形成保护层。
17.如权利要求16所述的芯片封装体的形成方法，其中接合该芯片的步骤包括将部分的该芯片压入该柔性绝缘层中。
18.如权利要求17所述的芯片封装体的形成方法，其中该芯片与该绝缘层直接接触。
19.如权利要求16所述的芯片封装体的形成方法，其中该绝缘层的形成包括于该暂时基底上形成第二柔性绝缘层，并将该第二柔性绝缘层硬化为该绝缘层。
20.如权利要求16所述的芯片封装体的形成方法，还包括在保护层上形成多个导电结构，所述导电结构电性连接至该芯片或该金属层。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104081521A (zh) * 2011-05-06 2014-10-01 3D加公司 用于在封装期间应用芯片支撑来生产重组晶片的方法

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9337116B2 (en) * 2010-10-28 2016-05-10 Stats Chippac, Ltd. Semiconductor device and method of forming stepped interposer for stacking and electrically connecting semiconductor die
DE112014006608B4 (de) * 2014-04-21 2024-01-25 Apple Inc. Verfahren, Systeme und elektronische Vorrichtungen zum Bestimmen der Kräfteaufteilung für Multi-Touch-Eingabevorrichtungen elektronischer Vorrichtungen
US10496213B2 (en) * 2015-02-27 2019-12-03 Tactual Labs Co. Alterable ground plane for touch surfaces
US20170102788A1 (en) * 2015-10-12 2017-04-13 Denso International America, Inc. Detachable operational device

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4966857A (en) * 1983-10-24 1990-10-30 Gao Gesellschaft Fur Automation Und Organisation Mbh Data carrier having an integrated circuit and a method for producing same
CN1253662A (zh) * 1997-04-30 2000-05-17 日立化成工业株式会社 半导体元件装配用基板及其制造方法和半导体器件
CN1543675A (zh) * 2000-12-15 2004-11-03 ض� 具有无凸块的叠片互连层的微电子组件
CN101256965A (zh) * 2007-03-01 2008-09-03 全懋精密科技股份有限公司 嵌埋半导体芯片的结构及其制法
US20080265383A1 (en) * 2007-04-30 2008-10-30 Infineon Technologies Ag Workpiece with Semiconductor Chips, Semiconductor Device and Method for Producing a Workpiece with Semiconductor Chips
CN101350338A (zh) * 2007-07-17 2009-01-21 南亚电路板股份有限公司 埋入式芯片基板结构
US20090039530A1 (en) * 2007-08-07 2009-02-12 Fryklund David J Near chip scale package integration process
CN101404267A (zh) * 2007-10-03 2009-04-08 松下电器产业株式会社 半导体装置与半导体装置的制造方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4966847A (en) * 1987-07-27 1990-10-30 Gary Stacey Recombinant DNA clones containing a broad host range gene from Bradyrhizobium japonicum
DE3923023A1 (de) * 1989-07-12 1991-01-24 Siemens Ag Uv-haertbarer klebstoff fuer ein halbleiterchipmontageverfahren
US5353498A (en) * 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
FR2736740A1 (fr) * 1995-07-11 1997-01-17 Trt Telecom Radio Electr Procede de production et d'assemblage de carte a circuit integre et carte ainsi obtenue
US6329213B1 (en) * 1997-05-01 2001-12-11 Micron Technology, Inc. Methods for forming integrated circuits within substrates
US6133634A (en) * 1998-08-05 2000-10-17 Fairchild Semiconductor Corporation High performance flip chip package
US6057601A (en) * 1998-11-27 2000-05-02 Express Packaging Systems, Inc. Heat spreader with a placement recess and bottom saw-teeth for connection to ground planes on a thin two-sided single-core BGA substrate
JP2004201285A (ja) * 2002-12-06 2004-07-15 Murata Mfg Co Ltd 圧電部品の製造方法および圧電部品
JP4082242B2 (ja) * 2003-03-06 2008-04-30 ソニー株式会社 素子転写方法
JP4200285B2 (ja) * 2003-04-02 2008-12-24 パナソニック株式会社 回路基板の製造方法
KR100510821B1 (ko) * 2003-06-09 2005-08-30 한국전자통신연구원 미세 구조물이 형성된 기판과 그 기판의 제조방법
TWI297537B (en) * 2006-06-26 2008-06-01 Univ Nat Cheng Kung Embedded metal heat sink for semiconductor device and method for manufacturing the same
US7911059B2 (en) * 2007-06-08 2011-03-22 SeniLEDS Optoelectronics Co., Ltd High thermal conductivity substrate for a semiconductor device
TWI355050B (en) * 2007-06-22 2011-12-21 Light Ocean Technology Corp Thin double-sided package substrate and manufactur
TW200901409A (en) * 2007-06-22 2009-01-01 Nan Ya Printed Circuit Board Corp Packaging substrate with embedded chip and buried heatsink
TWM354185U (en) * 2008-09-25 2009-04-01 Lighthouse Technology Co Ltd Improved packaging substrate and light-emitting device applying the same

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4966857A (en) * 1983-10-24 1990-10-30 Gao Gesellschaft Fur Automation Und Organisation Mbh Data carrier having an integrated circuit and a method for producing same
CN1253662A (zh) * 1997-04-30 2000-05-17 日立化成工业株式会社 半导体元件装配用基板及其制造方法和半导体器件
CN1543675A (zh) * 2000-12-15 2004-11-03 ض� 具有无凸块的叠片互连层的微电子组件
CN101256965A (zh) * 2007-03-01 2008-09-03 全懋精密科技股份有限公司 嵌埋半导体芯片的结构及其制法
US20080265383A1 (en) * 2007-04-30 2008-10-30 Infineon Technologies Ag Workpiece with Semiconductor Chips, Semiconductor Device and Method for Producing a Workpiece with Semiconductor Chips
CN101350338A (zh) * 2007-07-17 2009-01-21 南亚电路板股份有限公司 埋入式芯片基板结构
US20090039530A1 (en) * 2007-08-07 2009-02-12 Fryklund David J Near chip scale package integration process
CN101404267A (zh) * 2007-10-03 2009-04-08 松下电器产业株式会社 半导体装置与半导体装置的制造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104081521A (zh) * 2011-05-06 2014-10-01 3D加公司 用于在封装期间应用芯片支撑来生产重组晶片的方法
CN104081521B (zh) * 2011-05-06 2017-03-08 3D加公司 用于在封装期间应用芯片支撑来生产重组晶片的方法

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