TWI485825B - 晶片封裝體及其形成方法 - Google Patents

晶片封裝體及其形成方法 Download PDF

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TWI485825B
TWI485825B TW098145256A TW98145256A TWI485825B TW I485825 B TWI485825 B TW I485825B TW 098145256 A TW098145256 A TW 098145256A TW 98145256 A TW98145256 A TW 98145256A TW I485825 B TWI485825 B TW I485825B
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Taiwan
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insulating layer
wafer
forming
layer
chip package
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TW098145256A
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TW201104810A (en
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Baw Ching Perng
Chun Lung Huang
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Xintec Inc
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Publication of TW201104810A publication Critical patent/TW201104810A/zh
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Description

晶片封裝體及其形成方法
本發明係有關於晶片封裝體，且特別是有關於晶片下包覆有金屬層之晶片封裝體。
隨著半導體製程技術的不斷進步，可於更小的晶片中形成更多的半導體元件。除了使晶片的效能更為提升外，還能節省晶圓面積而降低成本。然而，隨著晶片尺寸縮小化與元件密度之增加，其輸出/輸入連接(I/O)之數目與密度亦增加，造成晶片與外界間的導電通路形成不易。此外，縮小化晶片中的高密度元件於運作時，容易產生過多的熱能而影響晶片的效能。
本發明一實施例提供一種晶片封裝體，包括基底；一凹槽，自基底之上表面向下延伸；金屬層，位於基底之上，且順應性覆蓋於此凹槽之側壁與底部上；一晶片，具有一上表面，設置於凹槽中之金屬層上，此晶片之上表面不低於凹槽外之金屬層之上表面；以及保護層，覆蓋於晶片之上。
本發明一實施例提供一種晶片封裝體的形成方法，包括提供暫時基底；於暫時基底上形成軟性絕緣層；於軟性絕緣層上接合晶片；將軟性絕緣層硬化為絕緣層；於暫時基底上形成金屬層，金屬層順應性覆蓋於絕緣層與晶片之上；於金屬層上形成介電層；移除暫時基底；移除絕緣層；以及於晶片上形成保護層。
本發明另一實施例提供一種晶片封裝體的形成方法，包括提供暫時基底；於暫時基底上形成絕緣層；於絕緣層上形成軟性絕緣層；於軟性絕緣層上接合至少一晶片；於暫時基底上形成金屬層，金屬層順應性覆蓋於軟性絕緣層與晶片之上；於金屬層上形成介電層；移除暫時基底；移除軟性絕緣層；以及於晶片上形成保護層。
以下將詳細說明本發明實施例之製作與使用方式。然應注意的是，本發明提供許多可供應用的發明概念，其可以多種特定型式實施。文中所舉例討論之特定實施例僅為製造與使用本發明之特定方式，非用以限制本發明之範圍。此外，在不同實施例中可能使用重複的標號或標示。這些重複僅為了簡單清楚地敘述本發明，不代表所討論之不同實施例及/或結構之間具有任何關連性。再者，當述及一第一材料層位於一第二材料層上或之上時，包括第一材料層與第二材料層直接接觸或間隔有一或更多其他材料層之情形。
第1A-1G圖顯示本發明一實施例之晶片封裝體的一系列製程剖面圖。如第1A圖所示，提供暫時基底100。暫時基底100包括半導體材料、絕緣材料、金屬材料、或前述之組合。在一實施例中，暫時基底100例如為矽晶圓或矽基底等。
接著，於暫時基底100上形成軟性絕緣層102。在後續製程中，軟性絕緣層102將用以固定設置於其上之晶片，因此軟性絕緣層較佳能使晶片陷入於其中而固定。軟性絕緣層102之材質例如為蠟、高分子材料、或前述之組合。軟性絕緣層102之形成方式例如包括網印塗佈(screen printing)、膠膜塗佈(lamination printing)、或旋轉塗佈(spin coating)。
如第1B圖所示，接著於軟性絕緣層102上接合一晶片104。此外，在其他實施例中，可於軟性絕緣層102上接合一個以上的其他晶片104。晶片與晶片之間可為不同種類的晶片，而各有其運作效能。例如，在一實施例中，晶片104可包括邏輯運算晶片、微機電系統晶片、微流體系統晶片、或利用熱、光線及壓力等物理變化量來測量的物理感測器晶片、射頻元件晶片、加速計晶片、陀螺儀晶片、微制動器晶片、表面聲波元件晶片、壓力感測器晶片、噴墨頭晶片、發光元件晶片、或太陽能電池晶片等。此外，晶片與晶片之間的尺寸或形狀可彼此不同。此外，雖然第1B圖中之晶片104的側壁大抵垂直於暫時基底100之上表面，然在其他實施例中，可選用或形成側壁傾斜於暫時基底100之上表面的晶片，可使後續形成之材料層(例如，金屬層)較容易順應性沉積。
在一實施例中，晶片104的接合步驟包括將晶片104壓入軟性絕緣層102中。如第1B圖所示，晶片104被部分壓入軟性絕緣層102中而固定。
如第1C圖所示，接著將軟性絕緣層102硬化為絕緣層102a。硬化後之絕緣層102a除了可進一步固定晶片104外，還可使暫時基底100較易於後續製程中移除。在一實施例中，軟性絕緣層102之硬化步驟包括以紫外線照射或是對軟性絕緣層102加熱而使之硬化為絕緣層102a。加熱溫度可視所採用之軟性絕緣層102的材質而定，例如可介於約120℃至約350℃之間。
接著，如第1C圖所示，於暫時基底100上形成金屬層106。金屬層106順應性覆蓋於絕緣層102a及晶片104上。在此實施例中，金屬層106係與晶片104直接接觸。在其他實施例中，可視情況於晶片104與金屬層106之間形成其他材料層，例如可為介電層或其他導電層等。金屬層106的形成方式例如可為物理氣相沉積、濺鍍、化學氣相沉積、電鍍、或無電鍍等。在一實施例中，金屬層106係整面地順應性形成於晶片104上。在另一實施例中，可進一步視需求而將金屬層106圖案化。例如，圖案化後金屬層106可作為晶片104下方之一被動元件的一部分。此外，金屬層106之形成有助於晶片104之散熱，或者可用作接地。
接著，如第1D圖所示，於金屬層106上形成介電層108。介電層108之材質可例如為環氧樹脂、防銲材料、或其他適合之絕緣物質，例如無機材料之氧化矽層、氮化矽層、氮氧化矽層、金屬氧化物、或前述之組合；或亦可為有機高分子材料之聚醯亞胺樹脂(polyimide)、苯環丁烯(butylcyclobutene,BCB,道氏化學公司)、聚對二甲苯(parylene)、萘聚合物(polynaphthalenes)、氟碳化物(fluorocarbons)、丙烯酸酯(acrylates)等。介電層108的形成方式可包含塗佈方式，例如旋轉塗佈(spin coating)、噴塗(spray coating)、或淋幕塗佈(curtain coating)，或其他適合之沈積方式，例如，液相沈積、物理氣相沈積、化學氣相沈積、低壓化學氣相沈積、電漿增強式化學氣相沈積、快速熱化學氣相沈積、或常壓化學氣相沈積等製程。在後續製程中，將改以介電層108作為承載晶片104之基底，因此介電層108較佳具有大抵平坦之上表面。
如第1E圖所示，將暫時基底100自已硬化之絕緣層102a之表面移除。接著，如第1F圖所示，移除絕緣層102a。在一實施例中，硬化後之絕緣層102a的材質為蠟，因此可輕易地移除。絕緣層102a之移除方式例如包括加熱到蠟融化的溫度如100℃再藉外力移除。在此實施例中，晶片104的上表面高於兩旁之金屬層106的上表面。在另一實施例中，當晶片104僅接合於軟性絕緣層102上而不陷入其中時，晶片104將整個位於介電層108中，因此晶片的上表面將與兩旁之金屬層106的上表面大抵等高而共平面。
如第1G圖所示，改以介電層108為基底，於晶片104上形成保護層110。保護層110之材質與形成方式可類似於介電層108。保護層110可保護晶片104免於受到外力衝擊或外界污染。
在第1G圖所示實施例中，進一步於保護層110上形成導電結構112。導電結構112進一步例如透過導通孔(未顯示)而電性連接至晶片104。在一實施例中，每一導電結構112個別電性連接至一晶片104。在另一實施例中，其中一導電結構112可同時電性連接至兩個(或以上)不同的晶片104，形成兩不同晶片問之訊號傳遞橋樑。應注意的是，同一晶片104可能與數個導電結構112相連，但不代表這些導電結構112彼此間係電性連接。這些導電結構112可能電性連接至晶片104中之不同接墊或元件區而彼此電性絕緣。在又一實施例中，導電結構112可電性連接至金屬層106，此時例如可作為接地電極。
在一實施例中，導電結構112例如是銲球。隨著晶片104尺寸縮小化與元件密度之增加，其輸出/輸入連接(I/O)之數目與密度亦增加，此時於有限的晶片面積上形成導電結構(例如，植球製程)是很困難的。本發明實施例透過形成保護層110，可使導電結構112(如銲球)分佈在較大面積的保護層110上，有助於舒緩植球密度過密之問題。本發明實施例較佳整合多晶片，使眾多晶片之對應銲球共同分佈在保護層110之上，可在舒緩導電結構的分佈密度之餘，還能有效利用保護層110上之面積，使整體晶片系統封裝體的尺寸縮小。
第2A-2G圖顯示本發明另一實施例之晶片封裝體的一系列製程剖面圖，其中相似的元件將採用相似或相同的標號，且相似或相同的材料層之材質與其形成方式將不重複敘述。
如第2A圖所示，提供暫時基底100。接著，於暫時基底100上形成絕緣層101a。絕緣層101a之材質例如為蠟、高分子材料、或前述之組合。在一實施例中，可先於暫時基底上形成軟性絕緣層，並接著將之硬化為絕緣層101a。例如，可透過加熱或照射光線(如紫外光)之方式將軟性絕緣層硬化為絕緣層101a。接著，於絕緣層101a上形成軟性絕緣層102。
如第2B圖所示，接著於軟性絕緣層102上接合至少一晶片104。在一實施例中，晶片104的接合步驟包括將晶片104壓入軟性絕緣層102中。如第2B圖所示，在此實施例中，晶片104被部分壓入軟性絕緣層102中而固定，且與絕緣層101a直接接觸。
接著，如第2C圖所示，於暫時基底100上形成金屬層106。金屬層106順應性覆蓋於軟性絕緣層102及晶片104上。在此實施例中，金屬層106係與晶片104直接接觸。在其他實施例中，可視情況於晶片104與金屬層106之間形成其他材料層，例如可為介電層或其他導電層等。金屬層106的形成方式例如可為物理氣相沉積、濺鍍、化學氣相沉積、電鍍、或無電鍍等。其中，當以濺鍍法形成金屬層106時，由於在絕緣層101a上形成了軟性絕緣層102，可保護其下之絕緣層101a免於離子轟擊而變質，有利於後續的移除步驟。
接著，如第2D圖所示，於金屬層106上形成介電層108。在後續製程中，將改以介電層108作為承載晶片104之基底，因此介電層108較佳具有大抵平坦之上表面。
如第2E圖所示，將暫時基底100自絕緣層101a之表面移除。接著，如第2F圖所示，移除絕緣層101a。在一實施例中，絕緣層101a的材質為蠟，且受到軟性絕緣層102之保護而免於變質，因此可輕易地移除。在第2F圖之實施例中，軟性絕緣層102仍保留，其上表面大抵與晶片104之上表面共平面。在另一實施例中，可完全或部分移除軟性絕緣層102。在又一實施例中，可將軟性絕緣層102硬化。
如第2G圖所示，改以介電層108為基底，於晶片104上形成保護層110。保護層110可保護晶片104免於受到外力衝擊或外界污染。在第2G圖所示實施例中，進一步於保護層110上形成複數個導電結構112。導電結構112進一步例如透過導通孔(未顯示)而電性連接至晶片104。
在第2G圖所示實施例中，絕緣層(軟性絕緣層102或其硬化後之絕緣層)位於金屬層106與保護層110之間，且其上表面不高於晶片104之上表面。例如，第2F圖之實施例中，絕緣層之上表面係與晶片104之上表面大抵等高而共平面。或者，在其他實施例中，可移除部份的絕緣層而使絕緣層102之上表面低於晶片104之上表面。
本發明實施例之晶片104的接合步驟不限於上述型式。例如，第4A-4C圖顯示本發明一實施例之晶片接合步驟的一系列製程剖面圖。如第4A圖所示，係於暫時基底100上依次形成軟性絕緣層201與軟性絕緣層202。接著，如第4B圖所示，於軟性絕緣層202上接合至少一晶片104。在此實施例中，晶片104的接合步驟包括將晶片104壓入軟性絕緣層202中。如第4B圖所示，晶片104被部分壓入軟性絕緣層202中而固定，且與軟性絕緣層201直接接觸。在另一實施例中，晶片104僅陷入軟性絕緣層202中，但不與軟性絕緣層201直接接觸。在又一實施例中，晶片104穿過軟性絕緣層201與軟性絕緣層202之間的界面而部分陷於軟性絕緣層201之中。晶片104陷於軟性絕緣層202及/或軟性絕緣層201之中的深度可視情況及需求而調整。
接著，如第4C圖所示，將軟性絕緣層201硬化為絕緣層201a以利於後續的暫時基底100移除步驟。在此實施例中，於硬化軟性絕緣層201的同時，亦將軟性絕緣層202硬化為絕緣層202a。例如，可採用加熱之方式使軟性絕緣層201與202之硬化同時進行。
或者，在其他實施例中，係先於暫時基底100上形成已硬化之絕緣層201a，之後才於絕緣層201a上形成軟性絕緣層202。並接著接合晶片104與將軟性絕緣層202硬化為絕緣層202a。晶片104之接合例如可將部分的晶片104壓入軟性絕緣層202中，並使與絕緣層201a直接接觸。接著，可形成金屬層106與後續的封裝製程。
第3A-3E圖顯示本發明數個實施例中之晶片封裝體的示意圖。第3A圖顯示一實施例之晶片封裝體的剖面圖。晶片封裝體包括基底(即用作基底之介電層108)；第一凹槽302a，自基底(介電層108)之上表面108a向下延伸；金屬層106，位於基底上，且順應性覆蓋於第一凹槽302a之側壁與底部上；第一晶片104a，具有第一上表面105a，設置於第一凹槽302a中之金屬層106上；以及保 護層110，覆蓋於第一晶片104a之上。本發明實施例之第一晶片104a的第一上表面105a不低於第一凹槽302a外之金屬層106的上表面107。例如，第一晶片104a的第一上表面105a可高於第一凹槽302a外之金屬層106的上表面107，或亦可能大抵與第一凹槽302a外之金屬層106的上表面107共平面。在此實施例中，金屬層106係與第一晶片104a直接接觸。當金屬層106係整面順應性形成於晶片上時，第一晶片104a與第一凹槽302a中之全部的金屬層106直接接觸。此外，本發明實施例之晶片封裝體還可包括設置於保護層上之導電結構112，其與第一晶片104a電性連接。此外，第一晶片104a之側壁大抵平行於第一凹槽302a之側壁。
第3C圖顯示一實施例之晶片封裝體的剖面圖，其與第3A圖之結構相似。主要區別在於第一凹槽302a之側壁係傾斜於基底(即介電層108)之上表面108a，且第一晶片104a之側壁亦傾斜於基底，並大抵平行於第一凹槽302a之側壁。
請繼續參照第3B圖，本發明實施例之晶片封裝體可包括第二晶片104b(及/或其他更多晶片)，設置於第二凹槽302b中之金屬層106上。第二凹槽302b係自基底(即介電層108)之上表面108a向下延伸。與第一晶片104a相似，第二晶片104b之第二上表面105b亦不低於第二凹槽302b外之金屬層106的上表面107。第一凹槽302a與第二凹槽302b之間可具有不同的尺寸或形狀。在此實施例中，金屬層106係與第二晶片104b直接接觸。當金 屬層106係整面順應性形成於晶片上時，第二晶片104b與第二凹槽302b中之全部的金屬層106直接接觸。
在第3B圖之實施例中，第一晶片104a與第二晶片104b彼此間具有不同的尺寸及形狀，且各自的功能亦可不同。此實施例之晶片封裝體亦包括保護層110及設置於其上之第一導電結構112a及第二導電結構112b，分別電性連接至第一晶片104a及第二晶片104b。這些導電結構之一可同時電性連接至第一晶片104a及第二晶片104b，可作為兩晶片間的訊號傳遞橋樑。或者，兩晶片可透過下方之金屬層106而彼此傳遞訊號。在其他實施例中，可進一步將金屬層106圖案化，使得第一凹槽302a中之金屬層106不與第二凹槽302b中之金屬層106電性連接。再者，第一導電結構112a及/或第二導電結構112b可視情況而與金屬層106電性連接，例如可透過穿過保護層110之導電插塞。
此外，在一實施例中，亦可進一步將金屬層106圖案化，圖案化後之金屬層與基底(即介電層108)可共同組成被動元件，例如是電容、電感、或電阻等。例如第3D圖與第3E圖所示，金屬層106經圖案化後可包括第一金屬圖案106a與第二金屬圖案106b(如第3E圖所示)，其與基底可共同形成一電容。形成於晶片底部之被動元件(電容)可例如透過金屬層106與導電結構112而與晶片104內之特定元件電性連接。或者，形成於晶片底部之被動元件可直接透過晶片內部的導電通路而與晶片104內之特定元件電性連接。
本發明實施例之晶片封裝體由於在晶片下形成有金屬層，可使晶片運作時所產生之熱能可順利導出。晶片下之金屬層還可有許多用途，例如可用作被動元件或接地。晶片封裝體之導電結構(例如，銲球)係分佈於較大面積的保護層之上，可在舒緩導電結構的分佈密度之餘，還能有效利用保護層110上之面積，使整體系統晶片封裝體的尺寸縮小。由於本發明實施例之晶片封裝體採用可硬化之軟性絕緣層來接合固定晶片，可便於控制晶片之高低位置，且軟性絕緣層於硬化後可輕易地移除，利於晶片封裝體製程的進行。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100‧‧‧暫時基底
102、201、202‧‧‧軟性絕緣層
102a、101a、201a、202a‧‧‧絕緣層
104、104a、104b‧‧‧晶片
106‧‧‧金屬層
106a、106b‧‧‧金屬圖案
108‧‧‧介電層
110‧‧‧保護層
112、112a、112b‧‧‧導電結構
302a、302b‧‧‧凹槽
105a、105b、107、108a‧‧‧表面
第1A-1G圖顯示本發明一實施例之晶片封裝體的一系列製程剖面圖。
第2A-2G圖顯示本發明另一實施例之晶片封裝體的一系列製程剖面圖。
第3A-3E圖顯示本發明數個實施例中之晶片封裝體的示意圖。
第4A-4C圖顯示本發明一實施例之晶片接合步驟的一系列製程剖面圖。
104．．．晶片
106．．．金屬層
108．．．介電層
110．．．保護層
112．．．導電結構

Claims (20)

  1. 一種晶片封裝體的形成方法，包括：提供一暫時基底；於該暫時基底上形成一第一軟性絕緣層；於該第一軟性絕緣層上接合至少一晶片；將該第一軟性絕緣層硬化為一第一絕緣層；於該暫時基底上形成一金屬層，該金屬層順應性覆蓋於該第一絕緣層與該晶片之上；於該金屬層上形成一介電層；移除該暫時基底；移除該第一絕緣層；以及於該晶片上形成一保護層。
  2. 如申請專利範圍第1項所述之晶片封裝體的形成方法，其中接合該晶片的步驟包括將部分的該晶片壓入該第一軟性絕緣層中。
  3. 如申請專利範圍第1項所述之晶片封裝體的形成方法，其中該第一軟性絕緣層之硬化步驟包括對該第一軟性絕緣層加熱或以紫外線照射而使硬化為該第一絕緣層。
  4. 如申請專利範圍第1項所述之晶片封裝體的形成方法，其中該第一軟性絕緣層之材質包括蠟。
  5. 如申請專利範圍第1項所述之晶片封裝體的形成方法，其中該晶片之一側壁傾斜於該暫時基底之一上表面。
  6. 如申請專利範圍第1項所述之晶片封裝體的形成 方法，更包括於形成該第一軟性絕緣層之前，於該暫時基底上形成一第二軟性絕緣層。
  7. 如申請專利範圍第6項所述之晶片封裝體的形成方法，其中於該第一軟性絕緣層上接合該晶片的步驟包括將部分的該晶片壓入該第一軟性絕緣層中，並使該晶片與該第二軟性絕緣層直接接觸。
  8. 如申請專利範圍第7項所述之晶片封裝體的形成方法，更包括將該第二軟性絕緣層硬化為一第二絕緣層。
  9. 如申請專利範圍第8項所述之晶片封裝體的形成方法，其中該第二軟性絕緣層之硬化步驟與該第一軟性絕緣層之硬化步驟係同時進行。
  10. 如申請專利範圍第6項所述之晶片封裝體的形成方法，更包括於形成該第一軟性絕緣層之前，將該第二軟性絕緣層硬化為一第二絕緣層。
  11. 如申請專利範圍第10項所述之晶片封裝體的形成方法，其中接合該晶片的步驟包括將部分的該晶片壓入該第一軟性絕緣層中，並使該晶片與該第二絕緣層直接接觸。
  12. 如申請專利範圍第1項所述之晶片封裝體的形成方法，更包括在形成該介電層之前，將該金屬層圖案化，圖案化後之該金屬層與該介電層共同組成一被動元件。
  13. 一種晶片封裝體的形成方法，包括：提供一暫時基底；於該暫時基底上形成一絕緣層； 於該絕緣層上形成一軟性絕緣層；於該軟性絕緣層上接合至少一晶片；於該暫時基底上形成一金屬層，該金屬層順應性覆蓋於該軟性絕緣層與該晶片之上；於該金屬層上形成一介電層；移除該暫時基底；移除該軟性絕緣層；以及於該晶片上形成一保護層。
  14. 如申請專利範圍第13項所述之晶片封裝體的形成方法，其中接合該晶片的步驟包括將部分的該晶片壓入該軟性絕緣層中。
  15. 如申請專利範圍第14項所述之晶片封裝體的形成方法，其中該晶片與該絕緣層直接接觸。
  16. 如申請專利範圍第13項所述之晶片封裝體的形成方法，其中該絕緣層之形成包括於該暫時基底上形成一第二軟性絕緣層，並將該第二軟性絕緣層硬化為該絕緣層。
  17. 如申請專利範圍第16項所述之晶片封裝體的形成方法，其中該絕緣層之材質包括蠟。
  18. 如申請專利範圍第13項所述之晶片封裝體的形成方法，更包括於保護層上形成複數個導電結構，該些導電結構電性連接至該晶片或該金屬層。
  19. 一種晶片封裝體，由上述申請專利範圍第1至12項其中一項所述之形成方法而製成。
  20. 一種晶片封裝體，由上述申請專利範圍第13至 18項其中一項所述之形成方法而製成。
TW098145256A 2009-07-28 2009-12-28 晶片封裝體及其形成方法 TWI485825B (zh)

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