CN101887879A - 内埋式单层金属层基板、应用之封装件及基板制造方法 - Google Patents

内埋式单层金属层基板、应用之封装件及基板制造方法 Download PDF

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CN101887879A
CN101887879A CN2009101659176A CN200910165917A CN101887879A CN 101887879 A CN101887879 A CN 101887879A CN 2009101659176 A CN2009101659176 A CN 2009101659176A CN 200910165917 A CN200910165917 A CN 200910165917A CN 101887879 A CN101887879 A CN 101887879A
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layer
dielectric layer
patterned metal
pattern dielectric
metal layer
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CN101887879B (zh
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黄士辅
苏洹漳
陈嘉成
陈家庆
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Abstract

一种单层金属层基板结构，应用于一封装件，其基板结构包括一第一图案化介电层(first patterned dielectric layer)、一图案化金属层(patterned metal layer)和一第二图案化介电层(second patterned dielectric layer)。图案化金属层内埋于第一图案化介电层，且图案化金属层的上表面与第一图案化介电层的上表面为一共平面，其中第一图案化介电层的下表面至少暴露出部分图案化金属层，以形成下方对外电性连接的数个第一接点。第二图案化介电层位于图案化金属层和第一图案化介电层的上方，且第二图案化介电层至少暴露出图案化金属层的部分上表面，以形成上方对外电性连接的数个第二接点。封装件结构则包括至少一晶粒(die)与上述基板的第二接点电性连接，和覆盖第一图案化介电层、图案化金属层、第二图案化介电层和晶粒的胶体(Molding Compound)。

Description

内埋式单层金属层基板、应用之封装件及基板制造方法
技术领域
本发明是有关于一种基板结构、应用之封装件结构及基板的制造方法，且特别是有关于一种内埋式单层金属层的基板及其封装件结构、和基板的制造方法。
背景技术
集成电路(IC)构装技术是电子产业中重要的一环，电子构装主要的功用在于保护、支撑、线路配置与制造出散热途径，并提供零件一个模块化与规格标准。在1990年代主要是利用球栅数组(Ball Grid Array，BGA)的封装方式进行电子构装，其优点为散热性佳与电性好、接脚数可以大量增加，可有效缩小封装体面积。
然而，随着全球个人计算机、消费性电子产品及通讯产品不断要求轻薄短小更要具备高效能的趋势下，芯片所要求的电气特性不但要愈好，整体体积要愈小，但I/O端口的数目却是往上提高。随着I/O数量增加、积体化线路间距缩小，要想在BGA基板上高效率地布置走线变得困难，例如在点18工艺(线宽0.18μm)或是高速(如800MHz以上)的IC设计上，有大幅增加I/O密度的趋势。因此开发出具有高I/O、细微的线路间距、和优良电性的载板一直是各载板厂争相努力的目标。除了这些需求，下游产品***整合化的要求将日趋明显，因此多芯片模块(Multi-chip Module，MCM)工艺对MCM载板的需求也大幅提高。而快速增加的微电子***需求(特别是关于***大小和芯片整合增益部分)也更加速了芯片级尺寸封装(Chip Scale Packaging，CSP)技术的采用。
随着芯片级尺寸封装(CSP)技术的成熟，追求性能与成本的***型半导体封装方式-***封装(System in Package，SiP)也成为封装技术的主流，主要是因为产品的尺寸越来越小、功能越趋繁多，必须应用SiP技术以满足市场的需求。***封装SiP包括了将芯片(Chip)或是被动组件(Passive Components)或是其它模块进行构装。***封装也包括了不同技术如PiP(Package in Package)、PoP(Package on Package)、平面型的多芯片模块封装、或是为节省面积将不同功能芯片堆栈(Stack)起来的3D堆栈封装，这些都属于***封装(SiP)技术的发展范畴，该用何种型态封装也视应用需求而有所差异。因此SiP的定义十分广泛。在***封装(SiP)技术中，所使用的接合技术也有很多种，例如是打线连接(Wire Bonding)、覆晶式(Flip Chip)接合和使用多种接合技术(Hybrid-type)等等。
以***封装(System in Package)裸晶为例，它可将不同数字或模拟功能的裸晶，以凸块(Bump)或打线(Wire Bond)方式连结于芯片载板上，该载板中已有部分内埋被动组件或线路设计，此具有电性功能的载板，称为整合性基板(Integrated Substrate)或功能性基板(Functional Substrate)。请参照第1A～1F图，其绘示一种传统整合性基板的工艺示意图。首先，提供一铜箔基板(copper clad laminate，CCL)，在一中心层(Core)102的上下表面各形成第一导电层103和第二导电层104，导电层的材料例如是金属铜，如图1A所示。接着，对铜箔基板进行钻孔，形成孔洞106，接着整体镀上铜层107，其铜层107形成于第一导电层103和第二导电层104上方，和孔洞内壁，如图1B、1C所示。之后，对于中心层102上下两侧的金属铜层进行图案化，以形成整合性基板所需的线路图形。如图1D所示，在中心层102上下两侧的金属铜层上分别形成(ex：曝光显影)图案化干膜108，再如图1E所示对金属铜层进行蚀刻，最后如图1F所示去除图案化干膜108，完成导线(Metal traces)的制作。之后可以再进行后续工艺，例如印制上防焊绿漆(Solder mask，SM)并对绿漆曝光/显影而暴露出所需的导线表面，再对导线表面进行处理如镀上镍/金(Ni/Au)，而完成最后产品。
另外，也有更高阶的整合性基板在工艺中是将通孔部份直接镀满导电材料(如金属铜)，再对于中心层上下两侧的金属铜层进行图案化，以形成整合性基板所需的线路图形，如图2所示，其为另一种传统整合性基板的示意图。然而，将通孔镀满的技术较为复杂，也需较长时间镀制，且金属铜层115、116、117厚度控制不易(特别是金属铜层117的部份)。又图1F和图2所示的基板结构主要是有2层导电铜层分别形成于中心层102/112的上下两侧，因此又习称为”2层基板”。
当电子产品的体积日趋缩小，所采用的基板结构的体积和线路间距也必须随的减小。然而，在目前现有的基板结构和工艺技术能力下，不论是如图1F或图2所示的基板态样，要使基板再薄化和线路间距再缩小的可能性很小，不利于应用在小型尺寸的电子产品上。再者，对于定位在较低市场价格的小型电子产品，除了尺寸和性能，其基板的制造成本也是必须考虑的重要因素之一。因此，如何开发出新颖的薄型整合性基板，不但工艺快速简单又适合量产，并可兼具低制造成本和高产品良率的优点，以符合应用电子产品对于尺寸、外型轻薄化和价格的需求，实为相关业者努力的一大重要目标。
发明内容
本发明是有关于一种内埋式单层金属层基板及应用其的封装件结构、和基板的制造方法。其基板制作主要是应用第一图案化介电层、图案化金属层和第二图案化介电层等三层结构，且图案化金属层内埋于第一图案化介电层。所形成的基板结构整体厚度降低，且工艺简单快速，适合量产，亦可降低制造成本但保有高产品良率，符合市场产品轻薄化和低成本的需求。
根据本发明，提出一种单层金属层基板结构，包括一第一图案化介电层(first patterned dielectric layer)、一图案化金属层(patterned metal layer)和一第二图案化介电层(second patterned dielectric layer)。图案化金属层内埋于第一图案化介电层，且图案化金属层的上表面与第一图案化介电层的上表面为一共平面，其中第一图案化介电层的下表面至少暴露出部分图案化金属层，以形成下方对外电性连接的数个第一接点。第二图案化介电层位于该图案化金属层及第一图案化介电层上方，且第二图案化介电层至少暴露出图案化金属层的部分上表面，以形成上方对外电性连接的数个第二接点。
根据本发明，提出一种封装件结构，包括：上述的基板结构；至少一晶粒(die)与第二接点电性连接；和一胶体(Molding Compound)，配置于第一图案化介电层的上表面上方，并覆盖第一图案化介电层、图案化金属层、第二图案化介电层和晶粒。
根据本发明，提出一种单层金属层基板的制造方法，包括：形成一图案化金属层；形成一第一图案化介电层于图案化金属层的下表面处；和形成一第二图案化介电层于图案化金属层的上表面处。其中，图案化金属层的上表面与第一图案化介电层的上表面成一平面，且第一图案化介电层的下表面至少暴露出部分图案化金属层的下表面，以形成下方对外电性连接的数个第一接点。形成第二图案化介电层于图案化金属层的上表面时，第二图案化介电层至少暴露出图案化金属层的部分上表面，以形成上方对外电性连接的数个第二接点。
为让本发明的上述内容能更明显易懂，下文特举较佳实施例，并配合所附图式，作详细说明如下：
附图说明
图1A～1F绘示一种传统整合性基板的工艺示意图。
图2为另一种传统整合性基板的示意图。
图3A～3I绘示本发明第一实施例的单层金属层基板的制造方法。
图4是绘示应用本发明第一实施例的图3I基板的封装件示意图。
图5A绘示本发明第二实施例的单层金属层基板的示意图。
图5B绘示应用本发明第二实施例的图5A基板的封装件示意图。
主要组件符号说明
102：中心层
103：第一导电层
104：第二导电层
106：孔洞
107、115、116、117：铜层
108：图案化干膜
20：载板
201、202：金属箔膜
301、302：图案化金属层
303、304：第一图案化介电层
305、306：第二图案化介电层
303a、303b、304a、304b、305a、305b、306a、306b：开口
308a：第一表面处理层
308b：第二表面处理层
3013：第二接点
3015：第一接点
3017：芯片垫
41、42：结构体
51、52：基板结构
522：芯片容置区域
61、62封装件结构
601黏性物质
602晶粒
603a、603b焊线
607胶体
d1、d2间距
h1第二图案化介电层的厚度
h2晶粒的厚度
具体实施方式
本发明提出一种内埋式单层金属层基板及应用其的封装件结构、和基板的制造方法，主要是应用第一图案化介电层、图案化金属层和第二图案化介电层等三层结构形成基板，其中，图案化金属层(patterned metal layer)内埋于第一图案化介电层，且图案化金属层的上表面与第一图案化介电层的上表面共平面，第一图案化介电层的下表面至少暴露出部分图案化金属层，以形成下方对外电性连接的数个第一接点(例如为锡球垫，ball pads)。。。第二图案化介电层则位于图案化金属层上方，且第二图案化介电层至少暴露出图案化金属层的部分上表面，以形成上方对外电性连接的数个第二接点(例如为焊垫，bonding pads)。
相较于传统的”2层基板”结构，本发明所提出的基板结构及应用此基板的封装件其整体厚度大为降低，轻薄的外型十分适合小尺寸应用产品的需求。再者，本发明所提出的基板结构及应用此基板的封装件，及其相关制造方法，不但工艺快速简单又适合量产，亦可兼具低制造成本和高产品良率的优点，符合应用电子产品对于尺寸、外型轻薄化和低价格的需求。特别是对于市场价格较低的小型电子产品，更是具有市场竞争力。
以下根据本发明提出实施例，以详细说明本发明的基板结构及应用的封装件的制造方法。然而，实施例中所提出的基板结构仅为举例说明之用，并非作为限缩本发明保护范围之用。应用时可依实际条件的需求对基板的结构态样稍作修改。再者，实施例的图标仅绘示本发明技术的相关组件，省略不必要的组件，以清楚显示本发明的技术特点。
第一实施例
请参照图3A～3I，其绘示本发明第一实施例的单层金属层基板的制造方法。首先，形成一内埋式图案化金属层。在第一实施例中应用一载板(carrier)完成图案化金属层的制作作说明，但本发明并不以此为限。
如图3A所示，提供一载板20，且载板20的上下表面皆具有一金属箔膜(metal foil)201、202。实际应用时，例如是使用厚度约12μm的铜箔作为金属箔膜201、202。
之后，如图3B所示，在金属箔膜201、202上各形成一图案化金属层301、302。其中，形成图案化金属层301、302的步骤例如是：分别形成一金属层(未显示)于金属箔膜201、202上，再形成干膜(dry film，未显示)于金属层上并进行曝光和显影以图案化干膜，根据干膜的图案对金属层进行蚀刻完成影像转移，以形成图案化金属层301、302，完成影像转移后移除图案化干膜。
接着，如图3C所示，在图案化金属层301、302的下表面处各形成一第一图案化介电层303、304，且第一图案化介电层303的下表面具有数个开口303a、303b，以暴露出部分图案化金属层301的下表面。同样的，第一图案化介电层304的下表面具有数个开口304a、304b，以暴露出部分图案化金属层302的下表面。
然后，如图3D所示，将目前载板20上所形成的结构体41、42自载板20上移除。其中，结构体41包括金属箔膜201、图案化金属层301和第一图案化介电层303；同样的，位于载板20另一侧的结构体42包括金属箔膜202、图案化金属层302和第一图案化介电层304。
接着，反转并重新设置结构体41、42，使两第一图案化介电层303、304的下表面分别设置于载体20上，如图3E所示。
之后，如图3F所示，移除金属箔膜201、202，此时图案化金属层301的上表面与第一图案化介电层303的上表面共平面；同样的，位于载板20另一侧的图案化金属层302的上表面与第一图案化介电层304的上表面齐平。因此，图案化金属层301、302分别内埋于第一图案化介电层303、304中。
然后，如图3G所示，于图案化金属层301、302和第一图案化介电层303、304的上表面处分别形成一第二图案化介电层305、306，且第二图案化介电层305、306分别具有开口305a、305b、306a、306b，以至少暴露出图案化金属层301、302的部分上表面。
接着，将所形成的结构自载板20上移除，如图3H所示。
以载板20上侧的基板结构为例，第一图案化介电层303的下表面至少暴露出部分图案化金属层301的下表面，以形成基板下方对外电性连接的数个第一接点3015，例如在某些应用例中可在第一接点处形成或填充一导电物质，如锡球，此时第一接点3015即为锡球垫(ball pads)。而第二图案化介电层305至少暴露出图案化金属层301的部分上表面，以形成基板上方对外电性连接的数个第二接点3013，例如某些应用例中的焊垫(bonding pads)。在实际应用时，第一图案化介电层303、304和第二图案化介电层305、306例如是包括至少一槽状开口(Slot opening)，以暴露出该些个第一接点3015和第二接点3013。
另外，在实施例中，第一图案化介电层303、304和第二图案化介电层305、306的材料例如是选用防焊绿漆(solder mask，SM)、液晶聚合物(liquid crystal polyester，LCP)、聚丙烯(polypropylene，PP)、或胶体(molding compound)等等，且第一图案化介电层303、304和第二图案化介电层305、306的材料可以相同或不同，本发明对此并不特别限制。
然后，可再对图案化金属层301裸露于第一、二图案化介电层303、305外的部分，进行后续表面处理而完成基板结构51的制造。如图3I所示，在裸露于第二图案化介电层305外的任一或多个第二接点3013的表面上形成第一表面处理层308a；在裸露于第一图案化介电层303外的任一或多个第一接点3015的表面上形成第二表面处理层308b。其中，第一、二表面处理层308a、308b的材料例如是包括镍/金、镍/银、金、锡及其合金(如锡铅合金)、或银。另外，也可依实际应用条件，以其它材料进行后处理，例如ENEPIG、OSP等，本发明对此并不多作限制。再者，于一应用例中，在第二接点3013上所形成的第一表面处理层308a亦可分别与第二图案化介电层305的侧壁相隔一间距(d1/d2)，且该些间距可以相同或相异，视应用时的实际图形而定，本发明对此并不多作限制。
图4是绘示应用本发明第一实施例的图3I基板的封装件示意图。如图4的封装件结构61所示，制作时应用一黏性物质(例如环氧树脂)601将一晶粒602黏附在第二图案化介电层305上方，并且经由焊线603a、603b电性连接晶粒602的一主动表面与第二接点3013处的第一表面处理层308a；之后，再形成一胶体(Molding Compound)607于第一图案化介电层303的上方，以密封第一图案化介电层303、图案化金属层301、第二图案化介电层305、晶粒602和焊线603a、603b。胶体607的材料一般为绝缘的封装材料，常见的例如是环氧树脂。
根据上述，在第一实施例中所制作的基板结构，如图3I和图4所示，所形成的图案化金属层301内埋于第一图案化介电层303中，且图案化金属层301的上表面与第一图案化介电层303的上表面齐平，之后再于图案化金属层301上方形成第二图案化介电层305。相较于传统的基板结构，依照本发明所制作的基板结构仅包括两层图案化介电层(303/305)和单层金属层(作为导线层)，其基板结构厚度仅约40μm～130μm，使整体厚度大为降低，如此轻薄的外型十分适合小尺寸应用产品的需求。另外，相较于传统工艺，第一实施例所提出的工艺更为简易迅速，并可制作出细微的线路间距。
再者，虽然在上述实施例中为提高生产力，在流程中于载板20的两侧同时制作出两组基板结构作说明，但本发明并不受限于此，实际应用时可视操作状况而进行调整，例如在图3A～3H中仅在载板20的单一侧进行工艺亦可形成如实施例图3I所示的基板结构，因此本发明对此并不多作限制。
第二实施例
除了第一实施例中所示的基板结构51(图3I)，也可稍加变化上述工艺而制作出本发明其它态样的基板。请参照图5A，其绘示本发明第二实施例的单层金属层基板的示意图。第一、二实施例中，相同组件沿用相同标号。
制作如图5A所示的基板结构52时，同样可应用如图3A～3H所示的步骤进行基板制作，在此不再赘述。第二实施例的图案化金属层301除了第一接点3015和第二接点3013，还包括了至少一芯片垫(die pad)3017。因此在第二实施例中，图案化金属层301包括了芯片垫2071、多个第一接点3015(ex：焊垫)和多个第二接点3013(ex：锡球垫)。与第一实施例不同的是，在第二实施例中形成第二图案化介电层305(图3G)时，第二图案化介电层305更在对应芯片垫3017的位置形成一芯片容置区域(die-receiving area)522。如图5A所示，芯片容置区域522完全暴露出芯片垫3017。
图5B绘示应用本发明第二实施例的图5A基板的封装件示意图。如图5B的封装件结构62所示，制作时亦应用一黏性物质(例如环氧树脂)601将一晶粒602设置在芯片容置区域522内并黏附于图案化金属层301的芯片垫3017上方，并且经由焊线603a、603b电性连接晶粒602的一主动表面与第二接点3013处的第一表面处理层308a；之后，再形成一胶体607(如环氧树脂)于第一图案化介电层303的上方，以密封第一图案化介电层303、图案化金属层301、第二图案化介电层305、晶粒602和焊线603a、603b。其中，晶粒602的厚度h2小于第二图案化介电层305的厚度h1，因此可再降低封装后的整体厚度。
同样的，对于图5A和图5B的基板结构而言，所形成的图案化金属层301亦内埋于第一图案化介电层303中，且图案化金属层301的上表面与第一图案化介电层303的上表面齐平。相较于传统的基板结构，依照本发明所制作的基板结构仅包括两层图案化介电层(303/305)和单层金属层(作为导线层)，其基板结构很薄，且封装件整体厚度更为降低，如此轻薄的外型十分适合小尺寸应用产品的需求。
值得注意的是，虽然上述实施例中提出两种基板结构61、62和相关封装件71、72作举例说明，但其最终结构仍是依照实际应用条件而作相关调整，例如封装时晶粒连接可采用打线或覆晶方式连接，介电层图案、金属层图案、...等等，该些选择并不局限于上述图式所绘制的态样。
综上所述，根据本发明实施例所制作出的内埋式基板结构，其厚度范围约在40μm～130μm，相较于传统的”2层基板”结构，本发明所提出的基板厚度、及应用此基板的封装件的整体厚度都可大为下降，其轻薄的外型十分适合小尺寸应用产品的需求。再者，本发明所提出此基板结构及应用其的封装件的制造方法，其工艺不但快速简单又十分适合量产，兼具低制造成本和高产品良率的优点，符合应用电子产品对于尺寸、外型轻薄化和低价格的需求。因此，比起传统的基板结构，本发明所提出的基板结构及应用其的封装件更是适合应用于市场价格较低的小型电子产品，十分具有市场竞争力。
综上所述，虽然本发明已以较佳实施例揭露如上，然其并非用以限定本发明。本发明所属技术领域中具有通常知识者，在不脱离本发明的精神和范围内，当可作各种的更动与润饰。因此，本发明的保护范围当视后附的权利要求书所界定者为准。

Claims (19)

1.一种单层金属层基板结构，包括：
一第一图案化介电层(first patterned dielectric layer)，具有一上表面和一下表面；
一图案化金属层(patterned metal layer)，内埋于该第一图案化介电层，且该图案化金属层的一上表面与该第一图案化介电层的该上表面为一共平面，其中该第一图案化介电层至少暴露出部分该图案化金属层，以形成下方对外电性连接的数个第一接点；和
一第二图案化介电层(second patterned dielectric layer)，位于该图案化金属层及该第一图案化介电层上方，且该第二图案化介电层至少暴露出该图案化金属层的部分该上表面，以形成上方对外电性连接的数个第二接点。
2.如权利要求1所述的基板结构，更包括：
一第一表面处理层(First surface finish layer)，形成于该些第二接点的任一或多者的表面上；和
一第二表面处理层(Second surface finish layer)，至少覆盖该些第一接点的任一或多者的表面。
3.如权利要求2所述的基板结构，其中该第一和该第二表面处理层的材料包括镍/金、镍/银、金、锡及其合金、银、或OSP。
4.如权利要求1所述的基板结构，其中该第一和该第二图案化介电层的材料为防焊绿漆(solder mask，SM)、液晶聚合物(liquid crystal polyester，LCP)、聚丙烯(polypropylene，PP)、或胶体(molding compound)。
5.如权利要求1所述的基板结构，其厚度范围约在40μm～130μm之间。
6.一种具有单层金属层基板的封装件结构，包括：
一单层金属层基板，其中该基板包含一第一图案化介电层、一图案化金属层、以及于该图案化金属层上方配置一第二图案化介电层，该图案化金属层是内埋于该第一图案化介电层，且该图案化金属层的一上表面与该第一图案化介电层的一上表面为一共平面，其中该第一图案化介电层至少暴露出部分该图案化金属层，以形成下方对外电性连接的数个第一接点，而该第二图案化介电层至少暴露出部分该图案化金属层的该上表面，以形成上方对外电性连接的数个第二接点；和
至少一晶粒(die)与该些第二接点电性连接；以及
一胶体(Molding compound)，配置于该第一图案化介电层的该上表面上方，并覆盖该第一图案化介电层、该图案化金属层、该第二图案化介电层和该晶粒。
7.如权利要求6所述的封装件结构，更包括：
一第一表面处理层(First surface finish layer)，形成于该些第二接点的任一或多者的表面；和
一第二表面处理层(Second surface finish layer)，至少覆盖该些第一接点的任一或多者的表面。
8.如权利要求7所述的封装件结构，其中该第一和该第二表面处理层的材料包括镍/金、镍/银、金、锡及其合金、银、或OSP。
9.如权利要求6所述的封装件结构，其中该第一和该第二图案化介电层的材料为防焊绿漆(solder mask，SM)、液晶聚合物(liquid crystal polyester，LCP)、聚丙烯(polypropylene，PP)、或胶体(molding compound)。
10.如权利要求6所述的封装件结构，其中该单层金属层基板的丨厚度范围约在40μm～130μm之间。
11.如权利要求6所述的封装件结构，包括数个条焊线电性连接该晶粒的一主动表面和该些第二接点。
12.如权利要求11所述的封装件结构，其中该些焊线的材质包括金、银、铜、铝及其合金。
13.如权利要求6所述的封装件结构，其中该些第一接点填充一导电物质，包括锡球。
14.一种单层金属层基板的制造方法，包括：
形成一图案化金属层(patterned metal layer)；
形成一第一图案化介电层于该图案化金属层的一下表面处，并使该图案化金属层的一上表面与该第一图案化介电层的一上表面成为一共平面，其中该第一图案化介电层至少暴露出部分该图案化金属层的该下表面，以形成下方对外电性连接的数个第一接点；和
形成一第二图案化介电层于该图案化金属层的该上表面，且该第二图案化介电层至少暴露出该图案化金属层的部分该上表面，以形成上方对外电性连接的数个第二接点。
15.如权利要求14项所述基板的制造方法，包括：
提供一载板(carrier)，且该载板至少一表面具有一金属箔膜(metal foil)；
在该金属箔膜上形成该图案化金属层；以及
在该图案化金属层的该下表面处形成该第一图案化介电层，且该第一图案化介电层形成有数个开口以暴露出部分该图案化金属层的该下表面，以形成该些第一接点。
16.如权利要求15项所述基板的制造方法，其中形成该图案化金属层的步骤包括：
形成一金属层于该金属箔膜上；
形成一干膜(dry film)于该金属层上并进行曝光和显影以图案化该干膜；
根据该干膜的图案对该金属层进行蚀刻以完成影像转移，形成该图案化金属层；和
移除该图案化干膜。
17.如权利要求14所述基板的制造方法，包括：
将该金属箔膜、该图案化金属层和该第一图案化介电层所形成的一结构体自该载板上移除；
反转并重新设置该结构体，使该第一图案化介电层设置于该载体上；
移除该金属箔膜，此时该图案化金属层的该上表面与该第一图案化介电层的该上表面齐平；
形成该第二图案化介电层于该图案化金属层的该上表面，且该第二图案化介电层至少暴露出该图案化金属层的部分该上表面，以形成该些第二接点；和
移除该载板。
18.如权利要求17所述基板的制造方法，其中在提供的该载板的上下两侧各形成一金属箔膜(metal foil)，并接着在该载板的上下两侧同时进行形成该图案化金属层、形成该第一图案化介电层、反转并重新设置该结构体于该载板、移除该金属箔膜、形成该第二图案化介电层、和移除该载板等步骤，以形成两组基板结构。
19.如权利要求14所述基板的制造方法，更包括：
形成一第一表面处理层于该些第二接点的任一或多者的表面上；和
形成一第二表面处理层，以至少覆盖该些第一接点的任一或多者的表面。
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CN101887874A (zh) 2010-11-17
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