CN101504939A - 半导体器件 - Google Patents
半导体器件 Download PDFInfo
- Publication number
- CN101504939A CN101504939A CNA200910003571XA CN200910003571A CN101504939A CN 101504939 A CN101504939 A CN 101504939A CN A200910003571X A CNA200910003571X A CN A200910003571XA CN 200910003571 A CN200910003571 A CN 200910003571A CN 101504939 A CN101504939 A CN 101504939A
- Authority
- CN
- China
- Prior art keywords
- mentioned
- memory chip
- chip
- mediplate
- limit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/16—Constructional details or arrangements
- G06F1/18—Packaging or power distribution
- G06F1/183—Internal mounting support structures, e.g. for printed circuit boards, internal connecting means
- G06F1/185—Mounting of expansion boards
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5388—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates for flat cards, e.g. credit cards
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06506—Wire or wire-like electrical connections between devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/0651—Wire or wire-like electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01023—Vanadium [V]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30105—Capacitance
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Theoretical Computer Science (AREA)
- Human Computer Interaction (AREA)
- General Engineering & Computer Science (AREA)
- Semiconductor Memories (AREA)
- Credit Cards Or The Like (AREA)
- Wire Bonding (AREA)
- Dram (AREA)
Abstract
Description
Claims (23)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201510472546.1A CN105140212A (zh) | 2008-02-08 | 2009-01-15 | 半导体器件 |
CN201210186284.9A CN102693746B (zh) | 2008-02-08 | 2009-01-15 | 半导体器件 |
Applications Claiming Priority (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008029691 | 2008-02-08 | ||
JP2008029691 | 2008-02-08 | ||
JP2008-029691 | 2008-02-08 | ||
JP2008-198535 | 2008-07-31 | ||
JP2008198535A JP5207868B2 (ja) | 2008-02-08 | 2008-07-31 | 半導体装置 |
JP2008198535 | 2008-07-31 |
Related Child Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201510472546.1A Division CN105140212A (zh) | 2008-02-08 | 2009-01-15 | 半导体器件 |
CN201210186284.9A Division CN102693746B (zh) | 2008-02-08 | 2009-01-15 | 半导体器件 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101504939A true CN101504939A (zh) | 2009-08-12 |
CN101504939B CN101504939B (zh) | 2012-11-21 |
Family
ID=40938208
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201510472546.1A Pending CN105140212A (zh) | 2008-02-08 | 2009-01-15 | 半导体器件 |
CN201210186284.9A Active CN102693746B (zh) | 2008-02-08 | 2009-01-15 | 半导体器件 |
CN200910003571XA Active CN101504939B (zh) | 2008-02-08 | 2009-01-15 | 半导体器件 |
Family Applications Before (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201510472546.1A Pending CN105140212A (zh) | 2008-02-08 | 2009-01-15 | 半导体器件 |
CN201210186284.9A Active CN102693746B (zh) | 2008-02-08 | 2009-01-15 | 半导体器件 |
Country Status (6)
Country | Link |
---|---|
US (4) | US7989960B2 (zh) |
JP (1) | JP5207868B2 (zh) |
KR (2) | KR101539464B1 (zh) |
CN (3) | CN105140212A (zh) |
HK (1) | HK1217138A1 (zh) |
TW (3) | TWI584445B (zh) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103681641A (zh) * | 2012-09-10 | 2014-03-26 | 佳能株式会社 | 层叠半导体器件和印刷电路板 |
TWI471996B (zh) * | 2011-03-24 | 2015-02-01 | Toshiba Kk | Semiconductor memory card |
CN106605184A (zh) * | 2014-06-30 | 2017-04-26 | 三星电子株式会社 | 存储卡 |
CN107407946A (zh) * | 2015-03-04 | 2017-11-28 | 谷歌公司 | 带有暴露的用户接口的微电子装置 |
CN108962856A (zh) * | 2017-05-18 | 2018-12-07 | 三星电子株式会社 | 半导体存储器芯片、半导体存储器封装及使用其的电子*** |
Families Citing this family (83)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5184951B2 (ja) * | 2008-04-15 | 2013-04-17 | 株式会社東芝 | 半導体パッケージ |
JP2010010407A (ja) * | 2008-06-27 | 2010-01-14 | Toshiba Corp | 半導体記憶装置 |
JP2010021449A (ja) * | 2008-07-11 | 2010-01-28 | Toshiba Corp | 半導体装置 |
US8472199B2 (en) * | 2008-11-13 | 2013-06-25 | Mosaid Technologies Incorporated | System including a plurality of encapsulated semiconductor chips |
JP5687202B2 (ja) * | 2009-11-04 | 2015-03-18 | ローム株式会社 | 圧力センサおよび圧力センサの製造方法 |
JP5515696B2 (ja) * | 2009-12-02 | 2014-06-11 | ミツミ電機株式会社 | カードデバイス |
US9420707B2 (en) * | 2009-12-17 | 2016-08-16 | Intel Corporation | Substrate for integrated circuit devices including multi-layer glass core and methods of making the same |
US8415808B2 (en) * | 2010-07-28 | 2013-04-09 | Sandisk Technologies Inc. | Semiconductor device with die stack arrangement including staggered die and efficient wire bonding |
US8553420B2 (en) | 2010-10-19 | 2013-10-08 | Tessera, Inc. | Enhanced stacked microelectronic assemblies with central contacts and improved thermal characteristics |
US8659166B2 (en) * | 2010-11-18 | 2014-02-25 | Headway Technologies, Inc. | Memory device, laminated semiconductor substrate and method of manufacturing the same |
US8587088B2 (en) * | 2011-02-17 | 2013-11-19 | Apple Inc. | Side-mounted controller and methods for making the same |
US8952516B2 (en) | 2011-04-21 | 2015-02-10 | Tessera, Inc. | Multiple die stacking for two or more die |
US8633576B2 (en) | 2011-04-21 | 2014-01-21 | Tessera, Inc. | Stacked chip-on-board module with edge connector |
US8304881B1 (en) | 2011-04-21 | 2012-11-06 | Tessera, Inc. | Flip-chip, face-up and face-down wirebond combination package |
US8928153B2 (en) | 2011-04-21 | 2015-01-06 | Tessera, Inc. | Flip-chip, face-up and face-down centerbond memory wirebond assemblies |
US8970028B2 (en) | 2011-12-29 | 2015-03-03 | Invensas Corporation | Embedded heat spreader for package with multiple microelectronic elements and face-down connection |
US9013033B2 (en) | 2011-04-21 | 2015-04-21 | Tessera, Inc. | Multiple die face-down stacking for two or more die |
US8338963B2 (en) | 2011-04-21 | 2012-12-25 | Tessera, Inc. | Multiple die face-down stacking for two or more die |
US8502390B2 (en) | 2011-07-12 | 2013-08-06 | Tessera, Inc. | De-skewed multi-die packages |
US8823165B2 (en) | 2011-07-12 | 2014-09-02 | Invensas Corporation | Memory module in a package |
US8513817B2 (en) | 2011-07-12 | 2013-08-20 | Invensas Corporation | Memory module in a package |
KR20130019290A (ko) * | 2011-08-16 | 2013-02-26 | 삼성전자주식회사 | 유니버설 인쇄 회로 기판 및 그것을 포함하는 메모리 카드 |
JP5646415B2 (ja) * | 2011-08-31 | 2014-12-24 | 株式会社東芝 | 半導体パッケージ |
KR101909200B1 (ko) | 2011-09-06 | 2018-10-17 | 삼성전자 주식회사 | 수동소자가 형성된 지지 부재를 포함하는 반도체 패키지 |
JP5887414B2 (ja) | 2011-10-03 | 2016-03-16 | インヴェンサス・コーポレイション | 平行な窓を有するマルチダイのワイヤボンドアセンブリのスタブ最小化 |
US8659141B2 (en) | 2011-10-03 | 2014-02-25 | Invensas Corporation | Stub minimization using duplicate sets of terminals for wirebond assemblies without windows |
US8659139B2 (en) | 2011-10-03 | 2014-02-25 | Invensas Corporation | Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate |
KR20140069343A (ko) | 2011-10-03 | 2014-06-09 | 인벤사스 코포레이션 | 패키지의 중심으로부터 옵셋된 단자 그리드를 구비하는 스터드 최소화 |
US8345441B1 (en) | 2011-10-03 | 2013-01-01 | Invensas Corporation | Stub minimization for multi-die wirebond assemblies with parallel windows |
US8610260B2 (en) | 2011-10-03 | 2013-12-17 | Invensas Corporation | Stub minimization for assemblies without wirebonds to package substrate |
TWI501254B (zh) | 2011-10-03 | 2015-09-21 | Invensas Corp | 用於具有正交窗之多晶粒導線結合總成之短線最小化 |
US8441111B2 (en) | 2011-10-03 | 2013-05-14 | Invensas Corporation | Stub minimization for multi-die wirebond assemblies with parallel windows |
US8436457B2 (en) | 2011-10-03 | 2013-05-07 | Invensas Corporation | Stub minimization for multi-die wirebond assemblies with parallel windows |
US8659143B2 (en) | 2011-10-03 | 2014-02-25 | Invensas Corporation | Stub minimization for wirebond assemblies without windows |
WO2013071399A1 (en) * | 2011-11-14 | 2013-05-23 | Mosaid Technologies Incorporated | Package having stacked memory dies with serially connected buffer dies |
JP6122290B2 (ja) | 2011-12-22 | 2017-04-26 | 三星電子株式会社Samsung Electronics Co.,Ltd. | 再配線層を有する半導体パッケージ |
US9368477B2 (en) | 2012-08-27 | 2016-06-14 | Invensas Corporation | Co-support circuit panel and microelectronic packages |
US8787034B2 (en) | 2012-08-27 | 2014-07-22 | Invensas Corporation | Co-support system and microelectronic assembly |
US8848391B2 (en) | 2012-08-27 | 2014-09-30 | Invensas Corporation | Co-support component and microelectronic assembly |
US8848392B2 (en) | 2012-08-27 | 2014-09-30 | Invensas Corporation | Co-support module and microelectronic assembly |
KR102084553B1 (ko) | 2013-01-03 | 2020-03-04 | 삼성전자주식회사 | 메모리 시스템 |
US9070423B2 (en) | 2013-06-11 | 2015-06-30 | Invensas Corporation | Single package dual channel memory with co-support |
KR102122460B1 (ko) * | 2013-07-17 | 2020-06-12 | 삼성전자주식회사 | 반도체 패키지 |
US9123555B2 (en) | 2013-10-25 | 2015-09-01 | Invensas Corporation | Co-support for XFD packaging |
KR102247916B1 (ko) * | 2014-01-16 | 2021-05-04 | 삼성전자주식회사 | 계단식 적층 구조를 갖는 반도체 패키지 |
USD730908S1 (en) * | 2014-05-02 | 2015-06-02 | Samsung Electronics Co., Ltd. | Memory card |
USD730907S1 (en) * | 2014-05-02 | 2015-06-02 | Samsung Electronics Co., Ltd. | Memory card |
USD730910S1 (en) * | 2014-05-02 | 2015-06-02 | Samsung Electronics Co., Ltd. | Memory card |
USD727913S1 (en) * | 2014-06-27 | 2015-04-28 | Samsung Electronics Co., Ltd. | Memory card |
USD727912S1 (en) * | 2014-06-27 | 2015-04-28 | Samsung Electronics Co., Ltd. | Memory card |
USD730909S1 (en) * | 2014-06-27 | 2015-06-02 | Samsung Electronics Co., Ltd. | Memory card |
USD727911S1 (en) * | 2014-06-27 | 2015-04-28 | Samsung Electronics Co., Ltd. | Memory card |
USD729251S1 (en) * | 2014-06-27 | 2015-05-12 | Samsung Electronics Co., Ltd. | Memory card |
USD736213S1 (en) * | 2014-07-01 | 2015-08-11 | Samsung Electronics Co., Ltd. | Memory card |
USD736214S1 (en) * | 2014-07-01 | 2015-08-11 | Samsung Electronics Co., Ltd. | Memory card |
USD736215S1 (en) * | 2014-07-01 | 2015-08-11 | Samsung Electronics Co., Ltd. | Memory card |
USD736212S1 (en) * | 2014-07-01 | 2015-08-11 | Samsung Electronics Co., Ltd. | Memory card |
USD727910S1 (en) * | 2014-07-02 | 2015-04-28 | Samsung Electronics Co., Ltd. | Memory card |
KR102251455B1 (ko) * | 2014-07-18 | 2021-05-17 | 삼성전자주식회사 | 외장 메모리 장치 |
USD739856S1 (en) * | 2014-07-30 | 2015-09-29 | Samsung Electronics Co., Ltd. | Memory card |
USD736216S1 (en) * | 2014-07-30 | 2015-08-11 | Samsung Electronics Co., Ltd. | Memory card |
US9281296B2 (en) | 2014-07-31 | 2016-03-08 | Invensas Corporation | Die stacking techniques in BGA memory package for small footprint CPU and memory motherboard design |
US9691437B2 (en) | 2014-09-25 | 2017-06-27 | Invensas Corporation | Compact microelectronic assembly having reduced spacing between controller and memory packages |
JP6253607B2 (ja) * | 2015-03-16 | 2017-12-27 | 東芝メモリ株式会社 | 半導体メモリカードの製造方法 |
USD773466S1 (en) * | 2015-08-20 | 2016-12-06 | Isaac S. Daniel | Combined secure digital memory and subscriber identity module |
USD798868S1 (en) * | 2015-08-20 | 2017-10-03 | Isaac S. Daniel | Combined subscriber identification module and storage card |
USD783621S1 (en) * | 2015-08-25 | 2017-04-11 | Samsung Electronics Co., Ltd. | Memory card |
USD783622S1 (en) * | 2015-08-25 | 2017-04-11 | Samsung Electronics Co., Ltd. | Memory card |
US10121767B2 (en) * | 2015-09-10 | 2018-11-06 | Toshiba Memory Corporation | Semiconductor storage device and manufacturing method thereof |
US9484080B1 (en) | 2015-11-09 | 2016-11-01 | Invensas Corporation | High-bandwidth memory application with controlled impedance loading |
USD772232S1 (en) * | 2015-11-12 | 2016-11-22 | Samsung Electronics Co., Ltd. | Memory card |
USD773467S1 (en) * | 2015-11-12 | 2016-12-06 | Samsung Electronics Co., Ltd. | Memory card |
US9679613B1 (en) | 2016-05-06 | 2017-06-13 | Invensas Corporation | TFD I/O partition for high-speed, high-density applications |
US9761564B1 (en) * | 2016-06-30 | 2017-09-12 | Micron Technology, Inc. | Layout of transmission vias for memory device |
KR20200007539A (ko) | 2018-07-13 | 2020-01-22 | 삼성전자주식회사 | 메모리 카드 및 메모리 카드 소켓 |
KR102653837B1 (ko) * | 2018-07-27 | 2024-04-02 | 에스케이하이닉스 주식회사 | 메모리 모듈 및 데이터 처리 시스템 |
KR102536269B1 (ko) * | 2018-09-14 | 2023-05-25 | 삼성전자주식회사 | 반도체 패키지 및 그 제조 방법 |
CN209298115U (zh) * | 2018-12-14 | 2019-08-23 | 深圳市江波龙电子股份有限公司 | 一种存储装置 |
TWI747308B (zh) * | 2019-06-14 | 2021-11-21 | 日商索尼半導體解決方案公司 | 半導體裝置 |
CN110518003B (zh) * | 2019-08-30 | 2020-07-31 | 甬矽电子(宁波)股份有限公司 | 芯片封装结构和芯片封装方法 |
CN110691463A (zh) * | 2019-09-02 | 2020-01-14 | 歌尔股份有限公司 | 一种pcb板 |
CN111224688B (zh) * | 2019-12-30 | 2021-10-15 | 中国电子科技集团公司第十三研究所 | 一种射频前端芯片结构 |
CN115171531B (zh) * | 2022-06-30 | 2023-10-20 | 广州国显科技有限公司 | 邦定装置以及邦定方法 |
Family Cites Families (50)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5614766A (en) * | 1991-09-30 | 1997-03-25 | Rohm Co., Ltd. | Semiconductor device with stacked alternate-facing chips |
FR2701153B1 (fr) * | 1993-02-02 | 1995-04-07 | Matra Marconi Space France | Composant et module de mémoire à semi-conducteur. |
US6748318B1 (en) * | 1993-05-18 | 2004-06-08 | Arrivalstar, Inc. | Advanced notification systems and methods utilizing a computer network |
US5998864A (en) * | 1995-05-26 | 1999-12-07 | Formfactor, Inc. | Stacking semiconductor devices, particularly memory chips |
US6005778A (en) * | 1995-06-15 | 1999-12-21 | Honeywell Inc. | Chip stacking and capacitor mounting arrangement including spacers |
JP3765952B2 (ja) * | 1999-10-19 | 2006-04-12 | 富士通株式会社 | 半導体装置 |
US6376904B1 (en) * | 1999-12-23 | 2002-04-23 | Rambus Inc. | Redistributed bond pads in stacked integrated circuit die package |
JP3818359B2 (ja) | 2000-07-18 | 2006-09-06 | セイコーエプソン株式会社 | 半導体装置、回路基板及び電子機器 |
JP2002217356A (ja) * | 2001-01-19 | 2002-08-02 | Nec Corp | 半導体装置及びその製造方法 |
US6900528B2 (en) * | 2001-06-21 | 2005-05-31 | Micron Technology, Inc. | Stacked mass storage flash memory package |
JP4633971B2 (ja) * | 2001-07-11 | 2011-02-16 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP2004063579A (ja) | 2002-07-25 | 2004-02-26 | Renesas Technology Corp | 積層型半導体装置 |
JP4615189B2 (ja) * | 2003-01-29 | 2011-01-19 | シャープ株式会社 | 半導体装置およびインターポーザチップ |
JP2005085089A (ja) * | 2003-09-10 | 2005-03-31 | Renesas Technology Corp | Icカードおよびその製造方法 |
JP3880572B2 (ja) * | 2003-10-31 | 2007-02-14 | 沖電気工業株式会社 | 半導体チップ及び半導体装置 |
JP2007066922A (ja) | 2003-11-28 | 2007-03-15 | Renesas Technology Corp | 半導体集積回路装置 |
JP4205613B2 (ja) | 2004-03-01 | 2009-01-07 | エルピーダメモリ株式会社 | 半導体装置 |
JP4651332B2 (ja) | 2004-04-26 | 2011-03-16 | ルネサスエレクトロニクス株式会社 | メモリカード |
CN101620687B (zh) * | 2004-04-26 | 2011-07-13 | 瑞萨电子株式会社 | 存储卡 |
JP2006086149A (ja) | 2004-09-14 | 2006-03-30 | Toshiba Corp | 半導体装置 |
JP4185499B2 (ja) * | 2005-02-18 | 2008-11-26 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置 |
US7354800B2 (en) * | 2005-04-29 | 2008-04-08 | Stats Chippac Ltd. | Method of fabricating a stacked integrated circuit package system |
JP2007004775A (ja) | 2005-05-23 | 2007-01-11 | Toshiba Corp | 半導体メモリカード |
US20060267173A1 (en) * | 2005-05-26 | 2006-11-30 | Sandisk Corporation | Integrated circuit package having stacked integrated circuits and method therefor |
JP2006351664A (ja) * | 2005-06-14 | 2006-12-28 | Renesas Technology Corp | 半導体装置 |
JP2007059541A (ja) * | 2005-08-23 | 2007-03-08 | Toshiba Corp | 半導体装置及びその組立方法 |
JP2007096071A (ja) | 2005-09-29 | 2007-04-12 | Toshiba Corp | 半導体メモリカード |
JP2007128953A (ja) * | 2005-11-01 | 2007-05-24 | Toshiba Corp | 半導体装置とそれを用いたメモリカード |
JP4726640B2 (ja) * | 2006-01-20 | 2011-07-20 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP4900661B2 (ja) * | 2006-02-22 | 2012-03-21 | ルネサスエレクトロニクス株式会社 | 不揮発性記憶装置 |
US7615409B2 (en) | 2006-06-29 | 2009-11-10 | Sandisk Corporation | Method of stacking and interconnecting semiconductor packages via electrical connectors extending between adjoining semiconductor packages |
JP2008084263A (ja) * | 2006-09-29 | 2008-04-10 | Renesas Technology Corp | メモリカードおよびその製造方法 |
JP4921937B2 (ja) * | 2006-11-24 | 2012-04-25 | 株式会社東芝 | 半導体集積回路 |
US8242607B2 (en) * | 2006-12-20 | 2012-08-14 | Stats Chippac Ltd. | Integrated circuit package system with offset stacked die and method of manufacture thereof |
JP2008166430A (ja) * | 2006-12-27 | 2008-07-17 | Toshiba Microelectronics Corp | 半導体装置 |
US7800211B2 (en) * | 2007-06-29 | 2010-09-21 | Stats Chippac, Ltd. | Stackable package by using internal stacking modules |
US7880309B2 (en) * | 2007-07-30 | 2011-02-01 | Qimonda Ag | Arrangement of stacked integrated circuit dice having a direct electrical connection |
US7906853B2 (en) * | 2007-09-06 | 2011-03-15 | Micron Technology, Inc. | Package structure for multiple die stack |
JP4498403B2 (ja) | 2007-09-28 | 2010-07-07 | 株式会社東芝 | 半導体装置と半導体記憶装置 |
TWI415201B (zh) * | 2007-11-30 | 2013-11-11 | 矽品精密工業股份有限公司 | 多晶片堆疊結構及其製法 |
JP2009164160A (ja) * | 2007-12-28 | 2009-07-23 | Panasonic Corp | 半導体デバイス積層体および実装方法 |
US7622794B1 (en) * | 2008-06-05 | 2009-11-24 | Powertech Technology Inc. | COL (Chip-On-Lead) multi-chip package |
KR20100049283A (ko) * | 2008-11-03 | 2010-05-12 | 삼성전자주식회사 | 반도체 패키지 및 그 제조 방법 |
JP2010165984A (ja) * | 2009-01-19 | 2010-07-29 | Toshiba Corp | 半導体デバイス |
JP2010245412A (ja) * | 2009-04-09 | 2010-10-28 | Renesas Electronics Corp | 半導体集積回路装置の製造方法 |
KR101053140B1 (ko) * | 2009-04-10 | 2011-08-02 | 주식회사 하이닉스반도체 | 적층 반도체 패키지 |
KR20100117977A (ko) * | 2009-04-27 | 2010-11-04 | 삼성전자주식회사 | 반도체 패키지 |
KR20100121231A (ko) * | 2009-05-08 | 2010-11-17 | 삼성전자주식회사 | 회로패턴 들뜸 현상을 억제하는 패키지 온 패키지 및 그 제조방법 |
JP2010278318A (ja) * | 2009-05-29 | 2010-12-09 | Renesas Electronics Corp | 半導体装置 |
KR101909203B1 (ko) * | 2011-07-21 | 2018-10-17 | 삼성전자 주식회사 | 멀티-채널 패키지 및 그 패키지를 포함한 전자 시스템 |
-
2008
- 2008-07-31 JP JP2008198535A patent/JP5207868B2/ja not_active Expired - Fee Related
- 2008-12-04 TW TW105101796A patent/TWI584445B/zh not_active IP Right Cessation
- 2008-12-04 TW TW103127854A patent/TWI527190B/zh not_active IP Right Cessation
- 2008-12-04 TW TW97147180A patent/TWI453889B/zh active
-
2009
- 2009-01-15 CN CN201510472546.1A patent/CN105140212A/zh active Pending
- 2009-01-15 CN CN201210186284.9A patent/CN102693746B/zh active Active
- 2009-01-15 CN CN200910003571XA patent/CN101504939B/zh active Active
- 2009-01-22 KR KR1020090005586A patent/KR101539464B1/ko active IP Right Grant
- 2009-02-04 US US12/365,806 patent/US7989960B2/en not_active Expired - Fee Related
-
2011
- 2011-06-12 US US13/158,430 patent/US8319352B2/en not_active Expired - Fee Related
-
2012
- 2012-11-09 US US13/673,990 patent/US8754534B2/en active Active
-
2014
- 2014-06-05 US US14/296,552 patent/US9377825B2/en active Active
-
2015
- 2015-04-24 KR KR1020150058231A patent/KR101540551B1/ko active IP Right Grant
-
2016
- 2016-04-21 HK HK16104580.0A patent/HK1217138A1/zh unknown
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI471996B (zh) * | 2011-03-24 | 2015-02-01 | Toshiba Kk | Semiconductor memory card |
CN103681641A (zh) * | 2012-09-10 | 2014-03-26 | 佳能株式会社 | 层叠半导体器件和印刷电路板 |
CN103681641B (zh) * | 2012-09-10 | 2017-04-12 | 佳能株式会社 | 层叠半导体器件和印刷电路板 |
CN106605184A (zh) * | 2014-06-30 | 2017-04-26 | 三星电子株式会社 | 存储卡 |
US10380055B2 (en) | 2014-06-30 | 2019-08-13 | Samsung Electronics Co., Ltd. | Memory card having multi-row terminals |
CN106605184B (zh) * | 2014-06-30 | 2020-10-27 | 三星电子株式会社 | 存储卡 |
CN107407946A (zh) * | 2015-03-04 | 2017-11-28 | 谷歌公司 | 带有暴露的用户接口的微电子装置 |
CN107407946B (zh) * | 2015-03-04 | 2019-08-02 | 谷歌有限责任公司 | 带有暴露的用户接口的微电子装置 |
CN108962856A (zh) * | 2017-05-18 | 2018-12-07 | 三星电子株式会社 | 半导体存储器芯片、半导体存储器封装及使用其的电子*** |
CN108962856B (zh) * | 2017-05-18 | 2023-06-06 | 三星电子株式会社 | 半导体存储器芯片、半导体存储器封装及使用其的电子*** |
Also Published As
Publication number | Publication date |
---|---|
KR20090086314A (ko) | 2009-08-12 |
JP5207868B2 (ja) | 2013-06-12 |
KR101539464B1 (ko) | 2015-07-24 |
TW201507100A (zh) | 2015-02-16 |
TWI584445B (zh) | 2017-05-21 |
HK1217138A1 (zh) | 2016-12-23 |
CN105140212A (zh) | 2015-12-09 |
US7989960B2 (en) | 2011-08-02 |
US20110233788A1 (en) | 2011-09-29 |
US8319352B2 (en) | 2012-11-27 |
TWI453889B (zh) | 2014-09-21 |
US8754534B2 (en) | 2014-06-17 |
CN101504939B (zh) | 2012-11-21 |
KR101540551B1 (ko) | 2015-07-29 |
TW200941694A (en) | 2009-10-01 |
CN102693746B (zh) | 2016-01-20 |
US20090200680A1 (en) | 2009-08-13 |
JP2009212486A (ja) | 2009-09-17 |
US20140347809A1 (en) | 2014-11-27 |
TWI527190B (zh) | 2016-03-21 |
US20130069249A1 (en) | 2013-03-21 |
US9377825B2 (en) | 2016-06-28 |
CN102693746A (zh) | 2012-09-26 |
KR20150051980A (ko) | 2015-05-13 |
TW201616633A (zh) | 2016-05-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN101504939B (zh) | 半导体器件 | |
US8530278B2 (en) | Semiconductor device and a manufacturing method of the same | |
KR100881198B1 (ko) | 반도체 패키지 및 이를 실장한 반도체 패키지 모듈 | |
JPH09246465A (ja) | Loc型半導体チップの積層チップパッケージ | |
JP2007096071A (ja) | 半導体メモリカード | |
KR101898678B1 (ko) | 반도체 패키지 | |
US6617700B2 (en) | Repairable multi-chip package and high-density memory card having the package | |
CN100578536C (zh) | 半导体存储卡 | |
JPH1154693A (ja) | 半導体装置 | |
JP2010232702A (ja) | 積層型半導体装置 | |
JP6023866B2 (ja) | 半導体装置 | |
KR0161619B1 (ko) | 칩의 특정 본딩 패드에 선택적 대응되는 복수개의 내부리드들을 갖는 리드온 칩 형 리드프레임을 이용한 적층 패키지 | |
CN103928416B (zh) | 具有无源器件的半导体封装件及其堆叠方法 | |
JP2011244022A (ja) | 半導体装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C41 | Transfer of patent application or patent right or utility model | ||
COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: TOKYO, JAPAN TO: KANAGAWA PREFECTURE, JAPAN |
|
TA01 | Transfer of patent application right |
Effective date of registration: 20101021 Address after: Kanagawa Applicant after: Renesas Electronics Corporation Address before: Tokyo, Japan, Japan Applicant before: Renesas Technology Corp. |
|
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CP02 | Change in the address of a patent holder |
Address after: Tokyo, Japan, Japan Patentee after: Renesas Electronics Corporation Address before: Kanagawa Patentee before: Renesas Electronics Corporation |
|
CP02 | Change in the address of a patent holder |