JP5646415B2 - 半導体パッケージ - Google Patents
半導体パッケージ Download PDFInfo
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- JP5646415B2 JP5646415B2 JP2011190021A JP2011190021A JP5646415B2 JP 5646415 B2 JP5646415 B2 JP 5646415B2 JP 2011190021 A JP2011190021 A JP 2011190021A JP 2011190021 A JP2011190021 A JP 2011190021A JP 5646415 B2 JP5646415 B2 JP 5646415B2
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Description
本実施形態は、系統毎の配線長の違いを抑制し、高速動作を実現できる半導体パッケージを提供することを目的とする。
図1は、第1の実施形態に係る半導体パッケージ1の平面図である。図2は、半導体パッケージ1の側面図である。図2(a)は、半導体パッケージ1の図1の矢印αの向きからみた側面図である。図2(b)は、半導体パッケージ1の図1の矢印βの向きからみた側面図である。なお、図1では、封止部材61及びボンディングワイヤB2,B3の図示を省略している。図2(a)では、封止部材61を透視した状態で半導体パッケージ1を図示している。図2(b)では、封止部材61を透視した状態で、かつボンディングワイヤB3の図示を省略している。
初めに、半導体パッケージ1の概要について説明する。半導体パッケージ1は、矩形の実装基板11と、矩形の半導体チップ21と、樹脂層31と、矩形の半導体チップ41〜44と、矩形の半導体チップ51〜54と、封止部材61とを備える。半導体チップ41〜44及び51〜54は、データの書込み及び読出しを行うためのメモリチップであり、この半導体チップ41〜44及び51〜54へのデータの書込み及び読出しは、制御チップ(コントローラ)である半導体チップ21により行われる。
実装基板11は、表面及び裏面に対応する第1主面11a及び第2主面11bを有する。実装基板11は、第1〜第4の辺(側面)A〜Dを有する矩形の基板である。実装基板11の第1主面11a上には、半導体チップ21との接続端子12a〜12dがそれぞれ第1〜第4の辺A〜D側に形成されている。また、実装基板11の第1主面11a上には、半導体チップ41〜44との接続端子12eと、半導体チップ51〜54との接続端子12fとが第1,第2の辺A,B側にそれぞれ形成されている。
図3〜図6は、半導体パッケージ1の作成手順を示した図である。以下、図3〜図6を参照して、半導体パッケージ1の作成手順について説明する。なお、図1、図2で説明した構成と同一の構成には同一の符号を付して重複した説明を省略する。
実装基板11を用意し、この実装基板11の第1主面11a上に半導体チップ21を載置する(図3(a)参照)。この際、半導体チップ21の辺a〜dが実装基板11の辺A〜Dと対応するように実装基板11の第1主面11a上に半導体チップ21を載置する。なお、半導体チップ21の裏面には、半導体チップ21を半導体基板(ウェハ)から切り出す際に接着フィルムが貼られている。
実装基板11の接続端子12a〜12dと半導体チップ21の電極21a〜21dとをボンディングワイヤB1でそれぞれ接続する(図3(b)参照)。
半導体チップ21の表面及び周囲に樹脂層31となるFOW樹脂Cを塗布する。FOW樹脂Cは、その表面(上面)がボンディングワイヤB1の上端よりも高い位置で、その大きさ(縦と横の長さ)が表面(上面)上に積層される半導体チップ41の裏面の大きさ(縦と横の長さ)と略同じとなるように塗布する(図4(a)参照)。
FOW樹脂Cが半硬化の状態で、FOW樹脂Cの表面に半導体チップ41〜44を、電極41a〜44aが形成された辺が、実装基板11の辺A側となるように樹脂層31上に位置をずらしながら積層する(図4(b))参照。なお、半導体チップ41〜44の裏面には、半導体チップ41〜44を半導体基板(ウェハ)から切り出す際に接着フィルムが貼られている。
半導体チップ41〜44の電極41a〜44aと、実装基板11の接続端子12eとをボンディングワイヤB2で接続する(図5(a)参照)。なお、ボンディングは、実装基板11の接続端子12e側から半導体チップ44の接続端子44a側へ順次接続してもよく、半導体チップ44の接続端子44a側から実装基板11の接続端子12e側へ順次接続してもよい。
積層した半導体チップ44の表面上に半導体チップ51〜54を、電極51a〜54aが形成された辺が、実装基板11の辺B側となるように位置をずらしながら積層する(図5(b))参照。なお、半導体チップ51〜54の裏面には、半導体チップ51〜54を半導体基板(ウェハ)から切り出す際に接着フィルムが貼られている。
半導体チップ51〜54の電極51a〜54aと、実装基板11の接続端子12fとをボンディングワイヤB3で接続する(図6(a)参照)。なお、ボンディングは、実装基板11の接続端子12f側から半導体チップ44の接続端子54a側へ順次接続してもよく、半導体チップ54の接続端子54a側から実装基板11の接続端子12f側へ順次接続してもよい。
実装基板11の第1主面11a上に実装した半導体チップ21、半導体チップ41〜44及び半導体チップ51〜54を封止部材61となる封止樹脂(モールド樹脂)で封止する(図6(b)参照)。
L2=L1×0.8…(1)
L4=L3×0.8…(2)
L6=L5×0.95…(3)
L8=L7×0.95…(4)
図7は、第2の実施形態に係る半導体パッケージ2の側面図である。図7(a)は、図1の矢印αの向きからみた半導体パッケージ2の側面図である。図7(b)は、図1の矢印βの向きからみた半導体パッケージ2の側面図である。なお、図7(a)では、封止部材61を透視した状態で半導体パッケージ2を図示している。図7(b)では、封止部材61を透視した状態で、かつボンディングワイヤB3の図示を省略している。以下、図7を参照して、半導体パッケージ2の構成について説明するが、図1,図2を参照して説明した半導体パッケージ1と同一の構成には、同一の符号を付して重複した説明を省略する。
図8は、第3の実施形態に係る半導体パッケージ3の側面図である。図8(a)は、図1の矢印αの向きからみた半導体パッケージ3の側面図である。図8(b)は、図1の矢印βの向きからみた半導体パッケージ3の側面図である。なお、図8(a)では、封止部材61を透視した状態で半導体パッケージ3を図示している。図8(b)では、封止部材61を透視した状態で、かつボンディングワイヤB3の図示を省略している。以下、図8を参照して、半導体パッケージ3の構成について説明するが、図1,図2を参照して説明した半導体パッケージ1と同一の構成には、同一の符号を付して重複した説明を省略する。
図9は、第4の実施形態に係る半導体パッケージ4の側面図である。図9(a)は、図1の矢印αの向きからみた半導体パッケージ3の側面図である。図9(b)は、図1の矢印βの向きからみた半導体パッケージ3の側面図である。なお、図9(a)では、封止部材61を透視した状態で半導体パッケージ4を図示している。図9(b)では、封止部材61を透視した状態で、かつボンディングワイヤB3の図示を省略している。以下、図9を参照して、半導体パッケージ4の構成について説明するが、図1,図2を参照して説明した半導体パッケージ1と同一の構成には、同一の符号を付して重複した説明を省略する。
図10は、第5の実施形態に係る半導体パッケージ5の平面図である。図11は、第5の実施形態に係る半導体パッケージ5の側面図である。図11(a)は、図1の矢印αの向きからみた半導体パッケージ3の側面図である。図11(b)は、図1の矢印βの向きからみた半導体パッケージ3の側面図である。なお、図11(a)では、封止部材61を透視した状態で半導体パッケージ5を図示している。図11(b)では、封止部材61を透視した状態で、かつボンディングワイヤB3の図示を省略している。以下、図11を参照して、半導体パッケージ5の構成について説明するが、図1,図2を参照して説明した半導体パッケージ1と同一の構成には、同一の符号を付して重複した説明を省略する。
なお、本発明のいくつかの実施形態を説明したが、上記実施形態は、例示であり、本発明を上記実施形態に限定することを意図するものではない。上記実施形態は、その他の様々な形態で実施することが可能であり、発明の要旨を逸脱しない範囲で種々の省略、置き換え、変更を行うことができる。
Claims (7)
- 第1主面と、前記第1主面に対向した第2主面とを有する矩形の基板と、
前記第1主面上に実装される矩形の第1の半導体チップと、
前記第1の半導体チップ上に積層される1以上の第2の半導体チップと、
前記1以上の第2の半導体チップ上に積層される1以上の第3の半導体チップと、
を備え、
前記基板は、
前記第1主面上の第1の辺側に、前記1以上の第2の半導体チップの電極と接続される第1の接続端子と、前記第1の接続端子と電気的に接続され、前記第1の半導体チップの第1の電極と接続される第3の接続端子と、を有し、
前記第1主面上の前記第1の半導体チップを挟んで前記第1の辺と対向する第2の辺側に、前記1以上の第3の半導体チップの第2の電極と接続される第2の接続端子と、前記第2の接続端子と電気的に接続され、前記第1の半導体チップの電極と接続される第4の接続端子と、を有し、
前記第1主面上の前記第1,第2の辺とは異なる第3,第4の辺側に、前記第1の半導体チップの第3,第4の電極とそれぞれ接続される第5,第6の接続端子を有し、
前記第2主面上の前記第3,第4の辺に対応する位置に、前記第5,第6の接続端子とそれぞれ電気的に接続された第1,第2の外部接続端子を有し、
前記第1に半導体チップは、
前記基板の前記第1の辺に対応する辺側に前記第1の電極を、前記基板の前記第2の辺に対応する辺側に前記第2の電極を、前記基板の前記第3の辺に対応する辺側に前記第3の電極を、前記基板の前記第4の辺に対応する辺側に前記第4の電極を、それぞれ有する半導体パッケージ。 - 第1主面と、前記第1主面に対向した第2主面とを有する矩形の基板と、
前記第1主面上に実装される第1の半導体チップと、
前記第1の半導体チップ上に積層される1以上の第2の半導体チップと、
前記1以上の第2の半導体チップ上に積層される1以上の第3の半導体チップと、
を備え、
前記基板は、
前記第1主面上の第1の辺側に、前記1以上の第2の半導体チップの電極と接続される第1の接続端子と、前記第1の接続端子と電気的に接続され、前記第1の半導体チップの第1の電極と接続される第3の接続端子と、を有し、
前記第1主面上の前記第1の半導体チップを挟んで前記第1の辺と対向する第2の辺側に、前記1以上の第3の半導体チップの第2の電極と接続される第2の接続端子と、前記第2の接続端子と電気的に接続され、前記第1の半導体チップの電極と接続される第4の接続端子と、を有する半導体パッケージ。 - 前記基板は、
前記第1主面上の前記第1,第2の辺とは異なる第3,第4の辺側に、前記第1の半導体チップの第3,第4の電極とそれぞれ接続される第5,第6の接続端子を有し、
前記第2主面上の前記第3,第4の辺に対応する位置に、前記第5,第6の接続端子とそれぞれ電気的に接続された第1,第2の外部接続端子を有する請求項2に記載の半導体パッケージ。 - 前記第1の半導体チップは、矩形であり
前記基板の前記第1の辺に対応する辺側に前記第1の電極を有し、
前記基板の前記第2の辺に対応する辺側に前記第2の電極を有する請求項3に記載の半導体パッケージ。 - 前記第1の半導体チップは、
前記基板の前記第3の辺に対応する辺側に前記第3の電極を有し、
前記基板の前記第4の辺に対応する辺側に前記第4の電極を有する請求項4に記載の半導体パッケージ。 - 前記第1の半導体チップの第1の電極から前記1以上の第2の半導体チップの電極までの配線長と、前記第1の半導体チップの第2の電極から前記1以上の第3の半導体チップの電極までの配線長とが略同じである請求項5に記載の半導体パッケージ。
- 前記第1の半導体チップの電極から前記第1の外部接続端子までの配線長と、前記第1の半導体チップの電極から前記第2の外部接続端子までの配線長とが略同じである請求項6に記載の半導体パッケージ。
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