CN101278394B - 半导体装置 - Google Patents
半导体装置 Download PDFInfo
- Publication number
- CN101278394B CN101278394B CN2006800366350A CN200680036635A CN101278394B CN 101278394 B CN101278394 B CN 101278394B CN 2006800366350 A CN2006800366350 A CN 2006800366350A CN 200680036635 A CN200680036635 A CN 200680036635A CN 101278394 B CN101278394 B CN 101278394B
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- sealing resin
- resin layer
- semiconductor chip
- semiconductor device
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 162
- 229920005989 resin Polymers 0.000 claims abstract description 145
- 239000011347 resin Substances 0.000 claims abstract description 145
- 238000007789 sealing Methods 0.000 claims abstract description 144
- 239000010410 layer Substances 0.000 claims description 197
- 239000011248 coating agent Substances 0.000 claims description 50
- 238000000576 coating method Methods 0.000 claims description 50
- 239000011229 interlayer Substances 0.000 claims description 43
- 239000000758 substrate Substances 0.000 claims description 11
- 239000011159 matrix material Substances 0.000 claims description 5
- 238000009434 installation Methods 0.000 description 19
- 239000007769 metal material Substances 0.000 description 18
- 239000003822 epoxy resin Substances 0.000 description 15
- 229920000647 polyepoxide Polymers 0.000 description 15
- 239000000463 material Substances 0.000 description 13
- 239000004642 Polyimide Substances 0.000 description 11
- 238000000034 method Methods 0.000 description 11
- 229920001721 polyimide Polymers 0.000 description 11
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 8
- 229910052802 copper Inorganic materials 0.000 description 8
- 239000010949 copper Substances 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 8
- 230000008878 coupling Effects 0.000 description 7
- 238000010168 coupling process Methods 0.000 description 7
- 238000005859 coupling reaction Methods 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 229910052759 nickel Inorganic materials 0.000 description 5
- 238000005538 encapsulation Methods 0.000 description 4
- 208000034189 Sclerosis Diseases 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 238000000227 grinding Methods 0.000 description 3
- 239000004850 liquid epoxy resins (LERs) Substances 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 239000012141 concentrate Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 235000019994 cava Nutrition 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000005868 electrolysis reaction Methods 0.000 description 1
- LNEPOXFFQSENCJ-UHFFFAOYSA-N haloperidol Chemical compound C1CC(O)(C=2C=CC(Cl)=CC=2)CCN1CCCC(=O)C1=CC=C(F)C=C1 LNEPOXFFQSENCJ-UHFFFAOYSA-N 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
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Abstract
本发明提供一种半导体装置,包括:半导体芯片;密封树脂层,其被层叠在该半导体芯片的表面上;立柱,其在半导体芯片和密封树脂层之间的层叠方向上贯通该密封树脂层而设置,在密封树脂层上突出,该突出的部分的周缘部在层叠方向上与密封树脂层的表面对置并接触;和外部连接端子,其被设置在密封树脂层上,并与立柱连接。从而能够防止对立柱上的外部连接端子局部地集中应力,由此能够防止外部连接端子的损伤的发生。
Description
技术领域
本发明涉及半导体装置,尤其涉及适用WL-CSP(晶圆级芯片封装:Wafer Level-Chip Scale Package)技术的半导体装置。
背景技术
最近,伴随着半导体装置的高功能化/多功能化,WL-CSP(晶圆级芯片封装:Wafer Level-Chip Scale Package)技术的实用化正在发展。WL-CSP技术中,在晶圆状态下完成封装(Packaging,パツケ-ジング)工序,通过切割切出的各个芯片大小为封装大小(package size)。
如图13所示,适用WL-CSP技术的半导体装置具备:表面整个区域由钝化膜91覆盖的半导体芯片92;层叠在钝化膜91上的聚酰亚胺层93;形成于聚酰亚胺层93上的再次布线94;层叠在聚酰亚胺层93以及再次布线94上的密封树脂层95;配置于密封树脂层95上的焊球96。钝化膜91中形成有用于使内部布线的一部分作为电极焊盘(pad)97露出的焊盘开口98。而且,再次布线94经由贯通聚酰亚胺层93而形成的贯通孔99与该电极焊盘97连接。此外,再次布线94经由贯通密封树脂层95的立柱100与焊球96连接。该半导体装置,通过焊球96与安装基板上的焊盘连接,从而实现对安装基板的安装(对安装基板的电气的以及机械的连接)。
这种半导体装置的制造工序中,准备有作入多个半导体芯片的晶圆。首先,在该晶圆的状态下,在被覆晶圆的表面的钝化膜91上形成聚酰亚胺层93以及再次布线94。接下来,在再次布线94上的规定位置上,通过镀敷等的方法形成立柱100。之后,向晶圆的表面供给密封树脂层95的材料即环氧树脂以使埋没立柱100。并且,在该环氧树脂的硬化后,环氧树脂的表面由研磨机(grinder)被研磨,使立柱100的表面(前端面)从环氧树脂露出。
但是,由于形成立柱100的铜等的金属材料具有延展性,因此在由研磨机进行的环氧树脂的研磨时,受到该研磨机的影响,立柱100的前端部如图13中虚线所示那样在环氧树脂(密封树脂层95)的表面上延伸并扩展(流出、だれる)。这种金属材料的流出会产生例如在多个立柱100间的短路等问题的可能性。
在此,在由研磨机进行的环氧树脂的研磨后,对晶圆的表面供给氨系的蚀刻液,进行用于除去在环氧树脂的表面上延伸并扩展的金属材料的蚀刻処理。该蚀刻処理之后,在立柱100上形成焊球96。而且,沿着在晶圆内的各半导体芯片之间设定的切割线来切断(切割)晶圆。由此,得到图13所示结构的半导体装置。
蚀刻処理后,如图13所示,立柱100的前端面的位置变为比密封树脂层95的表面的位置低一段。因此,形成于立柱100上的焊球96的基端部,与由密封树脂层95的表面和密封树脂层95的与立柱100的侧面相接触的面(配置立柱100的贯通孔的内面)所形成的角部90抵接。这种角部90与焊球96抵接时,在半导体芯片92或安装基板上产生热膨胀/收缩等时,应力集中在该角部90和焊球96之间的抵接部分,通过该应力会有产生裂缝进入焊球96等的损伤的可能性。
图14为表示适用WL-CSP技术的半导体装置的其他构造的截面图。
该半导体装置具备半导体芯片101。半导体芯片101采用钝化膜102覆盖其表面的整个区域。该钝化膜102中形成有用于使焊盘103露出的焊盘开口104。
在钝化膜102上层叠有聚酰亚胺层105。在聚酰亚胺层105上形成有再次布线106。该再次布线106经由贯通聚酰亚胺层105而形成的贯通孔107与焊盘103连接。
另一方面,在钝化膜102的下方,从构成半导体芯片101的基体的半导体基板108侧开始依次层叠有第1布线层109、第1层间膜110、第2布线层111以及第2层间膜112。第1布线层109和第2布线层111经由形成于第1层间膜110的过孔(via hole)113而电连接。并且,经由形成于第2层间膜112的过孔114,第2布线层111和焊盘103电气地连接。
此外,在聚酰亚胺层105以及再次布线106上层叠有由环氧树脂构成的密封树脂层115。再次布线106经由贯通该密封树脂层115的立柱116与配设于密封树脂层115的表面的焊球117连接。
在这种多层布线构造的半导体装置中,半导体芯片101、钝化膜102、第1层间膜110、第2层间膜112以及密封树脂层115的各侧面成为一面而露出。因此,在对半导体装置的侧面施加应力时,在该侧面中,产生钝化膜102、第1层间膜110以及第2层间膜112和其下层之间的龟裂(ひび割れ)(钝化膜102、第1层间膜110以及第2层间膜112的剥落)。这种龟裂前进直到半导体芯片101的元件形成区域上为止时,会有产生形成于该元件形成区域的功能元件的动作不良的可能性。
专利文献1:日本特开2001-210760号公报
专利文献2:日本特开2001-298120号公报
发明内容
在此,本发明的第1目的为提供一种能够防止应力对立柱上的外部连接端子局部地集中,由此能够防止外部连接端子的损伤的产生的半导体装置。
此外,本发明的第2目的为提供一种能够防止在钝化膜以及各层间膜和这些各膜的下层之间发生龟裂的半导体装置。
用于实现上述第1目的的本发明的半导体装置,包括:半导体芯片;密封树脂层,其被层叠在该半导体芯片的表面上;立柱,其在上述半导体芯片和上述密封树脂层之间的层叠方向上贯通该密封树脂层而设置,在上述密封树脂层上突出,该突出的部分的周缘部在上述层叠方向上与上述密封树脂层的表面对置并全部接触;和外部连接端子,其被设置在上述密封树脂层上,并与上述立柱连接。
通过该结构,从立柱的密封树脂层突出的部分的周缘部,在半导体芯片和密封树脂层之间的层叠方向上,与密封树脂层的表面对置而接触。因此,由密封树脂层的表面和密封树脂层的与立柱的侧面接触的面(配置立柱的孔的内面)所形成的角部与埋设在立柱的密封树脂层的部分和从密封树脂层突出的部分之间的边界抵接,处于通过该立柱覆盖的状态下。因此,能够防止该角部与外部连接端子抵接。因此,在半导体芯片或安装该半导体装置的安装基板上产生热膨胀/收缩等时,能够防止对外部连接端子局部地集中应力。其结果,能够防止这种应力集中所引起的外部连接端子的损伤的发生。
上述立柱也可为具备埋设于上述密封树脂层的埋设部;和与该埋设部连接且前端部分在上述密封树脂层上突出的突出部的结构。此时,上述突出部优选具有比上述外部连接端子高的刚性。如果突出部的刚性高,则能够有效地防止突出部由于来自密封树脂层的角部的应力集中而损伤。
此外,在具备上述埋设部以及上述突出部的结构中,优选上述埋设部,在在形成于上述密封树脂层的贯通孔内与上述贯通孔的内面之间隔开空隙而设置,上述突出部伸入到上述埋设部和上述贯通孔的内面之间的间隙中。通过将突出部***到埋设部和贯通孔的内面之间的间隙,突出部,在与埋设部之间的连接部分不具有与埋设部的前端面和贯通孔的内面相接触的直角的角部。由此,在半导体芯片或安装该半导体装置的安装基板上产生热膨胀/收缩等时,能够防止应力对突出部的与埋设部之间的连接部分局部地集中。
另外,埋设部和突出部也可采用相同的材料而形成,也可采用不同的材料来形成。
此外,上述立柱也可为具备:前端部分在上述密封树脂层上突出的柱状部;和包覆(被着)在该柱状部的上述前端部分的包覆部的结构。此时,上述柱状部也可具有:第1柱状部,其被埋设在上述密封树脂层;和第2柱状部,其与该第1柱状部连接,且前端部分在上述密封树脂层上突出。进而,上述包覆部也可具有:覆盖上述柱状部的上述前端部分的第1包覆部;和覆盖该第1包覆部的表面的第2包覆部。
此外,在具备上述柱状部和上述包覆部的结构中,优选上述柱状部,在形成于上述密封树脂层的贯通孔内与上述贯通孔的内面之间隔开空隙而设置,上述包覆部伸入到上述柱状部和上述贯通孔的内面之间的间隙中。通过包覆部伸入到柱状部和贯通孔的内面之间的间隙,包覆部,在与柱状部之间的连接部分不具有与柱状部的前端面和贯通孔的内面相接触的直角的角部。由此,在半导体芯片或安装该半导体装置的安装基板上产生热膨胀/收缩等时,能够防止应力对包覆部的与柱状部之间的连接部分局部地集中。
另外,柱状部和包覆部也可采用相同的材料形成,也可采用不同的材料形成。此外,关于第1柱状部以及第2柱状部,也可采用相同的材料来形成,也可采用不同的材料来形成。进而,关于第1包覆部以及第2包覆部,也可采用相同的材料来形成,也可采用不同的材料来形成。
用于实现上述第2目的的本发明的半导体装置,包括:半导体芯片,其在表面的周缘部具有在表面侧以及侧面侧开放的槽;和密封树脂层,其被层叠在该半导体芯片上,伸入到上述槽中,并用来密封上述半导体芯片的表面侧,上述半导体芯片具备:构成该半导体芯片的基体的半导体基板;在该半导体基板上上下地层叠的多个布线层;介于各布线层间的层间膜;和被覆最上层的布线层的表面的钝化膜,由伸入到上述密封树脂层的上述槽的部分覆盖各层间膜以及各钝化膜的侧面。
通过该结构,在半导体芯片的表面的周缘部形成槽,密封树脂层伸入到该槽。由此,半导体芯片的表层部的侧面,即层间膜以及钝化膜的各侧面,由伸入到该槽的密封树脂层来覆盖。因此,能够防止钝化膜以及各层间膜和上述各膜的下层之间的龟裂的发生。
上述半导体装置,还包括:多个立柱,其在上述半导体芯片和上述密封树脂层之间的层叠方向上贯通上述密封树脂层而设置,基端部与最上层的上述布线层电连接;和外部连接端子,其在各立柱的前端部上接触而形成,在上述密封树脂层上突出,优选上述密封树脂层,在上述半导体芯片的表面上涂敷未硬化的液状树脂,通过使该液状树脂硬化而形成。
通过该结构,采用液状树脂作为密封树脂层的材料,从而能够使该液状树脂良好地进入到多个立柱各个之间和槽。其结果,能够用密封树脂层可靠地填满多个立柱的各个之间或槽。
此外,用于实现上述第1以及第2目的的本发明的半导体装置,包括:半导体芯片,其在表面的周缘部具有在表面侧以及侧面侧开放的槽;密封树脂层,其被层叠在该半导体芯片上,伸入到上述槽中,并用来密封上述半导体芯片的表面侧;和多个立柱,其在上述半导体芯片和上述密封树脂层之间的层叠方向上贯通上述密封树脂层而设置,基端部与最上层的布线层电连接,在上述密封树脂层上突出,该突出的部分的周缘部在上述层叠方向上与上述密封树脂层的表面对置并全部接触;和外部连接端子,其在各立柱的突出的部分的前端部上接触而形成,在上述密封树脂层上突出,上述半导体芯片具备:构成该半导体芯片的基体的半导体基板;在该半导体基板上、上下地层叠的多个布线层;介于各布线层间的层间膜;和被覆最上层的布线层的表面的钝化膜,由上述密封树脂层的伸入到上述槽的部分覆盖各层间膜以及钝化膜的侧面。
通过该结构,立柱的从密封树脂层突出的部分的周缘部,在半导体芯片和密封树脂层之间的层叠方向中,与密封树脂层的表面对置并接触。因此,通过与密封树脂层的表面和密封树脂层的立柱的侧面接触的面(配置立柱的孔的内面)所形成的角部,与立柱的埋设于密封树脂层的部分和从密封树脂层突出的部分之间的边界抵接,处于通过该立柱覆盖的状态下。因此,能够防止该角部与外部连接端子抵接。因此,在半导体芯片或安装该半导体装置的安装基板上产生热膨胀/收缩等时,能够防止应力对外部连接端子局部地集中。其结果,能够防止这种应力集中所引起的外部连接端子的损伤的发生。
此外,在半导体芯片的表面的周缘部形成槽,密封树脂层伸入到该槽。由此,半导体芯片的表层部的侧面,即层间膜以及钝化膜的各侧面由伸入到该槽的密封树脂层来覆盖。因此,能够防止钝化膜以及各层间膜和上述各膜的下层之间的龟裂的发生。
本发明中的上述或者进而其他的目的、特征以及效果能参照附图而由以下所述的实施方式的说明来明确。
附图说明
图1为表示本发明的一实施方式相关的半导体装置的结构的图解的截面图。
图2为图1中所示的半导体装置中的立柱附近的图解的截面图。
图3为表示立柱的其他结构(具有第1柱状部、第2柱状部以及包覆部的结构)的图解的截面图。
图4为表示立柱的其他结构(具有柱状部以及包覆部的结构)的图解的截面图。
图5为表示立柱的其他结构(包覆部伸入到柱状部和贯通孔的内面之间的间隙中的结构)的图解的截面图。
图6为表示立柱的其他结构(具有柱状部、第1包覆部以及第2包覆部的结构)的图解的截面图。
图7为表示立柱的其他结构(突出部伸入到埋设部和贯通孔的内面之间的间隙中的结构)的图解的截面图。
图8为表示半导体装置的其他结构(对一个金属球设置多个立柱的结构)的截面图。
图9为表示图9中所示的半导体装置中的立柱的其他结构(具有柱状部以及包覆部的结构)的截面图。
图10为图解地表示再次布线、金属球以及电极焊盘的配置例的俯视图。
图11为表示本发明的其他实施方式相关的半导体装置的构造的截面图。
图12为按照工序顺序表示图11中所示的半导体装置的制造工序的截面图。
图13为表示现有的半导体装置的结构的图解的截面图。
图14为表示具有多层布线构造的现有的半导体装置的构造的图解的截面图。
符号的说明:
1半导体芯片
4密封树脂层
5立柱
6金属球
13周缘部
14埋设部
15突出部
16角部
17第1柱状部
18第2柱状部
19包覆部
20柱状部
21第1包覆部
22第2包覆部
41贯通孔
201半导体芯片
204密封树脂层
205金属球(外部连接端子)
211半导体基板
212第1布线层
213第1层间膜
214第2布线层
215第2层间膜
216第3布线层
217第3层间膜
218第4布线层
222钝化膜
231槽
233立柱
具体实施方式
以下,参照附图对本发明的实施方式进行详细的说明。
图1为表示本发明的一实施方式相关的半导体装置的结构的图解的截面图。
该半导体装置由WL-CSP(晶圆级芯片封装:Wafer Level-Chip ScalePackage)技术制作。该半导体装置具备:半导体芯片1;层叠在半导体芯片1上的应力缓和层2;配设在应力缓和层2上的多个再次布线3;层叠在应力缓和层2以及再次布线3上的密封树脂层4;贯通密封树脂层4而设置的多个立柱5;设置在密封树脂层4上并作为与各立柱5连接的外部连接端子的金属球6。并且,该半导体装置通过各金属球6与安装基板7上的焊盘8连接,而实现与安装基板7的安装(对安装基板7的电气的以及机械的连接)。
半导体芯片1例如为俯视为大致矩形状的硅芯片。该半导体芯片1在最表层部具有由氧化硅或氮化硅构成的钝化膜(表面保护膜)9。该钝化膜9中,形成有用于使与作入到半导体芯片1的功能元件电气地连接的内部布线部分地作为电极焊盘10露出的多个焊盘开口11。
应力缓和层2例如由聚酰亚胺构成。该应力缓和层2按照被覆钝化膜9的表面整个区域的方式形成,具有吸收施加到该半导体装置的应力并进行缓和的功能。此外,在应力缓和层2上,在与各电极焊盘10对置的位置贯通并形成贯通孔12。
再次布线3例如采用铜等的金属材料而形成。再次布线3在应力缓和层2的表面上从各贯通孔12到设置有各立柱5的位置延伸。而且,各再次布线3的一端部经由贯通孔12与电极焊盘10电气地连接。
密封树脂层4例如由环氧树脂构成。该密封树脂层4按照覆盖应力缓和层2以及再次布线3的表面的方式形成,密封该半导体装置中的半导体芯片1的表面侧。该密封树脂层4,在再次布线3上,例如具有圆筒状的内面的贯通孔41在与半导体芯片1的表面正交的方向上贯通而形成。此外,该密封树脂层4的表面形成为平坦面,并且其侧面形成为与半导体芯片1的侧面成为一面。由此,该半导体装置具有俯视中的大小与半导体芯片1的大小相等的大致长方体形状。
图2为立柱5的附近的图解的截面图。
立柱5由金属材料构成。立柱5配置在贯通孔41内,将密封树脂层4在半导体芯片1和密封树脂层4之间的层叠方向(以下,简称为“层叠方向”。)贯通而设置。立柱5的前端部在密封树脂层4上突出,该突出的部分的周缘部13形成为与密封树脂层4的表面在层叠方向对置并接触的形状。
更具体地来说,立柱5具备埋设到密封树脂层4的埋设部14和与该埋设部14连接且前端部分在密封树脂层4上突出的突出部15。
埋设部14例如由铜构成。该埋设部14形成为具有没有从密封树脂层4突出的厚度的扁平的柱状(圆柱状或者棱柱体)。
突出部15例如由镍构成。该突出部15具有比金属球6高的刚性。该突出部15的埋设于密封树脂层4的基端部分形成为具有与埋设部14相同的截面形状(通过与层叠方向正交的切断面切断时的截面形状)的扁平的柱状(例如厚度3~5μm)。此外,突出部15的从密封树脂层4突出的前端部分(例如厚度3~50μm)形成为与层叠方向正交的方向上的宽度(直径)比基端部分的相同方向中的宽度大,该周缘部13在与层叠方向正交的方向突出。由此,突出部15的前端部分的周缘部13在层叠方向上与密封树脂层4的表面对置并接触。而且,通过该突出部15的前端部分覆盖由密封树脂层4的表面和贯通孔41的内面所形成的角部16。
金属球6采用例如焊锡材料而形成为球状,覆盖立柱5从密封树脂层4突出的部分(突出部15的前端部分)的所有露出面(表面以及侧面)。
图10为图解地表示再次布线3、金属球6以及电极焊盘10的配置例的俯视图。另外,在半导体装置已完成的状态下,再次布线3以及电极焊盘10由密封树脂层4覆盖而不能够看到,但在图10中,用实线来表示它们。此外,为了防止图面的复杂化,仅对再次布线3、金属球6以及电极焊盘10的一部分分别付与符号。
电极焊盘10沿半导体芯片1的外周缘以俯视矩形环状排列并配置。互相邻接的电极焊盘10之间分别空开适当的间隔。
金属球6设置与电极焊盘10相同的数目。而且,金属球6按照在俯视下,在比电极焊盘10更内侧的区域矩形环状地排列并配置2列。
再次布线3一对一地连接电极焊盘10和金属球6。各再次布线3按照互相不交差的方式形成在应力缓和层2的表面上。
如上所述,立柱5的从密封树脂层4突出的部分的周缘部13在层叠方向与密封树脂层4的表面对置并接触。因此,通过密封树脂层4的表面和贯通孔41的内面所形成的角部16与立柱5的埋设在密封树脂层4的部分和从密封树脂层4突出的部分之间的边界抵接,处于由立柱5(突出部15)覆盖的状态下。因此,能够防止该角部16与金属球6抵接。其结果,在半导体芯片1或安装该半导体装置的安装基板7中产生热膨胀/收缩等时,能够防止对金属球6局部地集中应力,能够防止由这种应力集中所产生的金属球6的损伤的发生。
在该半导体装置的制造工序中,准备作入多个半导体芯片1的晶圆。首先,在该晶圆的状态下,在被覆晶圆的表面的钝化膜9上形成应力缓和层2以及再次布线3。之后,在再次布线3上的规定位置,通过镀敷等的方法,将立柱5的形成埋设部14的金属材料堆积为柱状。接下来,对晶圆的表面供给密封树脂层4的材料即环氧树脂,以使埋没柱状地堆积的金属材料。而且,在该环氧树脂的硬化后,通过采用研磨机研磨环氧树脂的表面,从而柱状地堆积的金属材料的表面(前端面)从环氧树脂露出。由此,实现形成密封树脂层4。之后,对晶圆的表面供给蚀刻液,通过由研磨机进行研磨而将贯通密封树脂层4的柱状的金属材料的前端部与在密封树脂层4上延伸的金属材料一起除去,从而得到具有比密封树脂层4的表面低一段的前端面的埋设部14。该蚀刻処理之后,通过无电解镀敷的方法在埋设部14上形成突出部15,进而在其前端部形成金属球6。并且,沿在晶圆内的各半导体芯片1之间设定的切割线,切断(切割)晶圆。由此,得到图1所示的结构的半导体装置。
另外,在该实施方式中,埋设部14由铜构成,突出部15由镍构成,但埋设部14以及突出部15也可分别采用其他种类的金属材料来形成。作为形成埋设部14以及突出部15的金属材料,除了铜、镍之外,还能例示银、金、钴等。此外,埋设部14以及突出部15也可采用相同的金属材料来形成。
图3为表示立柱5的其他结构的截面图。在该图3中,与图2中所示的各部分对应的部分付与并表示与图2的情况相同的参照符号。
该图3中所示的立柱5具备:埋设在密封树脂层4中的第1柱状部17;与第1柱状部连接,前端部分从密封树脂层上突出的第2柱状部18;和包覆(在覆盖的状态下付着)在第2柱状部18的前端部分的包覆部19。
第1柱状部17由例如铜构成,形成为具有没有从密封树脂层4突出的厚度的扁平的柱状(圆柱状或棱柱体)。
第2柱状部18由例如镍构成,形成为具有与第1柱状部17相同的截面形状(以与层叠方向正交的切断面切断时的截面形状)的扁平的柱状(例如厚度3~50μm)。
包覆部19由例如金构成,按照覆盖第2柱状部18的从密封树脂层4突出的部分的所有露出面的方式进行包覆。
在该结构中,包覆部19在层叠方向与密封树脂层4的表面对置并接触。由此,通过由密封树脂层4的表面和贯通孔41的内面所形成的角部16,与第2柱状部18的侧面和包覆部19的下端面之间的边界抵接,而不与金属球6抵接。因此,能够实现与图2所示的结构相同的作用效果。
另外,第1柱状部17和第2柱状部18也可采用相同的金属材料(例如铜)来形成。此时,第1柱状部17以及第2柱状部18成为一体,如图4所示,前端部分构成在密封树脂层4上突出的柱状部20。
此外,该柱状部20,如图5所示,也可形成为具有下述部分的形状:与半导体芯片1的表面大致平行的平坦状的前端面51;按照越靠近前端侧(金属球6侧)越逐渐变细的方式倾斜的倾斜侧面52;和与前端面51和倾斜侧面52接续的截面大致圆弧状的接续面53。而且,包覆部19也可伸入到在柱状部20的接续面53和贯通孔41的内面之间形成的间隙。
通过包覆部19伸入到柱状部20和贯通孔41的内面之间的间隙,从而包覆部19,在与柱状部20之间的连接部分,不具有与柱状部20的前端面51和贯通孔41的内面相接触的直角的角部。由此,能够防止在半导体芯片1或安装该半导体装置的安装基板上产生热膨胀/收缩等时,对包覆部19的与柱状部20之间的连接部分局部地集中应力。
此外,包覆部19和柱状部20(第1柱状部17以及第2柱状部18)也可采用相同的金属材料形成。
进而此外,如图6所示,包覆部19也可具有覆盖柱状部20的前端部分的第1包覆部21和覆盖该第1包覆部21的表面的第2包覆部22。此时,第1包覆部21和第2包覆部22也可采用相同的金属材料来形成,也可采用不同的金属材料来形成。例如也可由镍形成第1包覆部,由金形成第2包覆部。
图7为表示立柱5的其他结构的截面图。在该图7中,对与图2中所示的各部分对应的部分付与并表示与图2的情况相同的参照符号。
该图7所示的立柱5的埋设部14形成具有下述部分的形状:与半导体芯片1的表面大致平行的平坦状的前端面71;按照相对贯通孔41的内面越接近前端侧(突出部15侧)产生越大间隙的方式倾斜的倾斜侧面72;和沿贯通孔41的贯通方向(与半导体芯片1的表面正交的方向)的截面形状具有大致圆弧状,接续前端面71和倾斜侧面72的接续面73。由此,在埋设部14的接续面73和贯通孔41的内面之间,形成随着接近埋设部14的前端而逐渐扩大间隔的间隙。
而且,突出部15伸入到埋设部14的接续面73和贯通孔41的内面之间的间隙。
在该图7所示的结构中,也通过突出部15的前端部分覆盖由密封树脂层4的表面和贯通孔41的内面所形成的角部16,因此能够实现与图2所示的结构相同的作用效果。
此外,通过突出部15伸入到埋设部14的接续面73和贯通孔41的内面之间的间隙,从而突出部15,在与埋设部14之间的连接部分,不具有与埋设部14的前端面71和贯通孔41的内面相接触的直角的角部。由此,能够防止在半导体芯片1或安装该半导体装置的安装基板产生热膨胀/收缩等时,对突出部15的与埋设部14之间的接续部分局部地集中应力。
图8为表示半导体装置的其他结构的截面图。在该图8中,在与图2所示的各部分对应的部分,付与并表示与图2的情况相同的参照符号。
在图2所示的结构中,对1个金属球6设置一个立柱5,但在图8所示的结构中,对1个金属球6设置多个立柱5。
通过该图8所示的结构也能由各立柱5的突出部15的前端部分覆盖由密封树脂层4的表面和贯通孔41的内面所形成的角部16。因此,能够实现与图2所示的结构相同的作用效果。
此外,对1个金属球6设置多个立柱5,因此在半导体芯片1或安装该半导体装置的安装基板7中产生热膨胀/收缩等时,能够由多个立柱5分散应力。其结果,能够实现耐应力性的提高,能够增加半导体芯片1的对安装基板7的安装的可靠性。
另外,如图9所示,各立柱5也可为具有:形成为具有与贯通孔41的内径一致的外径的圆柱状的柱状部20;包覆在该柱状部20的从密封树脂层4突出的前端部分的包覆部19的结构。在该结构中,由密封树脂层4的表面和贯通孔41的内面所形成的角部16与柱状部20的侧面和包覆部19的下端面之间的边界抵接,与金属球6不抵接。因此,能够实现与图8所示的结构相同的作用效果。
图11为表示本发明的其他实施方式相关的半导体装置的构造的截面图。该半导体装置通过WL-CSP技术来制作。该半导体装置具备:半导体芯片201;层叠在半导体芯片201上的应力缓和层202;形成在应力缓和层202上的再次布线203;层叠在再次布线203上的密封树脂层204;和配置于密封树脂层204上的金属球205。
半导体芯片201具有多层布线构造。在构成该半导体芯片201的基体的半导体基板211上,第1布线层212、第1层间膜213、第2布线层214、第2层间膜215、第3布线层216、第3层间膜217以及第4布线层218从半导体基板211侧以该顺序被层叠。
第1布线层212、第2布线层214、第3布线层216以及第4布线层218形成在分别设计的图案上。而且,第1布线层212和第2布线层214经由形成于第1层间膜213的多个过孔219而电气地连接。此外,第2布线层214和第3布线层216经由形成于第2层间膜215的多个过孔220而电气地连接。第3布线层216和第4布线层218经由形成于第3层间膜217的多个过孔221而电气地连接。第3层间膜217以及第4布线层218的表面由构成半导体芯片201的最表层的钝化膜222来覆盖。钝化膜222上形成有用于将第4布线层218的一部分作为焊盘223露出的开口。
此外,半导体芯片201形成为俯视为大致矩形状。在半导体芯片201的表面的周缘部,横跨全周形成表面侧以及侧面侧开放的槽231。该槽231形成为越靠近半导体芯片201的背面侧、宽度越窄的截面三角形状,其最深部(最底部)到达半导体基板211。由此,在槽231内露出第1层间膜213、第2层间膜215、第3层间膜217以及钝化膜222的各侧面。
应力缓和层202由例如聚酰亚胺构成,在对该半导体装置施加应力时,为了吸收并缓和该应力而设置。在该应力缓和层202中,在与焊盘223对置的位置,贯通孔232贯通而形成。
再次布线203经由贯通孔232而与焊盘223连接。此外,再次布线203沿着应力缓和层202的表面而延伸到与夹持密封树脂层204的金属球205对置的位置。
密封树脂层204由例如环氧树脂构成,密封该半导体装置的表面侧。该密封树脂层204覆盖应力缓和层202以及再次布线203的表面,进而从上述部分的表面伸入到槽231,填满该槽231。由此,第1层间膜213、第2层间膜215、第3层间膜217以及钝化膜222的各侧面由伸入到密封树脂层204的槽231的部分来被覆。此外,密封树脂层204形成为表面为平坦面,并且其侧面与半导体芯片201的侧面为一面。由此,该半导体装置具有俯视中的大小与半导体芯片201的大小相等的大致长方体形状。
此外,密封树脂层204中,在再次布线203和金属球205之间贯通地设置有例如由铜等的金属构成的扁平的圆柱状的立柱233,通过该立柱233,再次布线203和金属球205被连接。
金属球205为用于与未图示的布线基板等进行连接(外部连接)的外部连接端子,采用例如焊锡等的金属材料来形成为球状。
如上所述,在半导体芯片201的表面的周缘部形成槽231,密封树脂层204伸入到该槽231。由此,半导体芯片201的表层部的侧面,即第1层间膜213、第2层间膜215、第3层间膜217以及钝化膜222的各侧面由伸入到该槽231的密封树脂层204覆盖。因此,能够防止第1层间膜213、第2层间膜215、第3层间膜217以及钝化膜222和这些各膜的下层之间的龟裂的发生。
图12为按照工序顺序表示图11所示的半导体装置的制造工序的截面图。
首先,准备多个半导体芯片201的表面整个区域由钝化膜222覆盖的晶圆W。之后,如图12(a)所示,在钝化膜222形成用于使焊盘223露出的开口。之后,在钝化膜222上依次形成应力缓和层202以及再次布线203。进而,在再次布线203上的规定位置(金属球205的形成位置)通过例如电解镀敷来形成多个立柱233。
接下来,如图12(b)所示,沿着切割线L,朝向晶圆W的背面成为逐渐变细的截面倒梯形状的凹部241按照从应力缓和层202的表面到第1布线层212的下方为止凹陷的方式而形成。该凹部241也可由例如激光加工来形成,也可采用周面的截面形状形成为与凹部241的形状对应的截面梯形状的刀片(未图示),通过半切(half cut,ハ-フカツト)的方法来形成。
之后,如图12(c)所示,在晶圆W的表面整个区域上形成密封树脂层204。在晶圆W的表面整个区域上涂敷未硬化的液状环氧树脂,使其硬化后,研磨该表面直至立柱233露出为止来形成该密封树脂层204。通过采用液状环氧树脂来作为密封树脂层204的材料,而能够使该液状环氧树脂良好地进入到多个立柱233的各个之间或凹部241。其结果,能够由密封树脂层204可靠地填满多个立柱233的各个之间或凹部241。
接下来,在各立柱233上形成金属球205。之后,如图12(d)所示,采用未图示的切割刀片,沿着切割线L来切断(切割)晶圆W。由此,晶圆W被切分为半导体芯片201的单个片,凹部241作为切割线L的两侧的半导体芯片201的槽231被分割,得到图11所示的结构的半导体装置。
除此之外,能够在专利请求的范围中所记载的事项的范围中实施各种设计变更。即上述的实施方式并不限于为了使本发明的技术内容明确而采用的具体例,本发明并不应限定地解释为这些具体例,本发明的精神以及范围仅由添加的请求的范围来限定。
例如图2~图9中所示的结构也能适用于图11中所示的半导体装置。
本申请与在2005年10月3日对日本国专利局提出的特愿2005-290167号、2005年12月9日对日本国专利局提出的特愿2005-356651号以及在2006年10月3日对日本国专利局提出的特愿2006-271658号相对应,上述申请的所有公开在此通过引用而被组入。
Claims (9)
1.一种半导体装置,其特征在于,包括:
半导体芯片;
密封树脂层,其被层叠在该半导体芯片的表面上;
立柱,其在上述半导体芯片和上述密封树脂层之间的层叠方向上贯通该密封树脂层而设置,在上述密封树脂层上突出,该突出的部分的周缘部在上述层叠方向上与上述密封树脂层的表面对置并全部接触;和
外部连接端子,其被设置在上述密封树脂层上,并与上述立柱连接。
2.根据权利要求1所述的半导体装置,其特征在于,
上述立柱具备:
埋设部,其被埋设在上述密封树脂层;和
突出部,其与该埋设部连接且前端部分在上述密封树脂层上突出。
3.根据权利要求2所述的半导体装置,其特征在于,
上述突出部具有比上述外部连接端子高的刚性。
4.根据权利要求2所述的半导体装置,其特征在于,
上述埋设部,在形成于上述密封树脂层的贯通孔内与上述贯通孔的内面之间隔开空隙而设置,
上述突出部伸入到上述埋设部和上述贯通孔的内面之间的间隙中。
5.根据权利要求1所述的半导体装置,其特征在于,
上述立柱具备:
前端部分在上述密封树脂层上突出的柱状部;和
包覆在该柱状部的上述前端部分的包覆部。
6.根据权利要求5所述的半导体装置,其特征在于,
上述柱状部具有:
第1柱状部,其被埋设在上述密封树脂层;和
第2柱状部,其与该第1柱状部连接,且前端部分在上述密封树脂层上突出。
7.根据权利要求5所述的半导体装置,其特征在于,
上述包覆部具有:
覆盖上述柱状部的上述前端部分的第1包覆部;和
覆盖该第1包覆部的表面的第2包覆部。
8.根据权利要求5所述的半导体装置,其特征在于,
上述柱状部,在形成于上述密封树脂层的贯通孔内与上述贯通孔的内面之间隔开空隙而设置,
上述包覆部伸入到上述柱状部和上述贯通孔的内面之间的间隙中。
9.一种半导体装置,其特征在于,包括:
半导体芯片,其在表面的周缘部具有在表面侧以及侧面侧开放的槽;
密封树脂层,其被层叠在该半导体芯片上,伸入到上述槽中,并用来密封上述半导体芯片的表面侧;和
多个立柱,其在上述半导体芯片和上述密封树脂层之间的层叠方向上贯通上述密封树脂层而设置,基端部与最上层的布线层电连接,在上述密封树脂层上突出,该突出的部分的周缘部在上述层叠方向上与上述密封树脂层的表面对置并全部接触;和
外部连接端子,其在各立柱的突出的部分的前端部上接触而形成,在上述密封树脂层上突出,
上述半导体芯片具备:构成该半导体芯片的基体的半导体基板;在该半导体基板上、上下地层叠的多个布线层;介于各布线层间的层间膜;和被覆最上层的布线层的表面的钝化膜,
由上述密封树脂层的伸入到上述槽的部分覆盖各层间膜以及钝化膜的侧面。
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JP2005356651A JP2007165402A (ja) | 2005-12-09 | 2005-12-09 | 半導体装置 |
JP2006271658A JP5279180B2 (ja) | 2005-10-03 | 2006-10-03 | 半導体装置 |
PCT/JP2006/319801 WO2007040229A1 (ja) | 2005-10-03 | 2006-10-03 | 半導体装置 |
JP271658/2006 | 2006-10-03 |
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2006
- 2006-10-03 WO PCT/JP2006/319801 patent/WO2007040229A1/ja active Application Filing
- 2006-10-03 KR KR1020087007892A patent/KR20080049807A/ko not_active Application Discontinuation
- 2006-10-03 CN CN2006800366350A patent/CN101278394B/zh active Active
- 2006-10-03 TW TW095136825A patent/TW200717743A/zh unknown
- 2006-10-03 US US11/992,985 patent/US8063495B2/en active Active
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2011
- 2011-10-17 US US13/274,738 patent/US8432046B2/en active Active
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Also Published As
Publication number | Publication date |
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KR20080049807A (ko) | 2008-06-04 |
US20090224409A1 (en) | 2009-09-10 |
WO2007040229A1 (ja) | 2007-04-12 |
CN101278394A (zh) | 2008-10-01 |
US20130221530A1 (en) | 2013-08-29 |
US8432046B2 (en) | 2013-04-30 |
US8063495B2 (en) | 2011-11-22 |
TW200717743A (en) | 2007-05-01 |
US20120032325A1 (en) | 2012-02-09 |
US8659174B2 (en) | 2014-02-25 |
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