CN101156164B - 非接触型信息存储介质及其制造方法 - Google Patents
非接触型信息存储介质及其制造方法 Download PDFInfo
- Publication number
- CN101156164B CN101156164B CN200680011593.5A CN200680011593A CN101156164B CN 101156164 B CN101156164 B CN 101156164B CN 200680011593 A CN200680011593 A CN 200680011593A CN 101156164 B CN101156164 B CN 101156164B
- Authority
- CN
- China
- Prior art keywords
- chip
- resin
- semiconducter
- protrusion
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
- G06K19/0775—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card arrangements for connecting the integrated circuit to the antenna
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49855—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers for flat-cards, e.g. credit cards
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/12—Supports; Mounting means
- H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q9/00—Electrically-short antennas having dimensions not more than twice the operating wavelength and consisting of conductive active radiating elements
- H01Q9/04—Resonant antennas
- H01Q9/16—Resonant antennas with feed intermediate between the extremities of the antenna, e.g. centre-fed dipole
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6661—High-frequency adaptations for passive devices
- H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13012—Shape in top view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13144—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13155—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
- H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/26165—Alignment aids
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29199—Material of the matrix
- H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29299—Base material
- H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/731—Location prior to the connecting process
- H01L2224/73101—Location prior to the connecting process on the same surface
- H01L2224/73103—Bump and layer connectors
- H01L2224/73104—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8112—Aligning
- H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
- H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
- H01L2224/8114—Guiding structures outside the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/819—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector with the bump connector not providing any mechanical bonding
- H01L2224/81901—Pressing the bump connector against the bonding areas by means of another connector
- H01L2224/81903—Pressing the bump connector against the bonding areas by means of another connector by means of a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8312—Aligning
- H01L2224/83136—Aligning involving guiding structures, e.g. spacers or supporting members
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8312—Aligning
- H01L2224/83136—Aligning involving guiding structures, e.g. spacers or supporting members
- H01L2224/83138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
- H01L2224/8314—Guiding structures outside the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
- H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00013—Fully indexed content
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01009—Fluorine [F]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01061—Promethium [Pm]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01068—Erbium [Er]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01075—Rhenium [Re]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/0665—Epoxy resin
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1902—Structure including thick film passive components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30105—Capacitance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Credit Cards Or The Like (AREA)
- Wire Bonding (AREA)
Abstract
一种非接触型信息存储介质,包括:至少具有存储信息的功能的半导体IC芯片(30),和形成有用于与***设备进行信号的交换的天线方向图(14)的树脂基板(10);其中,设置在树脂基板(10)上的天线方向图(14)的一个端部上的天线端子(141)与IC芯片(30)的电极端子(22)以相对的方式进行安装,并且在天线方向图(14)与IC芯片(30)的电路形成面(20)之间设置有至少5μm的间隙限制用绝缘层(32)。
Description
技术领域
本发明涉及与读写装置(R/W)等外部通信设备进行信息交换、能够不接触地读取或者存储包含各种信息的信号的非接触型信息存储介质及其制造方法。
背景技术
近年来,与ID卡、RF标签等非接触型信息存储介质(下面称作非接触卡)相关的技术急速进展。非接触卡由形成在树脂基板等上的天线方向图和连接到设置在天线方向图的一个端部的天线端子上的半导体IC芯片(下面称作IC芯片)构成。
现在,作为使用13.56MHz带的非接触卡,铁道公司等在月票、预付费卡等中有所使用。
这样的非接触卡通过技术开发的进展,小型化、低价格化不断推进,最近在更多样的领域中有所应用。例如,可以列举商品生产管理、流通管理中的线性管理***的构筑,以及小商品、书籍等的安全管理等的应用。但是,为了更广泛地普及,要求进一步提高非接触卡的便利性、降低成本。例如,要求实现具有柔性的非接触卡、延长通信距离以及减小通信距离的波动。
在此,作为用于延长通信距离的结构,在特开2002-298106号公报(下面记作“专利文献1”)中,公开了一种非接触卡,其包括:存储数据的IC芯片,使用电磁波非接触地收发所述数据的天线,和与天线相对地配置、向天线反射电磁波的反射单元。
根据所述专利文献1,由于设有反射单元,所以能够不安装电池地延 长通信距离。进而,不管背面的物质是什么,都能将数据的读写状态保持一定。
另外,在使用微波段时,为了抑制由基体材料的特性波动引起的通信距离的波动,在特开2005-71179号公报(下面记作“专利文献2”)中,公开了下述的结构。即,一种非接触卡,其包括:由纸构成的基体材料;从来自设置在基体材料上的外部读写装置的UHF波段中通过微波段的电磁波进行数据的收发的通信单元;具有以能够改写或者仅能够读取的方式存储数据的存储单元的IC芯片;由连接在IC芯片上的导电体构成的天线部,和设置在基体材料与天线部之间的介电常数的变化较小、并且由具有耐水性的材料构成的覆盖层。
另外,在特开2000-295024号公报(下面记作“专利文献3”)中,为了确保通信距离同时实现小型化,还公开了一种具有天线基板的非接触标签的结构,所述天线基板包括:具有规定的介电常数的电介质基板,和以使用天线导体使电流向同一方向流动的方式分离地形成在夹着电介质基板的两个面上的平面状的天线线圈。
但是,在专利文献1的非接触卡中,天线与反射单元的距离是由数据的读写所使用的电磁波的波长决定的,所以要延伸通信距离就需要设为规定的间隔。例如在使用2.45GHz时,最小间隔必须为7.7mm。因此,在该方式中,虽然能够增大通信距离,但是难以实现较薄的非接触卡。
另外,在专利文献2的非接触卡中,记载了通过抑制由纸构成的基体材料的介电常数的变化,能够减小天线部的共振频率的波动。但是,对于通过安装IC芯片时的安装状态而使通信距离波动的情况,则没有记载也没有暗示。
另外,在专利文献3的非接触标签中,通过形成在电介质基板的两面上的天线线圈之间的杂散电容(寄生电容)和天线线圈的电感,形成了共振电路,由此设为小型形状并增大了开口部,从而改善了通信距离。但是与专利文献2同样,对于通过安装IC芯片时的安装状态而使通信距离波动的情况,则没有记载也没有暗示。进而,上述结构在使用956MHz等超 短波、2.45GHz等微波时,难以成为有效的手段。
另外,一般在使用例如PET树脂这样的热塑性树脂基体材料作为非接触卡等基体材料的情况下,在IC芯片与天线方向图的天线端子的连接时,通过例如加热温度、加压载荷等条件,有时树脂基板会产生变形。进而,伴随着该变形,包含天线端子的天线方向图凹陷,由此有时IC芯片的电路形成面与天线端子的间隙会非常接近。
因此,本发明者等人新发现到,在IC芯片的电路形成面与天线端子的间隙变小时,通信距离会产生较大的波动。
发明内容
本发明的非接触卡,其结构为,包括:具有存储信息、处理信号的功能的半导体IC芯片,和由具有热塑性的基体材料构成、形成有用于与***设备进行信号的交换的天线方向图的树脂基板;其中,设置在该树脂基板上的天线方向图的一个端部上的天线端子与IC芯片的电极端子以相对的方式进行安装,并且在天线方向图与IC芯片的电路形成面之间设置有至少5μm的间隙。
通过该结构,能够充分减小在IC芯片的电路形成面与天线端子之间产生的杂散电容,所以预先设定的电容值不会波动。其结果,能够确保与设计值相同的通信距离,并且能够大幅度地抑制其波动。
另外,本发明的非接触卡的制造方法,其包括:向在聚酯类的基体材料上形成了天线方向图的树脂基板的天线端子上供给绝缘性粘接树脂或者各向异性导电性树脂的树脂供给工序;将在电极端子的表面上形成了具有至少5μm以上的厚度的***部的IC芯片配置在树脂基板上,从而对***部与天线端子进行对齐的对齐工序;对IC芯片进行按压并加热,从而使***部与天线端子直接接触或经由各向异性导电性树脂电气性地连接的安装工序;和使绝缘性粘接树脂或者各向异性导电性树脂固化的固化工序;其中,将安装工序以及固化工序中的加压力设为0.5 MPa~2.5MPa的范围内。
通过该方法,即使是使用通过加热而软化的聚酯类的基体材料的树脂基板,在安装工序以及固化工序中也能够抑制由按压引起的树脂基板的***、天线方向图的凹陷等变形。其结果,能够将天线端子与IC芯片的电路形成面的间隙设为作为***部的高度的5μm以上,能够抑制通信距离的波动。
附图说明
图1A是表示本发明者等人所使用的非接触卡的整体结构的俯视图。
图1B是图1A的IC芯片的安装部的放大俯视图。
图2是通过以往的安装条件以及固化条件、使用各向异性导电性树脂将IC芯片安装在图1B所示的树脂基板上时的沿着图1B的1B-1B线的剖面图。
图3是表示本发明的第1实施方式的非接触卡的构造的沿着图1B的1B-1B线的剖面图。
图4A是表示构成本发明的第1实施方式的非接触卡的IC芯片的构造的从电路形成面观察时俯视图。
图4B是沿着图4A的4B-4B线的剖面图。
图5是表示本发明的第1实施方式的非接触卡的构造的剖面图。
图6A是表示本发明的第2实施方式的非接触卡中、树脂基板的主要部分结构即安装IC芯片的区域的俯视图。
图6B是沿着图6A的6B-6B线的剖面图。
图7A是表示本发明的第3实施方式的非接触卡的构造的剖面图。
图7B是沿着图7A的7B-7B线的剖面图。
图8A是表示用于说明本发明的第4实施方式的非接触卡的制造方法的主要工序即将IC芯片相对于粘贴了硬质板的树脂基板进行对齐的状态的剖面图。
图8B是表示用于说明本发明的第4实施方式的非接触卡的制造方法的主要工序即对IC芯片进行按压从而经由各向异性导电性树脂将***部 (bump)与天线端子连接起来的状态的剖面图。
图8C是表示用于说明本发明的第4实施方式的非接触卡的制造方法的主要工序即连接IC芯片后除去硬质板的状态的剖面图。
符号说明
10、34、38:树脂基板
12:基体材料
14:天线方向图
16、30:半导体IC芯片(IC芯片)
18:硅单结晶基板
20:电路形成面
24:***部
26:虚***部(dummy bump)
28:各向异性导电性树脂
32、36:间隙限制用绝缘层
40:加强板
42:硬质板
141:天线端子
具体实施方式
下面,参照附图对本发明的实施方式进行详细说明。另外,在下面的附图中,对于相同要素附以相同符号,有时说明从略。
首先,对与树脂基板的变形有关的通信距离及其波动,说明本发明者等所发现的结果,所述树脂基板的变形是在使用将作为热塑性树脂的聚对苯二甲酸乙二醇酯(PET)树脂为基体材料的树脂基板、通过各向异性导电性树脂安装IC芯片时的变形。
图1A是表示本发明者等所使用的非接触卡的整体结构的俯视图,图1B是图1A的IC芯片的安装部的放大俯视图。另外,该非接触卡是与已经确认了是在微波段使用的2.45GHz相对应的结构。
IC芯片16使用单晶硅基板18,通过公知的半导体加工而制作。在形成***部24的面上,形成有包括模拟电路(未图示)、接地电路(未图示)等的各种电路,该面为电路形成面20。另外,模拟电路以及接地电路包括未图示但形成有***部24的区域而形成,与天线端子141重合。另外,本实验中所使用的IC芯片16具有2个***部24和1个虚***部26,外形约0.7mm□。
树脂基板10由PET树脂基体材料(厚度:约100μm)12构成,在其上形成有由铝(Al)箔(厚度:约15μm)构成的一对天线方向图14。另外,在天线方向图14的各自的一个端部上设有天线端子141。而且,与为了使安装IC芯片16时的对齐简单化,天线端子141与***部24的大小(约80μm,厚度:约15μm)相比,具有大约300μm□的非常大的形状。因此,IC芯片16的电路形成面20与天线端子141重合的区域(相对的面积)也变得较大。
图2是通过以往的安装条件以及固化条件、使用各向异性导电性树脂28安装IC芯片16时的沿着图1B的1B-1B线的剖面图。另外,各向异性导电性树脂28以树脂基体、固化剂以及导电性颗粒为主体而构成。
下面,表示以往的安装条件以及固化条件。即,作为安装条件,在常温下以60gf~100gf的加压力安装。作为固化条件,在加热温度180℃~230℃下施加300gf的加压力8秒钟进行固化。
在通过上述条件进行安装时,由PET树脂构成的基体材料12软化,伴随于此,在由Al箔构成的天线方向图14的特别是天线端子141的区域产生了凹陷。由于该凹陷,在相邻的天线端子141之间产生了***。由此,通过显微镜观察的结果是,天线端子141与IC芯片16的电路形成面20的间隙S约为1μm左右。另外,间隙S是在多个场所进行测定并求其平均值所得的结果。具有这样的间隙的非接触卡的通信距离为0.3m。
下面,将在树脂基板10使用相同的各向异性导电性树脂28、使加压力变化进行安装时的间隙的测定值与通信距离的关系表示在(表1)中。
[表1]
在这里,间隙的测定是在测定完通信距离后、用显微镜观察非接触卡的剖面而求得的。另外,通信距离的测定是使用相同的读写器通过相同条件而测定的。
其结果如表(1)所示,发现在间隙的测定值小于5μm时,通信距离变小,并且其波动变大。
另外,在表(1)中,表示了通过相同方法测定的、与已经确认了是在UHF带使用的965MHz相对应时的结果。在965MHz时,天线方向图的结构与图1所示的结构不同,但安装IC芯片的区域部的形状大致相同。如表(1)所示,发现不管是965MHz时还是2.45GHz时都一样,通过将间隙设为5μm以上,能够延长通信距离,并且能够减小其波动。
非接触卡的通信距离依存于非接触卡内的IC芯片上所形成的电路的消耗电力与将从读写器接收的电波转换成DC时的转换效率。而且,一般来说,通信距离(D)与发送功率(P)的1/2次方和天线增益的1/2次方,与频率(f)成反比。例如,在将天线增益(G)增大到4倍(6dB)时,通信距离(D)增大到2倍。
另外,在非接触卡中,一般的方法是以IC芯片的电路形成面的模拟电路、接地电路与天线端子相重合的配置进行安装。其原因是IC芯片的***部仅有2个,为了降低安装成本,不用高精度的对齐地进行高速的安装。
但是,如果在安装时,天线端子与模拟电路以及接地电路的重合(相对的面积)、其间隔有波动,则杂散电容会波动。从而,杂散电容的波动 会产生Q值的降低,所以可以推测其结果是缩短了通信距离,并且其波动变大。
即,在使用由热塑性树脂构成的基体材料时,在将IC芯片安装在树脂基板上的工序中,由于由实际传递到树脂基板上的温度、压力的波动引起的间隙的窄小化以及天线端子与接地电路等的重合状态的波动等,其杂散电容会波动。特别是,在间隙变短时,杂散电容会急剧增大,所以间隙的影响比重合状态更大。
因此,发现控制间隙非常重要。
另外,为了增大间隙,升高***部也是比较有效的方法,但会招致IC芯片的高成本化,所以不优选。因此,优选将IC芯片的***部高度抑制为最小限度。
下面,对本发明的实施方式进行具体说明。
(第1实施方式)
图3是表示本发明的第1实施方式的非接触卡的构造的沿着图1B的1B-1B线的剖面图。另外,图4A是表示从构成本实施方式的非接触卡的IC芯片30的电路形成面观察时俯视图,图4B是沿着图4A的4B-4B线的剖面图。另外,在本实施方式中,对使用了图1A和图1B所示的树脂基板的例子进行了说明。
本实施方式的非接触卡包括:至少具有存储信息的功能的IC芯片30,和由具有热塑性的基体材料12构成、形成有用于与***设备进行信号的交换的天线方向图14的树脂基板10。而且,设置在树脂基板10上的天线方向图14的一个端部上的天线端子141与IC芯片30的电极端子22通过倒装片方式而连接在一起。进而,在天线方向图14与IC芯片30的电路形成面之间设置有至少5μm的间隙S。
在这里,间隙S是IC芯片30的电路形成面20中、形成有模拟电路(未图示)以及接地电路(未图示)的面与天线端子141之间的间隙S。另外,模拟电路和接地电路也设置在与天线端子141连接的电极端子22的附近。
而且,在IC芯片30的电路形成面20中的至少形成有模拟电路和接地电路的面上,形成有具有5μm以上并比形成在IC芯片30的电极端子22的表面上的***部24的高度薄的膜厚的间隙限制用绝缘层32。
下面,进一步详细说明。
树脂基板10由PET树脂等基体材料(厚度:约100μm)12构成,在其上形成有由铝Al箔(厚度:约15μm)构成的天线方向图14。另外,在天线方向图14的各自的一个端部上设有天线端子141。
IC芯片30使用单晶硅基板18,通过公知的半导体加工而制作。在形成***部24的面上,形成有包括模拟电路(未图示)、接地电路(未图示)等的各种电路。另外,模拟电路、接地电路包括形成有***部24的区域而形成,进而也设置在与天线端子141重合的区域。
另外,在本实施方式中,在包括电路形成面20的大致整个面上形成有间隙限制用绝缘层32。间隙限制用绝缘层32可以使用例如光致抗蚀剂膜而形成。或者也可以使用液态的感光性或不感光性的聚酰胺而形成。另外,如果在形成***部24之前预先形成间隙限制用绝缘层32,可以使工序简略,所以优选,但也可以在形成***部24之后形成。另外,间隙限制用绝缘层32优选在制成一片IC芯片30之前的晶片状态形成。间隙限制用绝缘层32的膜厚,以电路形成面20的表面为基准设为5μm以上。但是,比***部24的高度薄。即,在将***部24的高度设定为15μm时,间隙限制用绝缘层32的厚度优选设定为5μm以上15μm以下的范围,例如7μm左右。
通过形成间隙限制用绝缘层32,即使如图3所示那样使用以往所使用的各向异性导电性树脂28并以与以往相同的条件进行安装,也能够将天线端子141与电路形成面20的间隙S设为5μm以上。
这样,通过预先在IC芯片30的电路形成面20上形成间隙限制用绝缘层32,在将IC芯片30安装在树脂基板10上的工序中,即使树脂基板10变形也能够将IC芯片30的电路形成面20和天线端子141之间的间隙S设为5μm以上。
其结果,即使产生与天线端子141接触的***部24的位置错位、安装条件的波动等,也能够减小通信距离的波动。因此,即使使用由便宜的热塑性树脂等基体材料12构成的树脂基板10,也能够制作成品率良好的非接触卡。
另外,作为间隙限制用绝缘层32,不仅限于上述的光致抗蚀剂、聚氨酯树脂,也可以是环氧树脂。作为该环氧树脂,可以是双酚F型环氧树脂、胺型环氧树脂、脂环族环氧树脂等。进而,也可以使用聚酯树脂、聚酰胺树脂或者丙烯树脂。另外,在使用环氧树脂族的热固化性树脂时,作为固化剂优选使用胺、咪唑、胺加成物或酸酐。作为环氧树脂的例子可以使用将例如JER制Ep828和Ep806等量混合、作为咪唑类固化剂可采用四国化成制的2P4MHZ的树脂。
另外,在本实施方式中,间隙限制用绝缘层32是远离IC芯片30的电路形成面30的外周部的划片区域而形成的,但也可以形成在晶片的整个面上,在硅晶片的划片时同时将间隙限制用绝缘层32切断。
另外,在本实施方式中,间隙限制用绝缘层32形成在IC芯片30的电路形成面30的大致整个面上,但本发明并不局限于此。如从图3可知,在间隙限制用绝缘层32仅形成在与天线端子重合的区域时,也能够得到相同的效果。
另外,对于本实施方式的非接触卡所使用的IC芯片30,必要的***部24仅为2个,但为了使安装时的IC芯片30的位置稳定,也设置有虚***部26。
另外,作为树脂基板10,除了聚对苯二甲酸乙二醇酯(PET),也可以使用丙烯腈-丁二烯-苯乙烯共聚物(ABS)、聚氯乙烯(PVC)、聚碳酸酯、聚萘二甲酸乙二醇酯(PEN)或聚对苯二甲酸乙二醇酯-1,4-环己烷二甲醇酯(PETG)。进而,作为天线方向图14,除了所述的Al箔以外,也可以使用铜(Cu)、镍(Ni)等金属箔。但是,在使用Cu箔时,优选预先在其表面上形成氧化防止覆盖膜。进而,天线方向图14不仅限于金属箔,也可以用由银(Ag)、Ag或Ag-Pd合金等导体粉末与热固化树脂等构成的导电性树脂膏,通过印刷而形成。在将导电性膏作为天线方向图14来使用时,其厚度优选设为15μm~30μm,更优选为25μm,并且表面粗糙度优选为5μm以内。
(第2实施方式)
图5是表示本发明的第2实施方式的非接触卡的构造的的剖面图。在本实施方式的非接触卡的情况下,对于IC芯片16与以往相同。另外,图6A是表示本实施方式中的树脂基板的安装IC芯片的区域的俯视图,图6B是沿着图6A的6B-6B线的剖面图。如从图6A和图6B可知,树脂基板34的基板结构与图1所示的树脂基板10相同。但是,在本实施方式的情况下,在相邻的天线端子141之间的树脂基板34的基体材料12上,形成有具有比天线端子141的厚度大5μm以上、并且比形成在IC芯片16的电极端子22的表面上的***部24的高度与天线端子141的厚度之和薄的膜厚的间隙限制用绝缘层36。
该间隙限制用绝缘层36可以使用例如光致抗蚀剂油墨通过印刷方式形成。或者也可以使用液态的感光性光致抗蚀剂材料涂布在整个面上,然后通过曝光处理等进行加工而形成。此时,间隙限制用绝缘层36也可以形成在形成IC芯片16的整个区域。另外,形成在树脂基板34的基体材料12上的间隙限制用绝缘层36优选在分割成一片树脂基板34之前的形成多个树脂基板34的薄片的状态时形成。由此,能够一次在多个树脂基板34上形成间隙限制用绝缘层36。
间隙限制用绝缘层36的膜厚设成比天线端子141的厚度大5μm以上、并且比形成在IC芯片16的电极端子22的表面上的***部24的高度与天线端子141的厚度之和薄。即,在将天线端子141的厚度设为15μm、将***部24的高度设为15μm时,间隙限制用绝缘层36的厚度如下所述那样设定。需要比天线端子141的厚度(15μm)大5μm以上,所以至少设成20μm以上。而且,设成比天线端子141的厚度(15μm)与***部24的高度(15μm)之和(30μm)薄。例如,如果设定为23μm左右,则能够可靠地进行由各向异性导电性树脂28进行的连接,并且能够将连接后的间隙确保为5μm以上。
这样,通过预先在天线端子141之间的树脂基板34的基体材料12上形成间隙限制用绝缘层36,在将IC芯片16安装在树脂基板34上的工序中,即使树脂基板34变形也能够将IC芯片30的电路形成面20和天线端子141之间的间隙可靠地设为5μm以上。其结果,即使产生与天线端子141接触的***部24的位置错位、安装条件的波动等,也能够减小通信距离的波动。因此,即使使用由便宜的热塑性树脂构成的基体材料12的树脂基板34,也能够制作成品率良好的非接触卡。
另外,作为间隙限制用绝缘层32,不仅限于上述的光致抗蚀剂、聚氨酯树脂,也可以是环氧树脂、聚氨酯树脂。作为环氧树脂,可以是双酚F型环氧树脂、胺型环氧树脂、脂环族环氧树脂等。进而,也可以使用聚酯树脂、聚酰胺树脂或者丙烯树脂。另外,在使用环氧树脂族的热固化性树脂时,作为固化剂优选使用胺、咪唑、胺加成物或酸酐。作为环氧树脂的例子可以使用将例如JER制Ep828和Ep806等量混合、作为咪唑类固化剂可采用四国化成制的2P4MHZ的树脂。
另外,在本实施方式中,将间隙限制用绝缘层36设在了相邻的天线端子141之间的树脂基板34的基体材料12上,但本发明并不局限于此。例如在包括天线端子141的天线方向图14上并且是与IC芯片重合的区域上,形成具有5μm以上、并且比形成在IC芯片16的电极端子22的表面上的***部24的高度薄的膜厚的间隙限制用绝缘层。由此,在IC芯片16的外周区域对间隙进行了限制,所以能够可靠且再现性良好地得到5μm以上的间隙。
(第3实施方式)
图7A是表示本发明的第3实施方式的非接触卡的构造的剖面图、图7B是沿着图7A的7B-7B线的剖面图。本实施方式中的非接触卡具有与将IC芯片16安装在具有与图1A和图1B所示的树脂基板10不同的结构的树脂基板38上的结构。
下面,以与图1A和图1B所示的树脂基板10不同的方面为主体进行说明。本实施方式的树脂基板38如第1实施方式所说明那样,具有下述的 结构:在制作成树脂基板10之后,再在与安装有IC芯片16的面相对的面上,设置具有比多个天线端子141的面积至少要大的形状的加强板40。在本实施方式中,加强板40为比IC芯片16的形状大、覆盖在包含相邻的天线端子141的天线方向图14上的形状,并被粘接固定在树脂基板38的基体材料12上。
作为加强板40,优选使用硬度、弯曲弹性以及耐热性比树脂基板38大的树脂材料,可以使用环氧树脂、密胺树脂、邻苯二甲酸二丙烯酯树脂等热固化性树脂。或者,也可以使用混入了玻璃纤维的树脂。在通过粘接剂将由这样的树脂构成的薄片粘接固定时,即使树脂基板38的基体材料12在安装时收到加热和加压而软化,通过加强板40的作用也能够抑制天线端子141之间的树脂基板38的***。其结果,能够设为与***部24的高度大致相同的间隙量。
另外,加强板40的厚度的最佳值因树脂基板38的基体材料12的厚度而不同。在基体材料12的厚度设为100μm以下时,优选将加强板40的厚度设为大约10μm~30μm左右。另外,加强板40也可以使用上述的树脂材料通过以印刷形成方式形成、固化的方法制作。
(第4实施方式)
图8A~图8C是用于说明本发明的第4实施方式的非接触卡的制造方法的主要工序的剖面图。图8A是表示将IC芯片16相对于粘贴了硬质板42的树脂基板10进行对齐的状态的剖面图,图8B是表示对IC芯片16进行按压从而经由各向异性导电性树脂28将***部24与天线端子141连接起来的状态的剖面图,图8C是表示连接IC芯片16后除去硬质板42的状态的剖面图。
首先,制作具有规定的形状的天线方向图的树脂基板10。作为树脂基板10的基体材料12,使用厚度50μm~100μm的PET树脂。在该基体材料12的面上形成了由Al箔构成的天线方向图14。Al箔的厚度约为15μm。在这样形成天线方向图14后,将形状比包含天线端子141的区域大的硬质板42粘接固定在基体材料12上。
接下来,如图8A所示那样,在包含天线端子141的IC芯片16的安装区域涂布各向异性导电性树脂28,将IC芯片16配置在天线端子141上。另外,在设置在IC芯片16的电路形成面20上的电极端子22上,设有由Ni和金(Au)的叠层结构构成的***部24。该***部24的高度设为大约15μm。
接下来,如图8B所示那样,在IC芯片16上施加载荷F并按压,一直加压到***部24与天线端子141经各向异性导电性树脂28而电气性地连接。此时的安装条件为将加热温度、时间以及加压力设为180℃、1秒钟、2MPa。此后的安装条件为将加热温度、时间以及加压力设为140℃、30秒钟、2MPa。另外,在该固化工序中,以通过压接头处理IC芯片16的状态进行。由于设成了这样的安装条件以及固化条件,并且在基体材料12的背面设置了硬质板42,所以在天线端子141之间的树脂基板10上基本上不会产生***,能够稳定地得到与***部24的高度大致相同的间隙量。
在使用PET树脂作为基体材料12时,优选将加压力设为0.5MPa~2.5MPa的范围内。在小于0.5MPa时,由各向异性导电性树脂28中的导电体颗粒产生的电气性的接触就会变得不充分,连接电阻容易波动。另外,在大于2.5MPa时,在天线方向图的按压部分容易产生凹陷,间隙变得比***部高度小。因此,在***部高度为接近5μm的值时,由于凹陷,有时会产生间隙变为5μm以下的情况。因此,优选将加压力设为0.5MPa~2.5MPa的范围内。更优选的是,设为1.5MPa~2.5MPa的范围内,能够更可靠地抑制连接电阻的波动。
另外,对于该加压力,在使用绝缘性粘接树脂连接时也一样。
接下来,如图8C所示那样,将IC芯片16电气性地、机械性地连接在树脂基板10上,然后除去硬质板42。作为其除去方法,例如可以将硬质板42设为透明玻璃,并使用通过照射紫外线而失去粘接性的粘接剂,这样可以容易除去。即使除去硬质板42,IC芯片16与树脂基板10的天线端子141的间隙也不会波动,能够确保为5μm以上。
根据本实施方式的制造方法,最终的形状与以往的非接触卡相同,但 能够稳定地确保间隙,所以能够使通信距离延长,并且使其波动变小。能够成品率良好地生产非接触卡。另外,在本实施方式的制造方法中,在树脂基板的基体材料上粘贴了硬质板,但在本发明的制造方法中不粘贴硬质板也能确保间隙。但是,通过粘贴硬质板,在安装工序、固化工序中,能够扩大条件的波动的允许范围,能够以较高的成品率进行制造。
另外,作为本发明的各向异性导电性树脂,可以使用将由球状的Ag粉、Cu粉或者Ag-pd合金粉构成的导电体颗粒混合在以双酚类环氧树脂和胺类固化剂为基体树脂的混合物中而成的树脂。进而,也可以使用在树脂球的表面上电镀Ni和Au的叠层膜、Ag或Cu等导电体的导电体颗粒。
另外,作为树脂基板的基体材料在本实施方式中,以PET为例进行使用,但也可以使用ABS、PVC、聚碳酸酯、PEN或者PETG等。
另外,在第1实施方式到第4实施方式中,表示了由各向异性导电性树脂将IC芯片与天线端子连接的结构,但本发明并不局限于此。在使用费导电性的、例如环氧树脂等绝缘性树脂、IC芯片的***部和天线端子机械性地接触的连接方式中,也能够得到同样的效果。
根据本发明的非接触卡及其制造方法,能够将天线端子与IC芯片的电路形成面的间隙设为5μm以上。由此,能够抑制杂散电容的影响,减小通信距离的波动,并且得到较长的通信距离,所以在利用RF标签等的非接触型信息存储介质的领域中有用。
Claims (6)
1.一种微波段用非接触型信息存储介质,其特征在于,包括:
具有存储信息、处理信号的功能的半导体IC芯片,和
形成有用于与***设备进行信号的交换的天线方向图的树脂基板;
其中,设置在所述树脂基板上的所述天线方向图的一个端部上的天线端子与所述半导体IC芯片的电极端子以相对的方式进行安装,并且在所述天线方向图与所述半导体IC芯片的电路形成面之间设置有至少5μm的间隙;
所述天线端子与所述半导体IC芯片的所述电极端子的安装结构为下述两种方式:使用各向异性导电性树脂,经由所述各向异性导电性树脂中的导电体颗粒将设置在所述电极端子上的***部与所述天线端子连接的方式;或者使用绝缘性树脂,使设置在所述电极端子上的***部与所述天线端子直接接触而连接的方式;
所述天线方向图为金属箔;
在所述半导体IC芯片的所述电路形成面中的至少形成有所述模拟电路以及所述接地电路的面上,形成有5μm以上并比形成在所述半导体IC芯片的所述电极端子的表面上的***部的高度薄的膜厚的间隙限制用绝缘层。
2.一种微波段用非接触型信息存储介质,其特征在于,包括:
具有存储信息、处理信号的功能的半导体IC芯片,和
形成有用于与***设备进行信号的交换的天线方向图的树脂基板;
其中,设置在所述树脂基板上的所述天线方向图的一个端部上的天线端子与所述半导体IC芯片的电极端子以相对的方式进行安装,并且在所述天线方向图与所述半导体IC芯片的电路形成面之间设置有至少5μm的间隙;
所述天线端子与所述半导体IC芯片的所述电极端子的安装结构为下述两种方式:使用各向异性导电性树脂,经由所述各向异性导电性树脂中的导电体颗粒将设置在所述电极端子上的***部与所述天线端子连接的方式;或者使用绝缘性树脂,使设置在所述电极端子上的***部与所述天线端子直接接触而连接的方式;
所述天线方向图为金属箔;
在所述天线端子之间的所述树脂基板上,形成有具有比所述天线端子的厚度大5μm以上、并且比形成在所述半导体IC芯片的所述电极端子的表面上的***部的高度与所述天线端子的厚度之和薄的膜厚的间隙限制用绝缘层。
3.一种微波段用非接触型信息存储介质,其特征在于,包括:
具有存储信息、处理信号的功能的半导体IC芯片,和
形成有用于与***设备进行信号的交换的天线方向图的树脂基板;
其中,设置在所述树脂基板上的所述天线方向图的一个端部上的天线端子与所述半导体IC芯片的电极端子以相对的方式进行安装,并且在所述天线方向图与所述半导体IC芯片的电路形成面之间设置有至少5μm的间隙;
所述天线端子与所述半导体IC芯片的所述电极端子的安装结构为下述两种方式:使用各向异性导电性树脂,经由所述各向异性导电性树脂中的导电体颗粒将设置在所述电极端子上的***部与所述天线端子连接的方式;或者使用绝缘性树脂,使设置在所述电极端子上的***部与所述天线端子直接接触而连接的方式;
所述天线方向图为金属箔;
在包括所述天线端子的所述天线方向图上并且是与所述半导体IC芯片重合的区域上,形成具有5μm以上、并且比形成在所述半导体IC芯片的所述电极端子的表面上的***部的高度薄的膜厚的间隙限制用绝缘层。
4.一种微波段用非接触型信息存储介质的制造方法,其特征在于,包括:
向在聚酯类的基体材料上形成了天线方向图的树脂基板的天线端子上供给绝缘性粘接树脂或者各向异性导电性树脂的树脂供给工序;
将在电极端子的表面上形成了具有至少5μm以上的厚度的***部的半导体IC芯片配置在所述树脂基板上,从而将所述***部与所述天线端子进行对齐的对齐工序;
对所述半导体IC芯片进行按压并加热,从而使所述***部与所述天线端子直接接触或经由所述各向异性导电性树脂电气性连接的安装工序;和
使所述绝缘性粘接树脂或者各向异性导电性树脂固化的固化工序;
其中,将所述安装工序以及所述固化工序中的加压力设为0.5MPa~2.5MPa的范围内;
所述半导体IC芯片在所述电路形成面中的至少形成有模拟电路以及接地电路的面上,形成有5μm以上并比形成在所述半导体IC芯片的所述电极端子的表面上的所述***部的高度薄的膜厚的间隙限制用绝缘层。
5.一种微波段用非接触型信息存储介质的制造方法,其特征在于,包括:
向在聚酯类的基体材料上形成了天线方向图的树脂基板的天线端子上供给绝缘性粘接树脂或者各向异性导电性树脂的树脂供给工序;
将在电极端子的表面上形成了具有至少5μm以上的厚度的***部的半导体IC芯片配置在所述树脂基板上,从而将所述***部与所述天线端子进行对齐的对齐工序;
对所述半导体IC芯片进行按压并加热,从而使所述***部与所述天线端子直接接触或经由所述各向异性导电性树脂电气性连接的安装工序;和
使所述绝缘性粘接树脂或者各向异性导电性树脂固化的固化工序;
其中,将所述安装工序以及所述固化工序中的加压力设为0.5MPa~2.5MPa的范围内;
所述树脂基板在所述天线端子之间的所述树脂基板上,形成有具有比所述天线端子的厚度大5μm以上、并且比形成在所述半导体IC芯片的所述电极端子的表面上的所述***部的高度薄的膜厚的间隙限制用绝缘层。
6.一种微波段用非接触型信息存储介质的制造方法,其特征在于,包括:
向在聚酯类的基体材料上形成了天线方向图的树脂基板的天线端子上供给绝缘性粘接树脂或者各向异性导电性树脂的树脂供给工序;
将在电极端子的表面上形成了具有至少5μm以上的厚度的***部的半导体IC芯片配置在所述树脂基板上,从而将所述***部与所述天线端子进行对齐的对齐工序;
对所述半导体IC芯片进行按压并加热,从而使所述***部与所述天线端子直接接触或经由所述各向异性导电性树脂电气性连接的安装工序;和
使所述绝缘性粘接树脂或者各向异性导电性树脂固化的固化工序;
其中,将所述安装工序以及所述固化工序中的加压力设为0.5MPa~2.5MPa的范围内;
所述树脂基板在包括所述天线端子的所述天线方向图上并且是与所述半导体IC芯片重合的区域上,形成具有5μm以上、并且比形成在所述半导体IC芯片的所述电极端子的表面上的所述***部的高度薄的膜厚的间隙限制用绝缘层。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP277735/2005 | 2005-09-26 | ||
JP2005277735 | 2005-09-26 | ||
PCT/JP2006/318475 WO2007034764A1 (ja) | 2005-09-26 | 2006-09-19 | 非接触型情報記憶媒体とその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101156164A CN101156164A (zh) | 2008-04-02 |
CN101156164B true CN101156164B (zh) | 2014-05-07 |
Family
ID=37888808
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN200680011593.5A Expired - Fee Related CN101156164B (zh) | 2005-09-26 | 2006-09-19 | 非接触型信息存储介质及其制造方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US8083150B2 (zh) |
EP (1) | EP1930844B1 (zh) |
JP (1) | JPWO2007034764A1 (zh) |
CN (1) | CN101156164B (zh) |
WO (1) | WO2007034764A1 (zh) |
Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2009069053A1 (en) * | 2007-11-26 | 2009-06-04 | Nxp B.V. | Methods of manufacturing an antenna or a strap for accommodating an integrated circuit, an antenna on a substrate, a strap for an integrated circuit and a transponder |
FR2937165B1 (fr) * | 2008-10-15 | 2011-04-08 | Fasver | Procede de connexion d'un microcircuit a des bornes d'une antenne imprimee sur un support |
JP2010146411A (ja) * | 2008-12-19 | 2010-07-01 | Toshiba Corp | インレットの製造方法及びこの製造方法によって製造されるインレット |
FR2949018B1 (fr) * | 2009-08-06 | 2012-04-20 | Rfideal | Connexion ohmique au moyen de zones de connexion elargies dans un objet electronique portatif |
CN102064377A (zh) * | 2010-05-28 | 2011-05-18 | 上海集成电路研发中心有限公司 | Rfid天线制作方法及其结构 |
JP5730523B2 (ja) * | 2010-09-28 | 2015-06-10 | Ntn株式会社 | チップアンテナ及びその製造方法 |
JP2014053597A (ja) * | 2012-08-09 | 2014-03-20 | Hitachi Chemical Co Ltd | チップ型電子部品及び接続構造体 |
JP5956297B2 (ja) * | 2012-09-24 | 2016-07-27 | 富士通フロンテック株式会社 | Icチップの接合方法 |
US11354558B2 (en) | 2013-01-18 | 2022-06-07 | Amatech Group Limited | Contactless smartcards with coupling frames |
USD758372S1 (en) * | 2013-03-13 | 2016-06-07 | Nagrastar Llc | Smart card interface |
US9888283B2 (en) | 2013-03-13 | 2018-02-06 | Nagrastar Llc | Systems and methods for performing transport I/O |
EP2811427A1 (fr) * | 2013-06-07 | 2014-12-10 | Gemalto SA | Procédé de fabrication d'un dispositif électronique anti-fissuration |
DE102014201164A1 (de) * | 2014-01-23 | 2015-07-23 | Robert Bosch Gmbh | Flip-Chip-Schaltungsanordnung und Verfahren zum Herstellen einer Flip-Chip-Schaltungsanordnung |
WO2016153069A1 (ja) * | 2015-03-26 | 2016-09-29 | デクセリアルズ株式会社 | 可撓性実装モジュール体の製造方法 |
USD864968S1 (en) | 2015-04-30 | 2019-10-29 | Echostar Technologies L.L.C. | Smart card interface |
KR20180055549A (ko) | 2016-11-17 | 2018-05-25 | 엘지전자 주식회사 | 반도체 발광 소자를 이용한 디스플레이 장치 및 이의 제조방법 |
CN111602294B (zh) * | 2018-01-18 | 2023-09-05 | 株式会社村田制作所 | 带天线基板、以及天线模块 |
JP2020154886A (ja) * | 2019-03-20 | 2020-09-24 | キオクシア株式会社 | 半導体装置及びアンテナラベル |
GB2584106B (en) * | 2019-05-21 | 2024-03-27 | Pragmatic Printing Ltd | Flexible electronic structure |
TWI767537B (zh) * | 2021-01-26 | 2022-06-11 | 隆達電子股份有限公司 | 發光二極體封裝結構的製造方法 |
Family Cites Families (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3643138A (en) * | 1962-01-29 | 1972-02-15 | Texas Instruments Inc | Semiconductor device |
US4889980A (en) * | 1985-07-10 | 1989-12-26 | Casio Computer Co., Ltd. | Electronic memory card and method of manufacturing same |
JPS63149191A (ja) * | 1986-12-15 | 1988-06-21 | 日立マクセル株式会社 | Icカ−ド |
JPH07117385A (ja) * | 1993-09-01 | 1995-05-09 | Toshiba Corp | 薄型icカードおよび薄型icカードの製造方法 |
US5837992A (en) * | 1994-07-15 | 1998-11-17 | Shinko Nameplate Co., Ltd. | Memory card and its manufacturing method |
JP3724606B2 (ja) * | 1995-05-22 | 2005-12-07 | 日立化成工業株式会社 | 半導体チップの接続構造及びこれに用いる配線基板 |
DE69618458T2 (de) | 1995-05-22 | 2002-11-07 | Hitachi Chemical Co., Ltd. | Halbleiterteil mit einem zu einem verdrahtungsträger elektrisch verbundenem chip |
DE19543426C1 (de) | 1995-11-21 | 1997-05-07 | Siemens Ag | Kontaktlose Chipkarte und Verfahren zur Herstellung derselben |
JP3294986B2 (ja) | 1996-03-22 | 2002-06-24 | 富士通株式会社 | 温度依存性のない光素子 |
JPH09266210A (ja) | 1996-03-28 | 1997-10-07 | Sharp Corp | 半導体装置 |
JP2000114314A (ja) * | 1998-09-29 | 2000-04-21 | Hitachi Ltd | 半導体素子実装構造体およびその製造方法並びにicカード |
JP2000295024A (ja) | 1999-04-06 | 2000-10-20 | Sony Corp | 非接触タグ |
JP2001084343A (ja) | 1999-09-16 | 2001-03-30 | Toshiba Corp | 非接触icカード及びicカード通信システム |
JP3496598B2 (ja) * | 1999-11-15 | 2004-02-16 | 松下電工株式会社 | 半導体チップの実装方法 |
JP3487428B2 (ja) * | 2000-10-31 | 2004-01-19 | 松下電器産業株式会社 | 電源回路および非接触icカード |
JP2002298106A (ja) | 2001-03-30 | 2002-10-11 | Seiko Precision Inc | 非接触icタグ |
US7498196B2 (en) * | 2001-03-30 | 2009-03-03 | Megica Corporation | Structure and manufacturing method of chip scale package |
FR2826153B1 (fr) | 2001-06-14 | 2004-05-28 | A S K | Procede de connexion d'une puce a une antenne d'un dispositif d'identification par radio-frequence du type carte a puce sans contact |
JP3490987B2 (ja) | 2001-07-19 | 2004-01-26 | 沖電気工業株式会社 | 半導体パッケージおよびその製造方法 |
JP3936217B2 (ja) | 2002-03-27 | 2007-06-27 | トッパン・フォームズ株式会社 | Rf−idメディア及びその製造方法 |
JP4380127B2 (ja) * | 2002-03-28 | 2009-12-09 | 住友化学株式会社 | 熱硬化性樹脂組成物及び接着性フィルム |
DE10229902A1 (de) | 2002-07-03 | 2004-01-15 | Giesecke & Devrient Gmbh | Verfahren zur Herstellung von elektrisch leitfähigen Verbindungen auf Chipkarten |
JP3803085B2 (ja) * | 2002-08-08 | 2006-08-02 | 株式会社日立製作所 | 無線icタグ |
JP2004185208A (ja) * | 2002-12-02 | 2004-07-02 | Sony Corp | Icカード |
JP2005071179A (ja) | 2003-08-26 | 2005-03-17 | Kobayashi Kirokushi Co Ltd | Rfidデータキャリア |
JP2005242821A (ja) * | 2004-02-27 | 2005-09-08 | Toppan Forms Co Ltd | Rf−idメディアの製造方法 |
JP2005275802A (ja) * | 2004-03-24 | 2005-10-06 | Omron Corp | 電波読み取り可能なデータキャリアの製造方法および該製造方法に用いる基板並びに電子部品モジュール |
JP2006079175A (ja) * | 2004-09-07 | 2006-03-23 | Omron Corp | 非接触icタグの製造方法とその装置、及び非接触icタグ |
-
2006
- 2006-09-19 WO PCT/JP2006/318475 patent/WO2007034764A1/ja active Application Filing
- 2006-09-19 US US11/918,054 patent/US8083150B2/en not_active Expired - Fee Related
- 2006-09-19 EP EP06798086A patent/EP1930844B1/en not_active Expired - Fee Related
- 2006-09-19 CN CN200680011593.5A patent/CN101156164B/zh not_active Expired - Fee Related
- 2006-09-19 JP JP2007536480A patent/JPWO2007034764A1/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
US20090039168A1 (en) | 2009-02-12 |
JPWO2007034764A1 (ja) | 2009-03-26 |
WO2007034764A1 (ja) | 2007-03-29 |
US8083150B2 (en) | 2011-12-27 |
EP1930844A4 (en) | 2009-03-04 |
EP1930844B1 (en) | 2011-07-13 |
EP1930844A1 (en) | 2008-06-11 |
CN101156164A (zh) | 2008-04-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN101156164B (zh) | 非接触型信息存储介质及其制造方法 | |
AU713433B2 (en) | Contactless electronic module | |
US6943437B2 (en) | Smart card or similar electronic device | |
CN100442310C (zh) | 信息载体、信息记录介质、传感器、物品管理方法 | |
TW480447B (en) | IC card | |
JP2004062854A (ja) | Icモジュール及びこれを用いた無線情報記憶媒体並びに無線情報送受信装置 | |
CN101385402A (zh) | 电路基板以及电路基板的制造方法 | |
KR20080064728A (ko) | Ic칩 실장용 접속체, 안테나 회로, ic인렛, ic태그및 정전용량 조정방법 | |
CN108695595A (zh) | 射频识别天线 | |
CN102243723B (zh) | 无线ic器件 | |
JPH0216233B2 (zh) | ||
US8409928B2 (en) | Method for making contactless portable objects | |
US6365440B1 (en) | Method for contacting a circuit chip | |
JP4626192B2 (ja) | 半導体装置 | |
JP2005070915A (ja) | 複合icカードと複合icカードの製造方法 | |
JPH11259615A (ja) | Icカード | |
CN219591642U (zh) | 整合型天线 | |
JP2002207982A (ja) | 接触非接触両用icモジュール及びicカード | |
EP3079105B1 (en) | Dual-interface ic card components and method for manufacturing the dual-interface ic card components | |
JP2024059157A (ja) | Icモジュール用シート、電磁結合式icモジュール、およびデュアルicカード | |
JP2024056008A (ja) | Rfidインレイ | |
WO2021079165A1 (en) | Rfid device having an antenna with increased weight | |
US20120193804A1 (en) | Ohmic connection using widened connection zones in a portable electronic object | |
JP3231664B2 (ja) | 薄型icカード及びその製造方法 | |
JPH11250207A (ja) | Icモジュール、その製造方法及び該モジュールを搭載した非接触型icカード |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140507 Termination date: 20160919 |