CN100437942C - 沟槽栅半导体器件及制造方法 - Google Patents

沟槽栅半导体器件及制造方法 Download PDF

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CN100437942C
CN100437942C CNB038121794A CN03812179A CN100437942C CN 100437942 C CN100437942 C CN 100437942C CN B038121794 A CNB038121794 A CN B038121794A CN 03812179 A CN03812179 A CN 03812179A CN 100437942 C CN100437942 C CN 100437942C
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groove
drain
region
field plate
trench
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S·T·皮克
P·拉特
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Koninklijke Philips NV
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Abstract

利用具有改善的可重复性工艺来制造沟槽栅半导体器件，例如MOSFET或IGBT，其具有设置在沟槽栅极(8)下方的场板(24)。所述工艺包括下述步骤：在半导体主体(20)中蚀刻第一凹槽(28a)用于接收栅极(8)，和在半导体主体(20)的顶主表面(20a)中蚀刻第二凹槽(28b)，第二凹槽(28b)从第一凹槽(28a)的底部延伸，且比第一凹槽窄。本发明能更好地控制半导体主体的顶主表面(20a)下方栅极的垂直范围。

Description

沟槽栅半导体器件及制造方法
技术领域
本发明涉及沟槽栅半导体器件，例如绝缘栅功率场效应晶体管(通常术语为“MOSFET”)，或绝缘栅双极晶体管(通常术语为“IGBT”)。
背景技术
这种沟槽栅半导体器件是公知的，其具有通过与栅极相邻的沟道调节区分开的第一导电类型的源区和漏区。US-A-5998833描述了该类型的垂直型器件，其包括位于栅极电极和沟槽底部之间的基于沟槽的源极电极。所述基于沟槽的源极电极与器件的源极电极电相连。其显示了改善器件的击穿和高频开关特性，并对器件的特定开态电阻具有最小的影响。
EP-A-1170803公开了一种与上述US-A-5998833有关的结构。“屏蔽栅极”位于栅极电极下方，接近沟槽的底部。特别地，其公开了一种其中屏蔽电极与源区相连的器件。US-A-5998833和EP-A-1170803的内容在这里结合作为参考。
发明内容
本发明的一个目的是提供一种制造在栅极下方具有沟槽电极的沟槽栅半导体器件的改进的方法。
本发明提供了一种制造沟槽栅半导体器件的方法，该器件包括半导体主体，在半导体主体中形成的具有绝缘栅极的第一沟槽部分，从第一沟槽部分底部延伸到半导体主体内部的第二沟槽部分，所述半导体主体包括通过与第一沟槽部分邻近的沟道调节区而分开的第一导电类型的源区和漏区，漏区包括漏极漂移区和漏极接触区，其中漏极漂移区在沟道调节区与漏极接触区之间，且漏极漂移区掺杂的程度比漏极接触区更小，以及在栅极与漏极接触区之间第二沟槽部分中的场板，所述方法包括下述步骤：
(a)在半导体主体中蚀刻第一凹槽；
(b)邻近第一凹槽的侧壁形成间隔物，其定义了其间的窗口；
(c)通过间隔物之间的窗口在半导体主体中蚀刻第二凹槽，第二凹槽从第一凹槽的底部向着漏极接触区延伸，且比第一凹槽窄；以及
(d)通过氧化第二凹槽的底部和侧壁形成场板绝缘层。
在上述工序中，由于存在间隔物，所以场板绝缘层的垂直范围与第一凹槽的底部自对准。这就确保了在器件制造过程中其结构中较高的均匀性。
与之相反，例如在US-A-5998833所示的工序中，围绕基于沟槽的源极电极的绝缘层的垂直范围由回蚀刻步骤的终点确定，其与结构的其它部分不是自对准的。
在一个优选的实施方案中，本发明的方法包括下述步骤：
(e)通过用电极材料填充第一和第二凹槽而在第二凹槽内的场板绝缘层之上提供场板，并将其回蚀刻直到露出场板绝缘层；
(f)移除间隔物；
(g)在场板之上和第一凹槽的底部和侧壁上形成栅绝缘层；以及
(h)在栅绝缘层上提供栅极。
因此，场板电极的回蚀刻具有明确定义的终点，即露出场板绝缘层的上表面。由此场板的上部范围可以可靠和可再现地与第一凹槽的底部对准。使用公知的光谱测定技术来检测场板绝缘层的暴露。
在上述优选的实施方案中，进一步地，场板与源区相连。
依照可选择的优选实施方案，本发明的方法包括下述步骤：
(i)移除间隔物；
(j)在第一凹槽的底部和侧壁之上形成栅绝缘层；然后
(k)用电极材料填充第一和第二凹槽以形成栅极和场板。
本发明进一步提供一种依照这里所描述的方法制造的沟槽栅半导体器件，其中第一沟槽部分的宽度比第二沟槽部分的宽度大。
在场板与栅极绝缘的实施方案中，场板可以与源区相连。可选择地，其可以连接到比栅电位更大且接近漏极漂移区的体击穿电压的偏置电位上。在本申请人共同未决的英国专利申请No.0212564.9(我们的参考为PHGB020083)中描述了具有以这种方式连接的场板的器件及其制造方法，其内容在这里结合作为参考。
本发明人已经认识到，将这种绝缘的场板连接到接近于漏极漂移区的体击穿电压的电位，使得跨越漏极漂移区的电位降更加相当均匀地分散，尤其是当施加的电压大于体击穿电压时，因此，实质上提高了器件的击穿电压。相对于没有具有同样击穿特性的场板的器件来说，其能在漏极漂移区中使用较高水平的掺杂，由此提供了具有较低特定开态电阻的器件。
本发明还提供了一种模块，其包括具有上述定义结构的器件连同一个或多个其它半导体器件，其中场板方便地与模块的内部电压线相连。可选择地，可以在所述器件(在分立器件情形中)或所述模块上提供与场板电连接的附加外部端。这就能施加专用于场板的电压电平。
附图说明
现在将通过实施例的方式并参照附图来描述发明的实施方案，其中：
图1到6是依照本发明的一个实施方案，在制造沟槽栅半导体器件的连续阶段中，半导体主体的晶体管单元区域的横截面图；
图7是图6中所示器件的沿线A-A的横截面图；
图8是体现本发明的分立器件封装的内部平面图；
图9是体现本发明的模块封装的内部平面图；以及
图10和11是依照本发明另一个实施方案，在制造沟槽栅半导体器件的连续阶段中，半导体主体的晶体管单元区域的横截面图。
应当注意到，附图是示意性的，且不按比例绘制。为了在附图中清楚和方便起见，部分这些图的相应尺寸和比例已经在尺寸上夸大或缩小了。在修改的和不同的实施方案中，相同的参考标记一般用于指代相应的或相似的特征。
具体实施方式
图6说明了依照本发明的功率半导体器件的示例性实施方案。分别是第一导电类型(该实施例中是n型)的源区和漏区2和4被相反的第二导电类型(即，在该实施例中是p型)的沟道调节区6分开。
通过实例的方式，图6示出了垂直器件结构，其中区域4a可以是由较高电阻率(较低掺杂)的外延层在衬底上形成的漏极漂移区，相对高导电率的漏极接触区4b。漏极漂移和接触区4a和4b在其间形成结4c。漏极接触区4b可以是与区域4a相同的导电类型(该实施例中是n型)，来提供垂直MOSFET，或其可以是相反的导电类型(该实施例中是p型)来提供垂直IGBT。
栅极8存在于第一沟槽部分10a内，所述第一沟槽部分延伸穿过区域2和6并进入漏极漂移区4a的下层部分。在器件开态时向栅极8施加电压信号以公知的方式用于感应出区域6中的导电沟道16，并控制在源区和漏区2和4之间的该导电沟道16内的电流。
在MOSFET情形中，在器件半导体主体20(通常为单晶硅)的顶主表面20a处，源区2通过源极电极18接触。在MOSFET情形中，在器件半导体主体20的底主表面20b处，漏极接触区4b通过称作漏极电极的电极22接触。源极和漏极电极18和22在IGBT中分别公知作为发射极和集电极。
场板24设置在栅极8与漏极漂移区4a之间的第二沟槽部分10b内。所述场板优选由第一导电类型的掺杂多晶硅形成。可选择地，其可以例如由金属制成。场板24通过场板绝缘层26b而与周围的半导体主体20绝缘。栅极8通过栅绝缘层26a而与场板24、半导体主体20及源极电极28绝缘。该层可以由例如二氧化硅构成。
在图6示出的实施方案中，第二沟槽部分10b延伸进入半导体主体20，到达接近漏极漂移区和接触区4a和4b之间的结4c的深度。如本领域中公知的，实际上，因为存在掺杂剂原子从较高掺杂的漏极接触区向漏极漂移区的主要扩散，所以在区域4a和4b之间具有掺杂过渡区域。通常，该外扩散(out-diffusion)在结4c上方延伸1到1.5微米。优选地，第二沟槽部分10b紧挨在所述过渡区域上方延伸一定深度。
场板24通过厚度为t1的绝缘材料层26b而与第二沟槽部分10b的底部和侧壁隔开。栅极8通过厚度为t2的绝缘材料层而与半导体主体和场板隔开。例如，厚度t2可以是38nm的数量级，而t1可以是0.4微米的数量级。希望相对厚的层在场板下方(即t1)，特别是对于在漏极漂移区4a中的较高水平的掺杂，以使其能够经受住在沟槽拐角处产生的高电场。
图7显示了图6的器件沿线A-A的横截面。其说明了如何从半导体主体20的外部而独立于栅极电极和源极电极，来制造到场板24的连接的实例。
掺杂多晶硅接触层39设置为朝向第一沟槽部分10a的一端，并与场板24电连接。其从场板延伸到器件半导体主体20的顶主表面20a，其中它通过场板接触电极41而接触。栅极8电连接至栅极接触电极40朝向第一沟槽部分10a的另一端。
现在将参照图1到6描述制造图6的晶体管单元的连续阶段。
最初，在半导体主体20的顶主表面20a上生长二氧化硅薄层30(图1)。在其之上提供掩模32，掩模可以用光刻和蚀刻以标准的方式形成。所述掩模例如可以由光致抗蚀剂形成，并定义窗口32a。
现在在掩模32的窗口32a处进行蚀刻处理，以形成如图2所示的第一凹槽28a。然后沉积(例如)氮化硅的均匀层，并实施各向异性蚀刻，以在邻近第一凹槽28a的侧壁处留下间隔物34(见图3)。间隔物34在它们之间依次定义了用于进一步蚀刻处理的窗口34a，以形成从第一凹槽28a的底部向下延伸进入半导体主体的第二凹槽28b。
接下来，如图4所示，进行氧化处理，以在第二凹槽28b的底部和侧壁上形成氧化层26b。优选进行热氧化。这消耗了这些表面处的硅，且所产生的层远离最初硅表面的平面延伸大约相等的距离。例如，氧化物在各个方向上生长0.2微米，以形成0.4微米厚的层。场板绝缘层26b与半导体主体20之间的边界定义了最终器件的第二沟槽部分10b，同时第一凹槽28a定义了较宽的第一沟槽部分10a。然后以公知的方式沉积掺杂的多晶硅，然后进行回蚀刻，直到所述材料仅留在由绝缘层26b的三侧上围绕的空间中，从而形成场板24。该蚀刻步骤的终点被明确定义为在该点处，随着所述多晶硅被回蚀刻与第一沟槽部分的底部齐平，而暴露出绝缘层26b。例如可以用折射式监视来监测绝缘层26b上表面的暴露。
尽管在图4实施方案中，第一沟槽部分10a比第二沟槽部分10b宽，但应当理解到，可以如此进行所述工序，使得第一和第二沟槽部分10a和10b具有大致相同的宽度。
然后例如通过喷射蚀刻工艺移除间隔物34。薄栅绝缘层26a随后沉积在第一沟槽部分10a的侧壁和底部之上，以及场板24暴露的上表面之上。接下来进行第二顺序的掺杂多晶硅的沉积和回蚀刻，以在第一沟槽部分10a中形成栅极8，如图5所示。
以公知的方式进行进一步处理，以形成注入源区2和沟道调节区6、栅极8上的绝缘帽38、以及分别在半导体主体的顶部和底部主表面20a、20b上的源极和漏极电极18、22，从而形成图6中所示的结构。
如在US-A-5998833和EP-A-1170803中所提到的，在沟槽栅器件中包含与源区连接的沟槽场板对于器件的性能是有益的。此外，本发明人发现，对所述场板施加比栅极电势更大的、并接近于漏极漂移区的体击穿电压的偏置电位会提供进一步的性能改善。特别地，漏极漂移区的体击穿电压的大约60到100％的偏置电位是优选的。更特别地，漏极漂移区的体击穿电压的大约80％的偏置电位是优选的，因为其允许漏极漂移区和接触区之间的过渡区宽度的某些变化容限，这会引起在沟槽底部周围的漏极漂移区中掺杂水平的变化。
图8显示了依照本发明的一个实施方案，封装分立器件的内部平面图。MOSFET管芯40具有与其栅极接触电极连接的栅极接合焊盘42，与其源极接触电极连接的源极接合焊盘48，以及与其场板接触电极连接的用于向其施加独立偏置电位的场板接合焊盘44。MOSFET被装配在漏极焊盘46上，其与MOSFET管芯的底部主表面上的漏极电极22电连接。接合引线50将接合焊盘42、44、48连接到各自的端子或管脚52、54和58。漏极焊盘46直接接触各自的管脚56。可以以公知的方式完成所述封装。
在本发明优选的实施方案中，如上所述的半导体器件被包含在一个模块中，其场板与模块的内部电压线或水平(level)相连。作为其的一个例子，图9显示了封装模块60的内部平面图，所述模块60包括两个具有如上所述形式的偏置电位场板的半导体器件。模块是DC-DC转换器，例如用作PC主板中的VRM。公知的DC-DC转换器电路及其操作在本申请人的US-B-6175225(我们的参考，PHB34370)中有所描述，其内容在这里结合作为参考。图9中所示的结构是US-B-6175225的图3中所示电路的修改实施方案。
图9的模块包括控制MOSFET 62，“同步”MOSFET 64和驱动器IC66。MOSFET分别对应于US-B-6175225的图3的第一和第二开关5和6。它们在DC输入VDD与地VSS之间串联连接。所述开关响应于输入到驱动器IC 66的开关信号PWMIN交替地闭合。该类型电路进一步的操作在US-B-6175225中描述。
依照本发明，每个MOSFET 62，64都包括与每个MOSFET的各自场板接触电极连接的场板接合焊盘68。同步MOSFET 64的场板接合焊盘通过驱动器I C与电源电压VCC相连，例如所述电源电压通常可以为5或12V。在US-B-6175225的图3中所示的电路中，到控制MOSFET的栅极驱动(“第一开关5”)借助升压或储存电容器37连接于升压端33与Vout之间。在该情形中，控制MOSFET62的场板接合焊盘将与升压端33连接。
在VCC为12V的例子中，选择用于MOSFET62和64的硅可以具有例如大约15V或更大的体击穿电压。
应当理解，可以在模块内提供其它电位用于连接到MOSFET的场板接合焊盘，例如借助模块的外部管脚或通过在模块内包括附加电路。
通常低掺杂漏极漂移区4a可以生长作为第一导电类型的外延层。漂移区的掺杂浓度可以贯穿其整个深度为大致均匀的。然而，优选改变跨越漂移区的浓度。特别地，提供这样一种掺杂轮廓，其具有从漏极接触区4b向沟道调节区6的方向上浓度减小(例如以线性的方式)，这可以减小器件的开电阻。
上述关于图1到6的工艺可以在本发明进一步的实施方案中进行修改。特别是，在关于上面图4所述的场板绝缘层26b的生长之后，可以移除间隔物34，并在沉积电极材料以填充第一和第二沟槽部分10a、10b之前，在第一沟槽部分10a的侧壁和底部之上沉积(或热生长)栅绝缘层26a’，如图10中所示。在半导体主体20的顶主表面20a上，所述电极材料用二氧化硅层30平坦化成平面。因此，在该实施方案中，场板24与栅极8成为整体。提供在栅极电位下的延伸进入漏极漂移区的场板可以改善器件的击穿特性。
然后，以类似于图1到6的方式，以公知的方式进行进一步处理，从而分别形成注入的源区2和沟道调节区6、栅极8之上的绝缘帽38、以及半导体主体的顶和底主表面20a、20b上的源极和漏极电极18、22，从而形成图11中所示的结构。
很显然，在本发明的范围内可以进行许多变化和修改。上述特定的实施例是n沟道器件，其中源区和漏区2和4是n型导电率的，沟道调节主体区6是p型导电率的，并且通过栅极8在区域6中感应出电子反转沟道16。通过使用相反导电类型的掺杂剂，可以制造p沟道器件。在那种情形中，区域2和4是p型的，区域6是n型的，且通过栅极8在区域6中感应出空穴反转沟道。
此外，可以依照p沟道类型的本发明制造器件，其具有p型源区和漏区2和4以及p型沟道调节区6。其也可以在每个单元内具有n型深局部化区。N型多晶硅可以用于栅极8。在工作中，在开态时通过栅极8在区域6中感应出空穴聚集沟道16。低掺杂p型区域6在关态时，通过从绝缘栅极8及从深n型区域的耗尽层而完全耗尽。
已经参照图1到7图解了垂直的分立器件，其具有在主体20的背表面20b处与区域4b接触的漏极电极22。然而，依照本发明，也可以是集成器件。在该情形中，区域4b可以是在器件衬底与外延低掺杂漏区4a之间的掺杂掩埋层。所述隐埋层区域4b可以借助从表面20a延伸到隐埋层深度的掺杂***接触区，而在前主表面20a处通过电极接触。
除硅之外的其它半导体材料也可以用于依照本发明的器件，例如碳化硅。
在附图中没有示出垂直器件的单元布局几何形状的平面图，因为本发明适用于完全不同的、公知的单元几何形状。因而，例如单元可以具有正方形几何形状，或它们可以具有密集的六边形几何形状或延长的条纹几何形状。在每个情形中，沟槽10(与其栅极8)围绕每个单元的边界延伸。图1到7仅仅示出了两个单元，但典型地是，所述器件在电极18和22之间包括数百个这些平行单元。同样地，为了图解的目的，在图6中仅仅示出了一个单元。
可以通过各种公知的***终端方案(也没有示出)围绕主体20的***来限定器件的有源单元区域。这种方案通常包括在晶体管单元制造步骤之前，在主体表面20a的***区域形成厚的场氧化层。此外，各种公知的电路(例如栅极控制电路)可以与该器件集成在有源单元区域与***终端方案之间的主体20的区域内。典型地，可以利用一些与用于晶体管单元的相同掩蔽和掺杂步骤，在该电路区域中用它们本身的布局来制造它们的电路元件。
通过阅读本说明书，其它变化和修改对于本领域熟练技术人员是很显而易见的。这种变化和修改包括等价物和本领域中已经公知的并可以代替或加上这里已经描述的特征而使用的其它特征。
尽管权利要求在该申请中已经阐述了特征的特定组合，但应当理解到，本发明的公开范围还包括这里明确或暗含公开的任何新颖性特征或任何特征的新颖性组合或其任何概括，不管其是否涉及到与任意权利要求中目前要求的相同的发明，且不管是否缓解了任意或所有的本发明所解决的相同技术问题。
由此申请人给出通告，在本申请的申请过程或源自其的任何进一步申请过程中，新的权利要求可以阐述为这些特征和/或这些特征的组合。

Claims (12)

1.一种制造沟槽栅半导体器件的方法，该器件包括半导体主体(20)，在半导体主体(20)中形成的具有绝缘栅极(8)的第一沟槽部分(10a)，从第一沟槽部分(10a)底部延伸到半导体主体(20)内部的第二沟槽部分(10b)，所述半导体主体包括通过与第一沟槽部分(10a)邻近的沟道调节区(6)而分开的第一导电类型的源区(2)和漏区(4)，漏区(4)包括漏极漂移区(4a)和漏极接触区(4b)，其中漏极漂移区(4a)在沟道调节区(6)与漏极接触区(4b)之间，且漏极漂移区掺杂的程度比漏极接触区更小，以及在栅极(8)与漏极接触区(4b)之间第二沟槽部分(10b)中的场板(24)，所述方法包括下述步骤：
(a)在半导体主体(20)中蚀刻第一凹槽(28a)；
(b)邻近第一凹槽(28a)的侧壁形成间隔物(34)，其定义了其间的窗口(34a)；
(c)通过间隔物(34)之间的窗口(34a)在半导体主体(20)中蚀刻第二凹槽(28b)，第二凹槽(28b)从第一凹槽的底部向着漏极接触区(4b)延伸，且比第一凹槽(28a)更窄；
(d)通过氧化第二凹槽(28b)的底部和侧壁形成场板绝缘层(26b)；
(e)通过用电极材料填充第一和第二凹槽(28a、28b)而在第二凹槽(28b)内的场板绝缘层(26b)之上提供场板(24)，并将其回蚀刻直到露出场板绝缘层；
(f)移除间隔物(34)；
(g)在场板(24)之上和第一凹槽(28a)的底部和侧壁处形成栅绝缘层(26a)；以及
(h)在栅绝缘层之上提供栅极(8)。
2.一种制造沟槽栅半导体器件的方法，该器件包括半导体主体(20)，在半导体主体(20)中形成的具有绝缘栅极(8)的第一沟槽部分(10a)，从第一沟槽部分(10a)底部延伸到半导体主体(20)内部的第二沟槽部分(10b)，所述半导体主体包括通过与第一沟槽部分(10a)邻近的沟道调节区(6)而分开的第一导电类型的源区(2)和漏区(4)，漏区(4)包括漏极漂移区(4a)和漏极接触区(4b)，其中漏极漂移区(4a)在沟道调节区(6)与漏极接触区(4b)之间，且漏极漂移区掺杂的程度比漏极接触区更小，以及在栅极(8)与漏极接触区(4b)之间第二沟槽部分(10b)中的场板(24)，所述方法包括下述步骤：
(a)在半导体主体(20)中蚀刻第一凹槽(28a)；
(b)邻近第一凹槽(28a)的侧壁形成间隔物(34)，其定义了其间的窗口(34a)；
(c)通过间隔物(34)之间的窗口(34a)在半导体主体(20)中蚀刻第二凹槽(28b)，第二凹槽(28b)从第一凹槽的底部向着漏极接触区(4b)延伸，且比第一凹槽(28a)更窄；
(d)通过氧化第二凹槽(28b)的底部和侧壁形成场板绝缘层(26b)；
(i)移除间隔物(34)；
(j)在第一凹槽(28a)的底部和侧壁之上形成栅绝缘层(26a)；然后
(k)用电极材料填充第一和第二凹槽(28a，28b)以形成栅极(8)和场板(24)。
3.一种根据权利要求1或2的方法制造的沟槽栅半导体器件，其中第一沟槽部分(10a)的宽度比第二沟槽部分(10b)的宽度更大。
4.一种根据权利要求1的方法制造的沟槽栅半导体器件，其中场板(24)与源区(2)相连。
5.一种根据权利要求1的方法制造的沟槽栅半导体器件，其中场板(24)连接到比栅电位大且接近于漏极漂移区(4a)的体击穿电压的偏置电位。
6.根据权利要求5的沟槽栅半导体器件，其中提供与场板(24)电连接的附加外部端(54)。
7.权利要求5或6所述的沟槽栅半导体器件，其中所述偏置电位大约是漏极漂移区(4a)的体击穿电压的60到100％。
8.权利要求5或6所述的沟槽栅半导体器件，其中所述偏置电位大约是漏极漂移区(4a)的体击穿电压的80％。
9.一种包括权利要求5所述器件的模块(60)，其中场板(24)与模块的内部电压线相连。
10.权利要求9所述的模块，其中提供与场板(24)电连接的附加外部端(54)。
11.权利要求9或10所述的模块，其中所述偏置电位大约是漏极漂移区(4a)的体击穿电压的60到100％。
12.权利要求11所述的模块，其中所述偏置电位大约是漏极漂移区(4a)的体击穿电压的80％。
CNB038121794A 2002-05-31 2003-05-21 沟槽栅半导体器件及制造方法 Expired - Fee Related CN100437942C (zh)

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