CN100429766C - 电路装置及其制造方法 - Google Patents
电路装置及其制造方法 Download PDFInfo
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- CN100429766C CN100429766C CNB2006100926725A CN200610092672A CN100429766C CN 100429766 C CN100429766 C CN 100429766C CN B2006100926725 A CNB2006100926725 A CN B2006100926725A CN 200610092672 A CN200610092672 A CN 200610092672A CN 100429766 C CN100429766 C CN 100429766C
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- Casings For Electric Apparatus (AREA)
Abstract
本发明涉及一种电路装置及其制造方法,在框体内装有电路元件的电路装置中,防止框体内部气压的上升及凝露的产生。本发明的电路装置(10)具有由底部(12A)及侧部(12B)构成的框体(12)、和覆盖侧部(12B)上面的盖部(15),在框体(12)的内部空间内装有半导体元件(13A)等电路元件。在框体(12)的底部(12A)埋入有接合区(16)及引线(11),使框体(12)的内部空间(27)和外部连通的连通部(18)设于接合区(16)上。通过设置连通部(16),抑制伴随温度变化产生内部空间(27)的气压上升及凝露。另外,在由金属构成的接合区(16)上,通过进行蚀刻等可容易地形成连通部(16)。
Description
技术领域
本发明涉及在框体内部收纳有电路元件的电路装置及其制造方法。
背景技术
参照图8对现有的电路装置100的结构进行说明。图8(A)是电路装置100的平面图,图8(B)是其剖面图(专利文献1)。
参照图8(A)及图8(B),在电路装置100的中央部形成由导电材料构成的接合区102,使多个引线101的一端接近接合区102周围。引线101的一端经由金属细线105与半导体元件104电连接,另一端从密封树脂103露出。密封树脂103具有将半导体元件104、接合区102及引线101密封并一体支承的作用。另外,在采用光学元件作为半导体元件104时,采用对光具有透明性的树脂作为密封树脂103。
另外,作为密封半导体元件等电路元件的方法也有树脂密封以外的方法。例如,也有如下密封方法,即,由金属及树脂材料形成具有内部空间的框体,并在该内部空间内装电路元件,构成电路装置(专利文献2)。
专利文献1:特开平11-340257号公报
专利文献2:特开2005-26425号公报
但是,作为上述的半导体元件104,在采用进行波长短的光的发光及光接收的元件时,存在因该光使密封树脂103发生变色等的问题。另外,由于混入有分型剂等的密封树脂103的透明度不足,故也存在半导体元件接收发射的光因密封树脂103而衰减的问题。
另外,在框体内部收纳半导体元件的类型的电路装置中,由于框体内部的空间被密封,故伴随外部的温度变化,框体内部的气压产生变化,可能给予内装的电路元件恶影响。另外,由于框体的内部空间被密封,故存在当外部气体环境的温度变化时,水分在框体内部凝露,该凝露的水分使框体内部发生电气电路短路的问题。
发明内容
本发明是鉴于上述的问题点而构成的,本发明的主要目的在于,提供电路装置及其制造方法,即使在外部气体环境的温度变化的情况下,也可以抑制内装于框体内的电路元件的特性劣化。
本发明提供电路装置,其特征在于,该电路装置具有:框体,其具有内部空间;电路元件,其收纳于所述内部空间内;接合区,其埋入所述框体底部,载置所述电路元件;引线,其埋入所述框体的底部,与所述电路元件电连接;连通部,其设于所述接合区上,使所述内部空间和外部连通,所述连通部由槽部和连通孔构成,所述槽部在所述接合区的面向所述内部空间的表面以槽状设置,连续延伸到所述电路元件的配置区域的端部,所述连通孔设于所述槽部的区域,贯通所述接合区设置。
另外,本发明提供电路装置的制造方法,其特征在于,具有:准备具有接合区及使一侧接近所述接合区的引线,且设有贯通所述接合区的连通部的引线架的工序;通过射出成形绝缘性树脂,形成由埋入所述引线及所述接合区的底部和侧部构成的框体,从所述底部的上面及下面使所述接合区及所述引线的至少一部分露出的工序;在所述接合区的上面固定电路元件,将所述引线与所述电路元件电连接的工序;在所述侧部的上面粘接盖部的工序,所述连通部由在所述接合区的面向所述内部空间的表面以槽状设置的槽部、和设于所述槽部的区域并贯通所述接合区设置的连通孔构成,所述电路元件固定在包括形成有所述连通部的区域的所述接合区的上面。
根据本发明的电路装置,由于在埋入框体的接合区等的导电部件上形成有使框体内部和外部连通的连通部,故可抑制框体内部的气压的变化及凝露,且可防止内装于框体内的电路元件的特性劣化。
另外,通过在接合区表面以槽状设置的槽部及贯通接合区的连通孔构成上述连通部,从而可延长连通部的路径。由此,可防止粉尘经由连通部从外部侵入框体内部。
另外,由于在接合区等导电部件上形成连通部,故通过进行蚀刻处理等可容易地使连通部的内壁粗化,因此,可将粉尘在粗化了的连通部的内壁捕获,且可抑制粉尘进入框体内部。
根据本发明的电路装置的制造方法,由于在利用蚀刻加工及冲切加工可容易加工的接合区等导电部件上设置连通部,故可降低形成连通部的成本。另外,在接合区等导电部件上,也可以在任意位置形成连通部。
附图说明
图1是说明本发明电路装置的图,(A)是平面图,(B)是剖面图,(C)是剖面图;
图2是说明本发明电路装置的平面图;
图3是说明本发明电路装置的剖面图;
图4是说明本发明电路装置的制造方法的图,(A)是平面图,(B)是平面图,(C)是剖面图;
图5是说明本发明电路装置的制造方法的图,(A)是平面图,(B)是剖面图;
图6是说明本发明的电路装置的制造方法的图,(A)是平面图,(B)是剖面图,(C)是剖面图;
图7是说明本发明的电路装置的制造方法的图,(A)是平面图,(B)是剖面图;
图8是说明现有的电路装置的图,(A)是平面图,(B)是剖面图。
附图标记说明
10电路装置;18A槽部;28突出部;18B连通孔;16接合区;15盖部;12框体;11引线;13A半导体元件;14金属细线;17焊盘;13B片状元件;26绝缘性树脂;27内部空间;19粘接剂;12B侧部;12A底部;18连通部;24A露出部;24B露出部;22连接电极;21导电路;20安装衬底;31引线架;33块;32单元;34B第二连接部;34A第一连接部;32单元;18B连通孔;16接合区;34A第一连接部;34B第二连接部;17焊盘;25吊线;100电路装置;101引线;105金属细线;102接合区;104半导体元件;103密封树脂;103密封树脂;104半导体元件;105金属细线;101引线;102接合区。
具体实施方式
参照图1说明本发明的电路装置10的具体结构。图1(A)是电路装置10的平面图,图1(B)是图1(A)的B-B’线的剖面图,图1(C)是图1(A)的C-C’的剖面图。
本实施方式的电路装置10中,通过由盖部15覆盖由底部12A及侧部12B构成的框体12的上面,形成内装半导体元件13A等电路元件的内部空间27。在底部12A埋入有接合区16及引线11,两者的上面及背面从底部12A局部露出。在本实施方式中,将使内部空间27和外部连通的连通部18设置在接合区16上。下面详细说明本实施方式的电路装置10。
参照图1(A)及图1(B),框体12为由绝缘性树脂26将板状底部12A和额缘形状的侧部12B一体成形的结构。在底部12A的中央部埋入有接合区16,且该接合区16埋入有多个引线11,使引线一端接近该接合区16。考虑到模制工序中的模型的脱模,侧部12B的内壁上相对底部12A构成倾斜面。
引线11埋入底部12A,一端位于接合区16的附近,另一端延伸到电路装置10的周边部。参照图1(C),引线11的上面露出到框体12的内部空间27,经由金属细线14与半导体元件13A电连接。另外,引线11的背面从底部12A露出,形成露出部24A及露出部24B。露出部24A作为电路装置10整体的外部连接电极起作用。另外,露出部24B在成形框体12的模制工序中,与模制模型抵接,抑制树脂毛刺的产生。另外,露出部24B在形成金属细线14的工序中与工作台抵接,防止给予引线11的超声波能量衰减。引线11的这种截面形状可通过半蚀刻加工形成。
参照图1(A),通过部分加宽引线11的宽度,形成焊盘17。而且,在焊盘17上固定有两个片状元件13B。
接合区16被配置于电路装置10的中央部附近,且在其上部固定半导体元件13A。接合区16的平面上的大小形成与半导体元件13A相同或比其大。参照图1(C),对接合区16进行半蚀刻加工,使其与引线11相同,接合区16的背面部分地从底部12A露出到外部。即,接合区16的背面部分地由构成底部12A的绝缘性树脂26覆盖。由此,使构成底部12A的绝缘性树脂26和接合区16的密封强度提高,防止从接合区16的底部12A脱落。另外,在接合区16上形成有使内部空间27与外部连通的连通部18。后面详细叙述连通部18。
在上述的接合区16及引线11的露出面形成由Ni/Au构成的镀敷膜,提高接合性。另外,接合区16及引线11的材料采用以铜(Cu)为主材料的金属,以铝(Al)为主材料的金属或42合金。在此,42合金是含有42%的镍、58%的铁的合金。
在本实施方式中,由半导体元件13A和片状元件13B构成的电路元件内装于框体12内。半导体元件13A经由粘接剂19固定于接合区16的上面。另外,半导体元件13A经由金属细线14与引线11电连接。片状元件13B是片状电容或片状电阻等片状电路元件,经由焊锡或导电性膏固定在焊盘17上。
半导体元件13A采用CCD或CMOS等拍摄元件、发光二极管、半导体激光等。另外,可采用波长405nm左右的高频蓝激光进行接收发射的元件作为半导体元件13A。
片状元件13B和半导体元件13A在电路装置10内部经由引线11电连接。因此,可缩短片状元件13B和半导体元件13A的距离,在片状元件13B为用于降低干扰的电容的情况下,可增大该降低噪声的效果。
用于半导体元件13A的固定的粘接剂19优选双面粘片。这是由于,当在进行接合的工序中使用粘性降低的粘接剂时,槽部18A可能被粘接剂埋没。若使用双面粘片,则在进行接合的工序中也不会液状化,因此,可排除上述的可能性。
盖部15具有从上部塞住侧部12B的开口部的作用,作为其材料,采用对半导体元件13A接收发射的光具有透明性的材料。例如,在半导体元件13A为进行波长405nm左右的高频蓝激光的接收发射的元件的情况下,采用对该蓝激光具有透明性的材料作为盖部15。作为一例,玻璃作为盖部15是适合的材料。另外,盖部15经由绝缘性粘接剂粘接在框体12上。在此,也可以省略该盖部15构成整体。作为盖部的材料的玻璃由于是非常高价的材料,故可通过省去该材料的结构降低整体的制造成本。
本实施例的要点是设有使电路装置10的内部空间27和外部连通的连通部18。通过设置连通部18,使内部空间27与外部连通,可抑制内部空间27的气压的上升及凝露的产生。
在本实施方式中,在作为导电部件的接合区16上形成有连通部18。由42合金等金属构成的接合区16由于可进行蚀刻加工及冲切加工,故可较容易地形成连通部18。特别是当通过蚀刻加工而在接合区16上设置连通部18时,可仅通过改变蚀刻掩模的形状即可在任意位置形成所希望形状的连通部18。另外,通过进行蚀刻加工等使连通部18的内壁粗化,将从外部侵入的粉尘积极地捕获在连通部18的内壁,可抑制粉尘向内部的侵入。
另一方面,也可以在构成框体12的绝缘性树脂26上设置连通部18,但在该情况下,需要准备所形成的连通部18的形状的模制模型,因而成本非常高。因此,连通部18最好在由金属构成的接合区16或引线11上形成。
参照图1(A)及图1(B),连通部18由在接合区16表面以槽状设置的槽部18A、和贯通设有该槽部18A的部分的接合区16设置的连通孔18B构成。由于槽部18A的上面由半导体元件13A覆盖,从而形成连通部18的路径。另外,槽部18A的一部分从半导体元件13A的载置区域伸出而延伸,从而连通部18构成可与内部空间27连通的状态。在图1(A)中,直线状延伸的一条槽部18A的上下端从半导体元件13A的载置区域伸出而延伸。由此,由于可加长连通部18的路径,故即使在粉尘从外部侵入连通部18的情况下,也可以将粉尘在连通部18的内壁捕获,可抑制粉尘向内壁空间27的侵入。
另外,通过将连通部18设置在载置半导体元件13A的区域的接合区16上,不必另外确保用于形成连通部18的区域,因此,不使电路装置10大型化即可形成连通部18。
另外,在本发明中,在矩形的接合区16设置向周围突出的突出部28,并使槽18A从半导体元件13A的下方延伸到突出部28。由此,不使接合区16大型化,即可使槽18A从半导体元件13A下方伸出延伸。具体地说,为使槽18A构成与内壁空间27连通的状态,形成于接合区16表面的槽部18A需要伸出半导体元件13A的载置区域形成。但是,当为形成这样的槽部18A而增大整个接合区16时,导致电路装置的大型化。因此,在本实施方式中,在接合区16的周边部设置突出部28,且使槽部18A沿该突出部28的表面延伸。由此,由于仅是设有槽部18A的突出部28向外部突出,故可抑制接合区16整体面积的增加。
图2是从背面看到的电路装置10的平面图。该图中,斜线的阴影表示露出到外部的部分的引线11,虚线表示未露出到外部的部分的引线11。
通过将引线11的表面,局部地从底部12A露出,形成露出部24A及露出部24B。
露出部24A由在电路装置10周边部露出的引线11构成。露出部24A在周边部排列设有多个,其平面上的大小例如为0.5mm×0.3mm左右,成为可附着焊锡和导电膏的大小。另外,使露出部24A相互离开,使熔接在露出部24A背面的焊锡等相互不会短路。露出部24A相互离开的具体的距离例如为0.2mm左右。
露出部24B由在接合区16附近在背面露出的引线11构成。设有露出部24B的部分的引线11的上面露出在框体内部,如图1(C)所示,经由金属细线14与半导体元件13A连接。露出部24B为防止进行引线接合时的超声波能量的衰减等而设置,但也可以在露出部24B的背面附着焊锡等,作为外部连接电极使用。
接合区16的背面,设置槽部18A及连通孔18B的部分露出到外部,其它区域由绝缘性树脂覆盖。也可以将一部分露出的接合区16的背面作为外部连接电极使用。
参照图3的剖面图说明上述的结构的电路装置10的安装结构。参照同图,通过在电路装置10背面露出的露出部24A上熔接由焊锡或导电性膏构成的连接电极22,将电路装置10固定在安装衬底20上的导电路21上。在此,使用露出部24A的润湿性限制连接电极22的形状和位置,排出焊锡跨接(ブリツジ)引起的短路的危险性。另外,利用连接电极22使电路装置10的背面和安装衬底20的表面离开。因此,连通孔18B不由安装衬底20堵塞,而使电路装置10的内部空间和外部成为连通的状态。
参照图4~图7说明上述的电路装置10的制造方法。
首先,参照图4,形成具有由引线11及接合区16构成的单元32的引线架31。图4(A)是引线架31的平面图,图4(B)是单元32的平面图,图4(C)是图4(B)的C-C’线的剖面图。
参照图4(A),通过加工一片板状的金属板,形成引线架31。在短片状的引线架31上配置分开的多个块33。在各块33上矩阵状形成多个单元32。在此,“单元”是构成一个电路装置的要素单位。
引线架31的材料采用以铜(Cu)为主材料的金属、以铝(Al)为主材料的金属、或42合金。引线架31的加工方法可采用蚀刻或冲切加工。特别是当进行蚀刻加工时,加工的成本低廉,且可通过半蚀刻加工沿厚度方向部分除去引线架31。
各单元32在块33内部通过沿横向延伸的第一连接部34A和沿纵向延伸的第二连接部34B连接。
参照图4(B)说明单元32的具体结构。单元32由配置于中央部的接合区16和一侧接近该接合区16的引线11构成。接合区16在纸面上看经由吊线25与位于上下端部的第一连接部34A连接。另外,引线11的一端在纸面上看与位于左右端部的第二连接部34B连接。引线11的另一端延伸到接合区16的附近。在之后的分离工序中,为抑制毛刺的产生,使引线11和第二连接部34B的连接部的宽度比其它区域的引线11的宽度窄。另外,通过部分加宽引线11的宽度,形成安装片状元件的焊盘17。
在本工序中,在接合区16上形成槽部18A及连通孔18B。槽部18A是通过半蚀刻加工而设于接合区16表面的槽状的区域。连通孔18B是贯通形成槽部18A的部分的接合区16设置的部位。在本实施方式中,可由形成接合区16及引线11的蚀刻加工同时形成槽部18A及连通孔18B。因此,不增加工时,而能够形成槽部18A及连通孔18B。
参照图4(C),在引线11上形成在单元32的周边部向下方以凸状突出的露出部24A。并且引线11的前端部附近也形成突出向下方的露出部24B。露出部24A的背面作为电路装置整体的外部连接端子起作用。露出部24B在制造工序中具有将引线11的前端部在厚度方向固定的功能。露出部24B的具体的功能后述。
其次,参照图5,通过射出成形绝缘性树脂26,形成由一体化了的底部12A及侧部12B构成的框体12。图5(A)是放大了单元32的平面图,图5(B)是图4(A)的B-B’线的剖面图。
在本工序中,通过使用模型的射出成形而形成绝缘性树脂26。具体地说,首先,使引线11的下面与下模型(未图示)抵接,使具有与框体12的内部空间27对应的形状的上模型(未图示)与引线11的上面抵接。在该状态下向模型(未图示)的内部注入绝缘性树脂26,形成由底部12A及侧部12B构成的框体12。根据本工序,在构成底部12A的绝缘性树脂26埋入引线11及接合区16。引线11的上面及背面部分地从底部12A露出。引线11的上面从底部12A露出向内部空间27,与预定要进行载置的半导体元件等电连接。另外,设于引线11下部的露出部24A及24B从底部12A露出外部。对于接合区16,表面的大致整个区域从底部12A露出,背面部分地从底部12A露出到外部。
在本工序中,通过在引线11的前端部附近设置露出部24B,抑制在引线11的表面附着绝缘性树脂26。具体地说,在本工序中,引线的上面与上模型接触。另外,设于引线11前端部附近的露出部24B与下模型抵接。因此,由于引线11的前端部由下模型及上模型被在厚度方向上按压,故抑制了绝缘性树脂26进入引线11和上模型之间而产生的树脂毛刺。另外,即使在产生了树脂毛刺的情况下,其量也是极少的,故可通过高压清洗而容易地除去树脂毛刺。在本工序中,进行使用热塑性树脂的注入模制或使用热硬性树脂的传递模制。
在本工序终止后,由镀敷膜覆盖接出面16及引线11的露出面。在本工序中,形成于引线架上的各单元的引线11及接合区16全部被电连接。因此,可容易地对各接合区16及引线11进行电解镀敷处理。具体地说,引线11及接合区16的露出面由镍(Ni)膜及形成于其上面的金(Au)膜覆盖,提高接合性。
其次,参照图6,在各单元32上安装半导体元件13等电路元件。图6(A)是放大了单元的图。图6(B)是图6(A)的B-B’线的剖面图。图6(C)是图6(A)的C-C’线的剖面图。
参照图6(A),半导体元件13A被固定于接合区16上。形成于半导体元件13A表面的电极和引线11经由金属细线14电连接。另外,片状元件13B经由焊料固定于焊盘17上。
参照图6(B)及图6(C),半导体元件13A经由粘接剂19固定在接合区16的上面。在此,粘接剂19优选在进行小片接合的工序中不会液化的材料。假设考虑使用在小片接合时液化的粘接剂,则液化了的粘接剂会堵塞连通孔18B。粘接剂19最好为在小片接合时即使加热也不会液化的薄膜状的双面粘片。另外,若为在小片接合时的温度状态下不会液化的粘接剂,则也可以使用双面粘片以外的粘接剂。在此,半导体元件13A可采用进行光的发射及接收的光半导体元件。
在形成金属细线14时,设于引线11前端部附近的露出部24B与操作台抵接。因此,通过使露出部24B与操作台抵接,固定引线11前端部的位置,因此,将金属细线14与引线11的上面连接时的超声波能量不会分散。由此,可提高引线11和金属细线14的连接可靠性。
其次,参照图7,通过在各单元32上粘接盖部15,堵塞框体12的开口部。图7(A)是放大了单元32的图。图7(B)是图7(A)的B-B’线的剖面图。
盖部15可采用对半导体元件13A接收发射的光具有透明性的材料(例如玻璃)。另外,若半导体元件13A不是光半导体元件,则也可以采用由遮光性材料构成的盖部15。盖部15经由粘接剂粘接在框体12的上部。
在盖部15的接合结束后,通过由点划线所示的分割线L1将各单元32分割,得到各电路装置。该分离可通过划片或使用激光的分离方法进行。另外,由划片等分割的部分的引线11因半蚀刻加工而厚度变薄,所以,分割时的毛刺的产生被抑制。
Claims (10)
1、一种电路装置,其特征在于,具有:框体,其具有内部空间;电路元件,其收纳于所述内部空间内;接合区,其被埋入所述框体底部,载置所述电路元件;引线,其被埋入所述框体底部,与所述电路元件电连接;连通部,其设于所述接合区上,使所述内部空间和外部连通,
所述连通部由槽部和连通孔构成,所述槽部在所述接合区的面向所述内部空间的表面以槽状设置,连续延伸到所述电路元件的配置区域的端部,所述连通孔设于所述槽部的区域,贯通所述接合区设置。
2、如权利要求1所述的电路装置,其特征在于,在所述接合区的周边部设置向外侧突出的突出部,所述槽部从所述电路装置的下方延伸到所述突出部。
3、如权利要求1所述的电路装置,其特征在于,所述连通部通过蚀刻所述接合区而被设置。
4、如权利要求1所述的电路装置,其特征在于,所述电路元件是半导体元件,所述半导体元件面朝上载置于所述接合区上,所述半导体元件和所述引线经由金属细线电连接。
5、如权利要求1所述的电路装置,其特征在于,所述接合区的下部通过半蚀刻而部分除去,半蚀刻处理后的区域的所述接合区的下面由构成所述框体的绝缘性树脂覆盖。
6、如权利要求1所述的电路装置,其特征在于,所述电路元件采用相互电连接的半导体元件及片状电容。
7、如权利要求1所述的电路装置,其特征在于,所述电路元件是进行光的接收或发射的半导体元件,所述框体由通过一体成形而形成的底部及侧部、和载置于所述侧部的上面而使所述光透过的盖部构成。
8、一种电路装置的制造方法,其特征在于,具有:准备具有接合区及使一侧接近所述接合区的引线,且设有贯通所述接合区的连通部的引线架的工序;通过射出成形绝缘性树脂,形成由埋入所述引线及所述接合区的底部和侧部构成的框体,从所述底部的上面及下面使所述接合区及所述引线的至少一部分露出的工序;在所述接合区的上面固定电路元件,将所述引线与所述电路元件电连接的工序;在所述侧部的上面粘接盖部的工序,
所述连通部由在所述接合区的面向所述内部空间的表面以槽状设置的槽部、和设于所述槽部的区域并贯通所述接合区设置的连通孔构成,所述电路元件固定在包括形成有所述连通部的区域的所述接合区的上面。
9、如权利要求8所述的电路装置的制造方法,其特征在于,所述连通部由蚀刻加工或冲切加工形成。
10、如权利要求8所述的电路装置的制造方法,其特征在于,通过加工一片金属板,同时形成所述连通部、所述接合区及所述引线。
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JP4380748B2 (ja) | 2007-08-08 | 2009-12-09 | ヤマハ株式会社 | 半導体装置、及び、マイクロフォンパッケージ |
JP5110575B2 (ja) * | 2007-08-24 | 2012-12-26 | エムテックスマツムラ株式会社 | 中空パッケージ及び半導体装置 |
US7915717B2 (en) * | 2008-08-18 | 2011-03-29 | Eastman Kodak Company | Plastic image sensor packaging for image sensors |
TWI463868B (zh) * | 2008-10-09 | 2014-12-01 | Asia Optical Co Inc | Scalable image sensing module |
TWI395314B (zh) * | 2009-10-16 | 2013-05-01 | Neobulb Technologies Inc | 晶片導線架及光電能量轉換模組 |
JP5732286B2 (ja) * | 2011-03-16 | 2015-06-10 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
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