ATE232663T1 - Phasenregelkreis und verfahren zum automatischen einrasten auf einer veränderlichen eingangsfrequenz - Google Patents
Phasenregelkreis und verfahren zum automatischen einrasten auf einer veränderlichen eingangsfrequenzInfo
- Publication number
- ATE232663T1 ATE232663T1 AT98953611T AT98953611T ATE232663T1 AT E232663 T1 ATE232663 T1 AT E232663T1 AT 98953611 T AT98953611 T AT 98953611T AT 98953611 T AT98953611 T AT 98953611T AT E232663 T1 ATE232663 T1 AT E232663T1
- Authority
- AT
- Austria
- Prior art keywords
- division factor
- pll
- frequency
- input signal
- frequency division
- Prior art date
Links
- 238000010586 diagram Methods 0.000 abstract 2
- 230000001419 dependent effect Effects 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Networks Using Active Elements (AREA)
- Transmitters (AREA)
- Channel Selection Circuits, Automatic Tuning Circuits (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/951,650 US6049254A (en) | 1997-10-16 | 1997-10-16 | Phase-locked loop which can automatically adjust to and lock upon a variable input frequency |
PCT/US1998/021889 WO1999019987A1 (en) | 1997-10-16 | 1998-10-16 | Phase-locked loop and method for automatically locking to a variable input frequency |
Publications (1)
Publication Number | Publication Date |
---|---|
ATE232663T1 true ATE232663T1 (de) | 2003-02-15 |
Family
ID=25491969
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT98953611T ATE232663T1 (de) | 1997-10-16 | 1998-10-16 | Phasenregelkreis und verfahren zum automatischen einrasten auf einer veränderlichen eingangsfrequenz |
Country Status (7)
Country | Link |
---|---|
US (1) | US6049254A (de) |
EP (1) | EP1023776B1 (de) |
JP (1) | JP2001520471A (de) |
AT (1) | ATE232663T1 (de) |
AU (1) | AU1094199A (de) |
DE (1) | DE69811384T2 (de) |
WO (1) | WO1999019987A1 (de) |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100360995B1 (ko) * | 2000-03-03 | 2002-11-23 | 닛본 덴기 가부시끼가이샤 | 위상 동기 루프 회로 및 위상 동기 루프 회로에서의주파수 변조 방법 |
US6664775B1 (en) * | 2000-08-21 | 2003-12-16 | Intel Corporation | Apparatus having adjustable operational modes and method therefore |
JP4546716B2 (ja) * | 2003-11-10 | 2010-09-15 | シャープ株式会社 | Pllクロック信号生成回路 |
KR100652390B1 (ko) * | 2004-12-11 | 2006-12-01 | 삼성전자주식회사 | 데드락 방지회로를 구비하는 위상동기 루프 회로 및 이의데드락 방지방법 |
US7158443B2 (en) * | 2005-06-01 | 2007-01-02 | Micron Technology, Inc. | Delay-lock loop and method adapting itself to operate over a wide frequency range |
JP2007129306A (ja) | 2005-11-01 | 2007-05-24 | Nec Corp | Pll制御回路 |
KR100849222B1 (ko) * | 2006-04-10 | 2008-07-31 | 삼성전자주식회사 | 직렬 전송 방식에 사용되는 전송주파수 제어 방법, 이를기록한 기록매체 및 장치 |
US7602253B2 (en) * | 2006-12-11 | 2009-10-13 | Silicon Image, Inc. | Adaptive bandwidth phase locked loop with feedforward divider |
US8831140B2 (en) * | 2007-03-16 | 2014-09-09 | Altera Corporation | Protocol-agnostic automatic rate negotiation for high-speed serial interface in a programmable logic device |
CN101572543A (zh) * | 2008-05-04 | 2009-11-04 | 华为技术有限公司 | 一种稳定时钟的方法和装置 |
JP2010062707A (ja) | 2008-09-02 | 2010-03-18 | Nec Electronics Corp | 位相同期ループ回路 |
JP2010135956A (ja) * | 2008-12-03 | 2010-06-17 | Renesas Electronics Corp | Pll回路およびその制御方法 |
US8477831B2 (en) | 2010-02-17 | 2013-07-02 | Altera Corporation | Multi-protocol multiple-data-rate auto-speed negotiation architecture for a device |
CN102098044A (zh) * | 2010-12-10 | 2011-06-15 | 青岛海信信芯科技有限公司 | 一种像素锁相时钟频率发生方法及装置 |
US8188766B1 (en) | 2011-02-10 | 2012-05-29 | Avago Technologies Enterprise IP (Singapore) Pte. Ltd. | Self-contained systems including scalable and programmable divider architectures and methods for generating a frequency adjustable clock signal |
US8598925B1 (en) | 2012-07-16 | 2013-12-03 | Nanowave Technologies Inc. | Frequency determination circuit and method |
DE102018121971A1 (de) | 2018-09-10 | 2020-03-12 | Gustav Klauke Gmbh | Presswerkzeug |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5354456A (en) * | 1976-10-27 | 1978-05-17 | Mitsubishi Electric Corp | Phase synchronizing oscillator |
US4516083A (en) * | 1982-05-14 | 1985-05-07 | Motorola, Inc. | Fast lock PLL having out of lock detector control of loop filter and divider |
DE3803965C2 (de) * | 1988-02-10 | 1993-11-25 | Bosch Gmbh Robert | Schaltungsanordnung mit einem spannungsgesteuerten Oszillator |
US5281926A (en) * | 1992-10-06 | 1994-01-25 | Zenith Electronics Corp. | Phase locked loop made operative when stable input sync signal is detected |
US5371480A (en) * | 1992-12-04 | 1994-12-06 | Telefonaktiebolaget L M Ericsson | Step controlled signal generator |
US5334952A (en) * | 1993-03-29 | 1994-08-02 | Spectralink Corporation | Fast settling phase locked loop |
US5737694A (en) * | 1995-11-30 | 1998-04-07 | Scientific-Atlanta, Inc. | Highly stable frequency synthesizer loop with feedforward |
-
1997
- 1997-10-16 US US08/951,650 patent/US6049254A/en not_active Expired - Lifetime
-
1998
- 1998-10-16 AT AT98953611T patent/ATE232663T1/de not_active IP Right Cessation
- 1998-10-16 AU AU10941/99A patent/AU1094199A/en not_active Abandoned
- 1998-10-16 WO PCT/US1998/021889 patent/WO1999019987A1/en active IP Right Grant
- 1998-10-16 DE DE69811384T patent/DE69811384T2/de not_active Expired - Lifetime
- 1998-10-16 EP EP98953611A patent/EP1023776B1/de not_active Expired - Lifetime
- 1998-10-16 JP JP2000516436A patent/JP2001520471A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
EP1023776A1 (de) | 2000-08-02 |
AU1094199A (en) | 1999-05-03 |
DE69811384D1 (de) | 2003-03-20 |
DE69811384T2 (de) | 2003-12-11 |
EP1023776B1 (de) | 2003-02-12 |
WO1999019987A1 (en) | 1999-04-22 |
JP2001520471A (ja) | 2001-10-30 |
US6049254A (en) | 2000-04-11 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
UEP | Publication of translation of european patent specification |
Ref document number: 1023776 Country of ref document: EP |
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REN | Ceased due to non-payment of the annual fee |