JPS5354456A - Phase synchronizing oscillator - Google Patents

Phase synchronizing oscillator

Info

Publication number
JPS5354456A
JPS5354456A JP12991976A JP12991976A JPS5354456A JP S5354456 A JPS5354456 A JP S5354456A JP 12991976 A JP12991976 A JP 12991976A JP 12991976 A JP12991976 A JP 12991976A JP S5354456 A JPS5354456 A JP S5354456A
Authority
JP
Japan
Prior art keywords
phase synchronizing
synchronizing oscillator
oscillator
accelerated
quick
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12991976A
Other languages
Japanese (ja)
Inventor
Toshio Tachika
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP12991976A priority Critical patent/JPS5354456A/en
Publication of JPS5354456A publication Critical patent/JPS5354456A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

PURPOSE:To achieve a quick synchronism even with a narrow band width, by controlling the frequency division so that the change in te output signal is accelerated.
JP12991976A 1976-10-27 1976-10-27 Phase synchronizing oscillator Pending JPS5354456A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12991976A JPS5354456A (en) 1976-10-27 1976-10-27 Phase synchronizing oscillator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12991976A JPS5354456A (en) 1976-10-27 1976-10-27 Phase synchronizing oscillator

Publications (1)

Publication Number Publication Date
JPS5354456A true JPS5354456A (en) 1978-05-17

Family

ID=15021634

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12991976A Pending JPS5354456A (en) 1976-10-27 1976-10-27 Phase synchronizing oscillator

Country Status (1)

Country Link
JP (1) JPS5354456A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62126712A (en) * 1985-11-27 1987-06-09 Hitachi Ltd Pll circuit
JPH05145413A (en) * 1991-11-20 1993-06-11 Nippon Denki Musen Denshi Kk Phase locked loop circuit
WO1999019987A1 (en) * 1997-10-16 1999-04-22 Oasis Design, Inc. Phase-locked loop and method for automatically locking to a variable input frequency
JP2005143030A (en) * 2003-11-10 2005-06-02 Sharp Corp Pll clock signal generation circuit

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5080066A (en) * 1973-11-12 1975-06-28
JPS51317A (en) * 1974-06-20 1976-01-06 Nippon Telegraph & Telephone
JPS5115391A (en) * 1974-07-29 1976-02-06 Tokyo Shibaura Electric Co

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5080066A (en) * 1973-11-12 1975-06-28
JPS51317A (en) * 1974-06-20 1976-01-06 Nippon Telegraph & Telephone
JPS5115391A (en) * 1974-07-29 1976-02-06 Tokyo Shibaura Electric Co

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62126712A (en) * 1985-11-27 1987-06-09 Hitachi Ltd Pll circuit
JPH05145413A (en) * 1991-11-20 1993-06-11 Nippon Denki Musen Denshi Kk Phase locked loop circuit
WO1999019987A1 (en) * 1997-10-16 1999-04-22 Oasis Design, Inc. Phase-locked loop and method for automatically locking to a variable input frequency
JP2005143030A (en) * 2003-11-10 2005-06-02 Sharp Corp Pll clock signal generation circuit
JP4546716B2 (en) * 2003-11-10 2010-09-15 シャープ株式会社 PLL clock signal generation circuit

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