KR910017776A - 위상동기회로 - Google Patents
위상동기회로 Download PDFInfo
- Publication number
- KR910017776A KR910017776A KR1019910003797A KR910003797A KR910017776A KR 910017776 A KR910017776 A KR 910017776A KR 1019910003797 A KR1019910003797 A KR 1019910003797A KR 910003797 A KR910003797 A KR 910003797A KR 910017776 A KR910017776 A KR 910017776A
- Authority
- KR
- South Korea
- Prior art keywords
- phase
- controlled oscillators
- voltage
- frequency
- voltage controlled
- Prior art date
Links
- 238000001514 detection method Methods 0.000 claims 2
- 230000010355 oscillation Effects 0.000 claims 2
- 230000001360 synchronised effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/03—Astable circuits
- H03K3/0315—Ring oscillators
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
- H03L7/187—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using means for coarse tuning the voltage controlled oscillator of the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/354—Astable circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
- H03L7/0997—Controlling the number of delay elements connected in series in the ring oscillator
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/095—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Dram (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 제1실시예의 블럭구성도, 제4도는 제3도에 나타낸 단수선택기의 동작을 나타낸 타이밍챠트, 제5도는 본 발명의 제2실시예의 블럭 구성도.
Claims (2)
- 적어도 위상비교기(1)와 상기 위상비교기(1)에 접속되는 전압 제어 발진기(4a,4b)를 구비하고, 상기 전압 제어 발진기(4a,4b)의 발진출력의 주파수 및 위상과 외부로부터 입력되는 기준신호의 주파수 및 위상을 상기 위상비교기(1)에 있어서 비교하며, 그 비교결과를 상기 전압 제어 발진기(4a,4b)로 피드백시켜 상기 전압 제어 발진기(4a,4b)의 발진출력의 위상과 주파수를 상기 기준신호와 일치시키는 위상동기회로에 있어서, 상기 전압 제어 발진기(4a,4b)가 링오실레이터(39a,39b)를 포함하고 있고, 그 링오실레이터의 단수의 선택을 상기 전압 제어 발진기(4a,4b)로 입력되는 제어전압에 기초해서 행하도록 된 것을 특징으로 하는 위상동기회로.
- 제1항에 있어서 , 위상동기의 검출후에 상기 링오실레이터의 단수선택 상태를 고정시키는 동기검출회로(18)를 더 구비한 것을 특징으로 하는 위상동기회로.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP02-056432 | 1990-03-09 | ||
JP2-56,432 | 1990-03-09 | ||
JP2056432A JPH0799807B2 (ja) | 1990-03-09 | 1990-03-09 | 位相同期回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR910017776A true KR910017776A (ko) | 1991-11-05 |
KR940001724B1 KR940001724B1 (ko) | 1994-03-05 |
Family
ID=13026931
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019910003797A KR940001724B1 (ko) | 1990-03-09 | 1991-03-09 | 위상동기회로 |
Country Status (3)
Country | Link |
---|---|
US (1) | US5075640A (ko) |
JP (1) | JPH0799807B2 (ko) |
KR (1) | KR940001724B1 (ko) |
Families Citing this family (56)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5315271A (en) * | 1990-12-10 | 1994-05-24 | Aerospatiale Societe Nationale Industrielle | Process and device for synchronizing two digital pulse sequences S and RF of the same high frequency |
JPH05175834A (ja) * | 1991-12-25 | 1993-07-13 | Mitsubishi Electric Corp | 位相同期ループ回路 |
FR2689342A1 (fr) * | 1992-03-31 | 1993-10-01 | Sgs Thomson Microelectronics | Boucle à verrouillage de fréquence. |
US5313503A (en) * | 1992-06-25 | 1994-05-17 | International Business Machines Corporation | Programmable high speed digital phase locked loop |
JP2769660B2 (ja) * | 1992-09-21 | 1998-06-25 | 三菱電機株式会社 | Pll回路 |
JPH06152334A (ja) * | 1992-11-06 | 1994-05-31 | Mitsubishi Electric Corp | リングオシレータおよび定電圧発生回路 |
US5382921A (en) * | 1992-11-23 | 1995-01-17 | National Semiconductor Corporation | Automatic selection of an operating frequency in a low-gain broadband phase lock loop system |
US5349311A (en) * | 1992-11-23 | 1994-09-20 | National Semiconductor Corporation | Current starved inverter voltage controlled oscillator |
US5552733A (en) * | 1993-01-19 | 1996-09-03 | Credence Systems Corporation | Precise and agile timing signal generator based on a retriggered oscillator |
US5345186A (en) * | 1993-01-19 | 1994-09-06 | Credence Systems Corporation | Retriggered oscillator for jitter-free phase locked loop frequency synthesis |
EP1120912A1 (en) * | 1993-02-05 | 2001-08-01 | Sun Microsystems, Inc. | Method and apparatus for timing control |
US5375148A (en) * | 1993-03-01 | 1994-12-20 | Motorola, Inc. | VCO bias generator in a phase lock loop |
FR2703534A1 (fr) * | 1993-03-31 | 1994-10-07 | Cit Alcatel | Dispositif de contrôle numérique d'un oscillateur numérique variable. |
JPH06343022A (ja) * | 1993-06-01 | 1994-12-13 | Fujitsu Ltd | 電圧制御発振回路 |
DE4342266C2 (de) * | 1993-12-10 | 1996-10-24 | Texas Instruments Deutschland | Taktgenerator sowie Phasenkomparator zur Verwendung in einem solchen Taktgenerator |
JP2710214B2 (ja) * | 1994-08-12 | 1998-02-10 | 日本電気株式会社 | フェーズロックドループ回路 |
JP2697626B2 (ja) * | 1994-09-07 | 1998-01-14 | 日本電気株式会社 | 位相同期回路のロック検出器 |
JP3523718B2 (ja) | 1995-02-06 | 2004-04-26 | 株式会社ルネサステクノロジ | 半導体装置 |
DE19654935C2 (de) * | 1995-02-06 | 2002-06-13 | Mitsubishi Electric Corp | Halbleitereinrichtung |
JP3350349B2 (ja) * | 1995-09-26 | 2002-11-25 | 株式会社日立製作所 | ディジタル情報信号再生回路及びディジタル情報装置 |
US5638028A (en) * | 1995-10-12 | 1997-06-10 | Microsoft Corporation | Circuit for generating a low power CPU clock signal |
US5767713A (en) * | 1995-12-08 | 1998-06-16 | Cypress Semiconductor, Inc. | Phase locked loop having integration gain reduction |
JP3564855B2 (ja) * | 1996-02-29 | 2004-09-15 | ソニー株式会社 | リングオシレータ及びpll回路 |
JP2914287B2 (ja) * | 1996-03-08 | 1999-06-28 | 日本電気株式会社 | Pll回路 |
US5757240A (en) * | 1996-07-01 | 1998-05-26 | International Business Machines Corporation | Low gain voltage-controlled oscillator |
US5945883A (en) * | 1996-07-15 | 1999-08-31 | Mitsubishi Denki Kabushiki Kaisha | Voltage controlled ring oscillator stabilized against supply voltage fluctuations |
US5764110A (en) * | 1996-07-15 | 1998-06-09 | Mitsubishi Denki Kabushiki Kaisha | Voltage controlled ring oscillator stabilized against supply voltage fluctuations |
US5838204A (en) * | 1996-09-11 | 1998-11-17 | Oki America, Inc. | Phase locked loop with multiple, programmable, operating frequencies, and an efficient phase locked loop layout method |
US5892406A (en) * | 1996-10-23 | 1999-04-06 | Quality Semiconductor, Inc. | Mixed signal phase locked loop with process and temperature calibration |
US5920216A (en) * | 1997-04-03 | 1999-07-06 | Advanced Micro Devices, Inc. | Method and system for generating digital clock signals of programmable frequency employing programmable delay lines |
US6072348A (en) * | 1997-07-09 | 2000-06-06 | Xilinx, Inc. | Programmable power reduction in a clock-distribution circuit |
FR2769433B1 (fr) * | 1997-10-03 | 2000-01-28 | Sextant Avionique | Oscillateur a boucle de verrouillage de phase |
IT1295950B1 (it) * | 1997-11-06 | 1999-05-28 | Cselt Centro Studi Lab Telecom | Circuito ad aggancio di fase. |
US6292522B1 (en) * | 1997-11-13 | 2001-09-18 | Lsi Logic Corporation | Frequency decoder databank for phase-locked loop |
JP4018221B2 (ja) * | 1998-02-06 | 2007-12-05 | 富士通株式会社 | チャージポンプ回路、pll回路、及び、pll周波数シンセサイザ |
US6061418A (en) * | 1998-06-22 | 2000-05-09 | Xilinx, Inc. | Variable clock divider with selectable duty cycle |
EP0977361B1 (en) * | 1998-07-13 | 2001-10-24 | Agilent Technologies, Inc. (a Delaware corporation) | Frequency-providing circuit |
KR100295052B1 (ko) * | 1998-09-02 | 2001-07-12 | 윤종용 | 전압제어지연라인의단위지연기들의수를가변시킬수있는제어부를구비하는지연동기루프및이에대한제어방법 |
IT1303599B1 (it) | 1998-12-11 | 2000-11-14 | Cselt Ct Studi E Lab T | Circuito ad aggancio di fase. |
JP2001094419A (ja) | 1999-09-24 | 2001-04-06 | Toshiba Information Systems (Japan) Corp | Pll回路 |
DE19946764C2 (de) | 1999-09-29 | 2003-09-04 | Siemens Ag | Digitaler Phasenregelkreis |
US6404290B1 (en) * | 2000-11-10 | 2002-06-11 | Marvell International, Ltd. | Fast change charge pump having switchable boost function |
GB2379104A (en) * | 2001-08-21 | 2003-02-26 | Zarlink Semiconductor Ltd | Voltage controlled oscillators |
JP2003152507A (ja) | 2001-11-15 | 2003-05-23 | Mitsubishi Electric Corp | 電圧制御型発振回路 |
JP4158465B2 (ja) * | 2002-09-10 | 2008-10-01 | 日本電気株式会社 | クロック再生装置、および、クロック再生装置を用いた電子機器 |
DE60327900D1 (de) * | 2002-12-24 | 2009-07-16 | Fujitsu Microelectronics Ltd | Taktgenerator mit spektraler Dispersion |
US6901339B2 (en) * | 2003-07-29 | 2005-05-31 | Agilent Technologies, Inc. | Eye diagram analyzer correctly samples low dv/dt voltages |
US7263152B2 (en) * | 2003-11-18 | 2007-08-28 | Analog Devices, Inc. | Phase-locked loop structures with enhanced signal stability |
JP4651298B2 (ja) * | 2004-04-08 | 2011-03-16 | 三菱電機株式会社 | 周波数自動補正pll回路 |
KR20060072459A (ko) * | 2004-12-23 | 2006-06-28 | 삼성전자주식회사 | 주파수에 따라 부하 캐패시터가 가변되는 위상 고정 루프장치 |
US7355905B2 (en) | 2005-07-01 | 2008-04-08 | P.A. Semi, Inc. | Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage |
US7782143B2 (en) * | 2007-03-08 | 2010-08-24 | Integrated Device Technology, Inc. | Phase locked loop and delay locked loop with chopper stabilized phase offset |
US8094769B2 (en) * | 2008-07-25 | 2012-01-10 | Freescale Semiconductor, Inc. | Phase-locked loop system with a phase-error spreading circuit |
JP2012034212A (ja) * | 2010-07-30 | 2012-02-16 | Fujitsu Semiconductor Ltd | 位相ロックループ回路 |
KR20150037054A (ko) * | 2013-09-30 | 2015-04-08 | 에스케이하이닉스 주식회사 | 내부 전압 생성 회로 |
CN114665879B (zh) * | 2022-04-14 | 2024-06-07 | 南京邮电大学 | 一种电流-频率转换电路及其工作方法 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5843632A (ja) * | 1981-09-01 | 1983-03-14 | テクトロニツクス・インコ−ポレイテツド | 位相固定回路 |
JPH0260315A (ja) * | 1988-08-26 | 1990-02-28 | Hitachi Ltd | 電圧制御発振器回路 |
US4988960A (en) * | 1988-12-21 | 1991-01-29 | Yamaha Corporation | FM demodulation device and FM modulation device employing a CMOS signal delay device |
-
1990
- 1990-03-09 JP JP2056432A patent/JPH0799807B2/ja not_active Expired - Fee Related
-
1991
- 1991-03-06 US US07/665,248 patent/US5075640A/en not_active Expired - Lifetime
- 1991-03-09 KR KR1019910003797A patent/KR940001724B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
JPH03259619A (ja) | 1991-11-19 |
US5075640A (en) | 1991-12-24 |
JPH0799807B2 (ja) | 1995-10-25 |
KR940001724B1 (ko) | 1994-03-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR910017776A (ko) | 위상동기회로 | |
KR930005352A (ko) | 반도체 집적회로 | |
KR920704411A (ko) | 전압 제어형 발진 회로 및 위상 동기 회로 | |
KR910007267A (ko) | 시간축 발생기 회로와 동일 주파수의 2기준 신호 발생 방법 | |
KR970019094A (ko) | 수평발진회로(a horizontal oscillator) | |
KR950022154A (ko) | 클록 신호 발생 회로 | |
KR910002118A (ko) | 디글리처(deglicher)를 지닌 높은 해상도용 표본 클록 발생기 | |
KR900017372A (ko) | 수평 위상 동기회로 및 수평 위상 동기방법 | |
KR890009098A (ko) | 전압제어발진회로 | |
KR890001296A (ko) | 입력 클럭과 회로의 출력 펄스를 동기시키기 위한 장지 | |
KR960028380A (ko) | 위상동기루프회로의 클럭지연보상 및 듀티제어 장치 | |
KR890001351A (ko) | 텔레비젼 편향 장치 | |
KR940020699A (ko) | 디지탈 위상동기루프회로(digital phase-locked loop circuit) | |
KR830004009A (ko) | 오프셋트전압을 제거한 스위치된 텔레비젼 수평발진기 주파수제어루프 | |
KR920020856A (ko) | 동기 클록 발생 회로 | |
SE9700272D0 (sv) | Automatic frequency control oscillation circuit | |
KR890017885A (ko) | 샘플링 비 유도 장치 | |
KR890006059A (ko) | 텔레비젼 수상기 | |
KR970055559A (ko) | Pll 회로와 pll 회로용 노이즈 감소 방법 | |
KR910009071A (ko) | Aft 기능을 구비한 주파수 신세사이저형 텔레비젼 신호 수신 장치 및 그 제어 방법 | |
KR920015744A (ko) | 전압조절 발진기(vco)를 위한 o-위상 리스타트 보상회로 및 그 방법 | |
KR950007297A (ko) | 위상 동기 루프 및 동작 방법 | |
KR890007564A (ko) | 라인 동기화 회로 | |
KR920702577A (ko) | 위상 동기 회로 | |
KR850002364A (ko) | 주파수 제어장치 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
G160 | Decision to publish patent application | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20030228 Year of fee payment: 10 |
|
LAPS | Lapse due to unpaid annual fee |