WO2024119608A1 - 显示面板 - Google Patents

显示面板 Download PDF

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Publication number
WO2024119608A1
WO2024119608A1 PCT/CN2023/074954 CN2023074954W WO2024119608A1 WO 2024119608 A1 WO2024119608 A1 WO 2024119608A1 CN 2023074954 W CN2023074954 W CN 2023074954W WO 2024119608 A1 WO2024119608 A1 WO 2024119608A1
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WO
WIPO (PCT)
Prior art keywords
scan
pull
reverse
switch tube
scanning
Prior art date
Application number
PCT/CN2023/074954
Other languages
English (en)
French (fr)
Inventor
田超
李明月
管延庆
曹海明
艾飞
刘广辉
Original Assignee
武汉华星光电技术有限公司
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Filing date
Publication date
Application filed by 武汉华星光电技术有限公司 filed Critical 武汉华星光电技术有限公司
Publication of WO2024119608A1 publication Critical patent/WO2024119608A1/zh

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  • the present application relates to the field of display technology, and in particular to a display panel.
  • the gate driver on array (GOA) in the display screen is set in the non-display area NA, and the scan line is set in the display area AA.
  • the scan signal Gate in the scan line corresponding to the row of sub-pixels needs to be pulled down to a low level.
  • the scan line in the display area AA is relatively long, and low-level signals are transmitted from both ends of the scan line to the scan line, resulting in a large pull-down delay (delay from high level to low level) of the scan signal Gate in the scan line. If the scan signal Gate in the scan line cannot be pulled down to a low level in time, there will be a risk of mischarging, which will lead to uneven display.
  • the embodiments of the present application provide a display panel that can reduce the pull-down delay of a scan signal, reduce the risk of mischarging, and improve display uniformity.
  • An embodiment of the present application provides a display panel, including a display area, wherein the display panel includes: A plurality of scanning lines are located in the display area; A plurality of forward and reverse scan pull-down circuits, each of which comprises a pull-down module, a forward scan control module and a reverse scan control module; Among them, the multiple scan lines include a first scan line corresponding to the forward and reverse scan pull-down circuit, the pull-down module is located in the display area, and the control end of the pull-down module is respectively connected to the output end of the forward scan control module and the output end of the reverse scan control module, and the output end of the pull-down module is connected to the corresponding first scan line.
  • the forward scanning control module is located in the display area.
  • the reverse scanning control module is located in the display area.
  • the pull-down module includes a first switch tube;
  • the control end of the first switch tube is respectively connected to the output end of the forward scan control module and the output end of the reverse scan control module, the input end of the first switch tube is connected to a low level signal, and the output end of the first switch tube is connected to the corresponding first scan line.
  • the plurality of scan lines include a second scan line corresponding to the forward and reverse scan pull-down circuit
  • the forward scan control module includes a second switch tube;
  • the control end of the second switch tube is connected to the corresponding second scan line, the output end of the second switch tube is connected to the control end of the first switch tube, and the input end of the second switch tube is connected to the forward control signal.
  • the plurality of scan lines include a third scan line corresponding to the forward and reverse scan pull-down circuit
  • the reverse scan control module includes a third switch tube;
  • the control end of the third switch tube is connected to the corresponding third scan line
  • the output end of the third switch tube is connected to the control end of the first switch tube
  • the input end of the third switch tube is connected to a reverse control signal.
  • the third scan line, the first scan line and the second scan line corresponding to the forward and reverse scan pull-down circuit are arranged adjacent to each other in sequence.
  • the display panel further includes: The low level signal line is located in the display area, and the low level signal line is connected to the input end of the pull-down module.
  • the display panel further includes: A plurality of rows of pixel circuits are arranged correspondingly to the plurality of forward and reverse scanning pull-down circuits; The output end of the pull-down module in the forward and reverse scanning pull-down circuit is also connected to the scanning signal input end of the corresponding pixel circuit.
  • the display panel further includes a non-display area outside the display area, and the display panel further includes: A gate driving circuit, comprising a plurality of cascaded gate driving units, located in the non-display area;
  • the plurality of gate driving units are arranged in one-to-one correspondence with the plurality of forward and reverse scan pull-down circuits, the control end of the forward scan control module in the forward and reverse scan pull-down circuit is connected to the scan signal output end of the next-level gate driving unit, and the next-level gate driving unit is the next-level gate driving unit of the gate driving unit corresponding to the forward and reverse scan pull-down circuit;
  • the control end of the reverse scan control module in the forward and reverse scan pull-down circuit is connected to the scan signal output end of the previous-level gate driving unit, and the previous-level gate driving unit is the previous-level gate driving unit of the gate driving unit corresponding to the forward and reverse scan pull-down circuit.
  • connection point between the output end of the pull-down module and the corresponding first scan line is located in the middle of the corresponding first scan line.
  • the reverse scanning control module is located in the display area.
  • the first switch tube is a transistor.
  • control end of the first switch tube is the gate of the transistor
  • the input end of the first switch tube is the drain of the transistor
  • the output end of the first switch tube is the source of the transistor
  • the second switch tube is a transistor.
  • control end of the second switch tube is the gate of the transistor
  • the input end of the second switch tube is the drain of the transistor
  • the output end of the second switch tube is the source of the transistor
  • the third switch tubes are all transistors.
  • control end of the third switch tube is the gate of the transistor
  • the input end of the third switch tube is the drain of the transistor
  • the output end of the third switch tube is the source of the transistor
  • the beneficial effects of the present application are as follows: by setting a forward and reverse scan pull-down circuit, and the pull-down module in the forward and reverse scan pull-down circuit is located in the display area, the pull-down module and the scan line are connected in the display area, so that when a row of sub-pixels is charged, the pull-down delay (the delay from a high level to a low level) of the scan signal in the scan line is reduced, and the scan signal in the scan line corresponding to the sub-pixel in the row is promptly pulled down to a low level, thereby reducing the risk of mischarging, improving display uniformity, and realizing forward and reverse scan pull-down, with a simple structure.
  • FIG. 1 is a schematic diagram of the structure of a display panel provided in an embodiment of the present application.
  • FIG2 is a schematic diagram of a structure of a display panel provided in an embodiment of the present application
  • FIG3 is a schematic diagram of a structure of a display panel provided in an embodiment of the present application
  • FIG4 is a schematic structural diagram of a forward and reverse scan pull-down circuit in a display panel provided in an embodiment of the present application
  • FIG5 is a signal timing diagram of a forward scan of a display panel provided by an embodiment of the present application
  • FIG6 is a signal timing diagram of reverse scanning of a display panel provided in an embodiment of the present application
  • FIG7 is a schematic diagram of a structure of a display panel provided in an embodiment of the present application
  • FIG8 is a schematic structural diagram of a forward and reverse scan pull-down circuit in a display panel provided in an embodiment of the present application
  • FIG9a is a timing diagram of a scanning signal in the prior art
  • FIG9 b is a timing diagram of a scan signal in a display panel provided in an embodiment of the present application
  • FIG10 a is
  • the terms “installed”, “connected”, and “connected” should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components.
  • installed should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components.
  • FIG. 1 is a schematic diagram of the structure of a display panel provided by an embodiment of the present invention, wherein the display panel includes a display area AA and a non-display area NA, and the non-display area NA may be located on two opposite sides of the display area AA, that is, one non-display area NA may be provided on two opposite sides of the display area AA.
  • the display panel provided in the embodiment of the present invention includes a plurality of scan lines G, the plurality of scan lines G are located in the display area AA, and the plurality of scan lines G are arranged in parallel and at intervals.
  • the display area AA and the non-display area NA are arranged along a first direction A, and each scan line G extends along the first direction A to the non-display area NA.
  • the display area AA of the display panel is also provided with a plurality of sub-pixels 3 arranged in multiple rows and columns, the number of rows of sub-pixels 3 is the same as the number of scan lines G, and the plurality of scan lines G are connected to the plurality of rows of sub-pixels 3 in a one-to-one correspondence, so that when scanning each row of sub-pixels 3, a scan signal is input to the row of sub-pixels 3 through the scan lines G corresponding to the row of sub-pixels 3.
  • the display panel also includes at least one forward and reverse scan pull-down circuit 2, and the number of the forward and reverse scan pull-down circuits 2 may be equal to the number of scan lines G, or may be less than the number of scan lines G.
  • the plurality of scan lines G include a first scan line corresponding to the forward and reverse scan pull-down circuit 2.
  • the number of the forward and reverse scan pull-down circuits 2 is N, N ⁇ 1, and the plurality of scan lines G include N first scan lines arranged in a one-to-one correspondence with the N forward and reverse scan pull-down circuits 2.
  • the N scan lines G serve as the first scan lines of the N forward and reverse scan pull-down circuits 2 in a one-to-one correspondence.
  • the nth scan line G (n) is the first scan line of the nth forward and reverse scan pull-down circuit 2 (n)
  • the n-1th scan line G (n-1) is the first scan line of the n-1th forward and reverse scan pull-down circuit 2 (n-1)
  • the n+1th scan line G (n+) is the first scan line of the n+1th forward and reverse scan pull-down circuit 2 (n+1), 1 ⁇ n ⁇ N.
  • Each forward and reverse scan pull-down circuit 2 includes a pull-down module 21, a forward scan control module 22 and a reverse scan control module 23.
  • the pull-down module 21 is located in the display area AA, and the control end of the pull-down module 21 is respectively connected to the output end of the forward scan control module 22 and the output end of the reverse scan control module 23, and the output end of the pull-down module 21 is connected to the corresponding first scan line.
  • the forward and reverse scan pull-down circuit 2 can realize forward and reverse scan pull-down.
  • the forward scan control module 22 is used to control the pull-down module 21 to be turned on during forward scan
  • the reverse scan control module 23 is used to control the pull-down module 21 to be turned on during reverse scan
  • the pull-down module 21 is used to pull down the scan signal in the corresponding first scan line to a low level.
  • the forward scanning control modules 22 in the N forward and reverse scanning pull-down circuits 2 are turned on in sequence.
  • the pull-down module 21 in the n-th forward and reverse scanning pull-down circuit 2 (n) pulls down the high level in the first scanning line (i.e., the n-th scanning line G (n)) corresponding to the n-th row of sub-pixels 3 to a low level, and then the n+1-th row of sub-pixels 3 starts to be scanned.
  • the reverse scanning control modules 23 in the N forward and reverse scanning pull-down circuits 2 are turned on in sequence.
  • the pull-down module 21 in the n-th forward and reverse scanning pull-down circuit 2 (n) pulls down the high level in the first scanning line (i.e., the n-th scanning line G (n)) corresponding to the n-th row of sub-pixels 3 to a low level, and then the n-1-th row of sub-pixels 3 starts to be scanned.
  • the connection point of the output end of the pull-down module 21 on the first scan line corresponding thereto is located in the display area AA, so as to shorten the connection route of the pull-down module 21 and the first scan line corresponding thereto.
  • connection point of the output end of the pull-down module 21 and the corresponding first scan line is located in the middle position of the corresponding first scan line, so as to further shorten the connection route of the pull-down module 21 and the first scan line corresponding thereto, thereby shortening the transmission time length of the low-level signal output by the pull-down module 21 in the first scan line corresponding thereto, reducing the pull-down delay of the scan signal (i.e., the delay of the scan signal changing from a high level to a low level), reducing the risk of mischarging, and improving display uniformity.
  • the forward scanning control module 22 can be located in the display area AA or in the non-display area NA, and the reverse scanning control module 23 can be located in the display area AA or in the non-display area NA.
  • the pull-down module 21, the forward scanning control module 22, and the reverse scanning control module 23 are all located in the display area AA.
  • the pull-down module 21 is located in the display area AA, and the forward scanning control module 22 and the reverse scanning control module 23 are located in the non-display area NA.
  • the forward scanning control module 22 and/or the reverse scanning control module 23 are located in the display area AA, which can shorten the connection route between the forward scanning control module 22 and/or the reverse scanning control module 23 and the pull-down module 21, further reduce the signal transmission delay, and thus reduce the pull-down delay of the scanning signal.
  • the plurality of scan lines G also include a second scan line corresponding to the forward and reverse scan pull-down circuit 2. That is, the plurality of scan lines G also include N second scan lines arranged in one-to-one correspondence with the N forward and reverse scan pull-down circuits 2. It should be noted that the first scan lines corresponding to different forward and reverse scan pull-down circuits 2 are different, and the second scan lines corresponding to different forward and reverse scan pull-down circuits 2 are different, but the second scan line corresponding to one forward and reverse scan pull-down circuit 2 can be the first scan line corresponding to another forward and reverse scan pull-down circuit 2.
  • the n+1th scan line G (n+1) is the first scan line corresponding to the n+1th forward and reverse scan pull-down circuit 2 (n+1), and is also the second scan line corresponding to the nth forward and reverse scan pull-down circuit 2 (n).
  • the control end of the forward scanning control module 22 in each forward and reverse scanning pull-down circuit 2 is connected to the corresponding second scanning line, so that the forward scanning control module 22 is turned on or off according to the scanning signal in the corresponding second scanning line, that is, when the scanning signal in the corresponding second scanning line is at a high level, the forward scanning control module 22 is turned on, and when the scanning signal in the corresponding second scanning line is at a low level, the forward scanning control module 22 is turned off.
  • the forward scanning control module 22 is located in the display area AA, the connection route of the forward scanning control module 22 to the corresponding second scanning line can be shortened, further reducing the signal delay.
  • the plurality of scan lines G also include a third scan line corresponding to the forward and reverse scan pull-down circuit 2. That is, the plurality of scan lines G also include N third scan lines arranged in one-to-one correspondence with the N forward and reverse scan pull-down circuits 2. It should be noted that the third scan lines corresponding to different forward and reverse scan pull-down circuits 2 are different, but the third scan line corresponding to one forward and reverse scan pull-down circuit 2 can be the first scan line corresponding to another forward and reverse scan pull-down circuit 2, and can also be the second scan line corresponding to another forward and reverse scan pull-down circuit 2. That is to say, the same scan line can be used as the first scan line, the second scan line, and the third scan line of different forward and reverse scan pull-down circuits 2.
  • the nth scan line G (n) is the first scan line corresponding to the nth forward and reverse scan pull-down circuit 2 (n), and is also the second scan line corresponding to the n-1th forward and reverse scan pull-down circuit 2 (n-1), and is also the third scan line corresponding to the n+1th forward and reverse scan pull-down circuit 2 (n+1).
  • the control end of the reverse scan control module 23 in each forward and reverse scan pull-down circuit 2 is connected to the corresponding third scan line, so that the reverse scan control module 23 is turned on or off according to the scan signal in the corresponding third scan line, that is, when the scan signal in the corresponding third scan line is at a high level, the reverse scan control module 23 is turned on, and when the scan signal in the corresponding third scan line is at a low level, the reverse scan control module 23 is turned off.
  • the connection route of the reverse scan control module 23 to the corresponding third scan line can be shortened, further reducing the signal delay.
  • the third scan line, the first scan line, and the second scan line corresponding to each forward and reverse scan pull-down circuit 2 are sequentially arranged adjacent to each other, further shortening the overall connection line between the forward and reverse scan pull-down circuit 2 and its corresponding third scan line, first scan line, and second scan line, and further reducing the signal transmission delay.
  • the third scan line i.e., the n-1th scan line G(n-1)
  • the first scan line i.e., the nth scan line G(n)
  • the second scan line i.e., the n+1th scan line G(n+1)
  • the display panel may further include a forward control signal line U, a reverse control signal line D and a low-level signal line V.
  • Each forward and reverse scan pull-down circuit 2 is also respectively connected to the forward control signal line U, the reverse control signal line D and the low-level signal line V.
  • the input end of the forward scan control module 22 in each forward and reverse scan pull-down circuit 2 is connected to the forward control signal line U
  • the input end of the reverse scan control module 23 in each forward and reverse scan pull-down circuit 2 is connected to the reverse control signal line D
  • the input end of the pull-down module 21 in each forward and reverse scan pull-down circuit 2 is connected to the low-level signal line V.
  • the forward control signal line U is used to provide a forward control signal to the forward scanning control module 22.
  • the reverse control signal line D is used to provide a reverse control signal to the reverse scanning control module 23.
  • the low level signal line V is used to provide a low level signal to the pull-down module 21.
  • the forward control signal line U, the reverse control signal line D and the low-level signal line V can all be located in the display area AA, and the forward control signal line U, the reverse control signal line D and the low-level signal line V can be arranged in parallel and at intervals.
  • the forward control signal line U, the reverse control signal line D and the low-level signal line V can be arranged in the same layer.
  • the forward control signal line U and the plurality of scanning lines G can be arranged in an insulated cross-arrangement, that is, the forward control signal line U and the plurality of scanning lines G are arranged in different layers, and the forward projection of the forward control signal line U on the film layer where the scanning lines G are located intersects with the plurality of scanning lines G respectively.
  • the reverse control signal line D and the plurality of scanning lines G can be arranged in an insulated cross-arrangement, that is, the reverse control signal line D and the plurality of scanning lines G are arranged in different layers, and the forward projection of the reverse control signal line D on the film layer where the scanning lines G are located intersects with the plurality of scanning lines G respectively.
  • the low level signal line V and the multiple scanning lines G can be insulated and cross-arranged, that is, the low level signal line V and the multiple scanning lines G are arranged in different layers, and the orthographic projections of the low level signal line V on the film layer where the scanning lines G are located intersect with the multiple scanning lines G respectively.
  • the forward control signal line U, the reverse control signal line D, and the low level signal line V all extend along a second direction B, and the second direction B may be perpendicular to the first direction A.
  • n+1th scanning line G(n+1) i.e., the second scanning line corresponding to the nth forward and reverse scanning pull-down circuit 2(n)
  • the forward scanning control module 22 in the nth forward and reverse scanning pull-down circuit 2(n) is turned on.
  • the reverse scanning control module 23 is in the off state, and the forward control signal line U transmits a high-level forward control signal to the forward scanning control module 22 in the nth forward and reverse scanning pull-down circuit 2(n), so that the forward scanning control module 22 transmits a high-level signal to the corresponding pull-down module 21 to control the corresponding pull-down module 21 to pull down the scanning signal in its corresponding first scanning line (i.e., the nth scanning signal line G(n)) to a low level.
  • the n-1th scanning line G (n-1) that is, the third scanning line corresponding to the nth forward and reverse scanning pull-down circuit 2 (n) inputs a high-level scanning signal
  • the reverse scanning control module 23 in the nth forward and reverse scanning pull-down circuit 2 (n) is turned on.
  • the forward scanning control module 22 is in the off state, and the reverse control signal line D transmits a high-level reverse control signal to the reverse scanning control module 23 in the nth forward and reverse scanning pull-down circuit 2 (n), so that the reverse scanning control module 23 transmits a high-level signal to the corresponding pull-down module 21 to control the corresponding pull-down module 21 to pull down its corresponding first scanning line (that is, the scanning signal in the nth scanning signal G (n)) to a low level.
  • the forward scan control module 22 in the nth forward and reverse scan pull-down circuit 2 (n) can be arranged close to the n+1th scan line G (n+1) and the forward control signal line U.
  • the forward scan control module 22 in the nth forward and reverse scan pull-down circuit 2 (n) can be arranged at the intersection of the n+1th scan line G (n+1) and the forward control signal line U, so as to shorten the connection line connecting the forward scan control module 22 in the nth forward and reverse scan pull-down circuit 2 (n) with the n+1th scan line G (n+1) and the forward control signal line U, thereby reducing the signal transmission delay.
  • the reverse scan control module 23 in the nth forward and reverse scan pull-down circuit 2 (n) can be arranged close to the n-1th scan line G (n-1) and the reverse control signal line D.
  • the reverse scan control module 23 in the nth forward and reverse scan pull-down circuit 2 (n) can be arranged at the intersection of the n-1th scan line G (n-1) and the reverse control signal line D, so as to shorten the connection line between the reverse scan control module 23 in the nth forward and reverse scan pull-down circuit 2 (n) and the n-1th scan line G (n-1) and the reverse control signal line D, thereby reducing the signal transmission delay.
  • the pull-down module 21 in the nth forward and reverse scan pull-down circuit 2 (n) can be arranged close to the nth scan line G (n) and the low-level signal line V.
  • the pull-down module 21 in the nth forward and reverse scan pull-down circuit 2 (n) can be arranged at the intersection of the nth scan line G (n) and the low-level signal line V, so as to shorten the connection line between the pull-down module 21 in the nth forward and reverse scan pull-down circuit 2 (n) and the nth scan line G (n) and the low-level signal line V, thereby reducing the signal transmission delay.
  • the pull-down module 21 Since the pull-down module 21 is connected to the corresponding forward scanning control module 22 and the reverse scanning control module 23 respectively, the pull-down module 21 can be arranged between the corresponding forward scanning control module 22 and the reverse scanning control module 23 to shorten the first connection line between the pull-down module 21 and the corresponding forward scanning control module 22 and the second connection line between the pull-down module 21 and the corresponding reverse scanning control module 23, thereby reducing the signal transmission delay.
  • the first connection line and the second connection line can be arranged in the same layer, the first connection line and the second connection line can be arranged in different layers from the scanning line G, and can also be arranged in different layers from the forward control signal line U, the reverse control signal line D and the low-level signal line V.
  • the pull-down module 21 needs to be connected to the low-level signal line V
  • the forward scanning control module 22 needs to be connected to the forward control signal line U
  • the reverse scanning control module 23 needs to be connected to the reverse control signal line D
  • the low-level signal line V can be arranged between the forward control signal line U and the reverse control signal line D, that is, the reverse control signal line D, the low-level signal line V and the forward control signal line U are arranged in sequence along the first direction A.
  • the display panel may further include a plurality of data lines data, the plurality of data lines data are located in the display area AA, and the plurality of data lines data are arranged in parallel and at intervals.
  • the number of data lines data is the same as the number of columns of sub-pixels 3, that is, the plurality of data lines data are connected to the plurality of columns of sub-pixels 3 in a one-to-one correspondence.
  • Each data line data extends along the second direction B, and the data lines data and the scanning lines G are arranged in different layers, so that the plurality of data lines data and the plurality of scanning lines G are insulated and crossed to define a plurality of sub-pixels 3.
  • the data line data can be arranged in the same layer as the forward control signal line U, the reverse control signal line D and the low-level signal line V, and the data line data can be arranged in parallel with the forward control signal line U, the reverse control signal line D and the low-level signal line and spaced apart. There are gaps on both sides of each column of data lines data, and the forward control signal line U, the reverse control signal line D and the low-level signal line V can be arranged at the gaps on both sides of the data lines data.
  • the forward control signal line U, the reverse control signal line D and the low-level signal line V can be respectively arranged at the gaps on one side of the three data lines data.
  • the reverse control signal line D, the low level signal line V and the forward control signal line U are respectively arranged close to the three adjacent data lines data, that is, the reverse control signal line D, the low level signal line V and the forward control signal line U are respectively located on one side of the three adjacent data lines data, so as to shorten the length of the connection line between the pull-down module 21 and the forward scanning control module 22 and the reverse scanning control module 23, and reduce the signal delay.
  • the reverse control signal line D is located on one side of the data line data1
  • the low level signal line V is located on one side of the data line data
  • the forward control signal line U is located on one side of the data line data3.
  • the pull-down module 21 in each forward and reverse scan pull-down circuit 2 includes a first switch tube NTC.
  • the control end (such as the gate) of the first switch tube NTC is respectively connected to the output end of the corresponding forward scan control module 22 and the output end of the corresponding reverse scan control module 23, and the input end (such as the drain) of the first switch tube NTC is connected to the low-level signal, that is, the input end of the first switch tube NTC is connected to the low-level signal line V, and the output end (such as the source) of the first switch tube NTC is connected to the corresponding first scan line.
  • the forward scanning control module 22 in each forward and reverse scanning pull-down circuit 2 includes a second switch tube NTB.
  • the control end (such as the gate) of the second switch tube NTB is connected to the corresponding second scanning line
  • the output end (such as the drain) of the second switch tube NTB is connected to the control end of the first switch tube NTC
  • the input end (such as the source) of the second switch tube NTB is connected to the forward control signal, that is, the input end of the second switch tube NTB is connected to the forward control signal line U.
  • the reverse scan control module 23 in each forward and reverse scan pull-down circuit 2 includes a third switch tube NTA.
  • the control end (such as the gate) of the third switch tube NTA is connected to the corresponding third scan line
  • the output end (such as the drain) of the third switch tube NTA is connected to the control end of the first switch tube NTC
  • the input end (such as the source) of the third switch tube NTA is connected to the reverse control signal, that is, the input end of the third switch tube NTA is the reverse control signal line D.
  • the forward control signal line U provides a high-level signal VGH
  • the reverse control signal line D provides a low-level signal VGL.
  • the high-level scanning signal is sequentially input to the n-1th scanning line G(n-1), the nth scanning line G(n), and the n+1th scanning line G(n+1), so as to sequentially charge the n-1th row of sub-pixels 3, the nth row of sub-pixels, and the n+1th row of sub-pixels.
  • the scanning signal input to the n+1th scanning line G(n+1) is a high-level signal VGH
  • the second switch tube NTB is turned on. Since the forward control signal line U provides a high-level signal VGH, the node GQ is pulled up to a high level, the first switch tube NTC is turned on, and the low-level signal line V provides a low-level signal VGL, thereby pulling the scanning signal in the nth scanning line G(n) from a high level to a low level.
  • the forward control signal line U provides a low-level signal VGL
  • the reverse control signal line D provides a high-level signal VGH.
  • the high-level scanning signal is sequentially input to the n+1th scanning line G(n+1), the nth scanning line G(n), and the n-1th scanning line G(n-1), so as to sequentially charge the n+1th row of sub-pixels 3, the nth row of sub-pixels, and the n-1th row of sub-pixels.
  • the scanning signal input to the n-1th scanning line G(n-1) is a high-level signal VGH
  • the third switch tube NTA is turned on. Since the reverse control signal line D provides a high-level signal VGH, the node GQ is pulled up to a high level, the first switch tube NTC is turned on, and the low-level signal line V provides a low-level signal VGL, thereby pulling the scanning signal in the nth scanning line G(n) from a high level to a low level.
  • the node GQ is the connection point of the first switch tube NTC, the second switch tube NTB and the third switch tube NTA, that is, the control end of the first switch tube NTC is connected to the node GQ, the output end of the second switch tube NTB is connected to the node GQ, and the output end of the third switch tube NTA is connected to the node GQ, so that the control end of the first switch tube NTC is respectively connected to the output end of the second switch tube NTB and the output end of the third switch tube NTA.
  • the first switch tube NTC, the second switch tube NTB and the third opening tube NTA can be LTPS (Low Temperature Poly-silicon) transistors, a_Si (amorphous silicon) transistors, IGZO (indium gallium zinc oxide) transistors, OLED or LTPS&IGZO hybrid transistors.
  • LTPS Low Temperature Poly-silicon
  • a_Si amorphous silicon
  • IGZO indium gallium zinc oxide
  • OLED LTPS&IGZO hybrid transistors.
  • the display panel also includes a plurality of rows of pixel circuits 5 located in the display area AA.
  • the number of rows of pixel circuits 5 may be the same as the number of scan lines G, and the plurality of rows of pixel circuits 5 are connected in a one-to-one correspondence with the plurality of scan lines G.
  • the number of rows of pixel circuits 5 may be equal to the number of forward and reverse scan pull-down circuits 2, or may be greater than the number of forward and reverse scan pull-down circuits 2.
  • the plurality of rows of pixel circuits 5 include N rows of pixel circuits 5 arranged in a one-to-one correspondence with the N forward and reverse scan pull-down circuits 2.
  • the output end of the pull-down module 21 in the N forward and reverse scan pull-down circuits 2 is also connected in a one-to-one correspondence with the scan signal input end of the N rows of pixel circuits 5.
  • the output end of the pull-down module 21 in the nth forward and reverse scan pull-down circuit 2 (n) is also connected to the scan signal input end of the nth row pixel circuit 5 (n).
  • the output end (such as the source) of the first switch tube NTC in the nth forward and reverse scan pull-down circuit 2 (n) is also connected to the scan signal input end of the nth row pixel circuit 5 (n).
  • the display panel further includes a gate driving circuit 4 located in the non-display area NA, and the gate driving circuit 4 includes a plurality of cascaded gate driving units 41.
  • the number of the gate driving units 41 may be the same as the number of the scanning lines G, and the plurality of cascaded gate driving units 41 are connected one-to-one with the plurality of scanning lines G, and the plurality of cascaded gate driving units 41 are connected one-to-one with the plurality of rows of sub-pixels 3.
  • a scanning signal is input to the row of sub-pixels 3 through the gate driving units 41 corresponding to the row of sub-pixels 3 and the scanning lines G corresponding to the row of sub-pixels 3.
  • the gate driving circuit 4 may be unilaterally driven or bilaterally driven, which is not specifically limited here.
  • the number of the plurality of gate drive units 41 may be equal to the number of the forward and reverse scan pull-down circuits 2, or may be greater than the number of the forward and reverse scan pull-down circuits 2.
  • the plurality of gate drive units 41 includes N gate drive units 41 that are arranged in a one-to-one correspondence with the N forward and reverse scan pull-down circuits 2.
  • control end of the forward scan control module 22 in each forward and reverse scan pull-down circuit 2 is connected to the scan signal output end of the next-stage gate drive unit 41, and the next-stage gate drive unit 41 is the next-stage gate drive unit 41 of the gate drive unit 41 corresponding to the forward and reverse scan pull-down circuit 2;
  • control end of the reverse scan control module 23 in the forward and reverse scan pull-down circuit 2 is connected to the scan signal output end of the previous-stage gate drive unit 41, and the previous-stage gate drive unit 41 is the previous-stage gate drive unit 41 of the gate drive unit 41 corresponding to the forward and reverse scan pull-down circuit 2.
  • the control end of the forward scanning control module 22 in the nth forward and reverse scanning pull-down circuit 2 (n) is connected to the scanning signal output end of the n+1th gate driving unit 41 (n+1), and the control end of the reverse scanning control module 23 in the nth forward and reverse scanning pull-down circuit 2 (n) is connected to the scanning signal output end of the n-1th gate driving unit 41 (n-1).
  • control end (such as the gate) of the second switch tube NTB in the nth forward and reverse scanning pull-down circuit 2 (n) is connected to the scanning signal output end of the n+1th gate driving unit 41 (n+1), and the control end (such as the gate) of the third switch tube NTA in the nth forward and reverse scanning pull-down circuit 2 (n) is connected to the scanning signal output end of the n-1th gate driving unit 41 (n-1).
  • the scanning signal Gate in the scanning line G corresponding to the row of sub-pixels 3 is pulled down to a low level by the gate driving circuit 4 located in the non-display area NA, since the scanning line G is long, the delay of the low-level signal output by the gate driving circuit 4 in transmitting on the scanning line G is large, resulting in a large pull-down delay of the scanning signal Gate.
  • the pull-down delay of the scanning signal Gate at the edge areas AA1 and AA3 is large, and the pull-down delay of the scanning signal Gate at the middle area AA2 is larger than the pull-down delay of the scanning signal Gate at the edge areas AA1 and AA3.
  • the embodiment of the present invention adds a forward and reverse scan pull-down circuit 2 in the display panel, so that after a row of sub-pixels 3 is scanned, the scan signal Gate in the scan line G corresponding to the row of sub-pixels 3 is pulled down to a low level through the pull-down module 21 in the forward and reverse scan pull-down circuit 2. Since the pull-down module 21 is located in the display area AA, the transmission delay of the low-level signal output by the pull-down module 21 in the scan line G is shortened, and the pull-down delay of the scan signal Gate in the scan line G is reduced. As shown in FIG. 1 and FIG. 9b, the pull-down delay of the scan signal Gate in the middle area AA2 and the edge areas AA1 and AA3 is reduced.
  • the duration of the high-level timing signal is reduced, resulting in a reduction in the actual charging time of a row of sub-pixels 3, that is, the actual charging time of a row of sub-pixels 3 is less than the required charging time.
  • high-level multiplexing signals e.g., the high level of MUX1, the high level of MUX2, and the high level of MUX3 are sequentially inputted into the sub-pixels in the row of sub-pixels to charge the sub-pixels 3. Since the duration of the high-level timing signal is reduced, the duration allocated to each high-level multiplexing signal is reduced, resulting in a reduction in the charging duration of the sub-pixel.
  • the time interval reserved between the high-level timing signals inputted into two adjacent rows of sub-pixels 3 is reduced, or even no time interval is required.
  • there is no time interval between two adjacent high-level timing signals such as the high level of CK1 and the high level of CK2, and the high level of CK2 and the high level of CK3
  • the duration of the high-level timing signals inputted into a row of sub-pixels 3 (such as the high level of CK1, the high level of CK2, and the high level of CK3) is T2
  • the actual charging duration of a row of sub-pixels 3 is T2, which effectively increases the actual charging duration of a row of sub-pixels 3.
  • the increase in the duration of the high-level timing signal increases the duration allocated to each high-level multiplexing signal (such as the high level of MUX1, the high level of MUX2, and the high level of MUX3), effectively increasing the charging duration of the sub-pixels, thereby achieving high-frequency display.
  • the embodiments of the present application set up a forward and reverse scan pull-down circuit, and the pull-down module in the forward and reverse scan pull-down circuit is located in the display area, so that the pull-down module and the scan line are connected in the display area, so that when a row of sub-pixels is charged, the pull-down delay (the delay from a high level to a low level) of the scan signal in the scan line is reduced, and the scan signal in the scan line corresponding to the row of sub-pixels is promptly pulled down to a low level, thereby reducing the risk of mischarging, improving display uniformity, and realizing forward and reverse scan pull-down, and the structure is simple.

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Abstract

一种显示面板，包括：多条扫描线；多个正反扫下拉电路（2），正反扫下拉电路包括下拉模块（21）、正向扫描控制模块（22）和反向扫描控制模块（23）；下拉模块（21）位于显示区（AA），下拉模块（21）的控制端分别与正向扫描控制模块（22）的输出端和反向扫描控制模块（23）的输出端连接，下拉模块（21）的输出端与对应的扫描线连接。该正反扫下拉电路用于降低扫描信号的下拉时延，降低错充风险，改善显示面板的显示均一性。

Description

显示面板 技术领域
本申请涉及显示技术领域，尤其涉及一种显示面板。
 背景技术
显示屏中的栅极驱动电路（Gate Driver On Array，GOA）设置在非显示区NA，而扫描线设置在显示区AA。在一行子像素充电完成时，需要将该行子像素对应的扫描线中的扫描信号Gate下拉至低电平。但对于超宽显示屏，显示区AA的扫描线较长，从扫描线的两端向扫描线传输低电平信号，导致扫描线中的扫描信号Gate的下拉时延（由高电平变为低电平的时延）较大。而扫描线中的扫描信号Gate无法及时下拉至低电平，会存在错充风险，进而导致显示不均。
 技术问题
本申请实施例提供一种显示面板，能够降低扫描信号的下拉时延，降低错充风险，改善显示均一性。
 技术解决方案
本申请实施例提供了一种显示面板，包括显示区，所述显示面板包括：
多条扫描线，位于所述显示区；
多个正反扫下拉电路，每个所述正反扫下拉电路包括下拉模块、正向扫描控制模块和反向扫描控制模块；
其中，所述多条扫描线包括与所述正反扫下拉电路相对应的第一扫描线，所述下拉模块位于所述显示区，且所述下拉模块的控制端分别与所述正向扫描控制模块的输出端、所述反向扫描控制模块的输出端连接，所述下拉模块的输出端与对应的第一扫描线连接。
可选地，所述正向扫描控制模块位于所述显示区。
可选地，所述反向扫描控制模块位于所述显示区。
可选地，所述下拉模块包括第一开关管；
所述第一开关管的控制端分别连接所述正向扫描控制模块的输出端、所述反向扫描控制模块的输出端，所述第一开关管的输入端接入低电平信号，所述第一开关管的输出端连接所述对应的第一扫描线。
可选地，所述多条扫描线包括与所述正反扫下拉电路相对应的第二扫描线，所述正向扫描控制模块包括第二开关管；
所述第二开关管的控制端连接对应的第二扫描线，所述第二开关管的输出端连接所述第一开关管的控制端，所述第二开关管的输入端接入正向控制信号。
可选地，所述多条扫描线包括与所述正反扫下拉电路相对应的第三扫描线，所述反向扫描控制模块包括第三开关管；
所述第三开关管的控制端连接对应的第三扫描线，所述第三开关管的输出端连接所述第一开关管的控制端，所述第三开关管的输入端接入反向控制信号。
可选地，所述正反扫下拉电路对应的第三扫描线、第一扫描线和第二扫描线依次相邻设置。
可选地，所述显示面板还包括：
低电平信号线，位于所述显示区，且所述低电平信号线与所述下拉模块的输入端连接。
可选地，所述显示面板还包括：
多行像素电路，与多个所述正反扫下拉电路一一对应设置；
所述正反扫下拉电路中的下拉模块的输出端还与对应的像素电路的扫描信号输入端连接。
可选地，所述显示面板还包括位于所述显示区外的非显示区，所述显示面板还包括：
栅极驱动电路，包括多个级联的栅极驱动单元，位于所述非显示区；
多个所述栅极驱动单元与多个所述正反扫下拉电路一一对应设置，所述正反扫下拉电路中的正向扫描控制模块的控制端与下一级栅极驱动单元的扫描信号输出端连接，所述下一级栅极驱动单元为所述正反扫下拉电路对应的栅极驱动单元的下一级栅极驱动单元；所述正反扫下拉电路中的反向扫描控制模块的控制端与上一级栅极驱动单元的扫描信号输出端连接，所述上一级栅极驱动单元为所述正反扫下拉电路对应的栅极驱动单元的上一级栅极驱动单元。
可选地，所述下拉模块的输出端与所述对应的第一扫描线的连接点位于所述对应的第一扫描线的中间位置。
可选地，所述反向扫描控制模块位于所述显示区。
可选地，所述第一开关管为晶体管。
可选地，所述第一开关管的控制端为所述晶体管的栅极，所述第一开关管的输入端为所述晶体管的漏极，所述第一开关管的输出端为所述晶体管的源极。
可选地，所述第二开关管为晶体管。
可选地，所述第二开关管的控制端为所述晶体管的栅极，所述第二开关管的输入端为所述晶体管的漏极，所述第二开关管的输出端为所述晶体管的源极。
可选地，所述第三开关管均为晶体管。
可选地，所述第三开关管的控制端为所述晶体管的栅极，所述第三开关管的输入端为所述晶体管的漏极，所述第三开关管的输出端为所述晶体管的源极。
 有益效果
本申请的有益效果为：通过设置正反扫下拉电路，且正反扫下拉电路中的下拉模块位于显示区，使得下拉模块和扫描线连接在显示区，以在一行子像素充电完成时，减少扫描线中扫描信号的下拉时延（由高电平变为低电平的时延），及时将该行子像素对应的扫描线中的扫描信号下拉至低电平，降低错充风险，改善显示均一性，且实现正反扫下拉，结构简单。
 附图说明
下面结合附图，通过对本申请的具体实施方式详细描述，将使本申请的技术方案及其它有益效果显而易见。
图1为本申请实施例提供的显示面板的一个结构示意图。
图2为本申请实施例提供的显示面板的一个结构示意图；
图3为本申请实施例提供的显示面板的一种结构示意图；
图4为本申请实施例提供的显示面板中正反扫下拉电路的一个结构示意图；
图5为本申请实施例提供的显示面板正向扫描的信号时序图；
图6为本申请实施例提供的显示面板反向扫描的信号时序图；
图7为本申请实施例提供的显示面板的一种结构示意图；
图8为本申请实施例提供的显示面板中正反扫下拉电路的一个结构示意图；
图9a为现有技术中的扫描信号的时序图；
图9b为本申请实施例提供的显示面板中的扫描信号的时序图；
图10a为现有技术中的充电时序图；
图10b为本申请实施例提供的显示面板中的充电时序图。
本发明的实施方式
这里所公开的具体结构和功能细节仅仅是代表性的，并且是用于描述本申请的示例性实施例的目的。但是本申请可以通过许多替换形式来具体实现，并且不应当被解释成仅仅受限于这里所阐述的实施例。
在本申请的描述中，需要理解的是，术语“中心”、“横向”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。另外，术语“包括”及其任何变形，意图在于覆盖不排他的包含。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
这里所使用的术语仅仅是为了描述具体实施例而不意图限制示例性实施例。除非上下文明确地另有所指，否则这里所使用的单数形式“一个”、“一项”还意图包括复数。还应当理解的是，这里所使用的术语“包括”和/或“包含”规定所陈述的特征、整数、步骤、操作、单元和/或组件的存在，而不排除存在或添加一个或更多其他特征、整数、步骤、操作、单元、组件和/或其组合。
下面结合附图和实施例对本申请作进一步说明。
参见图1，是本发明实施例提供的显示面板的结构示意图。其中，显示面板包括显示区AA和非显示区NA，非显示区NA可以位于显示区AA的相对两侧，即显示区AA的相对两侧可以分别设有一个非显示区NA。
结合图2和图3所示，本发明实施例提供的显示面板包括多条扫描线G，多条扫描线G位于显示区AA，且多条扫描线G平行且间隔设置。显示区AA和非显示区NA沿第一方向A排列，每条扫描线G沿第一方向A延伸至非显示区NA。显示面板的显示区AA还设有呈多行多列排列的多个子像素3，子像素3的行数与扫描线G的条数相同，且多条扫描线G与多行子像素3一一对应连接，以在扫描每行子像素3时，通过该行子像素3对应的扫描线G向该行子像素3输入扫描信号。如图2和图3所示，每行子像素3的两侧具有间隙，每条扫描线G可以设置在其对应的一行子像素3一侧的间隙处。
显示面板还包括至少一个正反扫下拉电路2，正反扫下拉电路2的个数可以等于扫描线G的条数，也可以小于扫描线G的条数。多条扫描线G包括与正反扫下拉电路2相对应的第一扫描线。例如，正反扫下拉电路2的个数为N，N≥1，多条扫描线G包括与N个正反扫下拉电路2一一对应设置的N条第一扫描线。在正反扫下拉电路2的个数与扫描线G的条数相同（即扫描线G的条数为N）时，N条扫描线G一一对应地作为N个正反扫下拉电路2的第一扫描线。如图3所示，第n条扫描线G（n）为第n个正反扫下拉电路2（n）的第一扫描线，第n-1条扫描线G（n-1）为第n-1个正反扫下拉电路2（n-1）的第一扫描线，第n+1条扫描线G（n+）为第n+1个正反扫下拉电路2（n+1）的第一扫描线，1＜n＜N。
每个正反扫下拉电路2均包括下拉模块21、正向扫描控制模块22和反向扫描控制模块23。下拉模块21位于显示区AA，且下拉模块21的控制端分别与正向扫描控制模块22的输出端、反向扫描控制模块23的输出端连接，下拉模块21的输出端与对应的第一扫描线连接。
正反扫下拉电路2可以实现正反扫下拉。其中，正向扫描控制模块22用于在正向扫描时控制下拉模块21导通，反向扫描控制模块23用于在反向扫描时控制下拉模块21导通，下拉模块21用于将其对应的第一扫描线中的扫描信号下拉至低电平。
具体地，在正向扫描多行子像素3时，N个正反扫下拉电路2中的正向扫描控制模块22依次导通。当第n行子像素3扫描完成时，第n个正反扫下拉电路2（n）中的下拉模块21将第n行子像素3对应的第一扫描线（即第n条扫描线G（n））中的高电平下拉至低电平，然后第n+1行子像素3开始扫描。在反向扫描多行子像素3时，N个正反扫下拉电路2中的反向扫描控制模块23依次导通。当第n行子像素3扫描完成时，第n个正反扫下拉电路2（n）中的下拉模块21将第n行子像素3对应的第一扫描线（即第n条扫描线G（n））中的高电平下拉至低电平，然后第n-1行子像素3开始扫描。
由于下拉模块21和其对应的第一扫描线均位于显示区AA，下拉模块21的输出端在其对应的第一扫描线上的连接点位于显示区AA，以缩短下拉模块21与其对应的第一扫描线的连接路线。在一些实施例中，下拉模块21的输出端与对应的第一扫描线的连接点位于对应的第一扫描线的中间位置，以进一步缩短下拉模块21与其对应的第一扫描线的连接路线，从而缩短下拉模块21输出的低电平信号在其对应的第一扫描线中的传输时长，减小扫描信号的下拉时延（即扫描信号由高电平变为低电平的时延），降低错充风险，改善显示均一性。
正向扫描控制模块22可以位于显示区AA，也可以位于非显示区NA，反向扫描控制模块23可以位于显示区AA，也可以位于非显示区NA。如图2所示，下拉模块21、正向扫描控制模块22和反向扫描控制模块23均位于显示区AA。如图3所示，下拉模块21位于显示区AA，正向扫描控制模块22和反向扫描控制模块23位于非显示区NA。
正向扫描控制模块22和/或反向扫描控制模块23位于显示区AA，可以缩短正向扫描控制模块22和/或反向扫描控制模块23与下拉模块21的连接路线，进一步减小信号传输时延，从而减小扫描信号的下拉时延。
多条扫描线G还包括与正反扫下拉电路2相对应的第二扫描线。也就是说，多条扫描线G还包括与N个正反扫下拉电路2一一对应设置的N条第二扫描线。需要说明的是，不同正反扫下拉电路2对应的第一扫描线不同，不同正反扫下拉电路2对应的第二扫描线不同，但一个正反扫下拉电路2对应的第二扫描线可以为另一个正反扫下拉电路2对应的第一扫描线。如图3所示，第n+1条扫描线G（n+1）为第n+1个正反扫下拉电路2（n+1）对应的第一扫描线，同时为第n个正反扫下拉电路2（n）对应的第二扫描线。
每个正反扫下拉电路2中的正向扫描控制模块22的控制端与其对应的第二扫描线连接，使正向扫描控制模块22根据其对应的第二扫描线中的扫描信号导通或关断，即其对应的第二扫描线中的扫描信号为高电平时，正向扫描控制模块22导通，其对应的第二扫描线中的扫描信号为低电平时，正向扫描控制模块22关断。正向扫描控制模块22位于显示区AA时，可以缩短正向扫描控制模块22连接其对应的第二扫描线的连接路线，进一步减小信号时延。
多条扫描线G还包括与正反扫下拉电路2相对应的第三扫描线。也就是说，多条扫描线G还包括与N个正反扫下拉电路2一一对应设置的N条第三扫描线。需要说明的是，不同正反扫下拉电路2对应的第三扫描线不同，但一个正反扫下拉电路2对应的第三扫描线可以为另一个正反扫下拉电路2对应的第一扫描线，还可以为又一个正反扫下拉电路2对应的第二扫描线。也就是说，同一扫描线可以作为不同正反扫下拉电路2的第一扫描线、第二扫描线、第三扫描线。如图3所示，第n条扫描线G（n）为第n个正反扫下拉电路2（n）对应的第一扫描线，同时为第n-1个正反扫下拉电路2（n-1）对应的第二扫描线，同时为第n+1个正反扫下拉电路2（n+1）对应的第三扫描线。
每个正反扫下拉电路2中的反向扫描控制模块23的控制端与其对应的第三扫描线连接，使反向扫描控制模块23根据其对应的第三扫描线中的扫描信号导通或关断，即其对应的第三扫描线中的扫描信号为高电平时，反向扫描控制模块23导通，其对应的第三扫描线中的扫描信号为低电平时，反向扫描控制模块23关断。反向扫描控制模块23位于显示区AA时，可以缩短反向扫描控制模块23连接其对应的第三扫描线的连接路线，进一步减小信号时延。
在一些实施例中，每个正反扫下拉电路2对应的第三扫描线、第一扫描线和第二扫描线依次相邻设置，进一步缩短正反扫下拉电路2与其对应的第三扫描线、第一扫描线和第二扫描线的整体连接线路，进一步减小信号传输时延。如图3所示，第n个正反扫下拉电路2（n）对应的第三扫描线（即第n-1条扫描线G（n-1））、第一扫描线（即第n条扫描线G（n））和第二扫描线（即第n+1条扫描线G（n+1））依次相邻设置。
如图2所示，显示面板还可以包括正向控制信号线U、反向控制信号线D和低电平信号线V。每个正反扫下拉电路2还分别与所述正向控制信号线U、所述反向控制信号线D和所述低电平信号线V连接。具体地，每个正反扫下拉电路2中的正向扫描控制模块22的输入端与正向控制信号线U连接，每个正反扫下拉电路2中的反向扫描控制模块23的输入端与反向控制信号线D连接，每个正反扫下拉电路2中的下拉模块21的输入端与低电平信号线V连接。
其中，正向控制信号线U用于向正向扫描控制模块22提供正向控制信号。反向控制信号线D用于向反向扫描控制模块23提供反向控制信号。低电平信号线V用于向下拉模块21提供低电平信号。
如图2所示，在下拉模块21、正向扫描控制模块22和反向扫描控制模块23均位于显示区AA时，正向控制信号线U、反向控制信号线D和低电平信号线V可以均位于显示区AA，且正向控制信号线U、反向控制信号线D和低电平信号线V可以平行且间隔设置。另外，正向控制信号线U、反向控制信号线D和低电平信号线V可以同层设置。正向控制信号线U与多条扫描线G可以绝缘交叉设置，即正向控制信号线U与多条扫描线G不同层设置，且正向控制信号线U在扫描线G所在膜层上的正投影分别与多条扫描线G相交。反向控制信号线D与多条扫描线G可以绝缘交叉设置，即反向控制信号线D与多条扫描线G不同层设置，且反向控制信号线D在扫描线G所在膜层上的正投影分别与多条扫描线G相交。低电平信号线V与多条扫描线G可以绝缘交叉设置，即低电平信号线V与多条扫描线G不同层设置，且低电平信号线V在扫描线G所在膜层上的正投影分别与多条扫描线G相交。
在一些实施例中，正向控制信号线U、反向控制信号线D和低电平信号线V均沿第二方向B延伸，第二方向B可以与第一方向A相垂直。
在正向扫描多行子像素3的过程中，当第n行子像素3扫描完成时，第n+1条扫描线G（n+1）（即第n个正反扫下拉电路2（n）对应的第二扫描线）输入高电平的扫描信号，第n个正反扫下拉电路2（n）中的正向扫描控制模块22导通，此时反向扫描控制模块23处于关断状态，正向控制信号线U向第n个正反扫下拉电路2（n）中的正向扫描控制模块22传输高电平的正向控制信号，使得该正向扫描控制模块22向对应的下拉模块21传输高电平信号，以控制对应的下拉模块21将其对应的第一扫描线（即第n条扫描信线G（n））中的扫描信号下拉至低电平。
在反向扫描多行子像素3的过程中，当第n行子像素3扫描完成时，第n-1条扫描线G（n-1）（即第n个正反扫下拉电路2（n）对应的第三扫描线输入高电平的扫描信号），第n个正反扫下拉电路2（n）中的反向扫描控制模块23导通，此时正向扫描控制模块22处于关断状态，反向控制信号线D向第n个正反扫下拉电路2（n）中的反向扫描控制模块23传输高电平的反向控制信号，使得该反向扫描控制模块23向对应的下拉模块21传输高电平信号，以控制对应的下拉模块21将其对应的第一扫描线（即第n条扫描信号G（n）中的扫描信号）下拉至低电平。
如图2所示，在正向扫描控制模块22位于显示区AA时，第n个正反扫下拉电路2（n）中的正向扫描控制模块22可以靠近第n+1条扫描线G（n+1）和正向控制信号线U设置。具体地，第n个正反扫下拉电路2（n）中的正向扫描控制模块22可以设置在第n+1条扫描线G（n+1）和正向控制信号线U的交叉位置处，以缩短第n个正反扫下拉电路2（n）中的正向扫描控制模块22连接第n+1条扫描线G（n+1）和正向控制信号线U的连接线，减小信号传输时延。在反向扫描控制模块23位于显示区AA时，第n个正反扫下拉电路2（n）中的反向扫描控制模块23可以靠近所述第n-1条扫描线G（n-1）和反向控制信号线D设置。具体地，第n个正反扫下拉电路2（n）中的反向扫描控制模块23可以设置在第n-1条扫描线G（n-1）和反向控制信号线D的交叉位置处，以缩短第n个正反扫下拉电路2（n）中的反向扫描控制模块23连接第n-1条扫描线G（n-1）和反向控制信号线D的连接线，减小信号传输时延。另外，第n个正反扫下拉电路2（n）中的下拉模块21可以靠近第n条扫描线G（n）和低电平信号线V设置。具体地，第n个正反扫下拉电路2（n）中的下拉模块21可以设置在第n条扫描线G（n）和低电平信号线V的交叉位置处，以缩短第n个正反扫下拉电路2（n）中的下拉模块21连接第n条扫描线G（n）和低电平信号线V的连接线，减小信号传输时延。
由于下拉模块21分别与其对应的正向扫描控制模块22、反向扫描控制模块23连接，因此下拉模块21可以设置在其对应的正向扫描控制模块22与反向扫描控制模块23之间，以缩短下拉模块21与其对应的正向扫描控制模块22之间的第一连接线以及下拉模块21与其对应的反向扫描控制模块23之间的第二连接线，减小信号传输时延。第一连接线与第二连接线可以同层设置，第一连接线和第二连接线与扫描线G可以不同层设置，与正向控制信号线U、反向控制信号线D和低电平信号线V也可以不同层设置。由于下拉模块21需要与低电平信号线V连接，正向扫描控制模块22需要与正向控制信号线U连接，反向扫描控制模块23需要与反向控制信号线D连接，因此低电平信号线V可以设置在正向控制信号线U与反向控制信号线D之间，即反向控制信号线D、低电平信号线V和正向控制信号线U沿第一方向A依次排列。
显示面板还可以包括多条数据线data，多条数据线data位于显示区AA，且多条数据线data平行且间隔设置。数据线data的数量与子像素3的列数相同，即多条数据线data与多列子像素3一一对应连接。每条数据线data沿第二方向B延伸，且数据线data与扫描线G不同层设置，使得多条数据线data与多条扫描线G绝缘交叉限定出多个子像素3。
在下拉模块21、正向扫描控制模块22和反向扫描控制模块23均位于显示区AA时，数据线data可以与正向控制信号线U、反向控制信号线D和低电平信号线V同层设置，且数据线data可以与正向控制信号线U、反向控制信号线D和低电平信号线平行且间隔设置。每列数据线data的两侧具有间隙，正向控制信号线U、反向控制信号线D和低电平信号线V可以设置在数据线data两侧的间隙处。由于数据线data两侧的间隙较小，正向控制信号线U、反向控制信号线D和低电平信号线V可以分别设置在三条数据线data一侧的间隙处。在一些实施例中，所述反向控制信号线D、所述低电平信号线V和所述正向控制信号线U分别靠近相邻的三条数据线data设置，即所述反向控制信号线D、所述低电平信号线V和所述正向控制信号线U分别位于相邻三条数据线data的一侧，以缩短下拉模块21与正向扫描控制模块22、反向扫描控制模块23之间的连接线长度，减小信号时延。如图2所示，反向控制信号线D位于数据线data1的一侧，低电平信号线V位于数据线data2的一侧，正向控制信号线U位于数据线data3的一侧。
具体地，如图4所示，每个正反扫下拉电路2中的下拉模块21包括第一开关管NTC。所述第一开关管NTC的控制端（如栅极）分别连接对应的正向扫描控制模块22的输出端、对应的反向扫描控制模块23的输出端，所述第一开关管NTC的输入端（如漏极）接入低电平信号，即第一开关管NTC的输入端连接低电平信号线V，所述第一开关管NTC的输出端（如源极）连接对应的第一扫描线。
每个正反扫下拉电路2中的正向扫描控制模块22包括第二开关管NTB。所述第二开关管NTB的控制端（如栅极）连接对应的第二扫描线，所述第二开关管NTB的输出端（如漏极）连接所述第一开关管NTC的控制端，所述第二开关管NTB的输入端（如源极）接入正向控制信号，即第二开关管NTB的输入端连接正向控制信号线U。
每个正反扫下拉电路2中的反向扫描控制模块23包括第三开关管NTA。所述第三开关管NTA的控制端（如栅极）连接对应的第三扫描线，所述第三开关管NTA的输出端（如漏极）连接所述第一开关管NTC的控制端，所述第三开关管NTA的输入端（如源极）接入反向控制信号，即第三开关管NTA的输入端所述反向控制信号线D。
结合图5所示，在正向扫描多行子像素3的过程中，正向控制信号线U提供高电平信号VGH，反向控制信号线D提供低电平信号VGL。依次向第n-1条扫描线G(n-1)、第n条扫描线G(n)、第n+1条扫描线G(n+1)输入高电平的扫描信号，以便依次对第n-1行子像素3、第n行子像素、第n+1行子像素进行充电。具体地，在第n行子像素3完成充电后，第n+1条扫描线G（n+1）输入的扫描信号为高电平信号VGH，第二开关管NTB导通，由于正向控制信号线U提供高电平信号VGH，因此将节点GQ上拉至高电平，第一开关管NTC导通，而低电平信号线V提供低电平信号VGL，从而将第n条扫描线G（n）中的扫描信号由高电平下拉至低电平。
结合图6所示，在反向扫描多行子像素3的过程中，正向控制信号线U提供低电平信号VGL，反向控制信号线D提供高电平信号VGH。依次向第n+1条扫描线G(n+1)、第n条扫描线G(n)、第n-1条扫描线G(n-1)输入高电平的扫描信号，以便依次对第n+1行子像素3、第n行子像素、第n-1行子像素进行充电。具体地，当第n行子像素3充电完成时，第n-1条扫描线G（n-1）输入的扫描信号为高电平信号VGH，第三开关管NTA导通，由于反向控制信号线D提供高电平信号VGH，因此将节点GQ上拉至高电平，第一开关管NTC导通，而低电平信号线V提供低电平信号VGL，从而将第n条扫描线G（n）中的扫描信号由高电平下拉至低电平。
其中，节点GQ为第一开关管NTC、第二开关管NTB和第三开关管NTA的连接点，即第一开关管NTC的控制端连接节点GQ，第二开关管NTB的输出端连接节点GQ，第三开关管NTA的输出端连接节点GQ，使得第一开关管NTC的控制端分别与第二开关管NTB的输出端、第三开光管NTA的输出端连接。
其中，第一开关管NTC、第二开关管NTB和第三开光管NTA可以为LTPS（Low Temperature Poly-silicon，低温多晶硅）晶体管、a_Si（非晶硅）晶体管、IGZO (indium gallium zinc oxide，氧化铟镓锌)晶体管、OLED或LTPS&IGZO等杂化晶体管。
如图7所示，显示面板还包括位于显示区AA的多行像素电路5。像素电路5的行数可以与扫描线G的条数相同，且多行像素电路5与多条扫描线G一一对应连接。像素电路5的行数可以等于正反扫下拉电路2的个数，也可以大于正反扫下拉电路2的个数。在正反扫下拉电路2的个数为N时，多行像素电路5包括与N个正反扫下拉电路2一一对应设置的N行像素电路5。N个正反扫下拉电路2中的下拉模块21的输出端还与N行像素电路5的扫描信号输入端一一对应连接。
如图8所示，第n个正反扫下拉电路2（n）中的下拉模块21的输出端还与第n行像素电路5（n）的扫描信号输入端连接。具体地，第n个正反扫下拉电路2（n）中的第一开关管NTC的输出端（如源极）还与第n行像素电路5（n）的扫描信号输入端连接。
如图7所示，显示面板还包括位于非显示区NA的栅极驱动电路4，栅极驱动电路4包括多个级联的栅极驱动单元41。栅极驱动单元41的个数可以与扫描线G的条数相同，且多个级联的栅极驱动单元41与多条扫描线G一一对应连接，多个级联的栅极驱动单元41与多行子像素3一一对应连接。在扫描每行子像素3时，通过该行子像素3对应的栅极驱动单元41和该行子像素3对应的扫描线G向该行子像素3输入扫描信号。其中，栅极驱动电路4可以为单边驱动，也可以为双边驱动，此处不做具体限定。
多个栅极驱动单元41的个数可以等于正反扫下拉电路2的个数，也可以大于正反扫下拉电路2的个数。在正反扫下拉电路2的个数为N时，多个栅极驱动单元41包括与N个正反扫下拉电路2一一对应设置的N个栅极驱动单元41。具体地，每个正反扫下拉电路2中的正向扫描控制模块22的控制端与下一级栅极驱动单元41的扫描信号输出端连接，所述下一级栅极驱动单元41为正反扫下拉电路2对应的栅极驱动单元41的下一级栅极驱动单元41；所述正反扫下拉电路2中的反向扫描控制模块23的控制端与上一级栅极驱动单元41的扫描信号输出端连接，所述上一级栅极驱动单元41为所述正反扫下拉电路2对应的栅极驱动单元41的上一级栅极驱动单元41。
如图8所示，第n个正反扫下拉电路2（n）中的正向扫描控制模块22的控制端与第n+1级栅极驱动单元41（n+1）的扫描信号输出端连接，第n个正反扫下拉电路2（n）中的反向扫描控制模块23的控制端与第n-1级栅极驱动单元41（n-1）的扫描信号输出端连接。具体地，第n个正反扫下拉电路2（n）中的第二开关管NTB的控制端（如栅极）与第n+1级栅极驱动单元41（n+1）的扫描信号输出端连接，第n个正反扫下拉电路2（n）中的第三开关管NTA的控制端（如栅极）与第n-1级栅极驱动单元41（n-1）的扫描信号输出端连接。
在一行子像素3完成扫描后，若通过位于非显示区NA的栅极驱动电路4将该行子像素3对应的扫描线G中的扫描信号Gate下拉至低电平，由于扫描线G较长，栅极驱动电路4输出的低电平信号在扫描线G上传输的时延较大，导致扫描信号Gate的下拉时延较大。结合图1和图9a所示，边缘区域AA1和AA3处的扫描信号Gate的下拉时延均较大，而中间区域AA2处的扫描信号Gate的下拉时延比边缘区域AA1和AA3处的扫描信号Gate的下拉时延更大。
本发明实施例在显示面板中增加正反扫下拉电路2，以在一行子像素3完成扫描后，通过正反扫下拉电路2中的下拉模块21将该行子像素3对应的扫描线G中的扫描信号Gate下拉至低电平。由于下拉模块21位于显示区AA，缩短下拉模块21输出的低电平信号在扫描线G中的传输时延，减小扫描线G中扫描信号Gate的下拉时延。结合图1和图9b所示，中间区域AA2、边缘区域AA1和AA3中的扫描信号Gate的下拉时延均得以减小。
若扫描信号Gate的下拉时延较大，为了防止错充，相邻两行子像素3输入的高电平时序信号之间需要预留一个时间间隔。如图10a所示，一行子像素3所需的充电时长为T2（如14us），相邻两个高电平时序信号之间（如CK1的高电平与CK2的高电平之间，CK2的高电平与CK3的高电平之间）的时间间隔为t（如2us），使得输入至一行子像素3的高电平时序信号（如CK1的高电平、CK2的高电平、CK3的高电平）的持续时长缩短为T1（如12us），T2=T1+t。而高电平时序信号的持续时长减小，导致一行子像素3的实际充电时长减小，即一行子像素3的实际充电时长小于其所需的充电时长。另外，在向一行子像素3输入高电平时序信号期间，依次向该行子像素中的子像素输入高电平复用信号（如MUX1的高电平、MUX2的高电平、MUX3的高电平），以给子像素3充电。由于高电平时序信号的持续时长减小，使得分配给每个高电平复用信号的持续时长减小，导致子像素的充电时长减小。
若扫描信号Gate的下拉时延得以有效降低，则相邻两行子像素3输入的高电平时序信号之间预留的时间间隔减小，甚至无需预留时间间隔。如图10b所示，相邻两个高电平时序信号之间（如CK1的高电平与CK2的高电平之间，CK2的高电平与CK3的高电平之间）无时间间隔，使得输入至一行子像素3的高电平时序信号（如CK1的高电平、CK2的高电平、CK3的高电平）的持续时长为T2，即一行子像素3的实际充电时长为T2，有效提高一行子像素3的实际充电时长。而高电平时序信号的持续时长的增加，使得分配给每个高电平复用信号（如MUX1的高电平、MUX2的高电平、MUX3的高电平）的持续时长增加，有效提高子像素的充电时长，进而实现高频显示。
综上，本申请实施例通过设置正反扫下拉电路，且正反扫下拉电路中的下拉模块位于显示区，使得下拉模块和扫描线连接在显示区，以在一行子像素充电完成时，减少扫描线中扫描信号的下拉时延（由高电平变为低电平的时延），及时将该行子像素对应的扫描线中的扫描信号下拉至低电平，降低错充风险，改善显示均一性，且实现正反扫下拉，结构简单。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (18)

  1. 一种显示面板，其中，包括显示区，所述显示面板包括：
    多条扫描线，位于所述显示区；
    多个正反扫下拉电路，每个所述正反扫下拉电路包括下拉模块、正向扫描控制模块和反向扫描控制模块；
    其中，所述多条扫描线包括与所述正反扫下拉电路相对应的第一扫描线，所述下拉模块位于所述显示区，且所述下拉模块的控制端分别与所述正向扫描控制模块的输出端、所述反向扫描控制模块的输出端连接，所述下拉模块的输出端与对应的第一扫描线连接。
  2. 如权利要求1所述的显示面板，其中，所述正向扫描控制模块位于所述显示区。
  3. 如权利要求1所述的显示面板，其中，所述反向扫描控制模块位于所述显示区。
  4. 如权利要求1所述的显示面板，其中，所述下拉模块包括第一开关管；
    所述第一开关管的控制端分别连接所述正向扫描控制模块的输出端、所述反向扫描控制模块的输出端，所述第一开关管的输入端接入低电平信号，所述第一开关管的输出端连接所述对应的第一扫描线。
  5. 如权利要求4所述的显示面板，其中，所述多条扫描线包括与所述正反扫下拉电路相对应的第二扫描线，所述正向扫描控制模块包括第二开关管；
    所述第二开关管的控制端连接对应的第二扫描线，所述第二开关管的输出端连接所述第一开关管的控制端，所述第二开关管的输入端接入正向控制信号。
  6. 如权利要求5所述的显示面板，其中，所述多条扫描线包括与所述正反扫下拉电路相对应的第三扫描线，所述反向扫描控制模块包括第三开关管；
    所述第三开关管的控制端连接对应的第三扫描线，所述第三开关管的输出端连接所述第一开关管的控制端，所述第三开关管的输入端接入反向控制信号。
  7. 如权利要求6所述的显示面板，其中，所述正反扫下拉电路对应的第三扫描线、第一扫描线和第二扫描线依次相邻设置。
  8. 如权利要求1所述的显示面板，其中，所述显示面板还包括：
    低电平信号线，位于所述显示区，且所述低电平信号线与所述下拉模块的输入端连接。
  9. 如权利要求1所述的显示面板，其中，所述显示面板还包括：
    多行像素电路，与多个所述正反扫下拉电路一一对应设置；
    所述正反扫下拉电路中的下拉模块的输出端还与对应的像素电路的扫描信号输入端连接。
  10. 如权利要求1所述的显示面板，其中，所述显示面板还包括位于所述显示区外的非显示区，所述显示面板还包括：
    栅极驱动电路，包括多个级联的栅极驱动单元，位于所述非显示区；
    多个所述栅极驱动单元与多个所述正反扫下拉电路一一对应设置，所述正反扫下拉电路中的正向扫描控制模块的控制端与下一级栅极驱动单元的扫描信号输出端连接，所述下一级栅极驱动单元为所述正反扫下拉电路对应的栅极驱动单元的下一级栅极驱动单元；所述正反扫下拉电路中的反向扫描控制模块的控制端与上一级栅极驱动单元的扫描信号输出端连接，所述上一级栅极驱动单元为所述正反扫下拉电路对应的栅极驱动单元的上一级栅极驱动单元。
  11. 如权利要求1所述的显示面板，其中，所述下拉模块的输出端与所述对应的第一扫描线的连接点位于所述对应的第一扫描线的中间位置。
  12. 如权利要求2所述的显示面板，其中，所述反向扫描控制模块位于所述显示区。
  13. 如权利要求4所述的显示面板，其中，所述第一开关管为晶体管。
  14. 如权利要求13所述的显示面板，其中，所述第一开关管的控制端为所述晶体管的栅极，所述第一开关管的输入端为所述晶体管的漏极，所述第一开关管的输出端为所述晶体管的源极。
  15. 如权利要求5所述的显示面板，其中，所述第二开关管为晶体管。
  16. 如权利要求15所述的显示面板，其中，所述第二开关管的控制端为所述晶体管的栅极，所述第二开关管的输入端为所述晶体管的漏极，所述第二开关管的输出端为所述晶体管的源极。
  17. 如权利要求6所述的显示面板，其中，所述第三开关管均为晶体管。
  18. 如权利要求17所述的显示面板，其中，所述第三开关管的控制端为所述晶体管的栅极，所述第三开关管的输入端为所述晶体管的漏极，所述第三开关管的输出端为所述晶体管的源极。
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