WO2024093965A1 - 芯片及其制造、封装方法 - Google Patents

芯片及其制造、封装方法 Download PDF

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Publication number
WO2024093965A1
WO2024093965A1 PCT/CN2023/128156 CN2023128156W WO2024093965A1 WO 2024093965 A1 WO2024093965 A1 WO 2024093965A1 CN 2023128156 W CN2023128156 W CN 2023128156W WO 2024093965 A1 WO2024093965 A1 WO 2024093965A1
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Prior art keywords
die
chip
function
packaging process
interposer
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PCT/CN2023/128156
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English (en)
French (fr)
Inventor
韩中毅
张楠赓
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上海嘉楠捷思信息技术有限公司
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Publication of WO2024093965A1 publication Critical patent/WO2024093965A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N

Definitions

  • the present invention belongs to the field of packaging, and in particular relates to a chip and a manufacturing and packaging method thereof.
  • chip manufacturing is usually achieved using only one process and one package.
  • the most advanced process node is usually selected to achieve the purpose of reducing power consumption in order to pursue process dividends.
  • not all functions on a chip need to be implemented using the most advanced process.
  • the present invention provides the following solutions.
  • a chip comprising: a substrate layer, an interposer layer arranged above the substrate layer, and a first bare chip arranged above the interposer layer, which is manufactured based on a first process technology matching the function of the first bare chip.
  • a second die disposed above the interposer, which is made based on a second process technology that matches the function of the second die; wherein the second die and the first die are interconnected through the interposer.
  • the first die is manufactured based on a first packaging process that matches the function of the first die; and the second die is manufactured based on a second packaging process that matches the function of the second die.
  • the first die is configured as a die for performing a computing function.
  • the second die is configured as a die for performing auxiliary functions.
  • the second die includes one or more of the following: a control function die for performing chip control; a test function die for performing chip testing; an interface function die for providing an I/O interface.
  • the process technology matching the bare chip function is positively correlated with the first performance requirement of the bare chip function; the first performance requirement includes at least one of the following: rate requirement, power consumption requirement, and bandwidth requirement.
  • the packaging process that matches the bare die function is positively correlated with the second performance requirement of the bare die function; the second performance requirement includes at least one of the following: rate requirement, bandwidth requirement.
  • the first die is stacked on the interposer based on a first packaging process; the second die is tiled on the interposer based on a second packaging process.
  • the intermediate layer includes a main body portion arranged on the upper side of the substrate layer and a branch portion arranged along the stacking direction of the multiple bare chips; the at least one first bare chip stack is arranged on the upper side of the main body portion, and each of the at least one first bare chip extends laterally to be connected to the branch portion.
  • the interposer is an inverted T-shaped interposer.
  • the first packaging process is a 3D packaging process or an advanced packaging process that exceeds the 3D packaging process
  • the second packaging process is a 2.5D packaging process.
  • a chip manufacturing method including: generating an intermediate layer above a substrate layer; generating a first bare die above the intermediate layer, the first bare die being manufactured based on a first process technology matching its function; generating a second bare die above the intermediate layer, the second bare die being manufactured based on a second process technology matching its function; and interconnecting the second bare die and the first bare die through the intermediate layer.
  • the first die is packaged based on a first packaging process that matches the function of the first die; and the second die is packaged based on a second packaging process that matches the function of the second die.
  • the first die is configured as a die for performing a computing function.
  • the second die is configured as a die for performing auxiliary functions.
  • the second die includes one or more of the following: a control function die for performing chip control; a test function die for performing chip testing; an interface function die for providing an I/O interface.
  • the process technology matching the bare chip function is positively correlated with the first performance requirement of the bare chip function; the first performance requirement includes at least one of the following: rate requirement, power consumption requirement, and bandwidth requirement.
  • the packaging process that matches the bare die function is positively correlated with the second performance requirement of the bare die function; the second performance requirement includes at least one of the following: rate requirement, bandwidth requirement.
  • the method further includes: stacking the generated first die on the interposer based on a first packaging process, and tiling the second die on the interposer based on a second packaging process.
  • the intermediate layer includes a main body portion arranged on the upper side of the substrate layer and a branch portion arranged along the stacking direction of the multiple bare chips; the at least one first bare chip stack is arranged on the upper side of the main body portion, and each of the at least one first bare chip extends laterally to be connected to the branch portion.
  • the interposer is an inverted T-shaped interposer.
  • the first packaging process is a 3D packaging process or an advanced packaging process that exceeds the 3D packaging process
  • the second packaging process is a 2.5D packaging process.
  • a chip hybrid packaging method including: dividing a chip into multiple blocks according to function, determining a corresponding process technology according to a first computing requirement of each block; using different process technologies to respectively manufacture multiple blocks into multiple bare chips; determining a packaging process for the bare chips corresponding to each block at least according to the second computing requirement of each block; and reorganizing and interconnecting multiple bare chips using different packaging processes.
  • the plurality of blocks include: a computing block for performing integrated computing, and a functional block for performing auxiliary functions.
  • the method further includes: when the operation block includes multiple operation cores, the operation block is further divided into chips to obtain multiple operation sub-blocks corresponding to the multiple operation cores respectively.
  • the functional block includes one or more of the following: a control block for performing chip control; a test block for performing chip testing; and an interface block for providing an I/O interface.
  • the first computing requirement includes: one or more of a rate requirement, a power consumption requirement, and a bandwidth requirement of each block.
  • the second computing requirement includes: a rate requirement and/or a bandwidth requirement of each block.
  • determining the packaging process of the die corresponding to each block further includes: determining the packaging process of each die according to the size of each die and/or the packaging complexity of reorganizing and interconnecting multiple die.
  • it also includes: using a first packaging process to stack multiple bare chips corresponding to multiple first blocks on the upper side of the interposer; using a second packaging process to lay one or more bare chips corresponding to one or more second blocks on the upper side of the interposer; and realizing interconnection between the bare chips through the interposer connected to the substrate layer.
  • the first packaging process is a 3D packaging process and/or an advanced packaging process exceeding the 3D packaging process
  • the second packaging process is a 2.5D packaging process.
  • it also includes: using a special-shaped interposer, the special-shaped interposer having a main body portion arranged on the upper side of the substrate layer and a branch portion arranged along the stacking direction of multiple bare chips; multiple bare chips corresponding to the first block are stacked and arranged on the upper side of the main body portion, and the bare chips are laterally extended to connect to the branch portion.
  • the special-shaped interposer is an inverted T-shaped interposer.
  • the chip is a high computing power chip.
  • a hybrid packaged chip comprising: a chip manufactured using the method of the second or third aspect.
  • a hybrid packaged chip comprising: a substrate layer, an intermediate layer arranged above the substrate layer, and a plurality of bare dies arranged above the intermediate layer; wherein the plurality of bare dies have different process technologies, and the plurality of bare dies are reorganized and interconnected to the top of the intermediate layer using different packaging technologies.
  • the multiple bare dies correspond to multiple blocks divided by function in the chip, the multiple bare dies have different process technologies according to the first computing requirements of the corresponding blocks, and the multiple bare dies are reorganized and interconnected to the top of the intermediate layer using different packaging processes according to the second computing requirements of the corresponding blocks.
  • the method further includes: determining a process technology of each bare chip according to one or more of a rate requirement, a power consumption requirement, and a bandwidth requirement of a corresponding block of each bare chip.
  • the method further includes: determining the packaging process of each die according to one or more of the rate requirement and/or bandwidth requirement of the block corresponding to each die, the size of each die, and the packaging complexity of the reorganized interconnection.
  • the plurality of blocks include: a computing block for performing integrated computing and a functional block for performing auxiliary functions.
  • the computing block further includes: when the computing block includes multiple computing cores, the computing block is further divided into chips to obtain multiple computing sub-blocks corresponding to the multiple computing cores respectively.
  • the functional block includes one or more of the following: a control block for performing chip control; a test block for performing chip testing; and an interface block for providing an I/O interface.
  • multiple bare chips are reorganized and interconnected to the top of the interposer using different packaging processes, which also includes: using a first packaging process to stack multiple bare chips on the upper side of the interposer; and/or using a second packaging process to lay one or more bare chips on the upper side of the interposer; and realizing interconnection between the bare chips through the interposer connected to the substrate layer.
  • the first packaging process is a 3D packaging process and/or an advanced packaging process exceeding the 3D packaging process
  • the second packaging process is a 2.5D packaging process.
  • it also includes: using a special-shaped interposer, the special-shaped interposer having a main body portion arranged on the upper side of the substrate layer and a branch portion arranged along the stacking direction of the multiple bare chips; the multiple bare chips are stacked on the upper side of the main body portion, and each of the multiple bare chips is laterally extended to connect to the branch portion.
  • the special-shaped interposer is an inverted T-shaped interposer.
  • the chip is a high computing power chip.
  • One of the advantages of the above implementation is that by dividing a large single chip into smaller dies, and then integrating multiple homogeneous or heterogeneous dies into the same design through improved advanced packaging, the dies corresponding to different blocks use more suitable process technology and packaging technology, and each uses a more efficient way to interconnect dies (die)-die (die), thereby improving the computing power of the chip, and the chip achieves a compromise and optimization of bandwidth density, delay, power consumption, and cost to realize chip manufacturing and fully enjoy the advantages of bandwidth density, power consumption and cost reduction. It can prevent the size of the die from continuing to increase.
  • FIG1 is a schematic diagram of a chip structure according to an embodiment of the present invention.
  • FIG2 is a schematic diagram of a chip structure according to another embodiment of the present invention.
  • FIG3 is a schematic diagram of a chip structure according to another embodiment of the present invention.
  • FIG. 4 is a schematic flow chart of a chip manufacturing method according to an embodiment of the present invention.
  • FIG5 is a schematic diagram of a process of a chip hybrid packaging method according to an embodiment of the present invention.
  • FIG6 is a schematic structural diagram of a hybrid package chip according to an embodiment of the present invention.
  • FIG7 is a schematic structural diagram of a hybrid package chip according to an embodiment of the present invention.
  • FIG8 is a schematic structural diagram of a hybrid package chip according to an embodiment of the present invention.
  • FIG9 is a schematic structural diagram of a hybrid package chip according to an embodiment of the present invention.
  • FIG10 is a schematic structural diagram of a hybrid package chip according to an embodiment of the present invention.
  • A/B can mean A or B.
  • the “and/or” in this article is merely a way to describe the association relationship of associated objects, indicating that three relationships can exist.
  • a and/or B can mean: A exists alone, A and B exist at the same time, and B exists alone.
  • first”, “second”, etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as “first”, “second”, etc. may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, unless otherwise specified, "plurality" means two or more.
  • Chiplet It is a model in which multiple module chips are packaged together with the underlying basic chip through the die-to-die internal interconnection technology to form a multifunctional heterogeneous system-in-package (SiPs) chip.
  • SiPs system-in-package
  • Packaging It is the process of assembling integrated circuits into final chip products.
  • TSV Through Silicon Vias
  • Interposer is a silicon substrate layer made of silicon and organic materials. It connects the upper and lower layers through through-silicon vias (TSVs) and is then soldered to the traditional 2D packaging substrate layer through solder balls. It is a conduit for multi-chip modules in advanced packaging to transmit electrical signals.
  • TSVs through-silicon vias
  • an embodiment of the present invention provides a chip, the chip comprising:
  • a first die is disposed above the interposer and is manufactured based on a first process technology that matches the function of the first die;
  • the second bare chip is arranged above the intermediate layer and is manufactured based on a second process technology matching the function of the second bare chip; wherein the second bare chip and the first bare chip are interconnected through the intermediate layer.
  • the manufacturing process corresponding to each die may be proportional to its functional requirements, that is, the higher the functional requirements, the more advanced the manufacturing process adopted.
  • the functional requirements may include requirements in multiple dimensions such as bandwidth, rate, power consumption, etc.
  • the function of the first die is large-scale integrated computing, which has high requirements for interconnection bandwidth, speed, power consumption, etc.
  • a more advanced process technology can be selected for manufacturing, such as TSMC's 5nm process, and further, stdcell such as ELVT can be used to make the chip faster and consume less power.
  • the functional design of the second die has no speed requirements relative to the first die, but the overall chip power consumption needs to be considered, so a slightly lower process technology, such as TSMC 7nm, can be used to achieve it.
  • a more stable and mature process technology can also be selected, such as Samsung 14nm and SMIC 12nm.
  • a plurality of bare dies corresponding to a plurality of process technologies may be arranged on the chip, and is not limited to two bare dies. This embodiment is described by taking the first bare die and the second bare die as examples.
  • a chip comprising:
  • a first die is disposed above the interposer and is manufactured based on a first process technology that matches the function of the first die;
  • a second die is disposed above the interposer and is manufactured based on a second process technology that matches the function of the second die; wherein the second die and the first die are interconnected through the interposer;
  • the first bare die is manufactured based on a first packaging process that matches its function; and the second bare die is manufactured based on a second packaging process that matches its function.
  • a 2.5D packaging process can be used to package bare chips with lower computing requirements to save costs
  • a 3D packaging process or a more advanced advanced packaging process for example, 4D packaging, 5D packaging
  • 4D packaging, 5D packaging can be used to package other bare chips with higher computing requirements to achieve better technical effects.
  • the embodiment of the present application does not impose any specific limitation on the packaging process used for the first bare die and the second bare die, and any differentiated packaging process may be used for packaging as long as the chip packaging requirements can be met.
  • a chip comprising:
  • a first die is disposed above the interposer and is manufactured based on a first process technology that matches the function of the first die;
  • a second die is disposed above the interposer and is manufactured based on a second process technology that matches the function of the second die; wherein the second die and the first die are interconnected through the interposer;
  • the first die is configured as a die for performing a computing function. It can be understood that the requirements for computing functions are relatively high, and it is convenient to migrate the die corresponding to the computing function to an advanced process and an advanced packaging process.
  • the second die is configured as a die for performing auxiliary functions. It is understood that the requirements for the auxiliary functions are relatively low, which can facilitate maintaining a relatively conservative process and packaging process for the functions of the corresponding die to save costs and improve yield.
  • a chip comprising:
  • a first die is disposed above the interposer and is manufactured based on a first process technology that matches the function of the first die;
  • a second die is disposed above the interposer and is manufactured based on a second process technology that matches the function of the second die; wherein the second die and the first die are interconnected through the interposer;
  • the second die is configured as a die for performing auxiliary functions. It is understood that the requirements for the auxiliary functions are relatively low, which can facilitate maintaining the functions of the corresponding die in a relatively conservative process and packaging process to save costs and improve yield.
  • a chip comprising:
  • a first die is disposed above the interposer and is manufactured based on a first process technology that matches the function of the first die;
  • a second die is disposed above the interposer and is manufactured based on a second process technology that matches the function of the second die; wherein the second die and the first die are interconnected through the interposer;
  • the second die includes one or more of the following: a control die for executing chip control; a test die for executing chip testing; an interface die for providing an I/O interface. It can be understood that the control die, test die, and interface die are all functional chips with relatively low computing function requirements, and can adopt a more conservative process and packaging technology without affecting the actual use effect.
  • control function die, test function die and interface function die in the second die can also adopt differentiated process technology and packaging technology based on different computing requirements.
  • the design of the control function die has no speed requirements relative to the computing block, but the overall chip power consumption needs to be considered, so a relatively moderate process technology can be adopted.
  • the computing requirements of the test function die and the interface function die are relatively lower, so a more stable and mature process technology can be selected.
  • a chip comprising:
  • a first die is disposed above the interposer and is manufactured based on a first process technology that matches the function of the first die;
  • a second die is disposed above the interposer and is manufactured based on a second process technology that matches the function of the second die; wherein the second die and the first die are interconnected through the interposer;
  • the first die is manufactured based on a first packaging process that matches its function; the second die is manufactured based on a second packaging process that matches its function; the first die is configured as a die for performing a computing function. It can be understood that the requirements for computing functions are relatively high, and it is convenient to migrate the die corresponding to the computing function to advanced processes and advanced packaging processes.
  • a chip comprising:
  • a first die is disposed above the interposer and is manufactured based on a first process technology that matches the function of the first die;
  • a second die is disposed above the interposer and is manufactured based on a second process technology that matches the function of the second die; wherein the second die and the first die are interconnected through the interposer;
  • the first die is made based on a first packaging process that matches its function; the second die is made based on a second packaging process that matches its function; the first die is configured as a die for performing a computing function; the second die is configured as a die for performing an auxiliary function.
  • the requirements for computing functions are relatively high, which can facilitate the migration of the die corresponding to the computing function to advanced processes and advanced packaging processes, while the requirements for auxiliary functions are relatively low, which can facilitate the maintenance of the functions of the corresponding die in a relatively conservative process and packaging process to save costs and improve yield.
  • the process technology that matches the bare chip function is positively correlated with the first performance requirement of the bare chip function; the first performance requirement includes one or more of the speed requirement, power consumption requirement, and bandwidth requirement. It is understood that different process technologies usually meet different degrees of computing speed, power consumption, and bandwidth requirements, and this embodiment does not specifically limit this.
  • the packaging process that matches the bare chip function is positively correlated with the second performance requirement of the bare chip function; the second performance requirement includes at least one of the following: rate requirement, bandwidth requirement.
  • rate requirement includes at least one of the following: bandwidth requirement, bandwidth requirement.
  • Different packaging processes usually meet different degrees of computing rate, power consumption and bandwidth requirements, and this embodiment does not specifically limit this.
  • the first die is stacked and arranged on the interposer based on a first packaging process; and the second die is tiled and arranged on the interposer based on a second packaging process.
  • Figure 2 shows a hybrid packaging form, where multiple first bare chips are packaged by stacking in a 3D packaging form, and high-speed interconnection between the first bare chips is achieved through silicon vias (TSV); then the second bare chip is interconnected with the first bare chip through an interposer.
  • the interposer is connected to the substrate layer (Substrate) through bumps, and finally a 2.5D+3D hybrid packaging is achieved.
  • the interposer is a silicon substrate layer made of silicon and organic materials.
  • the upper and lower layers are connected through silicon vias (TSV), and then soldered to the traditional 2D packaging substrate layer through solder balls. It is a multi-core chip in advanced packaging.
  • the chip module is a pipeline for transmitting electrical signals.
  • TSV Through silicon via
  • 2.5D packaging solutions that is, copper is filled in the wafer to provide vertical interconnection through the silicon wafer bare chip, and the shortest path is used to electrically connect one side of the silicon chip to the other side.
  • hybrid packaging technology can be used to achieve high-density packaging of the first bare chip and the second bare chip.
  • the interposer includes a main body disposed on the upper side of the substrate layer and a branch portion disposed along the stacking direction of the plurality of dies; at least one first die is stacked on the upper side of the main body, and each of the at least one first die is laterally extended to connect to the branch portion.
  • the interposer may be an inverted T-shaped interposer.
  • the interposer can be designed as a special-shaped interposer in this embodiment, such as an inverted T-shaped interposer.
  • the height of the vertical part of the heterogeneous interposer can be set to be consistent with the height of the 3D package, and then the clock signal is connected to the interposer through the protrusion (Macrobumps) by extending the pins (pins) horizontally.
  • TSV silicon vias
  • the first packaging process is a 3D packaging process or an advanced packaging process exceeding the 3D packaging process
  • the second packaging process is a 2.5D packaging process.
  • the embodiments of the present disclosure also provide a chip manufacturing method, which is specifically the chip manufacturing method described in the above embodiments.
  • method 40 shows a flow chart of a chip manufacturing method according to an embodiment of the present disclosure. It should be understood that method 40 may also include additional blocks not shown and/or may omit the blocks shown, and the scope of the present disclosure is not limited in this respect.
  • Step 410 generating an interposer layer above the substrate layer
  • Step 420 generating a first die on the interposer, wherein the first die is manufactured based on a first process technology matching its function;
  • Step 430 generating a second die on the interposer, where the second die is manufactured based on a second process technology matching its function;
  • Step 440 interconnecting the second die and the first die through the interposer.
  • the first die before step 420, is packaged using a first packaging process that matches the function of the first die; and before step 430, the second die is packaged using a second packaging process that matches the function of the second die.
  • the first die is configured as a die for performing a computing function. It is understood that the higher the computing requirements, the higher the requirements for multiple dimensions such as bandwidth, rate, power consumption, etc. Therefore, a die for performing a computing function usually requires a higher level of process technology or packaging technology.
  • the second die is configured as a die for performing auxiliary functions. It is understood that any function that does not require high-intensity computing can be regarded as the auxiliary function.
  • the second die includes one or more of the following: a control function die for performing chip control; a test function die for performing chip testing; an interface function die for providing an I/O interface.
  • the process technology matching the bare chip function is positively correlated with the first performance requirement of the bare chip function; the first performance requirement includes at least one of the following: rate requirement, power consumption requirement, and bandwidth requirement.
  • the packaging process that matches the bare die function is positively correlated with the second performance requirement of the bare die function; the second performance requirement includes at least one of the following: rate requirement and bandwidth requirement.
  • the step 420 further includes: generating a first die by stacking on the interposer based on a first packaging process; and the step 430 further includes: tiling a second die on the interposer based on a second packaging process.
  • the intermediate layer includes a main body portion arranged on the upper side of the substrate layer and a branch portion arranged along the stacking direction of multiple bare chips; at least one first bare chip stack is arranged on the upper side of the main body portion, and each of the at least one first bare chip extends laterally to connect to the branch portion.
  • the interposer is an inverted T-shaped interposer.
  • the first packaging process is a 3D packaging process or an advanced packaging process exceeding the 3D packaging process
  • the second packaging process is a 2.5D packaging process.
  • chip manufacturing method in the embodiment of the present application achieves the same effects and functions as the aforementioned chip, and will not be repeated here.
  • FIG. 5 shows a flow chart for performing a chip hybrid packaging method according to an embodiment of the present disclosure. It should be understood that the method 50 may further include additional blocks not shown and/or may omit the blocks shown, and the scope of the present disclosure is not limited in this respect.
  • Step 510 dividing the chip into multiple blocks according to functions
  • the chip blocks can be divided according to function. By dividing the blocks responsible for different functions, it is convenient to migrate the core functional blocks of the chip to advanced processes, while the auxiliary blocks maintain the original more conservative process nodes.
  • the designed complete chip can be divided into different partitions such as operation block, control block, interface block, test block, etc., which are responsible for different chip functions.
  • This embodiment does not specifically limit the function and number of the divided blocks.
  • Step 520 determining a corresponding process technology according to the first computing requirement of each block
  • the process technology corresponding to each block can be proportional to its first computing requirement, that is, the higher the first computing requirement, the more advanced the process technology used.
  • the first computing requirement can include computing requirements in multiple dimensions such as bandwidth, rate, power consumption, etc.
  • the process technologies matched by the first computing requirements in different dimensions are also different.
  • the process technology used can be comprehensively considered based on the first computing requirements in these dimensions.
  • Step 530 Use different process technologies to manufacture multiple blocks into multiple bare chips respectively;
  • each block can be independently designed and manufactured for its own small chip.
  • existing functional chip IPs can be reused without designing dedicated functional chip IPs in the entire chip.
  • the computing block is responsible for large-scale integrated computing, and thus has very high requirements for interconnection bandwidth, speed, power consumption, etc.
  • a more advanced process technology can be chosen for manufacturing, such as TSMC's 5nm process, and further, stdcells such as ELVT can be used to make the chip faster and consume less power.
  • the design of the control block has no speed requirements relative to the computing block, but the overall chip power consumption needs to be considered, so a slightly lower process technology, such as TSMC 7nm, can be used to implement it.
  • the computing requirements of the interface block and the test block are relatively lower, so a more stable and mature process technology can be selected, such as Samsung 14nm and SMIC 12nm.
  • Step 540 Determine a packaging process of a die corresponding to each block at least according to the second computing requirement of each block;
  • Step 550 Re-interconnect multiple dies using different packaging processes.
  • the present embodiment adopts a hybrid packaging form, which can fully utilize the advantages of different packaging processes and adaptively adopt a packaging process suitable for each bare chip, thereby greatly improving the yield.
  • a 2.5D packaging process can be used to package a die with lower computing requirements to save costs
  • a 3D packaging process or a more advanced advanced packaging process e.g., 4D packaging, 5D packaging
  • 4D packaging, 5D packaging can be used to package other dies with higher computing requirements to achieve better technical effects.
  • the use of a hybrid packaging form can make full use of the different advantages of each package.
  • the present application embodiment does not specifically limit the packaging process used for each die, and any differentiated packaging process can be used for packaging as long as the chip packaging requirements can be met.
  • the dies corresponding to different blocks use more suitable process technology and packaging technology, and each uses a more efficient way to interconnect dies (die)-die (die), thereby improving the computing power of the chip, and the chip achieves a compromise and optimization of bandwidth density, delay, power consumption, and cost to realize chip manufacturing.
  • die die-die
  • the plurality of blocks may include: a computing block for performing integrated computing and a functional block for performing auxiliary functions.
  • the chip as a whole is divided into computing blocks with relatively high computing requirements and functional blocks with relatively low computing requirements, which can facilitate the migration of the computing blocks of the chip to advanced processes and advanced packaging processes, while the functional blocks maintain relatively conservative processes and packaging processes to save costs and improve yields.
  • the computing block in order to achieve the packaging effect of a computing block with higher computing requirements, when the computing block includes multiple computing cores, the computing block can be further divided into chips to obtain multiple computing sub-blocks corresponding to the multiple computing cores.
  • the computing core dies corresponding to the equivalent computing sub-blocks can be packaged in a stacked manner, saving space and better matching the bandwidth density, latency, and power consumption requirements of the computing block.
  • the functional block includes one or more of the following: a control block for performing chip control; a test block for performing chip testing; and an interface block for providing an I/O interface.
  • the various blocks in the above functional blocks can also adopt differentiated process technologies based on their respective first computing requirements, and differentiated packaging technologies based on their respective second computing requirements.
  • the design of the control block has no speed requirements relative to the computing block, but the overall chip power consumption needs to be considered, so a relatively moderate process technology can be adopted.
  • the computing requirements of the interface block and the test block are relatively lower, so a more stable and mature process technology can be selected.
  • the existing block design chip can be reused, which can effectively save costs and speed up time.
  • the first computing requirement includes: one or more of the rate requirement, power consumption requirement, and bandwidth requirement of each block.
  • Different process technologies usually meet different degrees of computing rate, power consumption, and bandwidth requirements, and this embodiment does not specifically limit this.
  • the second computing requirement includes: a rate requirement and/or a bandwidth requirement of each block.
  • Different packaging processes usually meet computing rate and bandwidth requirements to different degrees, and this embodiment does not impose any specific limitation on this.
  • the packaging process of each die may be determined according to the size of each die and/or the packaging complexity of reorganizing and interconnecting multiple dies. In addition to considering the computing requirements of the corresponding blocks, we can also consider the size of each die and the overall packaging complexity of the chip.
  • 3D packaging can be selected and implemented through TSV.
  • the bare chips corresponding to the remaining control blocks, test blocks, and interface blocks considering the packaging complexity and the area of the overall chip (too large an area will affect the PCB and the product), 2.5D packaging can be selected, and finally the two types of small chips of the above packaging types can be interconnected on the substrate layer through an interposer.
  • a first packaging process may be used to stack multiple bare chips corresponding to multiple first blocks on the upper side of the interposer; and a second packaging process may be used to lay one or more bare chips corresponding to one or more second blocks on the upper side of the interposer; finally, the bare chips may be interconnected through the interposer connected to the substrate layer.
  • the first packaging process is a 3D packaging process and/or an advanced packaging process that exceeds the 3D packaging process
  • the second packaging process is a 2.5D packaging process.
  • FIG8 shows a hybrid packaging form, where multiple core dies (CORE Die) are stacked and packaged in a 3D packaging form, and high-speed interconnection between the core dies (CORE Die) is achieved through through-silicon vias (TSV); then the control die (TOP Die) is interconnected with the core die (CORE Die) through an interposer.
  • the interposer is connected to the substrate layer (Substrate) through bumps, and finally a 2.5D+3D hybrid packaging is achieved.
  • the interposer is a silicon substrate layer made of silicon and organic materials. It connects the upper and lower layers through through silicon vias (TSVs) and is then soldered to the traditional 2D packaging substrate layer through solder balls.
  • TSVs Through silicon vias
  • FIG9 shows another hybrid packaging form, where multiple core dies (CORE Die) are stacked in 3D to realize different columns (Slice), and then multiple core dies (CORE Die) are stacked in 3D packaging and interconnected through silicon vias (TSV), and then different columns (Slice) are connected to the interposer through bumps.
  • the control die (TOP Die) is connected to the substrate layer (Substrate) through the interposer in the form of 2.5D packaging. Therefore, through the hybrid packaging solution, we can enjoy the advantages of 3D packaging in terms of area and the packaging cost advantages of 2.5D packaging.
  • a special-shaped interposer may be used, which has a main body arranged on the upper side of the substrate layer and a branch portion arranged along the stacking direction of the plurality of dies; the plurality of dies corresponding to the first block are stacked on the upper side of the main body, and the dies are laterally extended and connected to the branch portion.
  • the special-shaped interposer may be formed as an inverted T-shaped interposer.
  • the interposer can be designed as a special-shaped interposer in this embodiment, such as an inverted T-shaped interposer.
  • the height of the vertical part of the special interposer can be set to be consistent with the height of the 3D package.
  • the clock signal is connected to the interposer through the protrusions (Macrobumps) by extending the pins (pins) horizontally.
  • Macrobumps protrusions
  • pins pins
  • TSV silicon vias
  • the chip is a high computing power chip.
  • an embodiment of the present invention further provides a hybrid packaged chip, which is a chip manufactured using the packaging method described in the above embodiment.
  • the embodiment of the present invention further provides a hybrid package chip.
  • the hybrid package chip includes: a substrate layer, an interposer layer disposed above the substrate layer, and a plurality of Bare chips; wherein the plurality of bare chips have different process technologies, and the plurality of bare chips are reorganized and interconnected to the top of the intermediate layer using different packaging processes.
  • the multiple bare dies correspond to multiple blocks divided by function in the chip, the multiple bare dies have different process technologies according to the first computing requirements of the corresponding blocks, and the multiple bare dies are reorganized and interconnected to the top of the intermediate layer using different packaging processes according to the second computing requirements of the corresponding blocks.
  • the process technology corresponding to each block can be proportional to its first computing requirement, that is, the higher the first computing requirement, the more advanced the process technology used.
  • the first computing requirement may include computing requirements in multiple dimensions such as bandwidth, rate, and power consumption.
  • the process technologies matched by the first computing requirements of different dimensions are also different.
  • the process technology used can be comprehensively considered based on the first computing requirements of these dimensions.
  • the packaging technology corresponding to each block can be proportional to its second computing requirement, that is, the higher the second computing requirement, the more advanced the packaging technology used.
  • the second computing requirement may include computing requirements in multiple dimensions such as bandwidth, rate, and so on.
  • the process technology of each die may be determined based on one or more of the rate requirement, power consumption requirement, and bandwidth requirement of the corresponding block of each die.
  • the packaging process of each die may be determined based on one or more of the rate requirement and/or bandwidth requirement of the corresponding block of each die, the size of each die, and the packaging complexity of the reorganized interconnect.
  • the plurality of blocks include: a computing block for performing integrated computing and a functional block for performing auxiliary functions. Dividing the entire chip into computing blocks with relatively high computing requirements and functional blocks with relatively low computing requirements can facilitate the migration of the computing blocks of the chip to advanced processes and advanced packaging processes, while the functional blocks maintain relatively conservative processes and packaging processes to save costs and improve yields.
  • the computing block further includes: when the computing block includes multiple computing cores, the computing block is further chip-divided to obtain multiple computing sub-blocks corresponding to the multiple computing cores.
  • the computing core dies corresponding to the computing sub-blocks can be packaged in a stacked manner, saving space and better matching the bandwidth density, latency, and power consumption requirements of the computing block.
  • the functional block includes one or more of the following: a control block for performing chip control; a test block for performing chip testing; and an interface block for providing an I/O interface.
  • the various blocks in the above functional blocks can also adopt differentiated process technologies based on their respective first computing requirements, and differentiated packaging technologies based on their respective second computing requirements.
  • the design of the control block has no speed requirements relative to the computing block, but the overall chip power consumption needs to be considered, so a relatively moderate process technology can be adopted.
  • the computing requirements of the interface block and the test block are relatively lower, so a more stable and mature process technology can be selected.
  • the existing block design chip can be reused, which can effectively save costs and speed up time.
  • multiple bare chips are reorganized and interconnected to the top of the interposer using different packaging processes, which also includes: using a first packaging process to stack multiple bare chips on the upper side of the interposer; and/or using a second packaging process to lay one or more bare chips on the upper side of the interposer; and realizing interconnection between the bare chips through the interposer connected to the substrate layer.
  • the first packaging process is a 3D packaging process and/or an advanced packaging process that exceeds the 3D packaging process
  • the second packaging process is a 2.5D packaging process.
  • a special-shaped interposer may also be used, which has a main body portion arranged on the upper side of the substrate layer and a branch portion arranged along the stacking direction of the multiple bare chips; the multiple bare chips are stacked on the upper side of the main body portion, and each of the multiple bare chips extends laterally to connect to the branch portion.
  • the special-shaped interposer may be an inverted T-shaped interposer.
  • the chip is a high computing power chip.
  • hybrid packaged chip in the embodiment of the present application achieves the same effects and functions as the aforementioned method, which will not be repeated here.

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Abstract

本发明提供了一种芯片及其制造、封装方法，该芯片包括：基板层，设置在基板层上方的中介层，还包括：第一裸片，设置在中介层上方，其基于与第一裸片的功能相匹配的第一制程工艺制成；第二裸片，设置在中介层上方，其基于与第二裸片的功能相匹配的第二制程工艺制成；其中，所述第二裸片和所述第一裸片通过所述中介层互联。该种芯片能够在实现芯片效果的前提下降低成本、提高良率。

Description

芯片及其制造、封装方法
本申请要求于2022年10月31日提交的、申请号为202211365836.2、标题为“芯片封装方法及芯片”的中国专利申请的优先权，以及要求2023年9月22日提交的、申请号为202311234978.X、标题为“芯片及其制造、封装方法”的中国专利申请的优先权，该等中国专利申请的公开内容以引用的方式并入本文。
技术领域
本发明属于封装领域，具体涉及一种芯片及其制造、封装方法。
背景技术
本部分旨在为权利要求书中陈述的本发明的实施方式提供背景或上下文。此处的描述不因为包括在本部分中就承认是现有技术。
现有芯片的技术方案中，芯片制造通常只采用一种工艺和一种封装来实现。针对高算力芯片设计，由于计算密集度很高，功耗相应也很高，那么通常为了追求工艺红利会选择最先进的工艺节点实现，以达到降低功耗的目的。但其实对于一个芯片上的所有功能并非都需要选用最先进工艺实现。
随着先进工艺的成本大幅提升，芯片的制造成本也在递增。随着工艺推进，晶体管成本下降速率急剧降低，芯片面积递增也带来了芯片良率的下降。
因此，如何实现芯片效果、成本和良率的平衡是一个亟待解决的问题。
发明内容
针对上述现有技术中存在的问题，提出了一种芯片混合封装方法及混合封装芯片，利用这种方法、装置及计算机可读存储介质，能够解决上述问题。
本发明提供了以下方案。
第一方面，提供一种芯片，芯片包括：基板层，设置在基板层上方的中介层，还包括：第一裸片，设置在所述中介层上方，其基于与所述第一裸片的功能相匹配的第一制程工艺制 成；第二裸片，设置在所述中介层上方，其基于与所述第二裸片的功能相匹配的第二制程工艺制成；其中，所述第二裸片和所述第一裸片通过所述中介层互联。
在一种实施方式中，所述第一裸片，基于与所述第一裸片的功能相匹配的第一封装工艺制成；所述第二裸片，基于与所述第二裸片的功能相匹配的第二封装工艺制成。
在一种实施方式中，所述第一裸片被配置为：用于执行运算功能的裸片。
在一种实施方式中，所述第二裸片被配置为：用于执行辅助功能的裸片。
在一种实施方式中，所述第二裸片包括以下中的一种或多种：用于执行芯片控制的控制功能裸片；用于执行芯片测试的测试功能裸片；用于提供I/O接口的接口功能裸片。
在一种实施方式中，与裸片功能相匹配的制程工艺与所述裸片功能的第一性能需求正相关；所述第一性能需求包括以下至少一种：速率需求、功耗需求、带宽需求。
在一种实施方式中，与裸片功能相匹配的封装工艺与所述裸片功能的第二性能需求正相关；所述第二性能需求包括以下至少一种：速率需求、带宽需求。
在一种实施方式中，所述第一裸片，其基于第一封装工艺堆叠设置在中介层上；所述第二裸片，其基于第二封装工艺平铺设置在所述中介层上。
在一种实施方式中，所述中介层包括设置在基板层上侧的主体部和沿所述多个裸片的堆叠方向设置的分支部；所述至少一个第一裸片堆叠设置在主体部的上侧，且所述至少一个第一裸片中的每一者横向延伸连接至所述分支部。
在一种实施方式中，所述中介层为倒T型中介层。
在一种实施方式中，所述第一封装工艺为3D封装工艺或超过3D封装工艺的先进封装工艺，所述第二封装工艺为2.5D封装工艺。
第二方面，提供一种芯片制造方法，包括：在基板层上方生成中介层；在所述中介层上方生成第一裸片，所述第一裸片基于与其功能相匹配的第一制程工艺制成；在所述中介层上方生成第二裸片，所述第二裸片基于与其功能相匹配的第二制程工艺制成；通过所述中介层将所述第二裸片和所述第一裸片互联。
在一种实施方式中，所述第一裸片，基于与所述第一裸片的功能相匹配的第一封装工艺封装制成；所述第二裸片，基于与所述第二裸片的功能相匹配的第二封装工艺封装制成。
在一种实施方式中，所述第一裸片被配置为：用于执行运算功能的裸片。
在一种实施方式中，所述第二裸片被配置为：用于执行辅助功能的裸片。
在一种实施方式中，所述第二裸片包括以下中的一种或多种：用于执行芯片控制的控制功能裸片；用于执行芯片测试的测试功能裸片；用于提供I/O接口的接口功能裸片。
在一种实施方式中，与裸片功能相匹配的制程工艺与所述裸片功能的第一性能需求正相关；所述第一性能需求包括以下至少一种：速率需求、功耗需求、带宽需求。
在一种实施方式中，与裸片功能相匹配的封装工艺与所述裸片功能的第二性能需求正相关；所述第二性能需求包括以下至少一种：速率需求、带宽需求。
在一种实施方式中，还包括：在所述中介层上方，基于第一封装工艺堆叠设置所述生成第一裸片，在所述中介层上方，其基于第二封装工艺平铺设置所述第二裸片。
在一种实施方式中，所述中介层包括设置在基板层上侧的主体部和沿所述多个裸片的堆叠方向设置的分支部；所述至少一个第一裸片堆叠设置在主体部的上侧，且所述至少一个第一裸片中的每一者横向延伸连接至所述分支部。
在一种实施方式中，所述中介层为倒T型中介层。
在一种实施方式中，所述第一封装工艺为3D封装工艺或超过3D封装工艺的先进封装工艺，所述第二封装工艺为2.5D封装工艺。第三方面，提供一种芯片混合封装方法，包括：按照功能将芯片划分为多个区块，根据各个区块的第一运算需求确定对应的制程工艺；使用不同的制程工艺分别将多个区块对应制成多个裸片；至少根据各个区块的第二运算需求，确定各个区块对应的裸片的封装工艺；使用不同的封装工艺将多个裸片重组互联。
在一种实施方式中，多个区块，包括：用于执行集成运算的运算区块，以及用于执行辅助功能的功能区块。
在一种实施方式中，还包括：在运算区块包括多个运算核的情况下，对运算区块再次进行芯片划分，得到分别对应于多个运算核的多个运算子区块。
在一种实施方式中，功能区块包括以下中的一种或多种：用于执行芯片控制的控制区块；用于执行芯片测试的测试区块；用于提供I/O接口的接口区块。
在一种实施方式中，第一运算需求包括：各个区块的速率需求、功耗需求、带宽需求中的一种或多种。
在一种实施方式中，第二运算需求包括：各个区块的速率需求和/或带宽需求。
在一种实施方式中，确定各个区块对应的裸片的封装工艺，还包括：还根据各个裸片的尺寸和/或对多个裸片进行重组互联的封装复杂度，确定各个裸片的封装工艺。
在一种实施方式中，还包括：采用第一封装工艺，将多个第一区块对应的多个裸片堆叠设置在中介层的上侧；采用第二封装工艺，将一个或多个第二区块对应的一个或多个裸片平铺设置在中介层的上侧；通过连接至基板层的中介层，实现裸片之间的互联。
在一种实施方式中，第一封装工艺为3D封装工艺和/或超过3D封装工艺的先进封装工艺，第二封装工艺为2.5D封装工艺。
在一种实施方式中，还包括：采用异型中介层，异型中介层具有设置在基板层上侧的主体部和沿多个裸片的堆叠方向设置的分支部；第一区块对应的多个裸片堆叠设置在主体部的上侧，且裸片横向延伸连接至分支部。
在一种实施方式中，异型中介层为倒T型中介层。
在一种实施方式中，芯片为高算力芯片。
第四方面，提供一种混合封装芯片，包括：利用第二或第三方面的方法制造出的芯片。
第五方面，提供一种混合封装芯片，包括：基板层，设置在基板层上方的中介层，以及设置在中介层上方的多个裸片；其中，多个裸片具有不同的制程工艺，且多个裸片采用不同的封装工艺重组互联至中介层的上方。
在一种实施方式中，多个裸片分别对应于芯片中按功能划分的多个区块，多个裸片根据对应区块的第一运算需求具有不同的制程工艺，且多个裸片根据对应区块的第二运算需求采用不同的封装工艺重组互联至中介层的上方。
在一种实施方式中，还包括：根据各个裸片的对应区块的速率需求、功耗需求、带宽需求中的一种或多种，确定各个裸片的制程工艺。
在一种实施方式中，还包括：根据各个裸片对应区块的速率需求和/或带宽需求、各个裸片的尺寸、重组互联的封装复杂度中的一种或多种，确定各个裸片的封装工艺。
在一种实施方式中，多个区块，包括：用于执行集成运算的运算区块和用于执行辅助功能的功能区块。
在一种实施方式中，运算区块，还包括：在运算区块包括多个运算核的情况下，对运算区块再次进行芯片划分，得到分别对应于多个运算核的多个运算子区块。
在一种实施方式中，功能区块包括以下中的一种或多种：用于执行芯片控制的控制区块；用于执行芯片测试的测试区块；用于提供I/O接口的接口区块。
在一种实施方式中，多个裸片采用不同的封装工艺重组互联至中介层的上方还包括：采用第一封装工艺，将多个裸片堆叠设置在中介层的上侧；和/或，采用第二封装工艺，将一个或多个裸片平铺设置在中介层的上侧；通过连接至基板层的中介层，实现裸片之间的互联。
在一种实施方式中，第一封装工艺为3D封装工艺和/或超过3D封装工艺的先进封装工艺，第二封装工艺为2.5D封装工艺。
在一种实施方式中，还包括：采用异型中介层，异型中介层具有设置在基板层上侧的主体部和沿多个裸片的堆叠方向设置的分支部；多个裸片堆叠设置在主体部的上侧，且多个裸片中的每一者横向延伸连接至分支部。
在一种实施方式中，异型中介层为倒T型中介层，
在一种实施方式中，芯片为高算力芯片。
上述实施方式的优点之一，通过将大型单体芯片分为较小的裸片，然后将多个同质或者异质的裸片，通过改进的先进封装形式整合到同一个设计中，让不同区块对应的裸片使用更为适合的制程工艺和封装工艺，各自采用更为高效的方式进行裸片(Die)-裸片(Die)互连，从而提高芯片的计算能力，芯片达到带宽密度、延时、功耗、成本多方面的折中和最优化，来实现芯片制造，充分享受带宽密度、功耗以及成本变小的优势。可以避免裸片的尺寸继续增大。
本发明的其他优点将配合以下的说明和附图进行更详细的解说。
应当理解，上述说明仅是本发明技术方案的概述，以便能够更清楚地了解本发明的技术手段，从而可依照说明书的内容予以实施。为了让本发明的上述和其它目的、特征和优点能够更明显易懂，以下特举例说明本发明的具体实施方式。
附图说明
通过阅读下文的示例性实施方式的详细描述，本领域普通技术人员将明白本文的优点和益处以及其他优点和益处。附图仅用于示出示例性实施方式的目的，而并不认为是对本发明的限制。而且在整个附图中，用相同的标号表示相同的部件。在附图中：
图1为根据本发明一实施方式的芯片结构示意图；
图2为根据本发明另一实施方式的芯片结构示意图；
图3为根据本发明又一实施方式的芯片结构示意图；
图4为根据本发明一实施方式的芯片制造方法的流程示意图。
图5为根据本发明一实施方式的芯片混合封装方法的流程示意图；
图6为根据本发明一实施方式的混合封装芯片的结构示意图；
图7为根据本发明一实施方式的混合封装芯片的结构示意图；
图8为根据本发明一实施方式的混合封装芯片的结构示意图；
图9为根据本发明一实施方式的混合封装芯片的结构示意图；
图10为根据本发明一实施方式的混合封装芯片的结构示意图；
在附图中，相同或对应的标号表示相同或对应的部分。
具体实施方式
下面将参照附图更详细地描述本公开的示例性实施方式。虽然附图中显示了本公开的示例性实施方式，然而应当理解，可以以各种形式实现本公开而不应被这里阐述的实施方式所限制。相反，提供这些实施方式是为了能够更透彻地理解本公开，并且能够将本公开的范围完整的传达给本领域的技术人员。
在本申请实施方式的描述中，应理解，诸如“包括”或“具有”等术语旨在指示本说明书中所公开的特征、数字、步骤、行为、部件、部分或其组合的存在，并且不旨在排除一个或多个其他特征、数字、步骤、行为、部件、部分或其组合存在的可能性。
除非另有说明，“/”表示或的意思，例如，A/B可以表示A或B；本文中的“和/或”仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。
术语“第一”、“第二”等仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”等的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请实施方式的描述中，除非另有说明，“多个”的含义是两个或两个以上。
为清楚阐述本申请实施方式，首先将介绍一些后续实施方式中可能会出现的概念。
芯粒(Chiplet)：是通过裸片-裸片内部互联技术将多个模块芯片与底层基础芯片封装在一起，构成多功能的异构***级封装(System in Packages，SiPs)芯片的模式。
封装(Package)：是把集成电路装配为芯片最终产品的过程。
硅通孔(Through Silicon Vias，简称TSV)，是一种通过整个芯片厚度的电子连接，它可以创建从芯片一侧到另一侧的最短路径。
中介层(Interposer)，是一种由硅和有机材料制成的硅基板层，通过硅通孔(TSV)联系上下层，再通过锡球焊接至传统2D的封装基板层上，是先进封装中多芯片模块传递电信号的管道。
参考图1，本发明实施方式提供一种芯片，该芯片包括：
基板层，设置在基板层上方的中介层；
第一裸片，设置在中介层上方，其基于与第一裸片的功能相匹配的第一制程工艺制成；
第二裸片，设置在中介层上方，其基于与第二裸片的功能相匹配的第二制程工艺制成；其中，第二裸片和第一裸片通过中介层互联。
具体地，每个裸片对应的制程工艺可以与其功能需求成正比，即，功能需求越高，采用的制程工艺越先进。该功能需求可以包括诸如带宽、速率、功耗等多种维度的需求。
例如，参考图1，假设该第一裸片的功能为大规模集成运算，进而对互联的带宽、速率、功耗等都具有很高的要求。在这种情况下，可以选择采用更为先进的制程工艺来制造，例如TSMC的5nm工艺，进一步还可以采用例如ELVT等的stdcell使芯片的速率更快功耗更低。该第二裸片的功能设计相对第一裸片没有速率方面的要求，但需要考虑整体芯片功耗，因此可以采用稍低的制程工艺，例如TSMC 7nm来实现。也可以选择更为稳定成熟的制程工艺，例如三星14nm和SMIC 12nm等实现。
可以理解，芯片上可以设置对应于多种制程工艺的多个裸片，并不仅限于两种裸片。本实施例仅以第一裸片和第二裸片为例进行陈述。
本实施例中，通过将大型芯片分为较小的裸片，然后将多个同质或者异质的裸片整合到同一个设计中，让负责不同功能的不同裸片使用更为适合的制程工艺，各自采用更为高效的方式进行裸片(Die)-裸片(Die)互连，从而提高芯片的计算能力，芯片达到带宽密度、延时、功耗、成本多方面的折中和最优化。充分享受带宽密度、功耗以及成本变小的优势。可以避免裸片的尺寸继续增大。
在一种实施方式中提供一种芯片，该芯片包括：
基板层，设置在基板层上方的中介层；
第一裸片，设置在中介层上方，其基于与第一裸片的功能相匹配的第一制程工艺制成；
第二裸片，设置在中介层上方，其基于与第二裸片的功能相匹配的第二制程工艺制成；其中，第二裸片和第一裸片通过中介层互联；
其中，第一裸片基于与其功能相匹配的第一封装工艺制成；第二裸片基于与其功能相匹配的第二封装工艺制成。
例如，可以采用2.5D封装工艺对运算需求较低的裸片进行封装，以节省成本，并采用3D封装工艺或者更先进的先进封装工艺(例如，4D封装、5D封装)对运算需求较高的其他裸片进行封装，以实现更优的技术效果，采用混合封装的形式，可以充分利用各自封装的不同优势。
本申请实施例对第一裸片和第二裸片采用的封装工艺不作具体限制，可以采用任何差异化的封装工艺进行封装，只要能满足芯片封装要求即可。
在一种实施方式中提供一种芯片，该芯片包括：
基板层，设置在基板层上方的中介层；
第一裸片，设置在中介层上方，其基于与第一裸片的功能相匹配的第一制程工艺制成；
第二裸片，设置在中介层上方，其基于与第二裸片的功能相匹配的第二制程工艺制成；其中，第二裸片和第一裸片通过中介层互联；
其中，第一裸片被配置为：用于执行运算功能的裸片。可以理解，运算功能的要求相对较高，能够便于将对应运算功能的裸片向先进制程及先进封装工艺进行迁移。
在上述实施方式中，第二裸片被配置为：用于执行辅助功能的裸片。可以理解，辅助功能的要求相对较低，能够便于将对应裸片的功能维持较为保守的制程及封装工艺，以节省成本，并提高良率。
在一种实施方式中提供一种芯片，该芯片包括：
基板层，设置在基板层上方的中介层；
第一裸片，设置在中介层上方，其基于与第一裸片的功能相匹配的第一制程工艺制成；
第二裸片，设置在中介层上方，其基于与第二裸片的功能相匹配的第二制程工艺制成；其中，第二裸片和第一裸片通过中介层互联；
其中，第二裸片被配置为：用于执行辅助功能的裸片。可以理解，辅助功能的要求相对较低，能够便于将对应裸片的功能维持较为保守的制程及封装工艺，以节省成本，并提高良率。
在一种实施方式中提供一种芯片，该芯片包括：
基板层，设置在基板层上方的中介层；
第一裸片，设置在中介层上方，其基于与第一裸片的功能相匹配的第一制程工艺制成；
第二裸片，设置在中介层上方，其基于与第二裸片的功能相匹配的第二制程工艺制成；其中，第二裸片和第一裸片通过中介层互联；
其中，第二裸片包括以下中的一种或多种：用于执行芯片控制的控制功能裸片；用于执行芯片测试的测试功能裸片；用于提供I/O接口的接口功能裸片。可以理解，该等控制功能裸片、测试功能裸片、接口功能裸片都是对于运算功能要求相对较低的功能芯片，可以采用较为保守的制程及封装工艺，而不影响实际使用效果。
可选地，第二裸片中的控制功能裸片、测试功能裸片和接口功能裸片也可以基于不同的运算需求采用区别化的制程工艺和封装工艺。例如，该控制功能裸片的设计相对运算区块没有速率方面的要求，但需要考虑整体芯片功耗，因此可以采用相对适中的制程工艺。与之相对的，测试功能裸片和接口功能裸片的运算需求相对更低，因此可以选择更为稳定成熟的制程工艺。
在一种实施方式中提供一种芯片，该芯片包括：
基板层，设置在基板层上方的中介层；
第一裸片，设置在中介层上方，其基于与第一裸片的功能相匹配的第一制程工艺制成；
第二裸片，设置在中介层上方，其基于与第二裸片的功能相匹配的第二制程工艺制成；其中，第二裸片和第一裸片通过中介层互联；
其中，第一裸片基于与其功能相匹配的第一封装工艺制成；第二裸片基于与其功能相匹配的第二封装工艺制成；第一裸片被配置为：用于执行运算功能的裸片。可以理解，运算功能的要求相对较高，能够便于将对应运算功能的裸片向先进制程及先进封装工艺进行迁移。
在一种实施方式中提供一种芯片，该芯片包括：
基板层，设置在基板层上方的中介层；
第一裸片，设置在中介层上方，其基于与第一裸片的功能相匹配的第一制程工艺制成；
第二裸片，设置在中介层上方，其基于与第二裸片的功能相匹配的第二制程工艺制成；其中，第二裸片和第一裸片通过中介层互联；
其中，第一裸片基于与其功能相匹配的第一封装工艺制成；第二裸片基于与其功能相匹配的第二封装工艺制成；第一裸片被配置为：用于执行运算功能的裸片；第二裸片被配置为：用于执行辅助功能的裸片。可以理解，运算功能的要求相对较高，能够便于将对应运算功能的裸片向先进制程及先进封装工艺进行迁移，辅助功能的要求相对较低，能够便于将对应裸片的功能维持较为保守的制程及封装工艺，以节省成本，并提高良率。
在一种实施方式中(包括但不限于前述任一实施方式)，与裸片功能相匹配的制程工艺与裸片功能的第一性能需求正相关；第一性能需求包括速率需求、功耗需求、带宽需求中的一种或多种。可以理解，不同的制程工艺通常会满足不同程度的运算速率、功耗及带宽需求，本实施例对此不作具体限制。
在一种实施方式中(包括但不限于前述任一实施方式)，与裸片功能相匹配的封装工艺与裸片功能的第二性能需求正相关；第二性能需求包括以下至少一种：速率需求、带宽需求。不同的封装工艺通常会满足不同程度的运算速率、功耗及带宽需求，本实施例对此不作具体限制。
在一种实施方式中(包括但不限于前述任一实施方式)，第一裸片基于第一封装工艺堆叠设置在中介层上；第二裸片基于第二封装工艺平铺设置在中介层上。
例如，图2示出一种混合封装形式，多个第一裸片通过3D封装形式堆叠进行封装，通过硅通孔(TSV)实现第一裸片之间的高速互联；然后第二裸片通过中介层(Interposer)和第一裸片之间实现互联。中介层(Interposer)通过凸块连接到基板层(Substrate)上，最终实现2.5D+3D的混合封装。中介层(Interposer)是一种由硅和有机材料制成的硅基板层，通过硅通孔(TSV)联系上下层，再通过锡球焊接至传统2D的封装基板层上，是先进封装中多芯 片模块传递电信号的管道，可以实现芯片间的互连，也可以实现与封装基板层的互连，充当多颗裸片和电路板之间的桥梁硅通孔(TSV)是2.5D封装解决方案的关键实现技术，即在晶圆中填充铜，提供贯通硅晶圆裸片的垂直互连，用最短路径将硅片一侧和另一侧进行电气连通。如此，可以采用混合封装技术实现第一裸片和第二裸片的高密度封装。
在一种实施方式中，参考图3，中介层包括设置在基板层上侧的主体部和沿多个裸片的堆叠方向设置的分支部；至少一个第一裸片堆叠设置在主体部的上侧，且至少一个第一裸片中的每一者横向延伸连接至分支部。如此，提供了一种更具创新性的混合封装方案，由于每个第一裸片到中介层的路线长度一致，其能够保证更高的时钟信号准确度。
具体地，中介层可以是倒T型中介层。
例如，以时钟信号举例，如果第一裸片是通过TSV之间互联逐级传递，势必会对信号质量传输造成损失，而且需要在第一裸片的出口位置加很多大驱动能力的CELL。基于此，参考图3，本实施例可以将中介层(Interposer)设计为异型中介层，比如设计为倒T型，该异性中介层的竖立部分高度可以设定为和3D封装高度一致，然后时钟信号通过横向延伸出管脚(pin)的方式通过凸起(Macrobumps)连接到中介层(Interposer)，中介层(Interposer)内部只有传输线，如此时钟等重要信号的传递的线损就会降到最低，能减小信号延迟，降低电容/电感，实现芯片间的低功耗，高速通讯，增加宽带。而第一裸片之间其他信号还可以通过硅通孔(TSV)来传递。
在一种实施方式中，第一封装工艺为3D封装工艺或超过3D封装工艺的先进封装工艺，第二封装工艺为2.5D封装工艺。
基于相同或相似的发明构思，本公开实施例还提供一种芯片制造方法，该芯片制造方法具体为上述实施例所述芯片的制造方法。
图4示出了根据本公开的实施方式的芯片制造方法的流程图。应当理解的是，方法40还可以包括未示出的附加框和/或可以省略所示出的框，本公开的范围在此方面不受限制。
步骤410，在基板层上方生成中介层；
步骤420，在中介层上方生成第一裸片，第一裸片基于与其功能相匹配的第一制程工艺制成；
步骤430，在中介层上方生成第二裸片，第二裸片基于与其功能相匹配的第二制程工艺制成；
步骤440，通过中介层将第二裸片和第一裸片互联。
在一种实施方式中，上述步骤420之前，还包括基于与第一裸片的功能相匹配的第一封装工艺封装制成该第一裸片；以及，上述步骤430之前，基于与第二裸片的功能相匹配的第二封装工艺封装制成第二裸片。
具体地，第一裸片被配置为：用于执行运算功能的裸片。可以理解，运算需求越高，诸如带宽、速率、功耗等多种维度的需求也会随之升高。因此，用于执行运算功能的螺片通常会要求更高级别的制程工艺或封装工艺。
具体地，第二裸片被配置为：用于执行辅助功能的裸片。可以理解，任何无需执行高强度运算的功能可以看作是该辅助功能。例如，第二裸片包括以下中的一种或多种：用于执行芯片控制的控制功能裸片；用于执行芯片测试的测试功能裸片；用于提供I/O接口的接口功能裸片。
在一种实施方式中，与裸片功能相匹配的制程工艺与裸片功能的第一性能需求正相关；第一性能需求包括以下至少一种：速率需求、功耗需求、带宽需求。
在一种实施方式中，与裸片功能相匹配的封装工艺与裸片功能的第二性能需求正相关；第二性能需求包括以下至少一种：速率需求、带宽需求。
在一种实施方式中，上述步骤420进一步包括：在中介层上方，基于第一封装工艺堆叠设置生成第一裸片；上述步骤430进一步包括：在中介层上方，基于第二封装工艺平铺设置第二裸片。
在一种实施方式中，中介层包括设置在基板层上侧的主体部和沿多个裸片的堆叠方向设置的分支部；至少一个第一裸片堆叠设置在主体部的上侧，且至少一个第一裸片中的每一者横向延伸连接至分支部。
在一种实施方式中，中介层为倒T型中介层。
在一种实施方式中，第一封装工艺为3D封装工艺或超过3D封装工艺的先进封装工艺，第二封装工艺为2.5D封装工艺。
需要说明的是，本申请实施方式中的芯片制造方法和前述芯片达到相同的效果和功能，这里不再赘述。
图5示出了根据本公开的实施方式的用于执行芯片混合封装方法的流程图。应当理解的是，方法50还可以包括未示出的附加框和/或可以省略所示出的框，本公开的范围在此方面不受限制。
步骤510、按照功能将芯片划分为多个区块；
具体地，在芯片设计阶段，可以按功能完成芯片区块的划分，通过将负责不同功能的区块分块，便于将芯片的核心功能区块向先进工艺进行迁移，而辅助区块维持原有较为保守的工艺节点。
例如，参考图5，可以将设计好的完整芯片划分为运算区块、控制区块、接口区块、测试区块等不同的分区，其分别负责不同芯片功能。本实施例对划分的区块功能和数量不作具体限定。
步骤520、根据各个区块的第一运算需求确定对应的制程工艺；
具体地，每个区块对应的制程工艺可以与其第一运算需求成正比，即，第一运算需求越高，采用的制程工艺越先进。该第一运算需求可以包括诸如带宽、速率、功耗等多种维度的运算需求，不同维度的第一运算需求所匹配的制程工艺也不同，可以基于该等维度的第一运算需求综合考虑所采用的制程工艺。
步骤530、使用不同的制程工艺分别将多个区块对应制成多个裸片；
具体地，完成上述区块划分和制程工艺选择后，可以就各个区块独立进行各自的小芯片设计和制造。可选地，针对芯片中的通用区块，比如接口区块和测试区块，可以复用现有的功能芯片IP，而无需在芯片整体中设计专门的功能芯片IP。
例如，参考图6，假设该运算区块负责大规模集成运算，进而对互联的带宽、速率、功耗等都具有很高的要求。在这种情况下，可以选择采用更为先进的制程工艺来制造，例如TSMC的5nm工艺，进一步还可以采用例如ELVT等的stdcell使芯片的速率更快功耗更低。该控制区块的设计相对运算区块没有速率方面的要求，但需要考虑整体芯片功耗，因此可以采用稍低的制程工艺，例如TSMC 7nm来实现。接口区块和测试区块的运算需求相对更低，因此可以选择更为稳定成熟的制程工艺，例如三星14nm和SMIC 12nm等实现。
步骤540、至少根据各个区块的第二运算需求，确定各个区块对应的裸片的封装工艺；
步骤550、使用不同的封装工艺将多个裸片重组互联。
具体地，本实施例采用混合封装形式，可以充分利用不同封装工艺的优点，自适应的采用适合每个裸片的封装工艺，使得良率大大提高。
例如，参考图7，可以采用2.5D封装工艺对运算需求较低的裸片进行封装，以节省成本，并采用3D封装工艺或者更先进的先进封装工艺(例如，4D封装、5D封装)对运算需求较高的其他裸片进行封装，以实现更优的技术效果，采用混合封装的形式，可以充分利用各自封装的不同优势。本申请实施例对各个裸片采用的封装工艺不作具体限制，可以采用任何差异化的封装工艺进行封装，只要能满足芯片封装要求即可。
本实施例中，通过将大型芯片分为较小的裸片，然后将多个同质或者异质的裸片，通过改进的先进封装形式整合到同一个设计中，让不同区块对应的裸片使用更为适合的制程工艺和封装工艺，各自采用更为高效的方式进行裸片(Die)-裸片(Die)互连，从而提高芯片的计算能力，芯片达到带宽密度、延时、功耗、成本多方面的折中和最优化，来实现芯片制造。充分享受带宽密度、功耗以及成本变小的优势。可以避免裸片的尺寸继续增大。
在一种实施方式中，上述多个区块可以包括：用于执行集成运算的运算区块和用于执行辅助功能的功能区块。本实施例中，将芯片整体划分为运算需求相对较高的运算区块，和运算需求相对较低的功能区块，能够便于将芯片的运算区块向先进制程及先进封装工艺进行迁移，而功能区块则维持较为保守的制程及封装工艺，以节省成本提高良率。
在一种实施方式中，为了实现运算需求较高的运算区块的封装效果，在运算区块包括多个运算核的情况下，可以对运算区块再次进行芯片划分，得到分别对应于多个运算核的多个运算子区块。由此，可以以堆叠方式对等运算子区块对应的运算核裸片进行封装，节省空间且更加匹配该运算区块的带宽密度、延时、功耗需求。
在一种实施方式中，功能区块包括以下中的一种或多种：用于执行芯片控制的控制区块；用于执行芯片测试的测试区块；用于提供I/O接口的接口区块。
可选地，在上述功能区块中的各种区块之间也可以基于各自的第一运算需求采用区别化的制程工艺，基于各自的第二运算需求采用区别化的封装工艺。例如，该控制区块的设计相对运算区块没有速率方面的要求，但需要考虑整体芯片功耗，因此可以采用相对适中的制程工艺。与之相对的，接口区块和测试区块的运算需求相对更低，因此可以选择更为稳定成熟的制程工艺。
可选地，在上述功能区块中，由于重新设计全覆盖的芯片整体的开发成本较高，针对诸如测试区块和/或接口区块等芯片通用区块，可以重复使用现有的区块设计芯片，进而可以有效节省成本和加快时间。
在一种实施方式中，上述第一运算需求包括：各个区块的速率需求、功耗需求、带宽需求中的一种或多种。不同的制程工艺通常会满足不同程度的运算速率、功耗及带宽需求，本实施例对此不作具体限制。
在一种实施方式中，第二运算需求包括：各个区块的速率需求和/或带宽需求。不同的封装工艺通常会满足不同程度的运算速率及带宽需求，本实施例对此不作具体限制。
在一种实施方式中，进一步地，还可以根据各个裸片的尺寸和/或对多个裸片进行重组互联的封装复杂度，确定各个裸片的封装工艺。即，针对各个裸片的封装工艺的选择，除了 要考虑对应区块的运算需求之外，还可以综合考虑各个裸片的尺寸情况和芯片整体的封装复杂度。
例如，如图6和图7所示，考虑到运算区块对应的多个裸片对带宽速率有要求，可以选择3D封装方式并通过TSV来实现。对于其余的控制区块、测试区块和接口区块对应的裸片，考虑到封装复杂度和整体芯片的面积(面积太大对PCB和产品会有影响)，可以选择2.5D封装实现，最后在基板层上通过中介层将上述两种封装类型的小芯片互联即可。
在一种实施方式中，在步骤500中，可以采用第一封装工艺，将多个第一区块对应的多个裸片堆叠设置在中介层的上侧；并采用第二封装工艺，将一个或多个第二区块对应的一个或多个裸片平铺设置在中介层的上侧；最后通过连接至基板层的中介层，实现裸片之间的互联。
其中，第一封装工艺为3D封装工艺和/或超过3D封装工艺的先进封装工艺，第二封装工艺为2.5D封装工艺。
例如，图8示出一种混合封装形式，多个运算核裸片(CORE Die)通过3D封装形式堆叠进行封装，通过硅通孔(TSV)实现运算核裸片(CORE Die)之间的高速互联；然后控制裸片(TOP Die)通过中介层(Interposer)和运算核裸片(CORE Die)之间实现互联。中介层(Interposer)通过凸块连接到基板层(Substrate)上，最终实现2.5D+3D的混合封装。中介层(Interposer)是一种由硅和有机材料制成的硅基板层，通过硅通孔(TSV)联系上下层，再通过锡球焊接至传统2D的封装基板层上，是先进封装中多芯片模块传递电信号的管道，可以实现芯片间的互连，也可以实现与封装基板层的互连，充当多颗裸片和电路板之间的桥梁硅通孔(TSV)是2.5D封装解决方案的关键实现技术，即在晶圆中填充铜，提供贯通硅晶圆裸片的垂直互连，用最短路径将硅片一侧和另一侧进行电气连通。
又例如，图9示出了另一种混合封装形式，多个运算核裸片(CORE Die)通过3D堆叠实现不同列(Slice)，然后多个运算核裸片(CORE Die)之间通过3D堆叠封装，通过硅通孔(TSV)实现互联，然后不同列(Slice)通过凸起连接到中介层(Interposer)上，同样的，控制裸片(TOP Die)以2.5D封装的形式通过中介层(Interposer)连接到基板层(Substrate)。由此，通过混合封装的方案，既能享受3D封装在面积方面的优势，也能获得2.5D封装的封装成本优势。
在一种实施方式中，还可以采用异型中介层，异型中介层具有设置在基板层上侧的主体部和沿多个裸片的堆叠方向设置的分支部；第一区块对应的多个裸片堆叠设置在主体部的上侧，且裸片横向延伸连接至分支部。如此，提供了一种更具创新性的混合封装方案，其能够保证更高的时钟信号准确度。
在一种实施方式中，异型中介层可以形成为倒T型中介层。
例如，以时钟信号举例，由于算法芯片对于运算核裸片(CORE Die)的时钟信号有很高的要求。那么如果运算核裸片(CORE Die)是通过TSV之间互联逐级传递，势必会对信号质量传输造成损失，而且需要在运算核裸片(CORE Die)的出口位置加很多大驱动能力的CELL。基于此，参考图10，本实施例可以将中介层(Interposer)设计为异型中介层，比如设计为倒T型，该异性中介层的竖立部分高度可以设定为和3D封装高度一致，然后时钟信号通过横向延伸出管脚(pin)的方式通过凸起(Macrobumps)连接到中介层(Interposer)，中介层(Interposer)内部只有传输线，如此时钟等重要信号的传递的线损就会降到最低，能减小信号延迟，降低电容/电感，实现芯片间的低功耗，高速通讯，增加宽带。而运算核裸片(CORE Die)之间其他信号还可以通过硅通孔(TSV)来传递。
在一种实施方式中，芯片为高算力芯片。
需要说明的是，本实施方式中未作详细说明的步骤可以参考图5所示实施方式中相关步骤中的描述，此处不再赘述。
在本说明书的描述中，参考术语“一些可能的实施方式”、“一些实施方式”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施方式或示例描述的具体特征、结构、材料或者特点包含于本发明的至少一个实施方式或示例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施方式或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施方式或示例以及不同实施方式或示例的特征进行结合和组合。
关于本申请实施方式的方法流程图，将某些操作描述为以一定顺序执行的不同的步骤。这样的流程图属于说明性的而非限制性的。可以将在本文中所描述的某些步骤分组在一起并且在单个操作中执行、可以将某些步骤分割成多个子步骤、并且可以以不同于在本文中所示出的顺序来执行某些步骤。可以由任何电路结构和/或有形机制(例如，由在计算机设备上运行的软件、硬件(例如，处理器或芯片实现的逻辑功能)等、和/或其任何组合)以任何方式来实现在流程图中所示出的各个步骤。
基于相同的技术构思，本发明实施方式还提供一种混合封装芯片，其是利用上述实施例所阐述的封装方法制造出的芯片。
基于相同或类似的技术构思，本发明实施方式还提供一种混合封装芯片，参考图3-6，该混合封装芯片包括：基板层，设置在基板层上方的中介层，以及设置在中介层上方的多个 裸片；其中，多个裸片具有不同的制程工艺，且多个裸片采用不同的封装工艺重组互联至中介层的上方。
在一种实施方式中，多个裸片分别对应于芯片中按功能划分的多个区块，多个裸片根据对应区块的第一运算需求具有不同的制程工艺，且多个裸片根据对应区块的第二运算需求采用不同的封装工艺重组互联至中介层的上方。
具体地，每个区块对应的制程工艺可以与其第一运算需求成正比，即，第一运算需求越高，采用的制程工艺越先进。该第一运算需求可以包括诸如带宽、速率、功耗等多种维度的运算需求，不同维度的第一运算需求所匹配的制程工艺也不同，可以基于该等维度的第一运算需求综合考虑所采用的制程工艺。每个区块对应的封装工艺可以与其第二运算需求成正比，即，第二运算需求越高，采用的封装工艺越先进。该第二运算需求可以包括诸如带宽、速率、等多种维度的运算需求。
在一种实施方式中，可以根据各个裸片的对应区块的速率需求、功耗需求、带宽需求中的一种或多种，确定各个裸片的制程工艺。
在一种实施方式中，可以根据各个裸片对应区块的速率需求和/或带宽需求、各个裸片的尺寸、重组互联的封装复杂度中的一种或多种，确定各个裸片的封装工艺。
在一种实施方式中，多个区块，包括：用于执行集成运算的运算区块和用于执行辅助功能的功能区块。将芯片整体划分为运算需求相对较高的运算区块，和运算需求相对较低的功能区块，能够便于将芯片的运算区块向先进制程及先进封装工艺进行迁移，而功能区块则维持较为保守的制程及封装工艺，以节省成本提高良率。
在一种实施方式中，运算区块，还包括：在运算区块包括多个运算核的情况下，对运算区块再次进行芯片划分，得到分别对应于多个运算核的多个运算子区块。由此，可以以堆叠方式对等运算子区块对应的运算核裸片进行封装，节省空间且更加匹配该运算区块的带宽密度、延时、功耗需求。
在一种实施方式中，功能区块包括以下中的一种或多种：用于执行芯片控制的控制区块；用于执行芯片测试的测试区块；用于提供I/O接口的接口区块。
可选地，在上述功能区块中的各种区块之间也可以基于各自的第一运算需求采用区别化的制程工艺，基于各自的第二运算需求采用区别化的封装工艺。例如，该控制区块的设计相对运算区块没有速率方面的要求，但需要考虑整体芯片功耗，因此可以采用相对适中的制程工艺。与之相对的，接口区块和测试区块的运算需求相对更低，因此可以选择更为稳定成熟的制程工艺。
可选地，在上述功能区块中，由于重新设计全覆盖的芯片整体的开发成本较高，针对诸如测试区块和/或接口区块等芯片通用区块，可以重复使用现有的区块设计芯片，进而可以有效节省成本和加快时间。
在一种实施方式中，多个裸片采用不同的封装工艺重组互联至中介层的上方还包括：采用第一封装工艺，将多个裸片堆叠设置在中介层的上侧；和/或，采用第二封装工艺，将一个或多个裸片平铺设置在中介层的上侧；通过连接至基板层的中介层，实现裸片之间的互联。
其中，第一封装工艺为3D封装工艺和/或超过3D封装工艺的先进封装工艺，第二封装工艺为2.5D封装工艺。
在一种实施方式中，还可以采用异型中介层，异型中介层具有设置在基板层上侧的主体部和沿多个裸片的堆叠方向设置的分支部；多个裸片堆叠设置在主体部的上侧，且多个裸片中的每一者横向延伸连接至分支部。
在一种实施方式中，异型中介层可以为倒T型中介层。
在一种实施方式中，芯片为高算力芯片。
需要说明的是，本申请实施方式中的混合封装芯片和前述方法达到相同的效果和功能，这里不再赘述。
虽然已经参考若干具体实施方式描述了本发明的精神和原理，但是应该理解，本发明并不限于所公开的具体实施方式，对各方面的划分也不意味着这些方面中的特征不能组合以进行受益，这种划分仅是为了表述的方便。本发明旨在涵盖所附权利要求的精神和范围内所包括的各种修改和等同布置。

Claims (60)

  1. 一种芯片，其特征在于，所述芯片包括：基板层，设置在基板层上方的中介层，还包括：
    第一裸片，设置在所述中介层上方，其基于与所述第一裸片的功能相匹配的第一制程工艺制成；
    第二裸片，设置在所述中介层上方，其基于与所述第二裸片的功能相匹配的第二制程工艺制成；其中，所述第二裸片和所述第一裸片通过所述中介层互联。
  2. 根据权利要求1所述的芯片，其特征在于，
    所述第一裸片，基于与所述第一裸片的功能相匹配的第一封装工艺制成；
    所述第二裸片，基于与所述第二裸片的功能相匹配的第二封装工艺制成。
  3. 根据权利要求1所述的芯片，其特征在于，所述第一裸片被配置为：用于执行运算功能的裸片。
  4. 根据权利要求1所述的芯片，其特征在于，所述第二裸片被配置为：用于执行辅助功能的裸片。
  5. 根据权利要求1所述的芯片，其特征在于，所述第二裸片包括以下中的一种或多种：
    用于执行芯片控制的控制功能裸片；用于执行芯片测试的测试功能裸片；用于提供I/O接口的接口功能裸片。
  6. 根据权利要求2所述的芯片，其特征在于，所述第一裸片被配置为：用于执行运算功能的裸片。
  7. 根据权利要求2或3所述的芯片，其特征在于，所述第二裸片被配置为：用于执行辅助功能的裸片。
  8. 根据权利要求2-4中任一项所述的芯片，其特征在于，所述第二裸片包括以下中的一种或多种：
    用于执行芯片控制的控制功能裸片；用于执行芯片测试的测试功能裸片；用于提供I/O接口的接口功能裸片。
  9. 根据权利要求1-5中任一项所述的芯片，其特征在于，与裸片功能相匹配的制程工艺与所述裸片功能的第一性能需求正相关；
    所述第一性能需求包括以下至少一种：速率需求、功耗需求、带宽需求。
  10. 根据权利要求1-5中任一项所述的芯片，其特征在于，与裸片功能相匹配的封装工艺与所述裸片功能的第二性能需求正相关；
    所述第二性能需求包括以下至少一种：速率需求、带宽需求。
  11. 根据权利要求1-5中任一项所述的芯片，其特征在于，
    所述第一裸片，其基于第一封装工艺堆叠设置在中介层上；
    所述第二裸片，其基于第二封装工艺平铺设置在所述中介层上。
  12. 根据权利要求8所述的芯片，其特征在于，
    所述中介层包括设置在基板层上侧的主体部和沿所述多个裸片的堆叠方向设置的分支部；
    所述至少一个第一裸片堆叠设置在主体部的上侧，且所述至少一个第一裸片中的每一者横向延伸连接至所述分支部。
  13. 根据权利要求1-5中任一项所述的芯片，其特征在于，所述中介层为倒T型中介层。
  14. 根据权利要求2所述的芯片，其特征在于，其中，所述第一封装工艺为3D封装工艺或超过3D封装工艺的先进封装工艺，所述第二封装工艺为2.5D封装工艺。
  15. 一种芯片制造方法，其特征在于，包括：
    在基板层上方生成中介层；
    在所述中介层上方生成第一裸片，所述第一裸片基于与其功能相匹配的第一制程工艺制成；
    在所述中介层上方生成第二裸片，所述第二裸片基于与其功能相匹配的第二制程工艺制成；
    通过所述中介层将所述第二裸片和所述第一裸片互联。
  16. 根据权利要求15所述的制造方法，其特征在于，
    所述第一裸片，基于与所述第一裸片的功能相匹配的第一封装工艺封装制成；
    所述第二裸片，基于与所述第二裸片的功能相匹配的第二封装工艺封装制成。
  17. 根据权利要求15所述的制造方法，其特征在于，所述第一裸片被配置为：用于执行运算功能的裸片。
  18. 根据权利要求15所述的制造方法，其特征在于，所述第二裸片被配置为：用于执行辅助功能的裸片。
  19. 根据权利要求15所述的制造方法，其特征在于，所述第二裸片包括以下中的一种或多种：
    用于执行芯片控制的控制功能裸片；用于执行芯片测试的测试功能裸片；用于提供I/O接口的接口功能裸片。
  20. 根据权利要求16所述的制造方法，其特征在于，所述第一裸片被配置为：用于执行运算功能的裸片。
  21. 根据权利要求16或17所述的制造方法，其特征在于，所述第二裸片被配置为：用于执行辅助功能的裸片。
  22. 根据权利要求16-18中任一项所述的制造方法，其特征在于，所述第二裸片包括以下中的一种或多种：
    用于执行芯片控制的控制功能裸片；用于执行芯片测试的测试功能裸片；用于提供I/O接口的接口功能裸片。
  23. 根据权利要求15-19中任一项所述的制造方法，其特征在于，与裸片功能相匹配的制程工艺与所述裸片功能的第一性能需求正相关；
    所述第一性能需求包括以下至少一种：速率需求、功耗需求、带宽需求。
  24. 根据权利要求15-19中任一项所述的制造方法，其特征在于，与裸片功能相匹配的封装工艺与所述裸片功能的第二性能需求正相关；
    所述第二性能需求包括以下至少一种：速率需求、带宽需求。
  25. 根据权利要求15-19中任一项所述的制造方法，其特征在于，还包括：
    在所述中介层上方，基于第一封装工艺堆叠设置所述生成第一裸片，
    在所述中介层上方，其基于第二封装工艺平铺设置所述第二裸片。
  26. 根据权利要求25所述的制造方法，其特征在于，
    所述中介层包括设置在基板层上侧的主体部和沿所述多个裸片的堆叠方向设置的分支部；
    所述至少一个第一裸片堆叠设置在主体部的上侧，且所述至少一个第一裸片中的每一者横向延伸连接至所述分支部。
  27. 根据权利要求15-19中任一项所述的制造方法，其特征在于，所述中介层为倒T型中介层。
  28. 根据权利要求16所述的制造方法，其特征在于，其中，所述第一封装工艺为3D封装工艺或超过3D封装工艺的先进封装工艺，所述第二封装工艺为2.5D封装工艺。
  29. 一种芯片封装方法，其特征在于，包括：
    确定与待封装芯片所需实现各项功能相匹配的制程工艺；
    采用与各项功能相匹配的制程工艺，生成对应于所述各项功能的裸片；
    对所述各项功能的裸片进行封装。
  30. 根据权利要求29所述的方法，其特征在于，所述对各项功能的裸片进行封装，包括：
    确定与待封装芯片所需实现各项功能相匹配的封装工艺；
    采用与各项功能相匹配的封装工艺对相应裸片进行封装。
  31. 根据权利要求29所述的方法，其特征在于，确定与待封装芯片所需实现各项功能相匹配的制程工艺，包括：
    根据待封装芯片所需实现各项功能的性能需求，确定与所述各项功能相匹配的制程工艺，其中，所述各项功能的性能需求越高，相应确定的制程工艺要求越高。
  32. 根据权利要求31所述的方法，其特征在于，确定与待封装芯片所需实现各项功能相匹配的封装工艺，包括：
    根据待封装芯片所需实现各项功能的性能需求，确定与所述各项功能相匹配的封装工艺，其中，所述各项功能的性能需求越高，相应确定的封装工艺要求越高。
  33. 根据权利要求29-32中任一项所述的方法，其特征在于，所述各项功能包括运算功能和辅助功能。
  34. 根据权利要求33所述的方法，其特征在于，所述根据待封装芯片所需实现各项功能的性能需求，确定与所述各项功能相匹配的制程工艺，包括：
    根据所述运算功能的性能需求，确定相匹配的第一制程工艺；
    根据所述辅助功能的性能需求，确定相匹配的第二制程工艺。
  35. 根据权利要求34所述的方法，其特征在于，所述运算功能实现为至少一个运算核；所述采用与各项功能相匹配的制程工艺，生成对应于所述各项功能的裸片，包括：
    采用所述第一制程工艺对所述至少一个运算核进行制程得到至少一个运算核裸片；
    采用所述第二制程工艺对所述辅助功能进行制程得到辅助裸片。
  36. 根据权利要求35所述的方法，其特征在于，所述采用与各项功能相匹配的封装工艺对相应裸片进行封装，包括：
    对所述至少一个运算核裸片采用第一封装工艺进行封装，对所述辅助裸片采用第二封装工艺进行封装。
  37. 根据权利要求33所述的方法，其特征在于，所述辅助功能包括以下中的一种或多种：
    用于执行芯片控制的控制功能；用于执行芯片测试的测试功能；用于提供I/O接口的接口功能。
  38. 根据权利要求31所述的方法，其特征在于，所述根据待封装芯片所需实现各项功能的性能需求，确定与所述各项功能相匹配的制程工艺，包括：
    根据待封装芯片所需实现各项功能的第一性能需求，确定与所述各项功能相匹配的制程工艺，其中，所述第一运算需求包括速率需求、功耗需求、带宽需求中的一种或多种。
  39. 根据权利要求32所述的方法，其特征在于，所述根据待封装芯片所需实现各项功能的性能需求，确定与所述各项功能相匹配的封装工艺，包括：
    根据待封装芯片所需实现的各项功能的第二性能需求，确定与所述各项功能相匹配的封装工艺，其中，所述第二运算需求包括速率需求和/或带宽需求。
  40. 根据权利要求36所述的方法，其特征在于，其中，所述第一封装工艺为3D封装工艺或超过3D封装工艺的先进封装工艺，所述第二封装工艺为2.5D封装工艺或者2D封装工艺。
  41. 根据权利要求36所述的方法，其特征在于，
    所述对所述至少一个运算核裸片采用第一封装工艺进行封装包括：采用第一封装工艺，将所述至少一个运算核裸片堆叠设置在中介层上；
    所述对所述辅助裸片采用第二封装工艺进行封装包括：采用第二封装工艺，将一个或多个辅助裸片平铺设置在所述中介层上。
  42. 根据权利要求41所述的方法，其特征在于，还包括：通过连接至基板层的所述中介层，实现所述裸片之间的互联。
  43. 根据权利要求42所述的方法，其特征在于，
    所述中介层包括设置在基板层上侧的主体部和沿所述多个裸片的堆叠方向设置的分支部；
    所述至少一个运算核裸片堆叠设置在主体部的上侧，且所述至少一个运算核裸片横向延伸连接至所述分支部。
  44. 根据权利要求43所述的方法，其特征在于，所述中介层为倒T型中介层。
  45. 一种芯片，其特征在于，
    利用权利要求15-28或者29-44中任一项所述的方法得到。
  46. 一种芯片，其特征在于，包括：
    基板层，设置在基板层上方的中介层，以及设置在所述中介层上方的多个裸片；
    其中，所述多个裸片对应于所述芯片的多项功能，所述多个裸片采用与所述各项功能相匹配的制程工艺。
  47. 根据权利要求46所述的芯片，其特征在于，所述多个裸片采用与所述各项功能相匹配的封装工艺。
  48. 根据权利要求46所述的芯片，其特征在于，其特征在于，所述各项功能相匹配的制程工艺与所述各项功能的性能需求正相关。
  49. 根据权利要求47所述的芯片，其特征在于，所述各项功能相匹配的封装工艺与所述各项功能的性能需求正相关。
  50. 根据权利要求48所述的芯片，其特征在于，所述各项功能包括运算功能和辅助功能。
  51. 根据权利要求50所述的芯片，其特征在于，
    所述运算功能对应的裸片，采用与所述运算功能的性能需求相匹配的第一制程工艺；
    所述辅助功能对应的裸片，采用与所述辅助功能的性能需求相匹配的第二制程工艺。
  52. 根据权利要求51所述的芯片，其特征在于，所述芯片包括对应于所述运算功能的至少一个运算核裸片和对应于所述辅助功能的辅助裸片；其中，
    所述至少一个运算核裸片，采用所述第一制程工艺；
    所述辅助裸片，采用所述第二制程工艺。
  53. 根据权利要求51所述的芯片，其特征在于，
    所述至少一个运算核裸片采用第一封装工艺，所述辅助裸片采用第二封装工艺。
  54. 根据权利要求52所述的芯片，其特征在于，所述辅助裸片包括以下中的一种或多种：
    用于执行芯片控制的控制功能裸片；用于执行芯片测试的测试功能裸片；用于提供I/O接口的接口功能裸片。
  55. 根据权利要求46所述的芯片，其特征在于，所述各项功能相匹配的制程工艺与所述各项功能的第一性能需求正相关，所述第一性能需求包括以下至少一种：速率需求、功耗需求、带宽需求。
  56. 根据权利要求47所述的芯片，其特征在于，所述各项功能相匹配的封装工艺与所述各项功能的第二性能需求正相关，所述第二性能需求包括以下至少一种：速率需求、带宽需求。
  57. 根据权利要求53所述的芯片，其特征在于，其中，所述第一封装工艺为3D封装工艺或超过3D封装工艺的先进封装工艺，所述第二封装工艺为2.5D封装工艺。
  58. 根据权利要求54所述的芯片，其特征在于，
    所述至少一个运算核裸片，采用第一封装工艺堆叠设置在中介层上；
    所述辅助裸片，采用第二封装工艺平铺设置在所述中介层上；
    所述至少一个运算核裸片和所述辅助裸片通过连接至基板层的所述中介层互联。
  59. 根据权利要求58所述的芯片，其特征在于，
    所述中介层包括设置在基板层上侧的主体部和沿所述多个裸片的堆叠方向设置的分支部；
    所述至少一个运算核裸片堆叠设置在主体部的上侧，且所述至少一个运算核裸片中的每一者横向延伸连接至所述分支部。
  60. 根据权利要求59所述的芯片，其特征在于，所述中介层为倒T型中介层。
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