CN113451292A - 一种高集成2.5d封装结构及其制造方法 - Google Patents

一种高集成2.5d封装结构及其制造方法 Download PDF

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CN113451292A
CN113451292A CN202110906696.4A CN202110906696A CN113451292A CN 113451292 A CN113451292 A CN 113451292A CN 202110906696 A CN202110906696 A CN 202110906696A CN 113451292 A CN113451292 A CN 113451292A
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die
silicon interposer
chip
chips
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马晓建
刘卫东
高瑞锋
苏亚兰
张婕
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Huatian Technology Xian Co Ltd
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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Abstract

本发明涉及芯片封装技术领域，具体为一种高集成2.5D封装结构及其制造方法，包括Package Substrate和埋die的硅Interposer，所述埋die的硅Interposer的上下表面均开设有凹槽，所述埋die的硅Interposer的凹槽内设置有预埋芯片，埋die的硅Interposer和预埋芯片之间设置有胶水，埋die的硅Interposer的下表面设置有Package Substrate，埋die的硅Interposer的上表面的右侧设置有逻辑芯片，埋die的硅Interposer的上表面的左侧设置有HBM芯片，同时在埋die的硅Interposer的顶面和底面时贴装多个预埋芯片，提高产品电性表现，缩短了芯片和芯片之间的导通回路，方便提高电性能，通过堆叠或并排放置在具有硅通孔的埋die的硅Interposer顶部，埋die的硅Interposer可提供芯片之间的互联，从而增加整个2.5D封装的集成度。

Description

一种高集成2.5D封装结构及其制造方法
技术领域
本发明涉及芯片封装技术领域，具体为一种高集成2.5D封装结构及其制造方法。
背景技术
封装技术伴随集成电路发明应运而生，主要功能是完成电源分配、信号分配、散热和保护，伴随着芯片技术的发展，封装技术不断革新，封装互连密度不断提高，封装厚度不断减小，三维封装、***封装手段不断演进，随着集成电路应用多元化，智能手机、物联网、汽车电子、高性能计算、5G、人工智能等新兴领域对先进封装提出更高要求，封装技术发展迅速，创新技术不断出现，为解决有机基板布线密度不足的问题，带有TSV垂直互连通孔和高密度金属布线的硅Interposer应运而生，应用TSV转接板的封装结构称为2.5DInterposer，2.5D封装技术也称为晶圆级封装，2.5D封装技术是把芯片封装到硅转接板上，并使用硅转接板上的高密度走线进行互联，随着半导体工业的发展，封装内芯片通过金线键合底层封装体到基板上，同样的，上层封装中的芯片通过金线再将两个封装层之间的基板键合，然后整个封装成一个整体的封装体，2.5D封装是传统2DIC封装技术的进步，可实现更精细的线路与空间利用。
在2.5D Interposer封装中，若干个芯片并排排列在Interposer上，但众多的裸片堆叠或并排放置在具有硅通孔(TSV)的中介层顶部，仍然使得封装的集成度增加的有限，因此对于高集成的高速产品封装需求，提出一种结构，增加封装集成度同时，有效缩短多个芯片间信号以及电源网络的通路，从而方便进一步提高电性能。
发明内容
本发明的目的在于提供一种高集成2.5D封装结构及其制造方法，以解决上述背景技术中提出的问题。
为实现上述目的，本发明提供如下技术方案：一种高集成2.5D封装结构及其制造方法，包括Package Substrate和埋die的硅Interposer，所述埋die的硅Interposer的上下表面均开设有凹槽，所述埋die的硅Interposer的凹槽内设置有预埋芯片，埋die的硅Interposer和预埋芯片之间设置有胶水，埋die的硅Interposer的下表面设置有PackageSubstrate，埋die的硅Interposer的上表面的右侧设置有逻辑芯片，埋die的硅Interposer的上表面的左侧设置有HBM芯片。
优选的，所述埋die的硅Interposer的上表面的中间开设有凹槽，埋die的硅Interposer的下表面的两侧均开设有凹槽，且下表面的两个凹槽呈对称分布，埋die的硅Interposer的凹槽的形状和预埋芯片的形状一致。
优选的，所述埋die的硅Interposer的两端均开设有硅通孔(TSV)，埋die的硅Interposer和预埋芯片之间的缝隙通过胶水填充，胶水将预埋芯片固定在埋die的硅Interposer的凹槽中。
优选的，所述埋die的硅Interposer上扇出有线路层。
优选的，所述埋die的硅Interposer的下表面贴装到Package Substrate的上表面，Package Substrate的尺寸大于埋die的硅Interposer，埋die的硅Interposer和Package Substrate之间设置有胶水。
优选的，所述埋die的硅Interposer的上表面贴装有逻辑芯片和HBM芯片，且逻辑芯片和HBM芯片并排放置。
与现有技术相比，本发明的有益效果是：本发明结构设置合理，功能性强，具有以下优点：
1.本发明提出的高集成2.5D封装结构及其制造方法同时在埋die的硅Interposer的顶面和底面时贴装多个预埋芯片，方便增加封装的集成度，提高产品电性表现；
2.本发明提出的高集成2.5D封装结构及其制造方法中的埋die的硅Interposer的上下两面贴装的预埋芯片，便于缩短芯片和芯片之间的导通回路，方便提高电性能，同时实现预埋芯片之间、预埋芯片和逻辑芯片之间、预埋芯片和HBM芯片之间以及预埋芯片与Package Substrate之间更高密度的互连，；
3.本发明提出的高集成2.5D封装结构及其制造方法中通过堆叠或并排放置在具有硅通孔的埋die的硅Interposer顶部，埋die的硅Interposer可提供芯片之间的互联，从而增加整个2.5D封装的集成度，通过硅通孔(TSV)等结构，埋die的硅Interposer可提供芯片之间的互联，同时实现芯片与芯片、芯片与封装基板间更高密度的互连。
附图说明
图1为本发明单个Unit结构示意图；
图2为本发明中硅Interposer上蚀刻出凹槽的示意图；
图3为本发明贴装芯片结构示意图；
图4为本发明中TSV+填胶+扇出线路层后结构示意图；
图5为本发明中硅转接板贴装到封装载板上的结构示意图；
图6为本发明中贴装HBM堆叠芯片和逻辑芯片结构示意图。
图中：1、Package Substrate；2、埋die的硅Interposer；3、预埋芯片；4、逻辑芯片；5、HBM芯片；6、胶水。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参阅图1至图6，本发明提供一种技术方案：一种高集成2.5D封装结构及其制造方法，包括Package Substrate 1和埋die的硅Interposer 2，埋die的硅Interposer 2的上下表面均开设有凹槽，埋die的硅Interposer 2的上表面的中间开设有凹槽，埋die的硅Interposer 2的下表面的两侧均开设有凹槽，且下表面的两个凹槽呈对称分布，凹槽的形状和预埋芯片3的形状一致，埋die的硅Interposer 2的凹槽内设置有预埋芯片3，埋die的硅Interposer 2和预埋芯片3之间的缝隙通过胶水6填充，胶水6将预埋芯片3固定在埋die的硅Interpose 2的凹槽中，埋die的硅Interposer 2的上下表面均进行蚀刻，从而增加同一个埋die的硅Interposer 2上贴装的预埋芯片3的数量，方便增加2.5D封装结构的集成度，缩短了芯片和芯片之间的导通回路，从而提高产品电性表现和电性能，埋die的硅Interposer 2的两端均开设有硅通孔，埋die的硅Interposer 2上扇出有线路层，硅通孔(TSV)可以通过垂直互连减小互联长度，减小信号延迟，降低电容、电感，实现芯片间的低功耗，高速通讯，然后在表面扇出线路层。
埋die的硅Interposer 2的下表面设置有Package Substrate 1，埋die的硅Interposer 2的下表面贴装到Package Substrate 1的上表面，Package Substrate 1的尺寸大于埋die的硅Interposer 2，，埋die的硅Interposer 2和Package Substrate 1间设置有胶水6，埋die的硅Interposer 2的上表面的右侧设置有逻辑芯片4，埋die的硅Interposer 2的上表面的左侧设置有HBM芯片5，埋die的硅Interposer 2的上表面贴装有逻辑芯片4和HBM芯片5，且逻辑芯片4和HBM芯片5并排放置，预埋芯片3、逻辑芯片4和HBM芯片5堆叠或并排放置在具有硅通孔(TSV)的埋die的硅Interposer 2顶部，埋die的硅Interposer 2可提供芯片之间的互联，从而通过电性能，同时实现预埋芯片3与预埋芯片3之间、预埋芯片3和逻辑芯片4之间、预埋芯片3和HBM芯片5之间以及预埋芯片3与PackageSubstrate 1间更高密度的互连。
工作原理：实际工作时，如图1是本发明中单个Unit的具体结构，可以看到高集成2.5D的封装结构的全貌，图2到图6是本发明一些实施的封装结构制造方法，图2中在埋die的硅Interposer 2上下表面均蚀刻出多个凹槽，图3是在埋die的硅Interposer 2的凹槽中贴装预埋芯片3，缩小导电通路，图4是在埋die的硅Interposer 2的两端上钻出硅通孔(TSV)后填上胶水6，同时将预埋芯片3通过胶水6固定在埋die的硅Interposer 2的凹槽中，硅通孔(TSV)可以通过垂直互连减小互联长度，减小信号延迟，降低电容、电感，实现芯片间的低功耗，高速通讯，然后在表面扇出线路层，图5将埋die的硅Interposer 2贴装到Package Substrate 1的上表面，方便将埋die的硅Interposer 2固定，图6则是将逻辑芯片4和HBM芯片分别贴装到埋die的硅Interposer 2的上表面，从而完成2.5D的封装贴装流程，通过在埋die的硅Interposer 2的上下表面均进行蚀刻，从而增加同一个埋die的硅Interposer 2上贴装的预埋芯片3的数量，方便增加2.5D封装结构的集成度，缩短了芯片和芯片之间的导通回路，从而提高产品电性表现和电性能，然后扇出线路层，可以进行多芯片的***封装；具有更薄的封装尺寸、优异的电性能、易于多芯片***集成等优点，在2.5D埋die的硅Interposer 2封装中，预埋芯片3、逻辑芯片4和HBM芯片5堆叠或并排放置在具有硅通孔(TSV)的埋die的硅Interposer 2顶部，通过埋die的硅Interposer 2上的硅通孔(TSV)结构等，埋die的硅Interposer 2可提供芯片之间的互联，同时实现预埋芯片3与预埋芯片3之间、预埋芯片3和逻辑芯片4之间、预埋芯片3和HBM芯片5之间以及预埋芯片3与PackageSubstrate 1之间更高密度的互连，便于提高电性能，通过胶水6将Package Substrate 1和埋die的硅Interposer 2固定。
尽管已经示出和描述了本发明的实施例，对于本领域的普通技术人员而言，可以理解在不脱离本发明的原理和精神的情况下可以对这些实施例进行多种变化、修改、替换和变型，本发明的范围由所附权利要求及其等同物限定。

Claims (6)

1.一种高集成2.5D封装结构及其制造方法，包括Package Substrate(1)和埋die的硅Interposer(2)，其特征在于：所述埋die的硅Interposer(2)的上下表面均开设有凹槽，所述埋die的硅Interposer(2)的凹槽内设置有预埋芯片(3)，埋die的硅Interposer(2)和预埋芯片(3)之间设置有胶水(6)，埋die的硅Interposer(2)的下表面设置有PackageSubstrate(1)，埋die的硅Interposer(2)的上表面的右侧设置有逻辑芯片(4)，埋die的硅Interposer(2)的上表面的左侧设置有HBM芯片(5)。
2.根据权利要求1所述的一种高集成2.5D封装结构及其制造方法，其特征在于：所述埋die的硅Interposer(2)的上表面的中间开设有凹槽，埋die的硅Interposer(2)的下表面的两侧均开设有凹槽，且下表面的两个凹槽呈对称分布，埋die的硅Interposer(2)的凹槽的形状和预埋芯片(3)的形状一致。
3.根据权利要求1所述的一种高集成2.5D封装结构及其制造方法，其特征在于：所述埋die的硅Interposer(2)的两端均开设有硅通孔(TSV)，埋die的硅Interposer(2)和预埋芯片(3)之间的缝隙通过胶水(6)填充，胶水(6)将预埋芯片(3)固定在埋die的硅Interposer(2)的凹槽中。
4.根据权利要求1所述的一种高集成2.5D封装结构及其制造方法，其特征在于：所述埋die的硅Interposer(2)上扇出有线路层。
5.根据权利要求1所述的一种高集成2.5D封装结构及其制造方法，其特征在于：所述埋die的硅Interposer(2)的下表面贴装到Package Substrate(1)的上表面，PackageSubstrate(1)的尺寸大于埋die的硅Interposer(2)，埋die的硅Interposer(2)和PackageSubstrate(1)之间设置有胶水(6)。
6.根据权利要求1所述的一种高集成2.5D封装结构及其制造方法，其特征在于：所述埋die的硅Interposer(2)的上表面贴装有逻辑芯片(4)和HBM芯片(5)，且逻辑芯片(4)和HBM芯片(5)并排放置。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024051124A1 (zh) * 2022-09-06 2024-03-14 华进半导体封装先导技术研发中心有限公司 一种多层高带宽存储器及其制造方法

Citations (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020175402A1 (en) * 2001-05-23 2002-11-28 Mccormack Mark Thomas Structure and method of embedding components in multi-layer substrates
JP2006128229A (ja) * 2004-10-26 2006-05-18 Murata Mfg Co Ltd 複合多層基板
US20090091022A1 (en) * 2007-10-09 2009-04-09 Infineon Technologies Ag Semiconductor chip package, semiconductor chip assembly, and method for fabricating a device
KR20090131877A (ko) * 2008-06-19 2009-12-30 삼성전기주식회사 칩 내장 인쇄회로기판 및 그 제조방법
US20100058580A1 (en) * 2008-09-06 2010-03-11 Farhang Yazdani Stacking Integrated Circuits containing Serializer and Deserializer Blocks using Through Silicon Via
US20100140782A1 (en) * 2008-12-08 2010-06-10 Samsung Electronics Co., Ltd. Printed circuit board having built-in integrated circuit package and fabrication method therefor
KR20100064468A (ko) * 2008-12-05 2010-06-15 삼성전기주식회사 칩 내장 인쇄회로기판 및 그 제조방법
CN103208471A (zh) * 2013-04-23 2013-07-17 山东华芯半导体有限公司 多芯片封装体
JP2014056925A (ja) * 2012-09-12 2014-03-27 Shinko Electric Ind Co Ltd 半導体パッケージ、半導体装置及び半導体パッケージの製造方法
US20150010694A1 (en) * 2013-07-03 2015-01-08 Taiyo Yuden Co., Ltd. Method of manufacturing substrate having cavity
US20150145141A1 (en) * 2013-11-22 2015-05-28 Invensas Corporation Multiple Bond Via Arrays of Different Wire Heights on a Same Substrate
JP2016162977A (ja) * 2015-03-04 2016-09-05 株式会社イースタン 配線基板およびその製造方法
TW201643488A (zh) * 2015-01-26 2016-12-16 奧瑞可國際公司 封裝光電模組
CN107275296A (zh) * 2017-06-30 2017-10-20 中国电子科技集团公司第五十八研究所 一种基于tsv技术的埋置型三维集成封装结构
US20170354031A1 (en) * 2016-06-02 2017-12-07 Intel Corporation Top-side connector interface for processor packaging
US20180145051A1 (en) * 2016-11-21 2018-05-24 Intel Corporation Package-bottom through-mold via interposers for land-side configured devices for system-in-package apparatus
CN109716509A (zh) * 2016-09-30 2019-05-03 英特尔公司 内插器封装上的嵌入式管芯
CN110797335A (zh) * 2019-11-28 2020-02-14 中南大学 异质集成芯片的***级封装结构
US20200303343A1 (en) * 2019-03-18 2020-09-24 Kepler Computing Inc. Artificial intelligence processor with three-dimensional stacked memory

Patent Citations (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020175402A1 (en) * 2001-05-23 2002-11-28 Mccormack Mark Thomas Structure and method of embedding components in multi-layer substrates
JP2006128229A (ja) * 2004-10-26 2006-05-18 Murata Mfg Co Ltd 複合多層基板
US20090091022A1 (en) * 2007-10-09 2009-04-09 Infineon Technologies Ag Semiconductor chip package, semiconductor chip assembly, and method for fabricating a device
KR20090131877A (ko) * 2008-06-19 2009-12-30 삼성전기주식회사 칩 내장 인쇄회로기판 및 그 제조방법
US20100058580A1 (en) * 2008-09-06 2010-03-11 Farhang Yazdani Stacking Integrated Circuits containing Serializer and Deserializer Blocks using Through Silicon Via
KR20100064468A (ko) * 2008-12-05 2010-06-15 삼성전기주식회사 칩 내장 인쇄회로기판 및 그 제조방법
US20100140782A1 (en) * 2008-12-08 2010-06-10 Samsung Electronics Co., Ltd. Printed circuit board having built-in integrated circuit package and fabrication method therefor
JP2014056925A (ja) * 2012-09-12 2014-03-27 Shinko Electric Ind Co Ltd 半導体パッケージ、半導体装置及び半導体パッケージの製造方法
CN103208471A (zh) * 2013-04-23 2013-07-17 山东华芯半导体有限公司 多芯片封装体
US20150010694A1 (en) * 2013-07-03 2015-01-08 Taiyo Yuden Co., Ltd. Method of manufacturing substrate having cavity
US20150145141A1 (en) * 2013-11-22 2015-05-28 Invensas Corporation Multiple Bond Via Arrays of Different Wire Heights on a Same Substrate
TW201643488A (zh) * 2015-01-26 2016-12-16 奧瑞可國際公司 封裝光電模組
JP2016162977A (ja) * 2015-03-04 2016-09-05 株式会社イースタン 配線基板およびその製造方法
US20170354031A1 (en) * 2016-06-02 2017-12-07 Intel Corporation Top-side connector interface for processor packaging
CN109716509A (zh) * 2016-09-30 2019-05-03 英特尔公司 内插器封装上的嵌入式管芯
US20180145051A1 (en) * 2016-11-21 2018-05-24 Intel Corporation Package-bottom through-mold via interposers for land-side configured devices for system-in-package apparatus
CN107275296A (zh) * 2017-06-30 2017-10-20 中国电子科技集团公司第五十八研究所 一种基于tsv技术的埋置型三维集成封装结构
US20200303343A1 (en) * 2019-03-18 2020-09-24 Kepler Computing Inc. Artificial intelligence processor with three-dimensional stacked memory
CN110797335A (zh) * 2019-11-28 2020-02-14 中南大学 异质集成芯片的***级封装结构

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024051124A1 (zh) * 2022-09-06 2024-03-14 华进半导体封装先导技术研发中心有限公司 一种多层高带宽存储器及其制造方法

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