WO2023272474A1 - 显示基板、显示装置和显示基板的制作方法 - Google Patents

显示基板、显示装置和显示基板的制作方法 Download PDF

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Publication number
WO2023272474A1
WO2023272474A1 PCT/CN2021/102994 CN2021102994W WO2023272474A1 WO 2023272474 A1 WO2023272474 A1 WO 2023272474A1 CN 2021102994 W CN2021102994 W CN 2021102994W WO 2023272474 A1 WO2023272474 A1 WO 2023272474A1
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electrode
base substrate
layer
organic
orthographic projection
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PCT/CN2021/102994
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English (en)
French (fr)
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谢昌翰
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京东方科技集团股份有限公司
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Priority to PCT/CN2021/102994 priority Critical patent/WO2023272474A1/zh
Priority to CN202180001691.5A priority patent/CN115735276A/zh
Publication of WO2023272474A1 publication Critical patent/WO2023272474A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells

Definitions

  • the present disclosure relates to the technical field of semiconductors, and in particular, to a display substrate, a display device, and a method for manufacturing the display substrate.
  • An embodiment of the present disclosure provides a display substrate, which has a base substrate and a plurality of pixels located on one side of the base substrate, and the pixels include:
  • An organic thin film transistor includes a gate, an organic semiconductor layer, and a source and drain;
  • the first electrode has a plurality of first hollow structures
  • An organic protection layer covers the first electrode and the organic thin film transistor, and fills the first hollow structure.
  • the pixel includes a second electrode located on a side of the organic protective layer away from the first electrode;
  • the first electrode includes a plurality of first electrode strips extending along the first direction and electrically connected to each other, with the first hollow structure between adjacent first electrode strips;
  • the second electrode includes a plurality of strips along the The second electrode strips extending in the first direction and electrically connected to each other, and the second hollow structure located between adjacent second electrode strips;
  • the area of the orthographic projection of the second hollow structure on the substrate is smaller than the area of the orthographic projection of the first electrode strip on the substrate, and the orthographic projection of the second hollow structure on the substrate Located within the orthographic projection of the first electrode strip on the base substrate.
  • the orthographic projection of the first electrode strip on the base substrate is the same as the orthographic projection of the part of the second electrode strip around the second hollow structure on the base substrate. overlap.
  • the line width of the first electrode strips in a plane parallel to the base substrate and perpendicular to the first direction is greater than that of the second hollow structure in a plane parallel to the substrate.
  • the plane of the substrate is perpendicular to the width in the first direction.
  • the display substrate further includes a gate line, the gate line is electrically connected to the gate, and the material of the gate line is different from that of the gate.
  • the display substrate further includes a connection electrode in the same layer as the second electrode and insulated; the gate line is located on the side of the connection electrode away from the organic protection layer and connected to the The connection electrode is electrically connected to the contact; the connection electrode is electrically connected to the gate through a via hole, so as to electrically connect the gate line to the gate.
  • the material of the gate line includes molybdenum; the material of the gate includes indium tin oxide or indium gallium zinc oxide.
  • the orthographic projection area of the gate line on the base substrate is smaller than the orthographic projection area of the connecting electrode on the base substrate, and the gate line is on the base substrate
  • the orthographic projection of is located within the orthographic projection of the connection electrode on the base substrate.
  • the line width of the second electrode strips in a plane parallel to the base substrate and perpendicular to the first direction is in the range of 1 ⁇ m ⁇ 5 ⁇ m.
  • the orthographic projection area of the first hollow structure on the base substrate accounts for 20% to 80% of the orthographic projection area of the first electrode on the base substrate.
  • the organic semiconductor layer is located on a side of the source and drain away from the substrate, and the gate is located on a side of the organic semiconductor layer away from the source and drain;
  • the organic semiconductor layer is located on a side of the gate away from the substrate, and the source and drain are located between the organic semiconductor layer and the gate;
  • the orthographic area of the gate on the substrate is smaller than the orthographic area of the organic semiconductor layer on the substrate, and the gate is on the substrate The orthographic area of the substrate is located within the orthographic projection of the organic semiconductor layer on the base substrate;
  • the area of the orthographic projection of the organic semiconductor layer on the base substrate is approximately equal to the area of the orthographic projection of the organic gate insulating layer on the base substrate, and the orthographic area of the organic semiconductor layer on the base substrate The projection roughly coincides with the orthographic projection of the organic gate insulating layer on the base substrate.
  • the display substrate further includes a planar layer located between the organic thin film transistor and the base substrate, and the planar layer is connected to the organic protective layer at the first hollow structure. layers in direct contact.
  • the planar layer includes a first planar layer and a second planar layer stacked in layers, and the second planar layer is located on a side of the first planar layer away from the base substrate. On the side, the second planar layer is in direct contact with the organic protective layer at the first hollow structure.
  • the display substrate includes a shielding layer located between the first flat layer and the second flat layer, and the orthographic area of the organic semiconductor layer on the base substrate is smaller than The area of the orthographic projection of the shielding layer on the base substrate, and the orthographic projection of the organic semiconductor layer on the base substrate is located within the orthographic projection of the shielding layer on the base substrate.
  • the material of the shielding layer includes metal or black resin.
  • the first electrode is electrically connected to the source and drain; the first electrode is a pixel electrode, and the second electrode is a common electrode; the material of the first electrode is the same as the The material of the second electrode is the same; the substrate is an organic flexible substrate.
  • the material of the first electrode includes indium tin oxide or indium gallium zinc oxide.
  • An embodiment of the present disclosure further provides a display device, which includes the display substrate provided in the embodiment of the present disclosure, and further includes an opposite substrate opposite to the display substrate, and a display device located between the display substrate and the display substrate.
  • the liquid crystal layer between the opposing substrates.
  • An embodiment of the present disclosure also provides a method for manufacturing a display substrate, including:
  • An organic thin film transistor and a first electrode are formed on one side of the base substrate, wherein the organic thin film transistor includes a gate, an organic semiconductor layer, and a source and drain, and the first electrode includes a plurality of first hollow structures;
  • An organic protective layer covering the organic thin film transistor, the first electrode, and filling the first hollow structure is formed.
  • the forming an organic thin film transistor and a first electrode on one side of the base substrate includes:
  • the first electrode with a plurality of first hollow structures on the side of the source and drain away from the substrate;
  • a gate is formed on a side of the organic gate insulating layer away from the organic semiconductor layer.
  • the manufacturing method further includes:
  • the patterned metal layer includes a first pattern, and a gate line;
  • the first pattern is removed by etching.
  • the formation of the patterned metal layer on the side of the second thin film layer away from the organic protective layer includes: performing a first wet etching process on the second thin film layer facing away from the side of the organic protective layer forming a patterned metal layer;
  • the etching the second film layer under the shield of the patterned metal layer includes: performing a second wet etching process on the second thin film layer under the shield of the patterned metal layer.
  • the thin film layer is etched;
  • the etching to remove the first pattern includes: performing a third wet etching process to etch and remove the first pattern while retaining the gate lines.
  • the etching of the second thin film layer under the shield of the patterned metal layer through the second wet etching process includes:
  • the second thin film layer is etched under the shield of the patterned metal layer, and the orthographic projection area of the second electrode formed on the base substrate is made is smaller than the area of the orthographic projection of the first pattern on the base substrate, and the orthographic projection of the second electrode on the base substrate is located within the orthographic projection of the first pattern on the base substrate, and make the orthographic projection area of the connection electrode on the base substrate smaller than the orthographic projection area of the grid line on the base substrate, and make the orthographic projection of the connection electrode on the base substrate be located at the The grid lines are within the orthographic projection of the substrate substrate.
  • the manufacturing method when the etching removes the first pattern, the manufacturing method further includes:
  • the orthographic projection of the base substrate is located within the orthographic projection of the connection electrode on the base substrate.
  • the formation of the organic protective layer covering the organic thin film transistor, the first electrode, and filling the first hollow structure includes:
  • FIG. 1A is one of the cross-sectional views of a display substrate provided by an embodiment of the present disclosure
  • FIG. 1B is the second cross-sectional view of a display substrate provided by an embodiment of the present disclosure
  • FIG. 2 is one of the top views of a display substrate provided by an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of a first electrode and a second electrode provided by an embodiment of the present disclosure
  • FIG. 5 is a schematic diagram of the electric field when the line width of the first electrode strip is larger than that of the second hollow structure;
  • Fig. 6 is a schematic diagram of the electric field when the first electrode has no first hollow structure
  • FIG. 7 is a schematic diagram of the relationship between gate lines and connecting electrodes provided by an embodiment of the present disclosure.
  • FIG. 8 is a schematic cross-sectional view of a display device provided by an embodiment of the present disclosure.
  • FIG. 9 is one of the schematic diagrams of the manufacturing process of the display substrate provided by the embodiment of the present disclosure.
  • FIG. 10 is the second schematic diagram of the manufacturing process of the display substrate provided by the embodiment of the present disclosure.
  • FIG. 11 is the third schematic diagram of the manufacturing process of the display substrate provided by the embodiment of the present disclosure.
  • FIG. 12 is a schematic cross-sectional view of a display substrate with source and drain electrodes fabricated according to an embodiment of the present disclosure
  • FIG. 13 is a schematic top view of source and drain provided by an embodiment of the present disclosure.
  • FIG. 14 is a schematic cross-sectional view of a display substrate with a first electrode fabricated according to an embodiment of the present disclosure
  • FIG. 15 is a schematic top view of a first electrode provided by an embodiment of the present disclosure.
  • 16 is a schematic cross-sectional view of a display substrate with gates fabricated according to an embodiment of the present disclosure
  • FIG. 17 is a schematic top view of an organic semiconductor layer provided by an embodiment of the present disclosure.
  • FIG. 18 is a schematic top view of a gate provided by an embodiment of the present disclosure.
  • 19 is a schematic cross-sectional view of a display substrate with an organic protective layer provided by an embodiment of the present disclosure
  • FIG. 20 is a schematic cross-sectional view of a display substrate with a gate line metal thin film layer provided by an embodiment of the present disclosure
  • 21 is a schematic cross-sectional view of a fabricated display substrate including gate lines and a first pattern provided by an embodiment of the present disclosure
  • FIG. 22 is a schematic cross-sectional view of a display substrate etched with a first pattern for a second electrode provided by an embodiment of the present disclosure
  • FIG. 23 is a schematic top view of a second electrode provided by an embodiment of the present disclosure.
  • FIG. 24 is a schematic cross-sectional view of a display substrate after removing the first pattern provided by an embodiment of the present disclosure
  • FIG. 25 is a schematic top view of grid lines provided by an embodiment of the present disclosure.
  • FIG. 1A is a schematic cross-sectional view of FIG.
  • FIG. 1A is a schematic cross-sectional view of FIG.
  • the pixels P include:
  • An organic thin film transistor 3 the organic thin film transistor 3 includes a gate 34, an organic semiconductor layer 33, and a source and drain 31;
  • the first electrode 41, the first electrode 41 has a plurality of first hollow structures 410;
  • the organic protection layer 5 covers the first electrode 41 and the organic thin film transistor 3 , and fills the first hollow structure 410 .
  • the first electrode 41 has a plurality of first hollow structures 410
  • the organic protection layer 5 covers the first electrode 41 and the organic thin film transistor 3, and fills the first hollow structures 410
  • the first electrode The multiple first hollow structures 410 of 41 make the first electrode 41 have a concavo-convex structure, improve the surface roughness of the first electrode 41, reduce the interface ratio between the organic protective layer 5 and the inorganic first electrode 41, and improve the thickness of the first electrode 41.
  • the adhesion to the organic protective layer 5 avoids the problem of delamination or peeling between the organic protective layer 5 and the first electrode 41 .
  • the material of the organic protective layer 5 may be propylene glycol methyl ether acetate or photosensitive resin.
  • the pixel P includes a second electrode 42 located on the side of the organic protection layer 5 away from the first electrode 41;
  • the first electrode 41 includes a plurality of first electrode strips 411 extending along the first direction AB and electrically connected to each other. There is a first hollow structure 410 between adjacent first electrode strips 411; the second electrode 42 includes a plurality of electrodes along the first direction AB. The second electrode strips 421 extending in the direction AB and electrically connected to each other, and the second hollow structure 420 located between adjacent second electrode strips 421; the orthographic area of the second hollow structure 420 on the base substrate 1 is smaller than that of the first electrode The area of the orthographic projection of the bar 411 on the base substrate 1 , and the orthographic projection of the second hollow structure 420 on the base substrate 1 is located within the orthographic projection of the first electrode strip 411 on the base substrate 1 .
  • Fig. 2 and Fig. 3 only show the situation that the first electrode strip 411 extends along the first direction AB, but the embodiment of the present disclosure is not limited thereto, for example, the first electrode strip 411 may be a broken line shape, the first electrode strip 411 includes a part extending along the first direction AB, and a part extending along the second direction at the same time, the angle between the first direction AB and the second direction is not equal to 0 or 180; similarly, Fig. 2, Fig. 3 The figure only shows the situation that the second electrode strip 421 extends along the first direction AB, but the embodiment of the present disclosure is not limited thereto.
  • the angle between the first direction AB and the second direction is not equal to 0 or 180; correspondingly, the first hollow structure 410 and the second hollow structure 420 still meet the current requirements these restrictions.
  • the orthographic area of the second hollow structure 420 on the substrate 1 is larger than the orthographic area of the first electrode strip 411 on the substrate 1, and the first electrode strip 411
  • the orthographic projection of the base substrate 1 is located within the orthographic projection of the second hollow structure 420 on the base substrate 1.
  • the projected area is smaller than the orthographic projection area of the first electrode strip 411 on the substrate 1, and the orthographic projection of the second hollow structure 420 on the substrate 1 is located within the orthographic projection of the first electrode strip 411 on the substrate 1, which produces
  • the electric field is equivalent to the electric field generated when the first electrode 41 is not provided with the first hollow structure 410 (as shown in FIG. 6 ), that is, it has a strong effective electric field and can effectively control the deflection of the liquid crystal.
  • the orthographic projection of the first electrode strip 411 on the base substrate 1 is in the same position as the second electrode strip 421 around the second hollow structure 420 The orthographic projections of the base substrate 1 overlap.
  • the line width D of the first electrode strip 411 on the plane parallel to the base substrate 1 and perpendicular to the first direction AB is greater than that of the second hollow
  • the structure 420 has a width S in a plane parallel to the base substrate 1 and perpendicular to the first direction AB.
  • the first hollow structure 410 may be strip-shaped and located between two adjacent first electrode strips 411 .
  • FIG. 1A, FIG. 2, FIG. 3, and FIG. 5 it is possible to hollow out a part of the first electrode 41, and the hollowed out area is used as the first hollow structure 410, and the adjacent first hollow structure The area between 410 is used as the first electrode strip 411 ; the first hollow structure 410 may be strip-shaped and located between two adjacent first electrode strips 411 .
  • the first hollow structures 410 and the first electrode strips 411 are arranged alternately;
  • the width h1 on the plane of the base substrate 1 and perpendicular to the first direction AB can be the same;
  • the line width D of each first electrode strip 411 can be the same on the plane parallel to the base substrate 1 and perpendicular to the first direction AB;
  • the line width D of the strip 411 on the plane parallel to the base substrate 1 and perpendicular to the first direction AB may be larger than the width h1 of the first hollow structure 410 on the plane parallel to the base substrate 1 and perpendicular to the first direction AB.
  • the second hollow structures 420 and the second electrode strips 421 are arranged alternately; the width S of each second hollow structure 420 on the plane parallel to the base substrate 1 and perpendicular to the first direction AB can be the same ;
  • Each second electrode strip 421 can have the same line width h2 on a plane parallel to the base substrate 1 and perpendicular to the first direction AB; the second electrode strip 421 is on a plane parallel to the base substrate 1 and perpendicular to the first direction AB
  • the upper line width h2 may be smaller than the width S of the second hollow structure 420 on a plane parallel to the base substrate 1 and perpendicular to the first direction AB.
  • the line width D of the first electrode strip 411 on the plane parallel to the base substrate 1 and perpendicular to the first direction AB may be larger than the line width of the second electrode strip 421 on the plane parallel to the base substrate 1 and perpendicular to the first direction AB h2; the width h1 of the first hollow structure 410 on a plane parallel to the base substrate 1 and perpendicular to the first direction AB may be smaller than that of the second hollow structure 420 on a plane parallel to the base substrate 1 and perpendicular to the first direction Width S on AB.
  • the display substrate further includes a gate line 6 electrically connected to the gate 34 , and the materials of the gate line 6 and the gate 34 are different.
  • the material of the gate 34 may include indium tin oxide or indium gallium zinc oxide; the material of the gate line 6 may include molybdenum (Mo); the material of the source and drain electrodes 31 may include silver; the organic semiconductor layer 32, the organic gate insulation
  • the material of layer 33 may comprise a non-crosslinked material.
  • the materials of the gate line 6 and the gate 34 are not the same, so that if the material of the gate 34 is the same as that of the gate line 6 (the material of the gate 34 is also Mo), the gate 34 is During etching, since the organic semiconductor layer 32 and the organic gate insulating layer 33 are non-crosslinked materials, it is impossible to effectively block the corrosion of the source and drain electrodes 31 by the Mo etching solution, which in turn will affect the pattern of the source and drain electrodes 31, while the gate line 6 Different from the material of the gate 34, for example, the material of the gate line 6 is Mo, the material of the gate 34 is indium tin oxide, and the etchant for etching the gate 34 will not corrode the source and drain 31 , and then can not influence the pattern of source drain 31, that is, the material of source drain 31 comprises Ag; Therefore, the requirement for the material of the gate line 6 is that its wet etching solution must not corrode the source and drain electrodes 31 .
  • the gate line 6 is mainly due to wiring resistance considerations, Mo can be selected if there is no special requirement.
  • the organic semiconductor film layer, the organic gate insulating film layer coating and the gate thin film layer can be formed sequentially. After that, the gate electrode 34 is patterned first by using a wet etching process, and then a photolithography+dry etching process is used to stack the gate 34.
  • the organic semiconductor layer 32 and the organic gate insulating layer 33 are patterned. Specifically, the patterns of the organic semiconductor layer 32 and the organic gate insulating layer 33 may be approximately the same.
  • the display substrate further includes a connection electrode 422 in the same layer as the second electrode 42 and insulated; the gate line 6 is located on the side of the connection electrode 422 away from the organic protective layer 5 And it is electrically connected to the connecting electrode; the connecting electrode 422 is electrically connected to the gate 34 through the via hole, so as to electrically connect the gate line 6 to the gate 34 .
  • the material of the organic semiconductor layer 32 may be polyacetylene type, polyaromatic ring type or copolymer type.
  • the material of the organic gate insulating layer 33 can be a polymer insulating material, specifically, the material of the organic gate insulating layer 33 can include: polyvinyl alcohol (Polyvinyl alcohol, PVA), polyvinyl alcohol Vinyl (Polyvinyl chloride, PVC), polyvinyl pyrrolidone (Polyvinyl pyrrolidone, PVP), polymethyl methacrylate (Polymethyl methacrylate, PMMA) or polystyrene (Polystyrene, PS).
  • polyvinyl alcohol Polyvinyl alcohol, PVA
  • polyvinyl alcohol Vinyl Polyvinyl chloride
  • PVP polyvinyl pyrrolidone
  • PMMA polymethyl methacrylate
  • PS polystyrene
  • the area of the orthographic projection of the grid line 6 on the substrate 1 is smaller than the area of the orthographic projection of the connecting electrode 422 on the substrate 1
  • the area of the orthographic projection of the grid line 6 on the substrate 1 is smaller than that of the connection electrode 422 on the substrate 1 .
  • the orthographic projection of the base substrate 1 is located within the orthographic projection of the connection electrode 422 on the base substrate 1 .
  • the area of the orthographic projection of the grid line 6 on the base substrate 1 is smaller than the area of the orthographic projection of the connection electrode 422 on the base substrate 1, and the orthographic projection of the grid line 6 on the base substrate 1 is located where the connection electrode 422 is on the substrate.
  • the connection electrode 422 (ITO) pattern is smaller than or equal to the pattern of the gate line 6 (Mo)
  • the connection electrode 422 (ITO) is under the extended part of the gate line 6 (Mo) relative to the connection electrode 422 (ITO).
  • the line width h2 of the second electrode strips 421 on a plane parallel to the base substrate 1 and perpendicular to the first direction AB ranges from 1 ⁇ m to 5 ⁇ m.
  • the line width h2 of the second electrode strip 421 on the plane parallel to the base substrate 1 and perpendicular to the first direction AB ranges from 1 ⁇ m to 3 ⁇ m;
  • the second electrode strip 421 on the plane parallel to the base substrate 1 And the line width h2 perpendicular to the first direction AB ranges from 1 ⁇ m to 2 ⁇ m;
  • the line width h2 of the second electrode strip 421 on a plane parallel to the base substrate 1 and perpendicular to the first direction AB ranges from 1 ⁇ m to 1.5 ⁇ m;
  • the line width h2 of the second electrode strip 421 on a plane parallel to the base substrate 1 and perpendicular to the first direction AB may be 1 ⁇ m;
  • the second electrode strip 421 is on a plane parallel to the base substrate 1 and
  • the line width h2 of the second electrode strip 421 on the plane parallel to the base substrate 1 and perpendicular to the first direction AB ranges from 1 ⁇ m to 5 ⁇ m, so that the second electrode 42 can be connected with the first electrode 41 A stronger electric field distribution is formed to prevent the formation of the second electrode 42 and the first electrode 41 from being reduced when the line width h2 of the second electrode strip 421 parallel to the plane of the base substrate 1 and perpendicular to the first direction AB is too wide. the electric field strength.
  • the first pattern 601 which is roughly the same pattern as the second electrode 42, is shielded by the first pattern 601 when forming the second electrode 42 by etching, so as to avoid the low temperature photolithography process for the second electrode 42 in the display substrate including organic thin film transistor
  • the etching rate is faster, and it is easy to form the second electrode strip 421 formed on a plane parallel to the base substrate 1 and vertically.
  • the problem that the line width h2 in the first direction AB is wider.
  • the first pattern is not used to block the etching, and the line width h2 of the formed second electrode strips 421 on the plane parallel to the base substrate 1 and perpendicular to the first direction AB is 4 ⁇ m ⁇ 5 ⁇ m.
  • the orthographic projection area of the first hollow structure 410 on the base substrate 1 accounts for 20%-80% of the orthographic projection area of the first electrode 41 on the base substrate 1 .
  • the organic thin film transistor 3 may be a top-gate thin film transistor.
  • the organic semiconductor layer 5 is located on the side of the source and drain electrodes 31 away from the substrate 1, and the gate 6 is located on the side of the organic semiconductor layer 32 away from the source and drain electrodes 31; an organic gate insulating layer 33 is provided between the gate 34 and the organic semiconductor layer 32.
  • the organic semiconductor layer 5 cannot withstand the bombardment of the metal electrode sputtering (sputter) process, the organic thin film transistor 3 has only two types of top gate bottom contact and bottom gate bottom contact in the selection of structure; In the organic thin film transistor 3 with the contact structure, the effective carrier transport efficiency is better.
  • the display panel of the embodiment of the present disclosure may use top-gate bottom-contact organic thin film crystals.
  • the organic thin film transistor 3 may also be a bottom gate thin film transistor, the organic semiconductor layer 32 is located on the side of the gate 34 away from the substrate 1 , and the source and drain 31 are located on There is an organic gate insulating layer 33 between the organic semiconductor layer 32 and the gate 34 ; and between the gate 34 and the source and drain 31 .
  • the area of the orthographic projection of the gate 34 on the base substrate 1 is smaller than the area of the orthographic projection of the organic semiconductor layer 32 on the base substrate 1, and the gate 34 is
  • the orthographic projection of the base substrate 1 is located within the orthographic projection of the organic semiconductor layer 32 on the base substrate 1; The areas are approximately equal, and the orthographic projection of the organic semiconductor layer 32 on the base substrate 1 approximately coincides with the orthographic projection of the organic gate insulating layer 33 on the base substrate 1 .
  • the area of the orthographic projection of the organic semiconductor layer 32 on the base substrate 1 is approximately equal to the area of the orthographic projection of the organic gate insulating layer 33 on the base substrate 1.
  • the ratio of the projected areas of the two is in the range of 1:0.8 ⁇ 1:1.2.
  • the orthographic projection of the organic semiconductor layer 32 on the base substrate 1 roughly coincides with the orthographic projection of the organic gate insulating layer 33 on the base substrate 1 , which can be understood as 80% to 100% overlap of the two orthographic projections.
  • the area of the orthographic projection of the organic semiconductor layer 32 on the base substrate 1 is approximately equal to the area of the orthographic projection of the organic gate insulating layer 33 on the base substrate 1, and the pattern is basically the same.
  • the layer 33 and the organic semiconductor layer 32 can be patterned by one-step dry etching, which can simplify the manufacturing process of the display substrate.
  • the display substrate further includes a planar layer 2 located between the organic thin film transistor 3 and the base substrate 1 , and the planar layer 2 is connected to the organic protective layer at the first hollow structure 410 5 direct contact.
  • the flat layer 2 is in direct contact with the organic protective layer 2 at the first hollow structure 410 , which can improve the adhesion of the organic protective layer 5 and improve the problem that the organic protective layer 5 is easy to peel off from the first electrode 41 .
  • the material of the flat layer 2 may be a fluorine-free resin material.
  • the planar layer 2 includes a first planar layer 21 and a second planar layer 22 stacked in layers, and the second planar layer 21 is located on the side of the first planar layer 21 away from the substrate.
  • the second planar layer 22 is in direct contact with the organic protective layer 5 at the first hollow structure 410 .
  • the materials of the first flat layer 21 and the second flat layer 22 can be the same, the first flat layer 21 is used to flatten and protect the underlying film layer, and the second flat layer 22 is used to flatten the first flat layer 21 and the second flat layer. Occlusion layer 7 between layers 22.
  • the materials of the first flat layer 21 and the second flat layer 22 may also be different.
  • the display substrate includes a shielding layer 7 located between the first flat layer 21 and the second flat layer 22, and the orthographic area of the organic semiconductor layer 5 on the base substrate 1 is smaller than that of the shielding layer 7 on the substrate.
  • the area of the orthographic projection of the base substrate 1 , and the orthographic projection of the organic semiconductor layer 5 on the base substrate 1 is located within the orthographic projection of the shielding layer 7 on the base substrate 1 .
  • the orthographic projection of the organic semiconductor layer 5 on the base substrate 1 is located within the orthographic projection of the shielding layer 7 on the base substrate 1, and the organic semiconductor layer 5 can be shielded by the shielding layer 7 to prevent the organic semiconductor layer 5 from When irradiated by light, photogenerated carriers are generated, which affects the performance of organic thin film transistors.
  • the material of the shielding layer 7 may include metal or black resin.
  • the first electrode 41 is electrically connected to the source and drain electrodes 31; the first electrode 41 is a pixel electrode, and the second electrode 42 is a common electrode; the material of the first electrode 41 and the material of the second electrode 42 same.
  • both the first electrode 41 and the second electrode 42 may be transparent electrodes.
  • the material of the first electrode 41 may be indium tin oxide, zinc oxide, tin oxide, titanium oxide, or graphene.
  • the source and drain 31 may include a source 311 and a drain 312 , the source 311 may be integrally connected with the data line 313 , and the drain Specifically, 312 may be electrically connected to the first electrode 41 .
  • the orthographic projection of the data line 313 on the base substrate 1 overlaps with the orthographic projection of the second electrode 42 on the base substrate 1 .
  • the base substrate 1 is an organic flexible base substrate.
  • an embodiment of the present disclosure also provides a display device, including the display substrate provided by the embodiment of the present disclosure, and also includes an opposite substrate 8 opposite to the display substrate, and a display device located between the display substrate and the opposite substrate. 8 between the liquid crystal layers 9 .
  • the display device provided by the embodiment of the present disclosure may also include other structures, for example, sealing the opposing substrate 8 and a basic sealing frame for display.
  • other structures can be set as required. The implementation of the present disclosure Examples are not limited to this.
  • an embodiment of the present disclosure also provides a method for manufacturing a display substrate, which includes:
  • Step S100 providing a base substrate
  • Step S200 forming an organic thin film transistor and a first electrode on one side of the substrate, wherein the organic thin film transistor includes a gate, an organic semiconductor layer, and a source and drain, and the first electrode includes a plurality of first hollow structures;
  • Step S300 forming an organic protective layer covering the organic thin film transistor, the first electrode, and filling the first hollow structure.
  • this step may include: forming an organic protective layer covering the organic thin film transistor, the first electrode, and filling the first hollow structure by spin coating; UV curing, and post-baking at a temperature of 50 degrees to 250 degrees craft.
  • step S200 forming an organic thin film transistor and a first electrode on one side of the base substrate includes:
  • Step S210 forming source and drain electrodes on one side of the base substrate
  • Step S220 forming a first electrode with a plurality of first hollow structures on the side of the source and drain away from the substrate;
  • Step S230 forming an organic semiconductor layer on the side of the first electrode away from the source and drain;
  • Step S240 forming an organic gate insulating layer on the side of the organic semiconductor layer away from the first electrode
  • Step S250 forming a gate on the side of the organic gate insulating layer facing away from the organic semiconductor layer.
  • the manufacturing method further includes:
  • Step S400 forming a second thin film layer on the side of the organic protective layer away from the gate;
  • Step S500 forming a patterned metal layer on the side of the second thin film layer away from the organic protection layer, the patterned metal layer includes the first pattern and the gate line; specifically, it may be through the first wet etching process, A patterned metal layer is formed on the side of the second film layer away from the organic protective layer;
  • Step S600 etching the second thin film layer under the shield of the patterned metal layer to form a patterned second electrode and a connecting electrode, wherein the pattern of the second electrode is substantially the same as the first pattern, and the pattern of the connecting electrode It is roughly the same as the pattern of the grid line;
  • the second thin film layer may be etched under the shield of the patterned metal layer through a second wet etching process
  • the second thin film layer may be etched under the shield of the patterned metal layer through the second wet etching process, and the area of the orthographic projection of the second electrode on the base substrate is smaller than that of the first pattern.
  • the area of the orthographic projection of the base substrate, and the orthographic projection of the second electrode on the base substrate is located in the orthographic projection of the first pattern on the base substrate, and the orthographic projection area of the connecting electrode on the base substrate is smaller than that of the grid line on the substrate.
  • the orthographic projection area of the base substrate, and the orthographic projection of the connection electrode on the base substrate is located within the orthographic projection of the grid line on the base substrate;
  • Step S700 etching and removing the first pattern.
  • the manufacturing method may further include: etching a part of the gate line, so that the orthographic projection area of the grid line on the base substrate is smaller than the orthographic projection area of the connecting electrode on the base substrate , and the orthographic projection of the grid lines on the base substrate is located within the orthographic projection of the connecting electrodes on the base substrate.
  • Step 1 Provide a base substrate 1; specifically, the base substrate 1 can be a flexible organic base substrate, and the base substrate 1 can be attached to the glass substrate 12 through the adhesive layer 11 to facilitate subsequent film production. , after the fabrication of the display substrate is finally completed, the glass substrate 12, the adhesive layer 11 and the base substrate 1 can be peeled off;
  • Step 2 sequentially forming a first flat layer 21, a shielding layer 7, and a second flat layer 22 on one side of the base substrate 1;
  • Step 3 Form patterned source and drain electrodes 31 on the side of the second planar layer 22 away from the shielding layer 7, wherein the source and drain electrodes 31 may include a source electrode 311 and a drain electrode 312, and the source electrode 311 may specifically be connected to the data line 313 are integrally connected, and the drain 312 may be electrically connected to the subsequently formed first electrode 41, as shown in FIGS. 12 and 13 ;
  • Step 4 Form the first electrode 41 with a plurality of first hollow structures 410 on the side of the source and drain electrodes 31 facing away from the base substrate 1, as shown in FIG. 14 and FIG. 15, wherein FIG. Single-layer diagram; specifically, the first hollow structure 410 accounts for 20% to 80% of the total area of the first electrode 41, specifically, the first hollow structure 410 accounts for 30% to 70% of the total area of the first electrode 41, specifically Yes, the first hollow structure 410 accounts for 40% to 60% of the total area of the first electrode 41; specifically, specifically, the first hollow structure 410 accounts for 50% of the total area of the first electrode 41; specifically, the first hollow structure 410 accounts for 20% of the total area of the first electrode 41; specifically, the first hollow structure 410 accounts for 80% of the total area of the first electrode 41;
  • the first electrode 41 is made into a finger-like (finger) pattern, and is distributed alternately with the finger-like (finger) pattern of the second electrode 42 formed subsequently;
  • the first electrode strip 411 is parallel to the plane of the substrate 1 and vertical
  • the line width in the first direction AB is D
  • the width of the second hollow structure 420 of the second electrode 42 formed later on the plane parallel to the base substrate 1 and perpendicular to the first direction AB is S; with reference to FIG. 2 , shown in Figure 4, Figure 5 and Figure 6;
  • the effective electric field is smaller than the structure of the first electrode 41 without a finger pattern, which further leads to a decrease in the light efficiency of the device;
  • the finger line width D of the first electrode 41 needs to be greater than the finger line distance S of the second electrode, that is, D>S;
  • Step five forming an organic semiconductor layer 32 on the side of the first electrode 41 away from the source and drain electrodes 31; forming an organic gate insulating layer 33 on the side of the organic semiconductor layer 42 away from the first electrode 41; forming an organic gate insulating layer 33 on the organic gate insulating layer 33 A gate 34 is formed on a side away from the organic semiconductor layer 32, as shown in FIG. 16, FIG. 17 and FIG. 18;
  • the coating and film formation of the organic semiconductor film layer and the organic gate insulating film layer can be completed in sequence, and then the patterned gate 34 is fabricated, and then the stacking of the organic semiconductor film layer and the organic gate insulating film layer Perform patterning to form an organic semiconductor layer 32 and an organic gate insulating layer 33;
  • Step 6 coating and film forming of the organic protective film
  • Step 7 patterning the organic protective layer film to form an organic protective layer 5 with via holes for the gate 34 exposed, as shown in FIG. 19 ;
  • Step 8 sputtering deposits the second thin film layer 424 (for making the film layer of the second electrode 42), as shown in FIG. 20 ;
  • Step 9 sputtering and depositing the gate line metal thin film 60 (for making the film layer of the gate line 6 ), as shown in FIG. 20 ;
  • a patterned metal layer is formed on the side, wherein the patterned metal layer includes a first pattern 601 and gate lines 6, as shown in FIG. 21 ;
  • Step 10 Through the second wet etching process, the second thin film layer 424 is etched under the shield of the patterned metal layer to form the patterned second electrode 42 and the connecting electrode 422, as shown in FIG. 22 and FIG. 23 As shown, wherein, the pattern of the second electrode 42 is approximately the same as the first pattern 601, and the pattern of the connecting electrode 422 is approximately the same as the pattern of the gate line 6; The second thin film layer 424 is wet etched for the second time;
  • the area of the orthographic projection of the second electrode 42 on the base substrate 1 can be made smaller than the area of the orthographic projection of the first pattern 601 on the base substrate 1, and the second electrode 42 can be formed on the base substrate.
  • the orthographic projection of 1 is located in the orthographic projection of the first pattern 601 on the base substrate 1, and the orthographic projection area of the connection electrode 422 on the base substrate is smaller than the orthographic projection area of the grid line 6 on the base substrate 1, and the connection electrode
  • the orthographic projection of 422 on the base substrate 1 is located within the orthographic projection of the grid line 6 on the base substrate 1;
  • this method can greatly reduce the excessive line width (bias) of the second electrode strip 421 obtained under the low temperature photolithography process.
  • Step 11 Etching and removing the first pattern 601 through the third wet etching process, leaving the gate line 4 , as shown in FIG. 24 and FIG. 25 .
  • the manufacturing method may further include: etching a part of the gate line 6 so that the gate line 6 is on the positive side of the base substrate 1 .
  • the projected area is smaller than the orthographic projection area of the connection electrode 422 on the base substrate 1, and the orthographic projection of the grid line 6 on the base substrate 1 is located within the orthographic projection of the connection electrode 422 on the base substrate 1;
  • the first electrode 41 has a plurality of first hollow structures 410
  • the organic protection layer 5 covers the first electrode 41 and the organic thin film transistor 3, and fills the first hollow structures 410
  • the first electrode The multiple first hollow structures 410 of 41 make the first electrode 41 have a concavo-convex structure, improve the surface roughness of the first electrode 41, reduce the interface ratio between the organic protective layer 5 and the inorganic first electrode 41, and improve the thickness of the first electrode 41.
  • the adhesion to the organic protective layer 5 avoids the problem of delamination or peeling between the organic protective layer 5 and the first electrode 41 .

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Abstract

本公开实施例提供一种显示基板、显示装置和显示基板的制作方法。所述显示基板具有衬底基板，以及位于所述衬底基板一侧的多个像素，所述像素包括：有机薄膜晶体管，所述有机薄膜晶体管包括栅极、有机半导体层以及源漏极；第一电极，所述第一电极具有多个第一镂空结构；有机保护层，所述有机保护层覆盖所述第一电极以及所述有机薄膜晶体管，并填充所述第一镂空结构。

Description

显示基板、显示装置和显示基板的制作方法 技术领域
本公开涉及半导体技术领域，尤其涉及一种显示基板、显示装置和显示基板的制作方法。
背景技术
有机薄膜晶体管优异的耐弯折特性及较低的工艺温度，被认为非常适合作为低耐热塑料衬底柔性液晶显示器背板技术使用。
发明内容
本公开实施例提供一种显示基板，其中，具有衬底基板，以及位于所述衬底基板一侧的多个像素，所述像素包括：
有机薄膜晶体管，所述有机薄膜晶体管包括栅极、有机半导体层以及源漏极；
第一电极，所述第一电极具有多个第一镂空结构；
有机保护层，所述有机保护层覆盖所述第一电极以及所述有机薄膜晶体管，并填充所述第一镂空结构。
在一种可能的实施方式中，所述像素包括位于所述有机保护层背离所述第一电极一侧的第二电极；
所述第一电极包括多个沿第一方向延伸且相互电连接的第一电极条，相邻所述第一电极条之间具有所述第一镂空结构；所述第二电极包括多个沿所述第一方向延伸且相互电连接的第二电极条，以及位于相邻所述第二电极条之间的第二镂空结构；
所述第二镂空结构在所述衬底基板的正投影面积小于所述第一电极条在所述衬底基板的正投影面积，且所述第二镂空结构在所述衬底基板的正投影位于所述第一电极条在所述衬底基板的正投影内。
在一种可能的实施方式中，所述第一电极条在所述衬底基板的正投影，与所述第二镂空结构周边所述第二电极条的部分在所述衬底基板的正投影交叠。
在一种可能的实施方式中，所述第一电极条在平行于所述衬底基板的平面且垂直于所述第一方向上线宽，大于所述第二镂空结构在平行于所述衬底基板的平面且垂直于所述第一方向上的宽度。
在一种可能的实施方式中，其中，所述显示基板还包括栅线，所述栅线与所述栅极电连接，所述栅线与所述栅极的材料不相同。
在一种可能的实施方式中，所述显示基板还包括与所述第二电极同层且绝缘的连接电极；所述栅线位于所述连接电极背离所述有机保护层一侧且与所述连接电极接触电连接；所述连接电极通过过孔与所述栅极电连接，以将所述栅线与所述栅极电连接。
在一种可能的实施方式中，所述栅线的材料包括钼；所述栅极的材料包括氧化铟锡或氧化铟镓锌。
在一种可能的实施方式中，所述栅线在所述衬底基板的正投影面积小于所述连接电极在所述衬底基板的正投影面积，且所述栅线在所述衬底基板的正投影位于所述连接电极在所述衬底基板的正投影内。
在一种可能的实施方式中，所述第二电极条在平行于所述衬底基板的平面且垂直于所述第一方向上的线宽范围为：1μm～5μm。
在一种可能的实施方式中，所述第一镂空结构在所述衬底基板的正投影面积占所述第一电极在所述衬底基板正投影面积的20％～80％。
在一种可能的实施方式中，所述有机半导体层位于所述源漏极背离所述衬底基板的一侧，所述栅极位于所述有机半导体层背离所述源漏极的一侧；
所述栅极与所述有机半导体层之间具有有机栅极绝缘层。
在一种可能的实施方式中，所述有机半导体层位于所述栅极背离所述衬底基板的一侧，所述源漏极位于所述有机半导体层与所述栅极之间；
所述栅极与所述源漏极之间具有有机栅极绝缘层。
在一种可能的实施方式中，所述栅极在所述衬底基板的正投影面积小于所述有机半导体层在所述衬底基板的正投影面积，且所述栅极在所述衬底基板的正投影面积位于所述有机半导体层在所述衬底基板的正投影内；
所述有机半导体层在所述衬底基板的正投影面积与所述有机栅极绝缘层在所述衬底基板的正投影面积大致相等，且所述有机半导体层在所述衬底基板的正投影与所述有机栅极绝缘层在所述衬底基板的正投影大致重合。
在一种可能的实施方式中，所述显示基板还包括位于所述有机薄膜晶体管与所述衬底基板之间的平坦层，所述平坦层在所述第一镂空结构处与所述有机保护层直接接触。
在一种可能的实施方式中，所述平坦层包括叠层设置的第一平坦层和第二平坦层，所述第二平坦层位于所述第一平坦层的背离所述衬底基板的一侧，所述第二平坦层在所述第一镂空结构处与所述有机保护层直接接触。
在一种可能的实施方式中，所述显示基板包括位于所述第一平坦层与所述第二平坦层之间的遮挡层，所述有机半导体层在所述衬底基板的正投影面积小于所述遮挡层在所述衬底基板的正投影的面积，且所述有机半导体层在所述衬底基板的正投影位于所述遮挡层在所述衬底基板的正投影内。
在一种可能的实施方式中，所述遮挡层的材料包括金属或黑色树脂。
在一种可能的实施方式中，所述第一电极与所述源漏极电连接；所述第一电极为像素电极，所述第二电极为公共电极；所述第一电极的材料与所述第二电极的材料相同；所述衬底基板为有机柔性衬底基板。
在一种可能的实施方式中，所述第一电极的材料包括氧化铟锡或氧化铟镓锌。
本公开实施例还提供一种显示装置，其中，包括如本公开实施例提供的所述显示基板，还包括与所述显示基板相对而置的对向基板，以及位于所述显示基板与所述对向基板之间的液晶层。
本公开实施例还提供一种显示基板的制作方法，其中，包括：
提供一衬底基板；
在所述衬底基板的一侧形成有机薄膜晶体管以及第一电极，其中，有机薄膜晶体管包括栅极、有机半导体层以及源漏极，所述第一电极包括多个第一镂空结构；
形成覆盖所述有机薄膜晶体管，所述第一电极、以及填充所述第一镂空结构的有机保护层。
在一种可能的实施方式中，所述在所述衬底基板的一侧形成有机薄膜晶体管以及第一电极，包括：
在所述衬底基板的一侧形成源漏极；
在所述源漏极背离所述衬底基板的一侧形成具有多个所述第一镂空结构的所述第一电极；
在所述第一电极背离所述源漏极的一侧形成有机半导体层；
在所述有机半导体层背离所述第一电极的一侧形成有机栅极绝缘层；
在所述有机栅极绝缘层背离所述有机半导体层的一侧形成栅极。
在一种可能的实施方式中，在形成覆盖所述有机薄膜晶体管，所述第一电极、以及填充所述第一镂空结构的有机保护层之后，所述制作方法还包括：
在所述有机保护层的背离所述栅极的一侧形成第二薄膜层；
在所述第二薄膜层背离所述有机保护层的一侧形成图案化的金属层，图案化的所述金属层包括第一图案，以及栅线；
在图案化的所述金属层的遮挡下对所述第二薄膜层进行刻蚀，形成图案化的第二电极以及连接电极，其中，所述第二电极的图案与所述第一图案大致相同，所述连接电极的图案与所述栅线的图案大致相同；
刻蚀去除所述第一图案。
在一种可能的实施方式中，所述在所述第二薄膜层背离所述有机保护层的一侧形成图案化的金属层，包括：通过第一次湿刻工艺，在所述第二薄膜层背离所述有机保护层的一侧形成图案化的金属层；
所述在图案化的所述金属层的遮挡下对所述第二薄膜层进行刻蚀，包括：通过第二次湿刻工艺，在图案化的所述金属层的遮挡下对所述第二薄膜层进 行刻蚀；
所述刻蚀去除所述第一图案，包括：通过第三次湿刻工艺，刻蚀去除所述第一图案，保留所述栅线。
在一种可能的实施方式中，所述通过第二次湿刻工艺，在图案化的所述金属层的遮挡下对所述第二薄膜层进行刻蚀，包括：
通过第二次湿刻工艺，在图案化的所述金属层的遮挡下对所述第二薄膜层进行刻蚀，并使所述形成所述第二电极在所述衬底基板的正投影面积小于所述第一图案在所述衬底基板的正投影面积，且使所述第二电极在所述衬底基板的正投影位于所述第一图案在所述衬底基板的正投影内，以及使所述连接电极在所述衬底基板的正投影面积小于所述栅线在所述衬底基板的正投影面积，且使所述连接电极在所述衬底基板的正投影位于所述栅线在所述衬底基板的正投影内。
在一种可能的实施方式中，在所述刻蚀去除所述第一图案时，所述制作方法还包括：
对所述栅线的部分进行刻蚀，以使所述栅线在所述衬底基板的正投影面积小于所述连接电极在所述衬底基板的正投影面积，且使所述栅线在所述衬底基板的正投影位于所述连接电极在所述衬底基板的正投影内。
在一种可能的实施方式中，所述形成覆盖所述有机薄膜晶体管，所述第一电极、以及填充所述第一镂空结构的有机保护层，包括：
通过旋涂方式，形成覆盖所述有机薄膜晶体管，所述第一电极、以及填充所述第一镂空结构的有机保护层；
紫外固化，并在50度～250度的温度进行后烘的工艺。
附图说明
图1A为本公开实施例提供的显示基板的剖视图之一；
图1B为本公开实施例提供的显示基板的剖视图之二；
图2为本公开实施例提供的显示基板的俯视图之一；
图3为本公开实施例提供的第一电极与第二电极的示意图；
图4为第一电极条线宽小于第二镂空结构时的电场示意图；
图5为第一电极条线宽大于第二镂空结构时的电场示意图；
图6为第一电极无第一镂空结构时的电场示意图；
图7为本公开实施例提供的栅线与连接电极的关系示意图；
图8为本公开实施例提供的一种显示装置的剖视示意图；
图9为本公开实施例提供的显示基板的制作流程示意图之一；
图10为本公开实施例提供的显示基板的制作流程示意图之二；
图11为本公开实施例提供的显示基板的制作流程示意图之三；
图12为本公开实施例提供的制作完源漏极的显示基板剖视示意图；
图13为本公开实施例提供的源漏极俯视示意图；
图14为本公开实施例提供的制作完第一电极的显示基板剖视示意图；
图15为本公开实施例提供的第一电极的俯视示意图；
图16为本公开实施例提供的制作完栅极的显示基板剖视示意图；
图17为本公开实施例提供的有机半导体层的俯视示意图；
图18为本公开实施例提供的栅极的俯视示意图；
图19为本公开实施例提供的制作完有机保护层的显示基板剖视示意图；
图20为本公开实施例提供的制作完栅线金属薄膜层的显示基板剖视示意图；
图21为本公开实施例提供的制作完包括栅线与第一图案的显示基板剖视示意图；
图22为本公开实施例提供的利用第一图案刻蚀第二电极的显示基板剖视示意图；
图23为本公开实施例提供的第二电极的俯视示意图；
图24为本公开实施例提供的去除第一图案后的显示基板剖视示意图；
图25为本公开实施例提供的栅线的俯视示意图。
具体实施方式
为了使得本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
为了保持本公开实施例的以下说明清楚且简明，本公开省略了已知功能和已知部件的详细说明。
基于有机薄膜晶体管的显示基板，因为较低的工艺温度以及有机/无机介面等因素，导致在实际器件工艺当中容易出现介面附著力不佳，且进一步发生膜层剥离(peeling)等问题，因此如何在确保低工艺温度的条件下改善膜层附著力是一项技术关键。
实际操作中，因有机薄膜晶体管的保护层(材料为有机材料)本身特性，及使用较低的成膜固化温度，导致工艺中容易与第一透明电极发生peeling不良。
有鉴于此，本公开实施例提供一种显示基板，参见图1A、图2和图3所示，其中，图1A为图2沿虚线EF的截面示意图，显示基板具有衬底基板1，以及位于衬底基板1一侧的多个像素P，像素P包括：
有机薄膜晶体管3，有机薄膜晶体管3包括栅极34、有机半导体层33以及源漏极31；
第一电极41，第一电极41具有多个第一镂空结构410；
有机保护层5，有机保护层5覆盖第一电极41以及有机薄膜晶体管3，并填充第一镂空结构410。
本公开实施例提供的显示面板，其中，第一电极41具有多个第一镂空结构410，有机保护层5覆盖第一电极41以及有机薄膜晶体管3，并填充第一镂空结构410，第一电极41的多个第一镂空结构410使第一电极41具有凹凸结构，提高了第一电极41的表面粗糙度，降低有机保护层5与无机第一电极41的界面占比，提高第一电极41与有机保护层5的附著力，避免有机保护层5与第一电极41发生分层或剥离的不良问题。
在一种可能的实施方式中，有机保护层5的材料可以是丙二醇甲醚醋酸酯或光敏树脂。
在一种可能的实施方式中，结合图1A、图2和图3所示，像素P包括位于有机保护层5背离第一电极41一侧的第二电极42；
第一电极41包括多个沿第一方向AB延伸且相互电连接的第一电极条411，相邻第一电极条411之间具有第一镂空结构410；第二电极42包括多个沿第一方向AB延伸且相互电连接的第二电极条421，以及位于相邻第二电极条421之间的第二镂空结构420；第二镂空结构420在衬底基板1的正投影面积小于第一电极条411在衬底基板1的正投影面积，且第二镂空结构420在衬底基板1的正投影位于第一电极条411在衬底基板1的正投影内。
需要说明的是，图2、图3中仅示出了第一电极条411沿第一方向AB延伸的情形，但本公开实施例并不以此为限，例如第一电极条411可以为折线状，第一电极条411包括沿第一方向AB延伸的部分，同时沿第二方向延伸的部分，第一方向AB和第二方向夹角不等于0或者180；类似的，图2、图3中仅示出了第二电极条421沿第一方向AB延伸的情形，但本公开实施例并不以此为限，例如第二电极条421可以为折线状，第二电极条421包括沿第一 方向AB延伸的部分，同时沿第二方向延伸的部分，第一方向AB和第二方向夹角不等于0或者180；相应的，第一镂空结构410和第二镂空结构420依旧满足当前的这些限定。
在具体实施时，相比于如图4的结构，第二镂空结构420在衬底基板1的正投影面积大于第一电极条411在衬底基板1的正投影面积，且第一电极条411在衬底基板1的正投影位于第二镂空结构420在衬底基板1的正投影内，本公开实施例中，如图5所示的结构，第二镂空结构420在衬底基板1的正投影面积小于第一电极条411在衬底基板1的正投影面积，且第二镂空结构420在衬底基板1的正投影位于第一电极条411在衬底基板1的正投影内，其产生的电场，与第一电极41不设置第一镂空结构410时的结构(如图6所示)，产生的电场等效，即，具有较强的有效电场，可以有效的控制液晶的偏转。
在一种可能的实施方式中，结合图1A、图2或图5所示，第一电极条411在衬底基板1的正投影，与第二镂空结构420周边第二电极条421的部分在衬底基板1的正投影交叠。
在一种可能的实施方式中，结合图1A、图2或图5所示，第一电极条411在平行于衬底基板1的平面且垂直于第一方向AB上线宽D，大于第二镂空结构420在平行于衬底基板1的平面且垂直于第一方向AB上的宽度S。
在具体实施时，结合图1A、图2、图3、图5所示，可以通过在第一电极41的部分区域挖空，挖空的区域作为第一镂空结构410，相邻第一镂空结构410之间的区域作为第一电极条411；第一镂空结构410可以为条状，位于相邻两个第一电极条411之间。具体的，结合图1A、图2、图3、图5所示，同一第一电极41中，第一镂空结构410与第一电极条411交替排布；各第一镂空结构410在平行于衬底基板1的平面且垂直于第一方向AB上的宽度h1可以相同；各第一电极条411在平行于衬底基板1的平面且垂直于第一方向AB上线宽D可以相同；第一电极条411在平行于衬底基板1的平面且垂直于第一方向AB上线宽D，可以大于第一镂空结构410在平行于衬底基板1的平 面且垂直于第一方向AB上的宽度h1。同一第二电极41中，第二镂空结构420与第二电极条421交替排布；各第二镂空结构420在平行于衬底基板1的平面且垂直于第一方向AB上的宽度S可以相同；各第二电极条421在平行于衬底基板1的平面且垂直于第一方向AB上线宽h2可以相同；第二电极条421在平行于衬底基板1的平面且垂直于第一方向AB上线宽h2，可以小于第二镂空结构420在平行于衬底基板1的平面且垂直于第一方向AB上的宽度S。第一电极条411在平行于衬底基板1的平面且垂直于第一方向AB上线宽D，可以大于第二电极条421在平行于衬底基板1的平面且垂直于第一方向AB上线宽h2；第一镂空结构410在平行于衬底基板1的平面且垂直于第一方向AB上的宽度h1，可以小于第二镂空结构420在平行于衬底基板1的平面且垂直于第一方向AB上的宽度S。
在一种可能的实施方式中，结合图1A和图2所示，显示基板还包括栅线6，栅线6与栅极34电连接，栅线6与栅极34的材料不相同。具体的，栅极34的材料可以包括氧化铟锡或氧化铟镓锌；栅线6的材料可以包括钼(Mo)；源漏极31的材料可以包括银；有机半导体层32、有机栅极绝缘层33的材料可以包括非交联材料。本公开实施例中，栅线6与栅极34的材料不相同，可以避免若栅极34的材料与栅线6的材料相同(栅极34的材料也选择Mo)时，对栅极34进行刻蚀时，因有机半导体层32与有机栅极绝缘层33是非交联材料，无法有效阻挡Mo刻蚀液对源漏极31的腐蚀，进而会影响源漏极31的图案，而栅线6与栅极34的材料不相同，例如，栅线6的材料选择Mo，栅极34的材料选择氧化铟锡，刻蚀栅极34氧化铟锡的刻蚀液不会对源漏极31产生腐蚀，进而不会影响源漏极31的图案，即，源漏极31的材料包括Ag；栅线6的材料包括Mo，栅极34的材料如果也用Mo的话，Mo刻蚀液会对Ag有腐蚀，所以对栅线6材料的要求是其湿刻蚀液必须不会腐蚀源漏极31。栅线6主要是走线电阻考虑，无特殊需求，可以选择Mo。具体的，可以依次形成有机半导体膜层、有机栅极绝缘膜层涂布及栅极薄膜层，之后，采用湿刻工艺先对栅极34进行图案化，再通过一道光刻+干刻对叠层的有机半导体层 32与有机栅极绝缘层33进行图案化。具体的，有机半导体层32与有机栅极绝缘层33的图案可以大致相同。
在一种可能的实施方式中，结合图1A和图2所示，显示基板还包括与第二电极42同层且绝缘的连接电极422；栅线6位于连接电极422背离有机保护层5一侧且与连接电极接触电连接；连接电极422通过过孔与栅极34电连接，以将栅线6与栅极34电连接。
在一种可能的实施方式中，有机半导体层32的材料可以是聚乙炔型、聚芳环型或共聚物型。
在一种可能的实施方式中，有机栅极绝缘层33的材料可以是聚合物绝缘材料，具体的，有机栅极绝缘层33的材料可以包括：聚乙烯醇(Polyvinyl alcohol，PVA)、聚氯乙烯(Polyvinyl chloride，PVC)、聚乙烯吡咯烷酮(Polyvinyl pyrrolidone，PVP)、聚甲基丙烯酸甲酯(Polymethyl methacrylate，PMMA)或聚苯乙烯(Polystyrene，PS)。
在一种可能的实施方式中，结合图2与图7所示，栅线6在衬底基板1的正投影面积小于连接电极422在衬底基板1的正投影面积，且栅线6在衬底基板1的正投影位于连接电极422在衬底基板1的正投影内。本公开实施例中，栅线6在衬底基板1的正投影面积小于连接电极422在衬底基板1的正投影面积，且栅线6在衬底基板1的正投影位于连接电极422在衬底基板1的正投影内，可以避免若连接电极422(ITO)图形小于或等于栅线6(Mo)的图形时，在栅线6(Mo)相对连接电极422(ITO)延伸出部分下方，容易有水气或气体被困在该区域的问题。
在一种可能的实施方式中，第二电极条421在平行于衬底基板1的平面且垂直于第一方向AB上的线宽h2范围为：1μm～5μm。具体的，第二电极条421在平行于衬底基板1的平面且垂直于第一方向AB上的线宽h2范围为：1μm～3μm；第二电极条421在平行于衬底基板1的平面且垂直于第一方向AB上的线宽h2范围为：1μm～2μm；第二电极条421在平行于衬底基板1的平面且垂直于第一方向AB上的线宽h2范围为：1μm～1.5μm；第二电极 条421在平行于衬底基板1的平面且垂直于第一方向AB上的线宽h2可以为1μm；第二电极条421在平行于衬底基板1的平面且垂直于第一方向AB上的线宽h2可以为5μm。本公开实施例中，第二电极条421在平行于衬底基板1的平面且垂直于第一方向AB上的线宽h2范围为：1μm～5μm，可以使第二电极42与第一电极41形成较强的电场分布，避免第二电极条421在平行于衬底基板1的平面且垂直于第一方向AB上的线宽h2过宽时，会降低第二电极42与第一电极41形成的电场强度。本公开实施例中，在具体形成第二电极条421时，可以在形成栅线6时，结合图21和图22所示，将制作栅线6的金属层刻蚀成同时包括栅线6以及与第二电极42图案大致相同的第一图案601，在刻蚀形成第二电极42时，利用第一图案601进行遮挡，避免包括有机薄膜晶体管的显示基板中，采用低温光刻工艺对第二电极42进行刻蚀时，由于第二电极42本身在有机保护层5上的附着性差，刻蚀速率较快，容易形成使形成的第二电极条421在平行于衬底基板1的平面且垂直于第一方向AB上的线宽h2较宽的问题。常规不采用第一图案遮挡刻蚀，形成的第二电极条421在平行于衬底基板1的平面且垂直于第一方向AB上的线宽h2为4μm～5μm。
在一种可能的实施方式中，第一镂空结构410在衬底基板1的正投影面积占第一电极41在衬底基板1正投影面积的20％～80％。
在一种可能的实施方式中，结合图1A所示，有机薄膜晶体管3可以为顶栅型薄膜晶体管，具体的，有机半导体层5位于源漏极31背离衬底基板1的一侧，栅极6位于有机半导体层32背离源漏极31的一侧；栅极34与有机半导体层32之间具有有机栅极绝缘层33。在具体实施时，由于有机半导体层5无法承受金属电极溅射(sputter)过程的轰击，因此有机薄膜晶体管3在结构的选择上只有顶栅底接触跟底栅底接触两种；而顶栅底接触结构的有机薄膜晶体管3中，有效载流子传输效率更佳。优选的，本公开实施例的显示面板可以采用顶栅底接触有机薄膜晶体。
在一种可能的实施方式中，参见图1B所示，有机薄膜晶体管3也可以为 底栅型薄膜晶体管，有机半导体层32位于栅极34背离衬底基板1的一侧，源漏极31位于有机半导体层32与栅极34之间；栅极34与源漏极31之间具有有机栅极绝缘层33。
在一种可能的实施方式中，结合图1A、图2所示，栅极34在衬底基板1的正投影面积小于有机半导体层32在衬底基板1的正投影面积，且栅极34在衬底基板1的正投影位于有机半导体层32在衬底基板1的正投影内；有机半导体层32在衬底基板1的正投影面积与有机栅极绝缘层33在衬底基板1的正投影面积大致相等，且有机半导体层32在衬底基板1的正投影与有机栅极绝缘层33在衬底基板1的正投影大致重合。具体的，有机半导体层32在衬底基板1的正投影面积与有机栅极绝缘层33在衬底基板1的正投影面积大致相等，可以理解为二者投影面积的比值范围为1:0.8～1:1.2。具体的，有机半导体层32在衬底基板1的正投影与有机栅极绝缘层33在衬底基板1的正投影大致重合，可以理解为二者正投影存在80％～100％的重合。本公开实施例中，有机半导体层32在衬底基板1的正投影面积与有机栅极绝缘层33在衬底基板1的正投影面积大致相等，图案基本相同，在制作时，有机栅极绝缘层33可以跟有机半导体层32通过一步干刻形成图案化，可以简化显示基板的制作工序。
在一种可能的实施方式中，结合图1A所示，显示基板还包括位于有机薄膜晶体管3与衬底基板1之间的平坦层2，平坦层2在第一镂空结构410处与有机保护层5直接接触。本公开实施例中，平坦层2在第一镂空结构410处与有机保护层2直接接触，可以提高有机保护层5的附着力，改善有机保护层5易于与第一电极41剥离的问题。具体的，平坦层2的材料可以为不含氟的树脂类材料。
在一种可能的实施方式中，结合图1A所示，平坦层2包括叠层设置的第一平坦层21和第二平坦层22，第二平坦层21位于第一平坦层21的背离衬底基板1的一侧，第二平坦层22在第一镂空结构410处与有机保护层5直接接触。具体的，第一平坦层21与第二平坦层22的材料可以相同，第一平坦层 21用来平坦及保护下方膜层，第二平坦层22用来平坦第一平坦层21与第二平坦层22之间的遮挡层7。具体的，第一平坦层21与第二平坦层22的材料也可以不相同。
在一种可能的实施方式中，显示基板包括位于第一平坦层21与第二平坦层22之间的遮挡层7，有机半导体层5在衬底基板1的正投影面积小于遮挡层7在衬底基板1的正投影的面积，且有机半导体层5在衬底基板1的正投影位于遮挡层7在衬底基板1的正投影内。本公开实施例中，有机半导体层5在衬底基板1的正投影位于遮挡层7在衬底基板1的正投影内，可以通过遮挡层7对有机半导体层5进行遮挡，避免有机半导体层5受光照射时，产生光生载流子，影响有机薄膜晶体管的性能。
在一种可能的实施方式中，遮挡层7的材料可以包括金属或黑色树脂。
在一种可能的实施方式中，第一电极41与源漏极31电连接；第一电极41为像素电极，第二电极42为公共电极；第一电极41的材料与第二电极42的材料相同。具体的，第一电极41与第二电极42可以均为透明电极。第一电极41的材料具体可以为氧化铟锡，氧化锌、氧化锡、氧化钛、石墨烯。
在一种可能的实施方式中，结合图2、图12和图13所示，源漏极31可以包括源极311，以及漏极312，源极311具体可以与数据线313一体连接，漏极312具体可以与第一电极41电连接。数据线313在衬底基板1的正投影与第二电极42在衬底基板1的正投影存在交叠。
在一种可能的实施方式中，衬底基板1为有机柔性衬底基板。
参见图8所示，本公开实施例还提供一种显示装置，包括如本公开实施例提供的显示基板，还包括与显示基板相对而置的对向基板8，以及位于显示基板与对向基板8之间的液晶层9。
在具体实施时，本公开实施例提供的显示装置，还可以包括其它结构，例如，密封对向基板8与显示基本的密封框，在具体实施时，其它结构可以根据需要进行设置，本公开实施例不以此为限。
参见图9所示，本公开实施例还提供一种显示基板的制作方法，其中， 包括：
步骤S100、提供一衬底基板；
步骤S200、在衬底基板的一侧形成有机薄膜晶体管以及第一电极，其中，有机薄膜晶体管包括栅极、有机半导体层以及源漏极，第一电极包括多个第一镂空结构；
步骤S300、形成覆盖有机薄膜晶体管，第一电极、以及填充第一镂空结构的有机保护层。具体的，该步骤可以包括：通过旋涂方式，形成覆盖有机薄膜晶体管，第一电极、以及填充第一镂空结构的有机保护层；紫外固化，并在50度～250度的温度进行后烘的工艺。
在一种可能的实施方式中，参见图10所示，关于步骤S200、在衬底基板的一侧形成有机薄膜晶体管以及第一电极，包括：
步骤S210、在衬底基板的一侧形成源漏极；
步骤S220、在源漏极背离衬底基板的一侧形成具有多个第一镂空结构的第一电极；
步骤S230、在第一电极背离源漏极的一侧形成有机半导体层；
步骤S240、在有机半导体层背离第一电极的一侧形成有机栅极绝缘层；
步骤S250、在有机栅极绝缘层背离有机半导体层的一侧形成栅极。
在一种可能的实施方式中，参见图11所示，在步骤S300之后，即，在形成覆盖有机薄膜晶体管，第一电极、以及填充第一镂空结构的有机保护层之后，制作方法还包括：
步骤S400、在有机保护层的背离栅极的一侧形成第二薄膜层；
步骤S500、在第二薄膜层背离有机保护层的一侧形成图案化的金属层，图案化的金属层包括第一图案，以及栅线；具体的，可以是通过第一次湿刻工艺，在第二薄膜层背离有机保护层的一侧形成图案化的金属层；
步骤S600、在图案化的金属层的遮挡下对第二薄膜层进行刻蚀，形成图 案化的第二电极以及连接电极，其中，第二电极的图案与第一图案大致相同，连接电极的图案与栅线的图案大致相同；
具体的，可以是通过第二次湿刻工艺，在图案化的金属层的遮挡下对第二薄膜层进行刻蚀；
具体的，可以是通过第二次湿刻工艺，在图案化的金属层的遮挡下对第二薄膜层进行刻蚀，并使形成第二电极在衬底基板的正投影面积小于第一图案在衬底基板的正投影面积，且使第二电极在衬底基板的正投影位于第一图案在衬底基板的正投影内，以及使连接电极在衬底基板的正投影面积小于栅线在衬底基板的正投影面积，且使连接电极在衬底基板的正投影位于栅线在衬底基板的正投影内；
步骤S700、刻蚀去除第一图案。具体的，在刻蚀去除第一图案时，制作方法还可以包括：对栅线的部分进行刻蚀，以使栅线在衬底基板的正投影面积小于连接电极在衬底基板的正投影面积，且使栅线在衬底基板的正投影位于连接电极在衬底基板的正投影内。
为了更清楚地理解本公开实施例提供的显示基板的制作方法，以下结合图12-图25进行进一步说明如下：
步骤一、提供一衬底基板1；具体的，衬底基板1可以为柔性有机衬底基板，可以是将衬底基板1通过黏着层11贴附于玻璃基板12上，以方便后续膜层制作，在最终完成显示基板的制作后，可以将玻璃基板12、黏着层11与衬底基板1剥离；
步骤二、在衬底基板1的一侧依次形成第一平坦层21、遮挡层7、第二平坦层22；
步骤三、在第二平坦层22背离遮挡层7的一侧形成图案化的源漏极31，其中，源漏极31可以包括源极311，以及漏极312，源极311具体可以与数据线313一体连接，漏极312具体可以与后续形成的第一电极41电连接，如图12和图13所示；
步骤四、在源漏极31背离衬底基板1的一侧形成具有多个第一镂空结构410的第一电极41，如图14和图15所示，其中，图15为第一电极41的单膜层图；具体的，第一镂空结构410占第一电极41总面积的20％～80％，具体的，第一镂空结构410占第一电极41总面积的30％～70％，具体的，第一镂空结构410占第一电极41总面积的40％～60％；具体的，具体的，第一镂空结构410占第一电极41总面积的50％；具体的，第一镂空结构410占第一电极41总面积的20％；具体的，第一镂空结构410占第一电极41总面积的80％；
其中，第一电极41制作成手指状(finger)图案，且与后续形成的第二电极42的手指状(finger)图案交错分布；第一电极条411在平行于衬底基板1的平面且垂直于第一方向AB上的线宽为D，后续形成的第二电极42的第二镂空结构420在平行于衬底基板1的平面且垂直于第一方向AB上的宽度为S；结合图2、图4、图5和图6所示；
考虑到，当D>S时，如图5所示，其有效电场等效于未制作finger图案的第一电极41结构，如图6所示；
当D<S时，如图4所示，其有效电场小于未制作finger图案的第一电极41结构，进一步导致器件光效下降；
由上，第一电极41的finger线宽D需大于第二电极的finger线距S，即D>S；
步骤五、在第一电极41背离源漏极31的一侧形成有机半导体层32；在有机半导体层42背离第一电极41的一侧形成有机栅极绝缘层33；在有机栅极绝缘层33背离有机半导体层32的一侧形成栅极34，如图16、图17和图18所示；
具体的，可以是依序完成有机半导体膜层、有机栅极绝缘膜层涂布及成膜，再制作图型化栅极34，再对有机半导体膜层、有机栅极绝缘膜层的叠层进行图型化，形成有机半导体层32和有机栅极绝缘层33；
步骤六、进行有机保护薄膜的涂布及成膜；
步骤七、对有机保护层薄膜进行图型化，形成具有暴露部分栅极34过孔的有机保护层5，如图19所示；
步骤八、溅射沉积第二薄膜层424(用于制作第二电极42的膜层)，如图20所示；
步骤九、溅射沉积栅线金属薄膜60(用于制作栅线6的膜层)，如图20所示；通过第一次湿刻工艺，在第二薄膜层424背离有机保护层5的一侧形成图案化的金属层，其中，图案化的金属层包括第一图案601，以及栅线6，如图21所示；
步骤十、通过第二次湿刻工艺，在图案化的金属层的遮挡下对第二薄膜层424进行刻蚀，形成图案化的第二电极42以及连接电极422，如图22和图23所示，其中，第二电极42的图案与第一图案601大致相同，连接电极422的图案与栅线6的图案大致相同；即，第一次湿刻后，紧接著利用步骤十的图形对下方第二薄膜层424进行第二次湿刻；
具体的，结合图22所示，可以使形成第二电极42在衬底基板1的正投影面积小于第一图案601在衬底基板1的正投影面积，且使第二电极42在衬底基板1的正投影位于第一图案601在衬底基板1的正投影内，以及使连接电极422在衬底基板的正投影面积小于栅线6在衬底基板1的正投影面积，且使连接电极422在衬底基板1的正投影位于栅线6在衬底基板1的正投影内；
其中,通过利用第一图案601，以及栅线6作为第二电极42湿刻工艺的掩膜，该方法可大幅降低低温光刻工艺下获得的第二电极条421的线宽(bias)过大的问题；
步骤十一、通过第三次湿刻工艺，刻蚀去除第一图案601，保留栅线4，如图24和图25所示。具体的，结合图22和图24所示，在刻蚀去除第一图案601时，制作方法还可以包括：对栅线6的部分进行刻蚀，以使栅线6在衬底基板1的正投影面积小于连接电极422在衬底基板1的正投影面积，且使栅线6在衬底基板1的正投影位于连接电极422在衬底基板1的正投影内；
本公开实施例提供的显示面板，其中，第一电极41具有多个第一镂空结构410，有机保护层5覆盖第一电极41以及有机薄膜晶体管3，并填充第一镂空结构410，第一电极41的多个第一镂空结构410使第一电极41具有凹凸结构，提高了第一电极41的表面粗糙度，降低有机保护层5与无机第一电极41的界面占比，提高第一电极41与有机保护层5的附著力，避免有机保护层5与第一电极41发生分层或剥离的不良问题。
尽管已描述了本发明的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本发明范围的所有变更和修改。
显然，本领域的技术人员可以对本发明实施例进行各种改动和变型而不脱离本发明实施例的精神和范围。这样，倘若本发明实施例的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (27)

  1. 一种显示基板，其中，具有衬底基板，以及位于所述衬底基板一侧的多个像素，所述像素包括：
    有机薄膜晶体管，所述有机薄膜晶体管包括栅极、有机半导体层以及源漏极；
    第一电极，所述第一电极具有多个第一镂空结构；
    有机保护层，所述有机保护层覆盖所述第一电极以及所述有机薄膜晶体管，并填充所述第一镂空结构。
  2. 如权利要求1所述的显示基板，其中，所述像素包括位于所述有机保护层背离所述第一电极一侧的第二电极；
    所述第一电极包括多个沿第一方向延伸且相互电连接的第一电极条，相邻所述第一电极条之间具有所述第一镂空结构；所述第二电极包括多个沿所述第一方向延伸且相互电连接的第二电极条，以及位于相邻所述第二电极条之间的第二镂空结构；
    所述第二镂空结构在所述衬底基板的正投影面积小于所述第一电极条在所述衬底基板的正投影面积，且所述第二镂空结构在所述衬底基板的正投影位于所述第一电极条在所述衬底基板的正投影内。
  3. 如权利要求2所述的显示基板，其中，所述第一电极条在所述衬底基板的正投影，与所述第二镂空结构周边所述第二电极条的部分在所述衬底基板的正投影交叠。
  4. 如权利要求3所述的显示基板，其中，所述第一电极条在平行于所述衬底基板的平面且垂直于所述第一方向上线宽，大于所述第二镂空结构在平行于所述衬底基板的平面且垂直于所述第一方向上的宽度。
  5. 如权利要求2所述的显示基板，其中，所述显示基板还包括栅线，所述栅线与所述栅极电连接，所述栅线与所述栅极的材料不相同。
  6. 如权利要求5所述的显示基板，其中，所述显示基板还包括与所述第 二电极同层且绝缘的连接电极；所述栅线位于所述连接电极背离所述有机保护层一侧且与所述连接电极接触电连接；所述连接电极通过过孔与所述栅极电连接，以将所述栅线与所述栅极电连接。
  7. 如权利要求6所述的显示基板，其中，所述栅线的材料包括钼；所述栅极的材料包括氧化铟锡或氧化铟镓锌。
  8. 如权利要求6所述的显示基板，其中，所述栅线在所述衬底基板的正投影面积小于所述连接电极在所述衬底基板的正投影面积，且所述栅线在所述衬底基板的正投影位于所述连接电极在所述衬底基板的正投影内。
  9. 如权利要求5所述的显示基板，其中，所述第二电极条在平行于所述衬底基板的平面且垂直于所述第一方向上的线宽范围为：1μm～5μm。
  10. 如权利要求1-9任一项所述的显示基板，其中，所述第一镂空结构在所述衬底基板的正投影面积占所述第一电极在所述衬底基板正投影面积的20％～80％。
  11. 如权利要求1-10任一项所述的显示基板，其中，所述有机半导体层位于所述源漏极背离所述衬底基板的一侧，所述栅极位于所述有机半导体层背离所述源漏极的一侧；
    所述栅极与所述有机半导体层之间具有有机栅极绝缘层。
  12. 如权利要求1-10任一项所述的显示基板，其中，所述有机半导体层位于所述栅极背离所述衬底基板的一侧，所述源漏极位于所述有机半导体层与所述栅极之间；
    所述栅极与所述源漏极之间具有有机栅极绝缘层。
  13. 如权利要求11或12所述的显示基板，其中，所述栅极在所述衬底基板的正投影面积小于所述有机半导体层在所述衬底基板的正投影面积，且所述栅极在所述衬底基板的正投影面积位于所述有机半导体层在所述衬底基板的正投影内；
    所述有机半导体层在所述衬底基板的正投影面积与所述有机栅极绝缘层在所述衬底基板的正投影面积大致相等，且所述有机半导体层在所述衬底基 板的正投影与所述有机栅极绝缘层在所述衬底基板的正投影大致重合。
  14. 如权利要求1-13任一项所述的显示基板，其中，所述显示基板还包括位于所述有机薄膜晶体管与所述衬底基板之间的平坦层，所述平坦层在所述第一镂空结构处与所述有机保护层直接接触。
  15. 如权利要求14所述的显示基板，其中，所述平坦层包括叠层设置的第一平坦层和第二平坦层，所述第二平坦层位于所述第一平坦层的背离所述衬底基板的一侧，所述第二平坦层在所述第一镂空结构处与所述有机保护层直接接触。
  16. 如权利要求15所述的显示基板，其中，所述显示基板包括位于所述第一平坦层与所述第二平坦层之间的遮挡层，所述有机半导体层在所述衬底基板的正投影面积小于所述遮挡层在所述衬底基板的正投影的面积，且所述有机半导体层在所述衬底基板的正投影位于所述遮挡层在所述衬底基板的正投影内。
  17. 如权利要求16所述的显示基板，其中，所述遮挡层的材料包括金属或黑色树脂。
  18. 如权利要求1所述的显示基板，其中，所述第一电极与所述源漏极电连接；所述第一电极为像素电极，所述第二电极为公共电极；所述第一电极的材料与所述第二电极的材料相同；所述衬底基板为有机柔性衬底基板。
  19. 如权利要求18所述的显示基板，其中，所述第一电极的材料包括氧化铟锡或氧化铟镓锌。
  20. 一种显示装置，其中，包括如权利要求1-19任一项所述的显示基板，还包括与所述显示基板相对而置的对向基板，以及位于所述显示基板与所述对向基板之间的液晶层。
  21. 一种显示基板的制作方法，其中，包括：
    提供一衬底基板；
    在所述衬底基板的一侧形成有机薄膜晶体管以及第一电极，其中，有机薄膜晶体管包括栅极、有机半导体层以及源漏极，所述第一电极包括多个第 一镂空结构；
    形成覆盖所述有机薄膜晶体管，所述第一电极、以及填充所述第一镂空结构的有机保护层。
  22. 如权利要求21所述的制作方法，其中，所述在所述衬底基板的一侧形成有机薄膜晶体管以及第一电极，包括：
    在所述衬底基板的一侧形成源漏极；
    在所述源漏极背离所述衬底基板的一侧形成具有多个所述第一镂空结构的所述第一电极；
    在所述第一电极背离所述源漏极的一侧形成有机半导体层；
    在所述有机半导体层背离所述第一电极的一侧形成有机栅极绝缘层；
    在所述有机栅极绝缘层背离所述有机半导体层的一侧形成栅极。
  23. 如权利要求22所述的制作方法，其中，在形成覆盖所述有机薄膜晶体管，所述第一电极，以及填充所述第一镂空结构的有机保护层之后，所述制作方法还包括：
    在所述有机保护层的背离所述栅极的一侧形成第二薄膜层；
    在所述第二薄膜层背离所述有机保护层的一侧形成图案化的金属层，图案化的所述金属层包括第一图案，以及栅线；
    在图案化的所述金属层的遮挡下对所述第二薄膜层进行刻蚀，形成图案化的第二电极以及连接电极，其中，所述第二电极的图案与所述第一图案大致相同，所述连接电极的图案与所述栅线的图案大致相同；
    刻蚀去除所述第一图案。
  24. 如权利要求23所述的制作方法，其中，
    所述在所述第二薄膜层背离所述有机保护层的一侧形成图案化的金属层，包括：通过第一次湿刻工艺，在所述第二薄膜层背离所述有机保护层的一侧形成图案化的金属层；
    所述在图案化的所述金属层的遮挡下对所述第二薄膜层进行刻蚀，包括：通过第二次湿刻工艺，在图案化的所述金属层的遮挡下对所述第二薄膜层进 行刻蚀；
    所述刻蚀去除所述第一图案，包括：通过第三次湿刻工艺，刻蚀去除所述第一图案，保留所述栅线。
  25. 如权利要求24所述的制作方法，其中，所述通过第二次湿刻工艺，在图案化的所述金属层的遮挡下对所述第二薄膜层进行刻蚀，包括：
    通过第二次湿刻工艺，在图案化的所述金属层的遮挡下对所述第二薄膜层进行刻蚀，并使所述形成所述第二电极在所述衬底基板的正投影面积小于所述第一图案在所述衬底基板的正投影面积，且使所述第二电极在所述衬底基板的正投影位于所述第一图案在所述衬底基板的正投影内，以及使所述连接电极在所述衬底基板的正投影面积小于所述栅线在所述衬底基板的正投影面积，且使所述连接电极在所述衬底基板的正投影位于所述栅线在所述衬底基板的正投影内。
  26. 如权利要求25所述的制作方法，其中，在所述刻蚀去除所述第一图案时，所述制作方法还包括：
    对所述栅线的部分进行刻蚀，以使所述栅线在所述衬底基板的正投影面积小于所述连接电极在所述衬底基板的正投影面积，且使所述栅线在所述衬底基板的正投影位于所述连接电极在所述衬底基板的正投影内。
  27. 如权利要求21所述的制作方法，其中，所述形成覆盖所述有机薄膜晶体管，所述第一电极、以及填充所述第一镂空结构的有机保护层，包括：
    通过旋涂方式，形成覆盖所述有机薄膜晶体管，所述第一电极、以及填充所述第一镂空结构的有机保护层；
    紫外固化，并在50度～250度的温度进行后烘的工艺。
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CN204905257U (zh) * 2015-09-24 2015-12-23 京东方科技集团股份有限公司 阵列基板、显示装置
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CN104597671A (zh) * 2015-01-22 2015-05-06 厦门天马微电子有限公司 阵列基板、显示面板及显示装置
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