WO2023184603A1 - 像素电路及显示面板 - Google Patents

像素电路及显示面板 Download PDF

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Publication number
WO2023184603A1
WO2023184603A1 PCT/CN2022/087128 CN2022087128W WO2023184603A1 WO 2023184603 A1 WO2023184603 A1 WO 2023184603A1 CN 2022087128 W CN2022087128 W CN 2022087128W WO 2023184603 A1 WO2023184603 A1 WO 2023184603A1
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Prior art keywords
driving transistor
driving
transistor
size
control signal
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PCT/CN2022/087128
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English (en)
French (fr)
Inventor
袁学斌
田超
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武汉华星光电技术有限公司
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Priority to US17/772,186 priority Critical patent/US20240144872A1/en
Publication of WO2023184603A1 publication Critical patent/WO2023184603A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/3406—Control of illumination source
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0804—Sub-multiplexed active matrix panel, i.e. wherein one active driving circuit is used at pixel level for multiple image producing elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0814—Several active elements per pixel in active matrix panels used for selection purposes, e.g. logical AND for partial update
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present application relates to the field of display technology, and specifically to a pixel circuit and a display panel.
  • liquid crystal display panels and OLED (Organic Light-Emitting Diode, organic light-emitting semiconductor) display panels are widely used.
  • OLED Organic Light-Emitting Diode, organic light-emitting semiconductor
  • Liquid crystal display panels using Mini-LED backlights, OLED display panels and Mini-LED/Micro-LED direct Display panels all use current-driven pixel circuits.
  • This application provides a pixel circuit and a display panel to alleviate the technical problem of a small number of displayable gray levels.
  • the present application provides a pixel circuit, which includes a light-emitting module and a driving module.
  • the light-emitting module is connected in series between a positive power signal and a negative power signal.
  • the driving module is connected in series with the light-emitting module.
  • the driving module includes at least two drivers connected in parallel. unit; each driving unit is connected to a corresponding data signal, and controls the light-emitting time of the light-emitting module according to the interval between the pulse start time of the first control signal and the pulse start time of the second control signal.
  • each driving unit writes a data signal according to the first control signal, and determines the starting time of the lighting time according to the pulse starting time of the first control signal; and each driving unit writes a data signal according to the pulse starting time of the second control signal.
  • the start time determines the end moment of the glow time.
  • the at least two driving units include a first driving unit and a second driving unit, the first driving unit includes a first driving transistor, and the first driving unit writes the first data signal according to the first control signal;
  • the two driving units include a second driving transistor, and the second driving unit writes a second data signal according to the first control signal; the pulse amplitude of the first data signal is different from the pulse amplitude of the second data signal, and the first driving transistor has The size is different from that of the second drive transistor.
  • a ratio of a size of one of the first driving transistor or the second driving transistor to a size of the other of the first driving transistor or the second driving transistor ranges from greater than or equal to 1.8 to less than or equal to 2.2.
  • a ratio of a size of one of the first driving transistor or the second driving transistor to a size of the other of the first driving transistor or the second driving transistor ranges from greater than or equal to 2.7 to less than or equal to 3.3.
  • a ratio of a size of one of the first driving transistor or the second driving transistor to a size of the other of the first driving transistor or the second driving transistor ranges from greater than or equal to 3.6 to less than or equal to 4.4.
  • the at least two driving units include a first driving unit, a second driving unit and a third driving unit
  • the first driving unit includes a first driving transistor, and the first driving unit writes the first driving transistor according to the first control signal.
  • a data signal the second driving unit includes a second driving transistor, and the second driving unit writes the second data signal according to the first control signal
  • the third driving unit includes a third driving transistor, and the third driving unit writes according to the first control signal.
  • Input the third data signal; the pulse amplitude of the first data signal, the pulse amplitude of the second data signal and the pulse amplitude of the third data signal are all different, and the size of the first driving transistor and the size of the second driving transistor and the size of the third drive transistor are all different.
  • the ratio of the size of the first driving transistor to the size of the second driving transistor ranges from greater than or equal to 1.8 to less than or equal to 2.2; and the ratio of the size of the second driving transistor to the size of the third driving transistor ranges from greater than or equal to 1.8 to less than or equal to 2.2; The range of the ratio is greater than or equal to 1.8 and less than or equal to 2.2.
  • each driving unit includes a driving transistor, a charging transistor, a discharging transistor and a storage capacitor.
  • One of the source/drain of the driving transistor is electrically connected to one end of the light-emitting module.
  • the source/drain of the driving transistor The other of the drain electrodes is connected to the negative signal of the power supply; alternatively, one of the source/drain electrodes of the driving transistor is connected to the positive signal of the power supply, and the other of the source/drain electrodes of the driving transistor is electrically connected to the other end of the light-emitting module.
  • one of the source/drain of the charging transistor is electrically connected to the gate of the driving transistor, the other of the source/drain of the charging transistor is connected to the corresponding data signal, and the gate of the charging transistor is connected to The first control signal; one of the source/drain of the discharge transistor is electrically connected to the gate of the driving transistor, the other of the source/drain of the discharge transistor is connected to the initial signal, and the gate of the discharge transistor is connected to The second control signal: one end of the storage capacitor is electrically connected to the gate of the driving transistor, and the other end of the storage capacitor is electrically connected to the other of the source/drain of the driving transistor.
  • the light-emitting module includes at least two light-emitting devices connected in series, and the at least two light-emitting devices are connected in series between the positive power signal and the negative power signal.
  • the present application provides a display panel, which includes the pixel circuit in at least one of the above embodiments, and the display panel is a self-luminous display panel.
  • each drive unit can be configured with a corresponding light-emitting current.
  • the sum of these light-emitting currents can achieve multiple light-emitting brightnesses of the light-emitting module. , thereby improving or increasing the number of displayable gray levels; at the same time, the luminous time can be changed by adjusting the interval time, and the luminous brightness of the light-emitting module can also be adjusted, and combined with the luminous current configured in each drive unit, it can further improve or increase
  • the number of grayscales can be displayed.
  • the pixel circuit and display panel provided by this application can also increase the control voltage corresponding to the light-emitting current by shortening the light-emitting time and increasing the pulse amplitude of the data signal, thereby improving or avoiding low gray-scale conditions and low Under the control voltage, the driving module's control of the luminous current may be inaccurate or even out of control.
  • the pixel circuit and display panel provided by this application control the light-emitting time of the light-emitting module through the interval between the pulse start time of the first control signal and the pulse start time of the second control signal, which is different from the traditional technical solution through one pulse.
  • the frequency of the first control signal and/or the second control signal can be reduced, thereby reducing the potential change frequency of the first control signal and/or the second control signal, which not only reduces power consumption, but also The design difficulty, load and cost of the circuit or chip that generates the first control signal and/or the second control signal can be reduced.
  • FIG. 1 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present application.
  • FIG. 2 is another schematic structural diagram of a pixel circuit provided by an embodiment of the present application.
  • FIG. 3 is a timing diagram of the pixel circuit shown in FIG. 1 or 2 .
  • the pixel circuit includes a light-emitting module. 200 and the driving module 100, the light-emitting module 200 is connected in series between the positive power signal VDD and the negative power signal VSS; the driving module 100 and the light-emitting module 200 are connected in series, and the driving module 100 includes at least two driving units connected in parallel; each driving unit is connected The corresponding data signal is used, and the light-emitting time of the light-emitting module 200 is controlled according to the interval time between the pulse start time of the first control signal and the pulse start time of the second control signal.
  • each driving unit can be configured with a corresponding light-emitting current.
  • the sum of these light-emitting currents can realize the light-emitting module 200.
  • the pixel circuit provided in this embodiment can also increase the control voltage corresponding to the light-emitting current by shortening the light-emitting time and increasing the pulse amplitude of the data signal, thereby improving or avoiding the lower control voltage in low gray-scale conditions. Under this condition, the driving module 100 may control the light-emitting current inaccurately or even lose control.
  • the pixel circuit provided in this embodiment controls the light-emitting time of the light-emitting module 200 through the interval between the pulse start time of the first control signal and the pulse start time of the second control signal, which is different from the traditional technical solution through a pulse signal.
  • the frequency of the first control signal and/or the second control signal can be reduced, thereby reducing the potential change frequency of the first control signal and/or the second control signal, which not only reduces power consumption, but also Reduce the design difficulty, load and cost of the circuit or chip that generates the first control signal and/or the second control signal.
  • each driving unit may be, but are not limited to, the same, or the data signals connected to each driving unit may have the same frequency but different pulse amplitudes. It can be understood that each driving unit is connected to data signals with different pulse amplitudes, and the luminous current flowing through the corresponding driving unit can be adjusted, thereby changing the luminous current flowing through the light-emitting module 200 to achieve the corresponding display gray scale of the light-emitting module 200 .
  • each driving unit writes a data signal according to the first control signal, and determines the starting moment of the lighting time according to the pulse starting time of the first control signal; and each driving unit writes the data signal according to the pulse starting time of the second control signal.
  • the start time determines the end moment of the glow time.
  • the pulse start time in this implementation is the rising edge of a positive pulse or the falling edge of a negative pulse.
  • Each lighting time can be a time period, and the time period has a start and end time, that is, a start time and an end time.
  • the interval time in the above embodiment may be the time between the start time of the light-emitting time and the end time of the light-emitting time in each frame.
  • the light emitting time of the light emitting module 200 is controlled by using the first control signal and the second control signal instead of the same control signal, and the frequency of the first control signal and the second control signal can be reduced.
  • the first control signal may be, but is not limited to, the N-1th level scanning signal SCAN-1
  • the second control signal may be, but is not limited to, the Nth level scanning signal SCAN, the N-1th level scanning signal SCAN-1, the Nth level scanning signal SCAN-1, and the N-th level scanning signal SCAN-1.
  • the N-level scan signal SCAN can be generated by two gate driving circuits respectively.
  • the first control signal can also be the Nth level scan signal SCAN
  • the second control signal can also be the N+1th level scan signal.
  • the Nth level scan signal SCAN and the N+1th level scan signal can be, but are not limited to, composed of two levels respectively. Generated by two gate drive circuits, or can be generated by the same gate drive circuit.
  • At least two driving units include a first driving unit 110 and a second driving unit 120 .
  • the first driving unit 110 includes a first driving transistor T3A.
  • the first driving unit 110 is configured according to the first driving transistor T3A.
  • a control signal is written into the first data signal DATA1;
  • the second driving unit 120 includes a second driving transistor T3B, and the second driving unit 120 is written into the second data signal DATA2 according to the first control signal; the pulse amplitude of the first data signal DATA1
  • the pulse amplitude of the second data signal DATA2 is different, and the size of the first driving transistor T3A is different from the size of the second driving transistor T3B.
  • the size of the driving transistor is proportional to the current flowing through the driving transistor. That is, as the size of the driving transistor becomes larger, the current flowing through the driving transistor becomes larger. Correspondingly, , will also increase the light-emitting current flowing through the light-emitting module 200.
  • the range of the ratio of the size of one of the first driving transistor T3A or the second driving transistor T3B to the size of the other of the first driving transistor T3A or the second driving transistor T3B is greater than or equal to 1.8 And less than or equal to 2.2, specifically it can be 2:1.
  • the size ratio in each embodiment of the present application may, but is not limited to, must be equal to the corresponding ratio, or may be approximately equal to the corresponding ratio. Among them, a fluctuation range of approximately 10% can be allowed, for example, the ratio of the size of one of the first driving transistor T3A or the second driving transistor T3B to the size of the other of the first driving transistor T3A or the second driving transistor T3B.
  • the range of the ratio of the size of one of the first driving transistor T3A or the second driving transistor T3B to the size of the other of the first driving transistor T3A or the second driving transistor T3B may be greater than or equal to 1.8 And less than or equal to 2.2. It can be understood that the smaller the fluctuation range, the closer the corresponding ratio is to the actual size of the corresponding driving transistor.
  • the allowable error range for the size of each driving transistor may be 5%.
  • the size of a 100-micron driving transistor allows an error of 5 microns
  • the size of a 200-micron driving transistor allows an error of 10 microns.
  • the range of the ratio of the size of one of the first driving transistor T3A or the second driving transistor T3B to the size of the other of the first driving transistor T3A or the second driving transistor T3B is greater than or equal to 2.7 And less than or equal to 3.3, specifically 3:1.
  • Each data signal is equivalent to three states of 0, 1, and 2, and can output a total of 9 linear states from 0 to 8. The corresponding relationship can be expressed as conversion from ternary to decimal. In the same way, more output states can be achieved by increasing the number of drive units and the number of ternary digits.
  • each linear state can correspond to a display gray scale.
  • the range of the ratio of the size of one of the first driving transistor T3A or the second driving transistor T3B to the size of the other of the first driving transistor T3A or the second driving transistor T3B is greater than or equal to 3.6 And less than or equal to 4.4, specifically it can be 4:1.
  • the driving voltage of the data signal is too small, it cannot reach the threshold voltage of the corresponding driving transistor, and the current differentiation effect cannot be achieved; when the driving voltage is too large, it enters the saturation zone and the current differentiation effect is not obvious. Therefore, the driving voltage in the intermediate state will not be set in many ways in use.
  • introducing an intermediate driving voltage for DC voltage dimming does not conflict with increasing the number of driving units. The two can be combined with each other to achieve a larger amount of light-emitting current to further increase the number of displayable gray levels.
  • At least two driving units include a first driving unit 110 , a second driving unit 120 and a third driving unit 130 .
  • the first driving unit 110 includes a first driving transistor T3A.
  • a driving unit 110 writes the first data signal DATA1 according to the first control signal;
  • the second driving unit 120 includes a second driving transistor T3B, and the second driving unit 120 writes the second data signal DATA2 according to the first control signal;
  • the unit 130 includes a third driving transistor T3C.
  • the third driving unit 130 writes the third data signal DATA3 according to the first control signal; the pulse amplitude of the first data signal DATA1, the pulse amplitude of the second data signal DATA2 and the third data
  • the pulse amplitudes of the signal DATA3 are all different, and the sizes of the first driving transistor T3A, the second driving transistor T3B and the third driving transistor T3C are all different.
  • the number of driving units is further increased, and correspondingly, a third driving transistor T3C is also added, which can further enrich the types of light-emitting current flowing through the light-emitting module 200 and further improve the luminous efficiency. Displays the number of grayscales.
  • the size of one of the first driving transistor T3A, the second driving transistor T3B and the third driving transistor T3C, the size of the other one of the first driving transistor T3A, the second driving transistor T3B and the third driving transistor T3C is 4:2:1.
  • the ratio of the size of the first driving transistor T3A to the size of the second driving transistor T3B ranges from greater than or equal to 1.8 to less than or equal to 2.2; and the ratio of the size of the second driving transistor T3B to the size of the third driving transistor T3C The range is greater than or equal to 1.8 and less than or equal to 2.2.
  • IZ has a total of 8 output states, and these 8 output states are theoretically linearly distributed. Each output state can Corresponding to a display grayscale, the corresponding relationship can be expressed as binary to decimal conversion.
  • each driving unit includes a driving transistor, a charging transistor, a discharging transistor, and a storage capacitor.
  • One of the source/drain electrodes of the driving transistor is electrically connected to one end of the light emitting module 200 , and the source electrode of the driving transistor The other of the source/drain of the driving transistor is connected to the negative power signal VSS; or, one of the source/drain of the driving transistor is connected to the positive power signal VDD, and the other of the source/drain of the driving transistor is connected to the light-emitting module 200
  • the other end of the charging transistor is electrically connected; one of the source/drain of the charging transistor is electrically connected to the gate of the driving transistor, and the other of the source/drain of the charging transistor is connected to the corresponding data signal.
  • the gate is connected to the first control signal; one of the source/drain of the discharge transistor is electrically connected to the gate of the driving transistor, and the other of the source/drain of the discharge transistor is connected to the initial signal VI, and the discharge transistor
  • the gate of the storage capacitor is connected to the second control signal; one end of the storage capacitor is electrically connected to the gate of the driving transistor, and the other end of the storage capacitor is electrically connected to the other of the source/drain of the driving transistor.
  • the first driving unit 110 may include a first driving transistor T3A, a first charging transistor T11 , a first discharging transistor T21 and a first storage capacitor CA.
  • the source of the first driving transistor T3A One of the source/drain electrodes of the first driving transistor T3A is electrically connected to one end of the light emitting module 200, and the other of the source/drain electrodes of the first driving transistor T3A is connected to the negative power supply signal VSS; or, the source/drain electrode of the first driving transistor T3A One of the source electrodes and the drain electrode of the first driving transistor T3A is electrically connected to the other end of the light emitting module 200 .
  • One of the source/drain of the first charging transistor T11 is electrically connected to the gate of the first driving transistor T3A, and the other of the source/drain of the first charging transistor T11 is connected to the first data signal DATA1,
  • the gate of the first charging transistor T11 is connected to the first control signal;
  • one of the source and drain of the first discharging transistor T21 is electrically connected to the gate of the first driving transistor T3A, and the source of the first discharging transistor T21
  • the other of the drains is connected to the initial signal VI, and the gate of the first discharge transistor T21 is connected to the second control signal;
  • one end of the first storage capacitor CA is electrically connected to the gate of the first driving transistor T3A, and the first The other end of the storage capacitor CA is electrically connected to the other one of the source/drain electrodes of the first driving transistor T3A.
  • the second driving unit 120 may include a second driving transistor T3B, a second charging transistor T12, a second discharging transistor T22 and a second storage capacitor CB.
  • the source/drain of the second driving transistor T3B One of the electrodes is electrically connected to one end of the light-emitting module 200, and the other of the source/drain electrodes of the second driving transistor T3B is connected to the negative power supply signal VSS; or, one of the source/drain electrodes of the second driving transistor T3B One of the source and drain electrodes of the second driving transistor T3B is electrically connected to the other end of the light-emitting module 200 .
  • One of the source/drain of the second charging transistor T12 is electrically connected to the gate of the second driving transistor T3B, and the other of the source/drain of the second charging transistor T12 is connected to the second data signal DATA2,
  • the gate of the second charging transistor T12 is connected to the second control signal;
  • one of the source and drain of the second discharging transistor T22 is electrically connected to the gate of the second driving transistor T3B, and the source of the second discharging transistor T22
  • the other one of the drains is connected to the initial signal VI, and the gate of the second discharge transistor T22 is connected to the second control signal;
  • one end of the second storage capacitor CB is electrically connected to the gate of the second driving transistor T3B, and the second The other end of the storage capacitor CB is electrically connected to the other one of the source/drain electrodes of the second driving transistor T3B.
  • the third driving unit 130 may include a third driving transistor T3C, a third charging transistor T13 , a third discharging transistor T23 and a third storage capacitor CC.
  • the source/drain of the third driving transistor T3C is One is electrically connected to one end of the light-emitting module 200, and the other of the source/drain of the third driving transistor T3C is connected to the negative power signal VSS; or, one of the source/drain of the third driving transistor T3C is connected to When the positive power signal VDD is input, the other one of the source electrode and the drain electrode of the third driving transistor T3C is electrically connected to the other end of the light emitting module 200 .
  • One of the source/drain of the third charging transistor T13 is electrically connected to the gate of the third driving transistor T3C, and the other of the source/drain of the third charging transistor T13 is connected to the third data signal DATA3.
  • the gate of the third charging transistor T13 is connected to the third control signal; one of the source/drain of the third discharging transistor T23 is electrically connected to the gate of the third driving transistor T3C, and the source of the third discharging transistor T23
  • the other one of the drains is connected to the initial signal VI, and the gate of the third discharge transistor T23 is connected to the third control signal; one end of the third storage capacitor CC is electrically connected to the gate of the third driving transistor T3C, and the third The other end of the storage capacitor CC is electrically connected to the other of the source/drain electrodes of the third driving transistor T3C.
  • the light-emitting module 200 includes at least two light-emitting devices connected in series, such as a first light-emitting device D1, a second light-emitting device D2, a third light-emitting device D3, and a fourth light-emitting device D4.
  • the at least two light-emitting devices are connected in series. Between the positive power signal VDD and the negative power signal VSS.
  • the light-emitting device in this embodiment may be, but is not limited to, an organic light-emitting diode, or may be one of a sub-millimeter light-emitting diode, a micro-light-emitting diode, and a quantum dot light-emitting diode.
  • the potential of the positive power supply signal VDD is low, and the current flowing through the wiring that transmits the positive power supply signal VDD is high, and the equivalent wire diameter of the wiring is required to be high; and for multiple By connecting several light-emitting devices in series, the potential of the positive power supply signal VDD can be set to a higher potential, which can reduce the current flowing through the wiring that transmits the positive power signal VDD, thereby reducing the requirements for these wirings.
  • the working process of the above pixel circuit is shown in Figure 3.
  • the corresponding charging transistor is turned on or turned on to write the corresponding data signal DATA.
  • the Nth level scanning When the rising edge of the signal SCAN arrives, the gate of the corresponding driving transistor is discharged to turn off or cut off the driving transistor.
  • the interval time from the rising edge of the N-1th level scanning signal SCAN-1 to the rising edge of the Nth level scanning signal SCAN is t2, which is the minimum subfield display time.
  • the data signal DATA may be at least one of the first data signal DATA1, the second data signal DATA2, and the third data signal DATA3.
  • this embodiment provides a display panel.
  • the display panel includes the pixel circuit in at least one of the above embodiments.
  • the display panel is a self-luminous display panel.
  • the self-luminous display panel can be, for example, an OLED display panel. , Mini-LED display panel, Micro-LED display panel and any of QLED display panel.
  • the display panel provided in this embodiment configures at least two driving units in parallel in the driving module 100, and each driving unit can be configured with a corresponding light-emitting current.
  • the sum of these light-emitting currents can realize the light-emitting module 200.
  • the display panel provided in this embodiment can also increase the control voltage corresponding to the light-emitting current by shortening the light-emitting time and increasing the pulse amplitude of the data signal, thereby improving or avoiding the low control voltage in low gray-scale conditions. Under this condition, the driving module 100 may control the light-emitting current inaccurately or even lose control.
  • the display panel provided in this embodiment controls the light-emitting time of the light-emitting module 200 through the interval between the pulse start time of the first control signal and the pulse start time of the second control signal, which is different from the traditional technical solution through a pulse signal.
  • the frequency of the first control signal and/or the second control signal can be reduced, thereby reducing the potential change frequency of the first control signal and/or the second control signal, which not only reduces power consumption, but also Reduce the design difficulty, load and cost of the circuit or chip that generates the first control signal and/or the second control signal.

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Abstract

一种像素电路及显示面板，像素电路包括发光模块（200）和驱动模块（100），驱动模块（100）包括并联的至少两个驱动单元，通过于驱动模块（100）中配置并联的至少两个驱动单元，每一驱动单元均可以对应配置一发光电流，这些发光电流之和可以实现发光模块（200）的多种发光亮度，进而提高或者增加了可显示灰阶数。

Description

像素电路及显示面板 技术领域
本申请涉及显示技术领域，具体涉及一种像素电路及显示面板。
背景技术
当今社会科技迅猛发展，手机、电脑和电视等电子产品广泛应用于生活中的各个方面。其中，液晶显示面板和OLED(Organic Light-Emitting Diode，有机发光半导体)显示面板等电子显示屏被广泛采用，采用Mini-LED背光的液晶显示面板、OLED显示面板及Mini-LED/Micro-LED直显面板均采用电流驱动型像素电路。
随着消费者对显示效果需求的不断提高，需要显示的颜色种类也随之增多，这就需要对应提高显示的灰阶数。
技术问题
本申请提供一种像素电路及显示面板，以缓解可显示灰阶数较少的技术问题。
技术解决方案
第一方面，本申请提供一种像素电路，其包括发光模块和驱动模块，发光模块串联于电源正信号、电源负信号之间；驱动模块与发光模块串联，驱动模块包括并联的至少两个驱动单元；每个驱动单元接入对应的数据信号，且根据第一控制信号的脉冲开始时间与第二控制信号的脉冲开始时间之间的间隔时间控制发光模块的发光时间。
在其中一些实施方式中，每个驱动单元根据第一控制信号写入数据信号，并根据第一控制信号的脉冲开始时间确定发光时间的开始时刻；且每个驱动单元根据第二控制信号的脉冲开始时间确定发光时间的结束时刻。
在其中一些实施方式中，至少两个驱动单元包括第一驱动单元和第二驱动单元，第一驱动单元包括第一驱动晶体管，第一驱动单元根据第一控制信号写入第一数据信号；第二驱动单元包括第二驱动晶体管，第二驱动单元根据第一控制信号写入第二数据信号；第一数据信号的脉冲幅值与第二数据信号的脉冲 幅值不同，且第一驱动晶体管的尺寸与第二驱动晶体管的尺寸不同。
在其中一些实施方式中，第一驱动晶体管或者第二驱动晶体管中的一个的尺寸与第一驱动晶体管或者第二驱动晶体管中的另一个的尺寸之比的范围为大于或者等于1.8且小于或者等于2.2。
在其中一些实施方式中，第一驱动晶体管或者第二驱动晶体管中的一个的尺寸与第一驱动晶体管或者第二驱动晶体管中的另一个的尺寸之比的范围为大于或者等于2.7且小于或者等于3.3。
在其中一些实施方式中，第一驱动晶体管或者第二驱动晶体管中的一个的尺寸与第一驱动晶体管或者第二驱动晶体管中的另一个的尺寸之比的范围为大于或者等于3.6且小于或者等于4.4。
在其中一些实施方式中，至少两个驱动单元包括第一驱动单元、第二驱动单元以及第三驱动单元，第一驱动单元包括第一驱动晶体管，第一驱动单元根据第一控制信号写入第一数据信号；第二驱动单元包括第二驱动晶体管，第二驱动单元根据第一控制信号写入第二数据信号；第三驱动单元包括第三驱动晶体管，第三驱动单元根据第一控制信号写入第三数据信号；第一数据信号的脉冲幅值、第二数据信号的脉冲幅值以及第三数据信号的脉冲幅值均不相同，且第一驱动晶体管的尺寸、第二驱动晶体管的尺寸以及第三驱动晶体管的尺寸均不相同。
在其中一些实施方式中，第一驱动晶体管的尺寸与第二驱动晶体管的尺寸之比的范围为大于或者等于1.8且小于或者等于2.2；且第二驱动晶体管的尺寸与第三驱动晶体管的尺寸之比的范围为大于或者等于1.8且小于或者等于2.2。
在其中一些实施方式中，每个驱动单元包括驱动晶体管、充电晶体管、放电晶体管以及存储电容，驱动晶体管的源极/漏极中的一个与发光模块的一端电性连接，驱动晶体管的源极/漏极中的另一个接入电源负信号；或者，驱动晶体管的源极/漏极中的一个接入电源正信号，驱动晶体管的源极/漏极中的另一个与发光模块的另一端电性连接；充电晶体管的源极/漏极中的一个与驱动晶体管的栅极电性连接，充电晶体管的源极/漏极中的另一个接入对应的数据信号，充电晶体管的栅极接入第一控制信号；放电晶体管的源极/漏极中的一 个与驱动晶体管的栅极电性连接，放电晶体管的源极/漏极中的另一个接入初始信号，放电晶体管的栅极接入第二控制信号；存储电容的一端与驱动晶体管的栅极电性连接，存储电容的另一端与驱动晶体管的源极/漏极中的另一个电性连接。
在其中一些实施方式中，发光模块包括串联的至少两个发光器件，至少两个发光器件串联于电源正信号与电源负信号之间。
第二方面，本申请提供一种显示面板，其包括上述至少一实施方式中的像素电路，显示面板为自发光型显示面板。
有益效果
本申请提供的像素电路及显示面板，通过于驱动模块中配置并联的至少两个驱动单元，每一驱动单元均可以对应配置一发光电流，这些发光电流之和可以实现发光模块的多种发光亮度，进而提高或者增加了可显示灰阶数；同时，可以通过调整间隔时间进而改变发光时间，也能够调整发光模块的发光亮度，与各驱动单元配置的发光电流进行组合和，能够进一步提高或者增加可显示灰阶数。
又，本申请提供的像素电路及显示面板，也可以通过缩短发光时间、增加数据信号的脉冲幅值来提高与发光电流对应的控制电压，进而可以改善或者避免在低灰阶情况且较低的控制电压下，驱动模块对发光电流控制不精确甚至失控的情况发生。
又，本申请提供的像素电路及显示面板，通过第一控制信号的脉冲开始时间与第二控制信号的脉冲开始时间之间的间隔时间控制发光模块的发光时间，与传统技术方案中通过一个脉冲信号控制发光时间相比，可以降低第一控制信号和/或第二控制信号的频率，进而能够减少第一控制信号和/或第二控制信号的电位变化频率，不仅降低了功耗，而且也能够减少生成第一控制信号和/或第二控制信号的电路或者芯片的设计难度、负载量以及成本。
附图说明
图1为本申请实施例提供的像素电路的一种结构示意图。
图2为本申请实施例提供的像素电路的另一种结构示意图。
图3为图1或者图2所示像素电路的时序示意图。
本发明的实施方式
为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
有鉴于上述提及的可显示灰阶数较少的技术问题，本实施例提供了一种像素电路，请参阅图1至图3，如图1或者图2所示，该像素电路包括发光模块200和驱动模块100，发光模块200串联于电源正信号VDD、电源负信号VSS之间；驱动模块100与发光模块200串联，驱动模块100包括并联的至少两个驱动单元；每个驱动单元接入对应的数据信号，且根据第一控制信号的脉冲开始时间与第二控制信号的脉冲开始时间之间的间隔时间控制发光模块200的发光时间。
可以理解的是，本实施例提供的像素电路，通过于驱动模块100中配置并联的至少两个驱动单元，每一驱动单元均可以对应配置一发光电流，这些发光电流之和可以实现发光模块200的多种发光亮度，进而提高或者增加了可显示灰阶数；同时，可以通过调整间隔时间进而改变发光时间，也能够调整发光模块200的发光亮度，与各驱动单元配置的发光电流进行组合和，能够进一步提高或者增加可显示灰阶数。
又，本实施例提供的像素电路，也可以通过缩短发光时间、增加数据信号的脉冲幅值来提高与发光电流对应的控制电压，进而可以改善或者避免在低灰阶情况且较低的控制电压下，驱动模块100对发光电流控制不精确甚至失控的情况发生。
又，本实施例提供的像素电路，通过第一控制信号的脉冲开始时间与第二控制信号的脉冲开始时间之间的间隔时间控制发光模块200的发光时间，与传统技术方案中通过一个脉冲信号控制发光时间相比，可以降低第一控制信号和/或第二控制信号的频率，进而能够减少第一控制信号和/或第二控制信号的电位变化频率，不仅降低了功耗，而且也能够减少生成第一控制信号和/或第二控制信号的电路或者芯片的设计难度、负载量以及成本。
其中，需要进行说明的是，在本实施例中，各驱动单元接入的数据信号可以但不限于相同，也可以是各驱动单元接入的数据信号的频率相同而脉冲幅值不同。可以理解的是，各驱动单元接入脉冲幅值不同的数据信号，可以调整流经对应驱动单元的发光电流，进而改变流经发光模块200的发光电流，以实现发光模块200的对应显示灰阶。
在其中一个实施例中，每个驱动单元根据第一控制信号写入数据信号，并根据第一控制信号的脉冲开始时间确定发光时间的开始时刻；且每个驱动单元根据第二控制信号的脉冲开始时间确定发光时间的结束时刻。
需要进行说明的是，本实施中的脉冲开始时间为正脉冲的上升沿或者负脉冲的下降沿。每个发光时间可以为一个时间段，该时间段具有起止时间即开始时刻和结束时刻。
可以理解的是，上述实施例中的间隔时间可以为每帧中发光时间的开始时刻至发光时间的结束时刻之间的时间所构成。又，本实施通过第一控制信号、第二控制信号而非同一控制信号来控制发光模块200的发光时间，能够降低第一控制信号、第二控制信号的频率。
其中，第一控制信号可以但不限于为第N-1级扫描信号SCAN-1，第二控制信号可以但不限于为第N级扫描信号SCAN，第N-1级扫描信号SCAN-1、第N级扫描信号SCAN可以分别由两个栅极驱动电路生成。第一控制信号也可以为第N级扫描信号SCAN，第二控制信号也可以为第N+1级扫描信号，第N级扫描信号SCAN、第N+1级扫描信号可以但不限于分别由两个栅极驱动电路生成，也可以由同一栅极驱动电路生成。
在其中一个实施例中，如图1所示，至少两个驱动单元包括第一驱动单元110和第二驱动单元120，第一驱动单元110包括第一驱动晶体管T3A，第一驱动单元110根据第一控制信号写入第一数据信号DATA1；第二驱动单元120包括第二驱动晶体管T3B，第二驱动单元120根据第一控制信号写入第二数据信号DATA2；第一数据信号DATA1的脉冲幅值与第二数据信号DATA2的脉冲幅值不同，且第一驱动晶体管T3A的尺寸与第二驱动晶体管T3B的尺寸不同。
需要进行说明的是，在本实施例中，驱动晶体管的尺寸与流经该驱动晶体 管的电流成正比，即随着驱动晶体管的尺寸越大，流经该驱动晶体管的电流也越大，对应地，也会提高流经发光模块200的发光电流。
在其中一个实施例中，第一驱动晶体管T3A或者第二驱动晶体管T3B中的一个的尺寸与第一驱动晶体管T3A或者第二驱动晶体管T3B中的另一个的尺寸之比的范围为大于或者等于1.8且小于或者等于2.2，具体可以为2:1。
需要进行说明的是，本实施例中对对应驱动晶体管之间的尺寸之比作出了进一步的限制，但是由于在实际工艺制造过程中，各驱动晶体管的尺寸会存在或多或少的误差，因此，在本申请各实施例中的尺寸之比可以但不限于必须等于对应的比值，也可以为约等于对应的比值。其中，约等于可以允许10％的波动范围，例如，第一驱动晶体管T3A或者第二驱动晶体管T3B中的一个的尺寸与第一驱动晶体管T3A或者第二驱动晶体管T3B中的另一个的尺寸之比为2:1，则第一驱动晶体管T3A或者第二驱动晶体管T3B中的一个的尺寸与第一驱动晶体管T3A或者第二驱动晶体管T3B中的另一个的尺寸之比的范围可以为大于或者等于1.8且小于或者等于2.2。可以理解的是，该波动范围越小，对应的比值与对应驱动晶体管的实际尺寸越接近。
具体地，每个驱动晶体管的尺寸允许的误差范围可以为5％，例如，100微米的驱动晶体管的尺寸允许5微米的误差，200微米的驱动晶体管的尺寸允许10微米的误差。
当驱动晶体管的栅极电位确定时，驱动晶体管的开态电流与该驱动晶体管的尺寸(TFT Size)正相关，因此，在图1示中，IA：IB≈T3A：T3B(实际情况下会略有波动，可适当对TFT Size做一些调整)，而IZ＝IA+IB。假设在尺寸上T3A＝2T3B，即当DATA1＝DATA2＝Vopen(这里定义Vopen为开态时对应驱动晶体管的栅极电位)时，IA＝2IB＝2Iopen，IZ＝3Iopen；当DATA1＝Vopen而DATA2＝Vclose时(定义Vclose为关态时对应驱动晶体管的栅极电位)，IA＝2Iopen，IB≈0，IZ＝IA+IB＝2Iopen；当DATA1＝Vclose而DATA2＝Vopen时，IA≈0，IB＝Iopen，IZ＝Iopen；当DATA1＝DATA2＝Vclose时，IA＝IB≈0，IZ≈0。上述情况我们整理至如下的表1，可以看出根据DATA1、DATA2的不同状态组合，IZ共有4种输出状态，且这4种输出状态理论上呈线性分布，每种输出状态可以对应一种显示灰阶，其对应关系可表示为二进制至十进制的转换。
表1：
Figure PCTCN2022087128-appb-000001
在其中一个实施例中，第一驱动晶体管T3A或者第二驱动晶体管T3B中的一个的尺寸与第一驱动晶体管T3A或者第二驱动晶体管T3B中的另一个的尺寸之比的范围为大于或者等于2.7且小于或者等于3.3，具体还可以3:1。
可以理解的是，在上述实施例中，各对应数据信号的电位仅有Vopen和Vclose两种状态，如加入Vhalf驱动状态(在对应驱动晶体管的栅极电位为Vhalf时，流经该驱动晶体管的电流等于该驱动晶体管的栅极电位为Vopen时的一半)。在此基础上，调整T3A：T3B＝3:1，引入Vhalf后，每个数据信号相当于有了0、1、2三种状态，可输出0～8共9种线性状态。其对应关系可表示为三进制至十进制的转换。同理，可通过增加驱动单元的数量，增加三进制的位数，以达到更多的输出状态。
具体地，该9种线性状态具体如下的表2所示，可以理解的是，每种线性状态均可以对应一种显示灰阶。
表2：
Figure PCTCN2022087128-appb-000002
在其中一个实施例中，第一驱动晶体管T3A或者第二驱动晶体管T3B中的一个的尺寸与第一驱动晶体管T3A或者第二驱动晶体管T3B中的另一个的尺寸之比的范围为大于或者等于3.6且小于或者等于4.4，具体可以为4:1。
可以理解的是，如果进一步增加对应数据信号处于中间态的驱动电压，如Vmid1、Vmid2(IVclose:IVmid2:IVmid1:IVopen＝0:1:2:3)，其中，IVclose为对应驱动晶体管的栅极电位为Vclose时流经该驱动晶体管的电流，IVmid2为 对应驱动晶体管的栅极电位为Vmid2时流经该驱动晶体管的电流，IVmid1为对应驱动晶体管的栅极电位为Vmid1时流经该驱动晶体管的电流，IVopen为对应驱动晶体管的栅极电位为Vopen时流经该驱动晶体管的电流。此种情况可以转换为如下表三所示的四进制至十进制的转换。理论上，对应数据信号处于中间态的驱动电压增加的越多，则流经发光模块200的发光电流的输出状态即可显示灰阶数也越多。但实际工作中，数据信号的驱动电压过小时，无法达到对应驱动晶体管的阈值电压，达不到电流区分的效果；当驱动电压过大时，进入饱和区，电流区分效果也不明显。因此，处于中间态的驱动电压在使用中不会设置太多种。同时，引入中间态的驱动电压进行直流电压调光与增加驱动单元的数量不冲突，二者可以相互结合以达到更大数量的发光电流，以进一步增加可显示灰阶数。
表三：
Figure PCTCN2022087128-appb-000003
在其中一个实施例中，如图2所示，至少两个驱动单元包括第一驱动单元110、第二驱动单元120以及第三驱动单元130，第一驱动单元110包括第一驱动晶体管T3A，第一驱动单元110根据第一控制信号写入第一数据信号DATA1；第二驱动单元120包括第二驱动晶体管T3B，第二驱动单元120根据第一控制信号写入第二数据信号DATA2；第三驱动单元130包括第三驱动晶体管T3C，第三驱动单元130根据第一控制信号写入第三数据信号DATA3；第一数据信号DATA1的脉冲幅值、第二数据信号DATA2的脉冲幅值以及第 三数据信号DATA3的脉冲幅值均不相同，且第一驱动晶体管T3A的尺寸、第二驱动晶体管T3B的尺寸以及第三驱动晶体管T3C的尺寸均不相同。
可以理解的是，在本实施例中进一步增加了驱动单元的数量，对应地，也增加了第三驱动晶体管T3C，其可以进一步丰富流经发光模块200的发光电流的种类，进而能够进一步提高可显示灰阶数。
在其中一个实施例中，第一驱动晶体管T3A、第二驱动晶体管T3B以及第三驱动晶体管T3C中的一个的尺寸、第一驱动晶体管T3A、第二驱动晶体管T3B以及第三驱动晶体管T3C中的另一个的尺寸、第一驱动晶体管T3A、第二驱动晶体管T3B以及第三驱动晶体管T3C中的再一个的尺寸之比为4:2:1。
例如，第一驱动晶体管T3A的尺寸与第二驱动晶体管T3B的尺寸之比的范围为大于或者等于1.8且小于或者等于2.2；且第二驱动晶体管T3B的尺寸与第三驱动晶体管T3C的尺寸之比的范围为大于或者等于1.8且小于或者等于2.2。
可以理解的是，本实施例可以根据如下表四所示的DATA1、DATA2、DATA3的不同状态组合，IZ共有8种输出状态，且这8种输出状态理论上呈线性分布，每种输出状态可以对应一种显示灰阶，其对应关系可表示为二进制至十进制的转换。
表四：
Figure PCTCN2022087128-appb-000004
在其中一个实施例中，每个驱动单元包括驱动晶体管、充电晶体管、放电晶体管以及存储电容，驱动晶体管的源极/漏极中的一个与发光模块200的一端电性连接，驱动晶体管的源极/漏极中的另一个接入电源负信号VSS；或者，驱动晶体管的源极/漏极中的一个接入电源正信号VDD，驱动晶体管的源极/ 漏极中的另一个与发光模块200的另一端电性连接；充电晶体管的源极/漏极中的一个与驱动晶体管的栅极电性连接，充电晶体管的源极/漏极中的另一个接入对应的数据信号，充电晶体管的栅极接入第一控制信号；放电晶体管的源极/漏极中的一个与驱动晶体管的栅极电性连接，放电晶体管的源极/漏极中的另一个接入初始信号VI，放电晶体管的栅极接入第二控制信号；存储电容的一端与驱动晶体管的栅极电性连接，存储电容的另一端与驱动晶体管的源极/漏极中的另一个电性连接。
例如，如图1或者图2所示，第一驱动单元110可以包括第一驱动晶体管T3A、第一充电晶体管T11、第一放电晶体管T21以及第一存储电容CA，第一驱动晶体管T3A的源极/漏极中的一个与发光模块200的一端电性连接，第一驱动晶体管T3A的源极/漏极中的另一个接入电源负信号VSS；或者，第一驱动晶体管T3A的源极/漏极中的一个接入电源正信号VDD，第一驱动晶体管T3A的源极/漏极中的另一个与发光模块200的另一端电性连接。第一充电晶体管T11的源极/漏极中的一个与第一驱动晶体管T3A的栅极电性连接，第一充电晶体管T11的源极/漏极中的另一个接入第一数据信号DATA1，第一充电晶体管T11的栅极接入第一控制信号；第一放电晶体管T21的源极/漏极中的一个与第一驱动晶体管T3A的栅极电性连接，第一放电晶体管T21的源极/漏极中的另一个接入初始信号VI，第一放电晶体管T21的栅极接入第二控制信号；第一存储电容CA的一端与第一驱动晶体管T3A的栅极电性连接，第一存储电容CA的另一端与第一驱动晶体管T3A的源极/漏极中的另一个电性连接。
如图1或者图2所示，第二驱动单元120可以包括第二驱动晶体管T3B、第二充电晶体管T12、第二放电晶体管T22以及第二存储电容CB，第二驱动晶体管T3B的源极/漏极中的一个与发光模块200的一端电性连接，第二驱动晶体管T3B的源极/漏极中的另一个接入电源负信号VSS；或者，第二驱动晶体管T3B的源极/漏极中的一个接入电源正信号VDD，第二驱动晶体管T3B的源极/漏极中的另一个与发光模块200的另一端电性连接。第二充电晶体管T12的源极/漏极中的一个与第二驱动晶体管T3B的栅极电性连接，第二充电晶体管T12的源极/漏极中的另一个接入第二数据信号DATA2，第二充电晶体 管T12的栅极接入第二控制信号；第二放电晶体管T22的源极/漏极中的一个与第二驱动晶体管T3B的栅极电性连接，第二放电晶体管T22的源极/漏极中的另一个接入初始信号VI，第二放电晶体管T22的栅极接入第二控制信号；第二存储电容CB的一端与第二驱动晶体管T3B的栅极电性连接，第二存储电容CB的另一端与第二驱动晶体管T3B的源极/漏极中的另一个电性连接。
如图3所示，第三驱动单元130可以包括第三驱动晶体管T3C、第三充电晶体管T13、第三放电晶体管T23以及第三存储电容CC，第三驱动晶体管T3C的源极/漏极中的一个与发光模块200的一端电性连接，第三驱动晶体管T3C的源极/漏极中的另一个接入电源负信号VSS；或者，第三驱动晶体管T3C的源极/漏极中的一个接入电源正信号VDD，第三驱动晶体管T3C的源极/漏极中的另一个与发光模块200的另一端电性连接。第三充电晶体管T13的源极/漏极中的一个与第三驱动晶体管T3C的栅极电性连接，第三充电晶体管T13的源极/漏极中的另一个接入第三数据信号DATA3，第三充电晶体管T13的栅极接入第三控制信号；第三放电晶体管T23的源极/漏极中的一个与第三驱动晶体管T3C的栅极电性连接，第三放电晶体管T23的源极/漏极中的另一个接入初始信号VI，第三放电晶体管T23的栅极接入第三控制信号；第三存储电容CC的一端与第三驱动晶体管T3C的栅极电性连接，第三存储电容CC的另一端与第三驱动晶体管T3C的源极/漏极中的另一个电性连接。
在其中一个实施例中，发光模块200包括串联的至少两个发光器件，例如第一发光器件D1、第二发光器件D2、第三发光器件D3以及第四发光器件D4，至少两个发光器件串联于电源正信号VDD与电源负信号VSS之间。
需要进行说明的是，本实施例中的发光器件可以但不限于为有机发光二极管，也可以为次毫米发光光二极管、微发光二极管以及量子点发光二极管中的一个。
其中，在同样功率的情况下，单个发光器件的话，电源正信号VDD的电位较低，流过传输电源正信号VDD的布线的电流较高，对该布线的等效线径要求高；而多个发光器件进行串联，可以设置电源正信号VDD的电位为较高的电位，这样可以降低流过传输电源正信号VDD的布线的电流，进而可以降低该些布线的要求。
上述像素电路的工作过程如图3所示，第N-1级扫描信号SCAN-1的脉冲持续时间t1中，对应的充电晶体管打开或者导通以写入对应的数据信号DATA，第N级扫描信号SCAN的上升沿到来时，对对应的驱动晶体管的栅极进行放电以关闭或者截止该驱动晶体管。其中，第N-1级扫描信号SCAN-1的上升沿至第N级扫描信号SCAN的上升沿的间隔时间即为t2，其为最小子场显示时间。数据信号DATA可以为第一数据信号DATA1、第二数据信号DATA2以及第三数据信号DATA3中的至少一个。
在其中一个实施例中，本实施例提供一种显示面板，该显示面板包括上述至少一实施例中的像素电路，显示面板为自发光型显示面板，自发光型显示面板例如可以为OLED显示面板、Mini-LED显示面板、Micro-LED显示面板以及QLED显示面板中的任一个。
可以理解的是，本实施例提供的显示面板，通过于驱动模块100中配置并联的至少两个驱动单元，每一驱动单元均可以对应配置一发光电流，这些发光电流之和可以实现发光模块200的多种发光亮度，进而提高或者增加了可显示灰阶数；同时，可以通过调整间隔时间进而改变发光时间，也能够调整发光模块200的发光亮度，与各驱动单元配置的发光电流进行组合和，能够进一步提高或者增加可显示灰阶数。
又，本实施例提供的显示面板，也可以通过缩短发光时间、增加数据信号的脉冲幅值来提高与发光电流对应的控制电压，进而可以改善或者避免在低灰阶情况且较低的控制电压下，驱动模块100对发光电流控制不精确甚至失控的情况发生。
又，本实施例提供的显示面板，通过第一控制信号的脉冲开始时间与第二控制信号的脉冲开始时间之间的间隔时间控制发光模块200的发光时间，与传统技术方案中通过一个脉冲信号控制发光时间相比，可以降低第一控制信号和/或第二控制信号的频率，进而能够减少第一控制信号和/或第二控制信号的电位变化频率，不仅降低了功耗，而且也能够减少生成第一控制信号和/或第二控制信号的电路或者芯片的设计难度、负载量以及成本。
可以理解的是，对本领域普通技术人员来说，可以根据本申请的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本申请所 附的权利要求的保护范围。

Claims (20)

  1. 一种像素电路，包括：
    发光模块，所述发光模块串联于电源正信号、电源负信号之间；和
    驱动模块，所述驱动模块与所述发光模块串联，所述驱动模块包括并联的至少两个驱动单元；每个所述驱动单元接入对应的数据信号，且根据第一控制信号的脉冲开始时间与第二控制信号的脉冲开始时间之间的间隔时间控制所述发光模块的发光时间。
  2. 根据权利要求1所述的像素电路，其中，每个所述驱动单元根据所述第一控制信号写入所述数据信号，并根据所述第一控制信号的脉冲开始时间确定所述发光时间的开始时刻；且每个所述驱动单元根据所述第二控制信号的脉冲开始时间确定所述发光时间的结束时刻。
  3. 根据权利要求1所述的像素电路，其中，所述至少两个驱动单元包括第一驱动单元和第二驱动单元，所述第一驱动单元包括第一驱动晶体管，所述第一驱动单元根据所述第一控制信号写入第一数据信号；所述第二驱动单元包括第二驱动晶体管，所述第二驱动单元根据所述第一控制信号写入第二数据信号；所述第一数据信号的脉冲幅值与所述第二数据信号的脉冲幅值不同，且所述第一驱动晶体管的尺寸与所述第二驱动晶体管的尺寸不同。
  4. 根据权利要求3所述的像素电路，其中，所述第一驱动晶体管或者所述第二驱动晶体管中的一个的尺寸与所述第一驱动晶体管或者所述第二驱动晶体管中的另一个的尺寸之比的范围为大于或者等于1.8且小于或者等于2.2。
  5. 根据权利要求3所述的像素电路，其中，所述第一驱动晶体管或者所述第二驱动晶体管中的一个的尺寸与所述第一驱动晶体管或者所述第二驱动晶体管中的另一个的尺寸之比的范围为大于或者等于2.7且小于或者等于3.3。
  6. 根据权利要求3所述的像素电路，其中，所述第一驱动晶体管或者所述第二驱动晶体管中的一个的尺寸与所述第一驱动晶体管或者所述第二驱动晶体管中的另一个的尺寸之比的范围为大于或者等于3.6且小于或者等于4.4。
  7. 根据权利要求1所述的像素电路，其中，所述至少两个驱动单元包括第一驱动单元、第二驱动单元以及第三驱动单元，所述第一驱动单元包括第一驱动晶体管，所述第一驱动单元根据所述第一控制信号写入第一数据信号；所 述第二驱动单元包括第二驱动晶体管，所述第二驱动单元根据所述第一控制信号写入第二数据信号；所述第三驱动单元包括第三驱动晶体管，所述第三驱动单元根据所述第一控制信号写入第三数据信号；所述第一数据信号的脉冲幅值、所述第二数据信号的脉冲幅值以及所述第三数据信号的脉冲幅值均不相同，且所述第一驱动晶体管的尺寸、所述第二驱动晶体管的尺寸以及所述第三驱动晶体管的尺寸均不相同。
  8. 根据权利要求7所述的像素电路，其中，所述第一驱动晶体管的尺寸与所述第二驱动晶体管的尺寸之比的范围为大于或者等于1.8且小于或者等于2.2；且所述第二驱动晶体管的尺寸与所述第三驱动晶体管的尺寸之比的范围为大于或者等于1.8且小于或者等于2.2。
  9. 根据权利要求1所述的像素电路，其中，每个所述驱动单元包括：
    驱动晶体管，所述驱动晶体管的源极/漏极中的一个与所述发光模块的一端电性连接，所述驱动晶体管的源极/漏极中的另一个接入所述电源负信号；或者，所述驱动晶体管的源极/漏极中的一个接入所述电源正信号，所述驱动晶体管的源极/漏极中的另一个与所述发光模块的另一端电性连接；
    充电晶体管，所述充电晶体管的源极/漏极中的一个与所述驱动晶体管的栅极电性连接，所述充电晶体管的源极/漏极中的另一个接入所述对应的数据信号，所述充电晶体管的栅极接入所述第一控制信号；
    放电晶体管，所述放电晶体管的源极/漏极中的一个与所述驱动晶体管的栅极电性连接，所述放电晶体管的源极/漏极中的另一个接入初始信号，所述放电晶体管的栅极接入所述第二控制信号；以及
    存储电容，所述存储电容的一端与所述驱动晶体管的栅极电性连接，所述存储电容的另一端与所述驱动晶体管的源极/漏极中的另一个电性连接。
  10. 根据权利要求1所述的像素电路，其中，所述发光模块包括串联的至少两个发光器件，所述至少两个发光器件串联于所述电源正信号与所述电源负信号之间。
  11. 一种显示面板，包括如权利要求1所述的像素电路，所述显示面板为自发光型显示面板。
  12. 根据权利要求11所述的显示面板，其中，每个所述驱动单元根据所 述第一控制信号写入所述数据信号，并根据所述第一控制信号的脉冲开始时间确定所述发光时间的开始时刻；且每个所述驱动单元根据所述第二控制信号的脉冲开始时间确定所述发光时间的结束时刻。
  13. 根据权利要求11所述的显示面板，其中，所述至少两个驱动单元包括第一驱动单元和第二驱动单元，所述第一驱动单元包括第一驱动晶体管，所述第一驱动单元根据所述第一控制信号写入第一数据信号；所述第二驱动单元包括第二驱动晶体管，所述第二驱动单元根据所述第一控制信号写入第二数据信号；所述第一数据信号的脉冲幅值与所述第二数据信号的脉冲幅值不同，且所述第一驱动晶体管的尺寸与所述第二驱动晶体管的尺寸不同。
  14. 根据权利要求13所述的显示面板，其中，所述第一驱动晶体管或者所述第二驱动晶体管中的一个的尺寸与所述第一驱动晶体管或者所述第二驱动晶体管中的另一个的尺寸之比的范围为大于或者等于1.8且小于或者等于2.2。
  15. 根据权利要求13所述的显示面板，其中，所述第一驱动晶体管或者所述第二驱动晶体管中的一个的尺寸与所述第一驱动晶体管或者所述第二驱动晶体管中的另一个的尺寸之比的范围为大于或者等于2.7且小于或者等于3.3。
  16. 根据权利要求13所述的显示面板，其中，所述第一驱动晶体管或者所述第二驱动晶体管中的一个的尺寸与所述第一驱动晶体管或者所述第二驱动晶体管中的另一个的尺寸之比的范围为大于或者等于3.6且小于或者等于4.4。
  17. 根据权利要求11所述的显示面板，其中，所述至少两个驱动单元包括第一驱动单元、第二驱动单元以及第三驱动单元，所述第一驱动单元包括第一驱动晶体管，所述第一驱动单元根据所述第一控制信号写入第一数据信号；所述第二驱动单元包括第二驱动晶体管，所述第二驱动单元根据所述第一控制信号写入第二数据信号；所述第三驱动单元包括第三驱动晶体管，所述第三驱动单元根据所述第一控制信号写入第三数据信号；所述第一数据信号的脉冲幅值、所述第二数据信号的脉冲幅值以及所述第三数据信号的脉冲幅值均不相同，且所述第一驱动晶体管的尺寸、所述第二驱动晶体管的尺寸以及所述第三 驱动晶体管的尺寸均不相同。
  18. 根据权利要求17所述的显示面板，其中，所述第一驱动晶体管的尺寸与所述第二驱动晶体管的尺寸之比的范围为大于或者等于1.8且小于或者等于2.2；且所述第二驱动晶体管的尺寸与所述第三驱动晶体管的尺寸之比的范围为大于或者等于1.8且小于或者等于2.2。
  19. 根据权利要求11所述的显示面板，其中，每个所述驱动单元包括：
    驱动晶体管，所述驱动晶体管的源极/漏极中的一个与所述发光模块的一端电性连接，所述驱动晶体管的源极/漏极中的另一个接入所述电源负信号；或者，所述驱动晶体管的源极/漏极中的一个接入所述电源正信号，所述驱动晶体管的源极/漏极中的另一个与所述发光模块的另一端电性连接；
    充电晶体管，所述充电晶体管的源极/漏极中的一个与所述驱动晶体管的栅极电性连接，所述充电晶体管的源极/漏极中的另一个接入所述对应的数据信号，所述充电晶体管的栅极接入所述第一控制信号；
    放电晶体管，所述放电晶体管的源极/漏极中的一个与所述驱动晶体管的栅极电性连接，所述放电晶体管的源极/漏极中的另一个接入初始信号，所述放电晶体管的栅极接入所述第二控制信号；以及
    存储电容，所述存储电容的一端与所述驱动晶体管的栅极电性连接，所述存储电容的另一端与所述驱动晶体管的源极/漏极中的另一个电性连接。
  20. 根据权利要求11所述的显示面板，其中，所述发光模块包括串联的至少两个发光器件，所述至少两个发光器件串联于所述电源正信号与所述电源负信号之间。
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