WO2023070703A1 - Dispositif à semi-conducteurs de puissance et son procédé de fabrication - Google Patents

Dispositif à semi-conducteurs de puissance et son procédé de fabrication Download PDF

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Publication number
WO2023070703A1
WO2023070703A1 PCT/CN2021/128397 CN2021128397W WO2023070703A1 WO 2023070703 A1 WO2023070703 A1 WO 2023070703A1 CN 2021128397 W CN2021128397 W CN 2021128397W WO 2023070703 A1 WO2023070703 A1 WO 2023070703A1
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Prior art keywords
type
trench
conductivity type
conductivity
region
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PCT/CN2021/128397
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English (en)
Chinese (zh)
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朱袁正
叶鹏
周锦程
杨卓
刘晶晶
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无锡新洁能股份有限公司
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Publication of WO2023070703A1 publication Critical patent/WO2023070703A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors

Definitions

  • the invention relates to the technical field of semiconductors, in particular to a power semiconductor device and a method for manufacturing the power semiconductor device.
  • the short-circuit mode In the short-circuit mode, a large amount of current flows through the shielded trench power device. When the short-circuit mode ends, the device is turned off. The parasitic inductance in the circuit causes the current to forcibly avalanche and break down the device, and the device will experience a very short period of time. High voltage and super high current state. Because the device has a breakdown weak point in the terminal and transition area, it will cause the current to concentrate and generate heat, and because the heat cannot be smoothly transferred to the active area due to the extremely short time, it will cause the device to have a burn point in the terminal or transition area.
  • the invention provides a power semiconductor device and a manufacturing method of the power semiconductor device, which solve the problem of low reliability in the short-circuit working mode existing in the related art.
  • a power semiconductor device including:
  • each first-type trench is completely filled with first-type conductive polysilicon, and a field oxygen layer composed of an insulating medium is arranged between the first-type conductive polysilicon and the first-conductivity-type epitaxial layer.
  • a second-type insulating dielectric layer is arranged above the first-type trenches, a source metal is arranged above the second-type insulating dielectric layer, and the source metal passes through the A first type of via hole is in ohmic contact with the first type of conductive polysilicon located in the first type of trench;
  • the inner part of part of the groove segment of each first-type trench is filled with the first-type conductive polysilicon, and the second-type conductive polysilicon is filled above the first-type conductive polysilicon, and the second-type conductive polysilicon and the first-type conductive polysilicon are filled.
  • a first-type insulating dielectric layer is filled between the conductive polysilicon, a gate oxide layer is provided between the second-type conductive polysilicon and the first-conductive-type epitaxial layer, and the first-type trench between every two adjacent first-type trenches
  • a second conductivity type body region is provided on the upper surface of one type of conductivity type epitaxial layer, and a first conductivity type source region is arranged on the upper surface of part of the second conductivity type body region, and the first type of trench and the first conductivity type
  • a second-type insulating dielectric layer is arranged above the source regions of the second type, and a source metal is arranged above part of the second-type insulating dielectric layer, and the source metal passes through the second-type insulating dielectric layer located in the second-type insulating dielectric layer.
  • the through holes are respectively in ohmic contact with the source region of the first conductivity type and the body region of the second conductivity type;
  • a first conductivity type well region is provided in the first conductivity type epitaxial layer, and the distribution area of the first conductivity type well region includes a side region below the second type through hole and covering the first type trench and the bottom region, the concentration of the first conductivity type impurity in the first conductivity type well region is higher than the concentration of the first conductivity type impurity in the first conductivity type epitaxial layer; or,
  • a first conductivity type well region is provided in the first conductivity type epitaxial layer, and the distribution area of the first conductivity type well region includes, in a direction parallel to the first type trench, the second type through hole the side region and the bottom region of the first-type trench between the second-type trench, the side region and the bottom region of the first-type trench between adjacent second-type through holes, and In the side region and the bottom region of the second type trench, the concentration of the first conductivity type impurity in the first conductivity type well region is lower than the concentration of the first conductivity type impurity in the first conductivity type epitaxial layer.
  • a first conductivity type well region is provided in the first conductivity type epitaxial layer, and the distribution area of the first conductivity type well region includes an area under the second type through hole and covering the first type trench bottom area as well as side area;
  • the boundaries of the first conductivity type well region along the direction parallel to the first type trenches are all located below the second type of through holes, and the first conductivity type epitaxial layer is close to the first type of trench.
  • the side region and the bottom region of at least one of the first-type trench segments of the second-type trench parallel to the similar-type trenches are not distributed with the first conductivity type well region;
  • the concentration of the impurity of the first conductivity type in the well region of the first conductivity type is 1.01 to 5 times the concentration of the impurity of the first conductivity type in the epitaxial layer of the first conductivity type.
  • the distribution region of the well region of the first conductivity type includes, in a direction parallel to the trench of the first type, the second hole between the through hole of the second type and the trench of the second type. the side area and the bottom area of the first type of trench, the side area and the bottom area of the first type of trench between the adjacent second type of through holes, and the side area and the bottom area of the second type of trench;
  • the well region of the first conductivity type extends along a boundary in a direction parallel to the trench of the first type to a partial region below the via hole of the second type, and the epitaxial layer of the first conductivity type is close to the The side region and the bottom region of at least one of the first-type trenches of the second-type trench segment parallel to the first-type trench are covered by the first-conductivity-type well region;
  • the concentration of the first conductivity type impurity in the first conductivity type epitaxial layer is 1.01 to 5 times the concentration of the first conductivity type impurity in the first conductivity type well region.
  • the inside of the second-type trench is filled with first-type conductive polysilicon, a field oxygen layer is set between the first-type conductive polysilicon and the first conductive epitaxial layer, and a field oxide layer is set above the second-type trench.
  • the second type of insulating dielectric layer, the source metal is arranged above the second type of insulating dielectric layer, the first type of conductive polysilicon in the second type of trench passes through the A first type of via is in ohmic contact with the source metal.
  • a body region of the second conductivity type is provided on the surface of the epitaxial layer of the first conductivity type between the segment of the trench of the second type parallel to the trench of the first type and the adjacent trench of the first type, and the A second-type insulating dielectric layer is disposed above the body region of the second conductivity type, and a source metal is disposed above the second-type insulating dielectric layer, and the source metal passes through the second insulating dielectric layer located in the second-type insulating dielectric layer.
  • the via-like hole is in ohmic contact with the second conductivity type body region.
  • a second type of insulating dielectric layer is disposed above each of the first type of trenches, and a gate metal is disposed above part of the second type of insulating dielectric layer, and the gate metal is positioned on the second type of trench.
  • the third type of through hole in the insulating dielectric layer is in ohmic contact with the second type of conductive polysilicon.
  • the power semiconductor device includes an N-type power semiconductor device and a P-type power semiconductor device.
  • the first conductivity type is N-type
  • the second conductivity type is P-type
  • the first conductivity type is P-type
  • the second conductivity type is N-type
  • a method for manufacturing a power semiconductor device as described above including:
  • a field oxide layer is formed on the surface of the epitaxial layer of the first conductivity type, the bottom region and side regions of the first type of trenches, and the bottom region and side regions of the second type of trenches ;
  • first-type conductive polysilicon in the first-type trench and the second-type trench respectively;
  • a first-type insulating dielectric layer is formed in the etched area
  • Impurities to form a well region of the first conductivity type including:
  • the photoresist After coating the photoresist, selectively retaining part of the photoresist, injecting impurities of the first conductivity type into the side region and the bottom region of the first type trench at a first angle to form a well region of the first conductivity type, the The distribution area of the well region of the first conductivity type includes the side region and the bottom region under the second type through hole and covering the trench of the first type, and the first conductivity type impurity in the well region of the first conductivity type The concentration is higher than the concentration of the first conductivity type impurity in the first conductivity type epitaxial layer; or,
  • the distribution region of the well region of the first conductivity type includes, in a direction parallel to the first type of trench, the first type of trench between the second type of through hole and the second type of trench.
  • the concentration of the impurity of the first conductivity type in the type well region is lower than the concentration of the impurity of the first conductivity type in the epitaxial layer of the first conductivity type.
  • the value range of the first angle is between 0° and 60°.
  • the device by setting the well region of the first conductivity type, it is avoided that the device has a large current gathering at the position of the terminal and the transition region, so that the terminal and the transition region are not damaged, thus improving the short-circuit working mode of the device. Reliability, while improving the short-circuit capability of the device.
  • FIG. 1 is a schematic top view of the metal and trenches of the device provided by the present invention.
  • Fig. 2 is a schematic cross-sectional structure cut along the dotted line AA' in Fig. 1 in an embodiment of the present invention.
  • Fig. 3 is a schematic cross-sectional structure cut along the dotted line BB' in Fig. 1 in an embodiment of the present invention.
  • Fig. 4 is a schematic cross-sectional structure cut along the dotted line CC' in Fig. 1 in an embodiment of the present invention.
  • Fig. 5 is a schematic cross-sectional structure cut along the dotted line DD' in Fig. 1 in an embodiment of the present invention.
  • FIG. 6 is a schematic cross-sectional structure diagram of growing a first conductivity type epitaxial layer on a first conductivity type substrate in an embodiment of the present invention.
  • FIG. 7 is a schematic cross-sectional structure diagram of forming a first-type trench and a second-type trench in an embodiment of the present invention.
  • FIG. 8 is a schematic cross-sectional structure diagram of forming a well region of the first conductivity type in an embodiment of the present invention.
  • FIG. 9 is a schematic diagram of a cross-sectional structure of removing photoresist and thick oxide layer in an embodiment of the present invention.
  • FIG. 10 is a schematic cross-sectional structure diagram of forming a field oxygen layer in an embodiment of the present invention.
  • FIG. 11 is a schematic cross-sectional structure diagram of forming the first type of conductive polysilicon in an embodiment of the present invention.
  • FIG. 12 is a schematic cross-sectional view of selectively etching the upper half of the conductive polysilicon in the first type of trench in an embodiment of the present invention.
  • FIG. 13 is a schematic cross-sectional view of the top half of the trench filled with an insulating dielectric layer deposited in an embodiment of the present invention.
  • FIG. 14 is a schematic cross-sectional structure diagram of removing the insulating dielectric layer above the epitaxial layer of the first conductivity type in an embodiment of the present invention.
  • FIG. 15 is a schematic cross-sectional structure diagram of forming a first type of insulating medium in an embodiment of the present invention.
  • FIG. 16 is a schematic cross-sectional structure diagram of forming a gate oxide layer in an embodiment of the present invention.
  • FIG. 17 is a schematic cross-sectional structure diagram of forming the second type of conductive polysilicon in an embodiment of the present invention.
  • FIG. 18 is a schematic cross-sectional structure diagram of forming a body region of the second conductivity type and a source region of the first conductivity type in an embodiment of the present invention.
  • FIG. 19 is a schematic cross-sectional structure diagram of forming a second type of insulating medium in an embodiment of the present invention.
  • 20 is a schematic cross-sectional structure diagram of forming the first type of through hole, the second type of through hole and the third type of through hole in the embodiment of the present invention.
  • Fig. 21 is a schematic cross-sectional structure diagram taken along the dotted line AA' in Fig. 1 in another embodiment of the present invention.
  • Fig. 22 is a schematic cross-sectional structure diagram taken along the dotted line BB' in Fig. 1 in another embodiment of the present invention.
  • Fig. 23 is a schematic cross-sectional structure diagram taken along the dotted line CC' in Fig. 1 in another embodiment of the present invention.
  • Fig. 24 is a schematic cross-sectional view taken along the dotted line DD' in Fig. 1 in another embodiment of the present invention.
  • FIG. 25 is a schematic cross-sectional structure diagram of a cell provided with a well region of the first conductivity type in an embodiment of the present invention.
  • FIG. 26 is a schematic cross-sectional structure diagram of a cell without a well region of the first conductivity type in an embodiment of the present invention.
  • Fig. 27 is a diagram of the electric field distribution cut along the dotted line FF' and the dotted line EE' when the cellular structures in Fig. 25 and Fig. 26 respectively break down.
  • Fig. 28 is a flow chart of the manufacturing method of the power semiconductor device provided by the present invention.
  • Fig. 29 is a schematic diagram of the positional relationship between the first type of groove and the second type of groove provided by the present invention.
  • FIG. 1 is a top view of a power semiconductor device provided according to an embodiment of the present invention.
  • FIG. 2 to FIG. The sectional views taken along CC' and dotted line DD', and Fig. 21 to Fig. 24 are the sectional views taken along dotted line AA', dotted line BB', dotted line CC' and dotted line DD' respectively in Fig. 1, including:
  • a first conductivity type substrate 1, a first conductivity type epitaxial layer 2 is disposed on the first conductivity type substrate 1, and the upper surface of the first conductivity type epitaxial layer 2 is disposed facing the first conductivity type epitaxial layer 2
  • At least one second-type groove 16 and a plurality of first-type grooves 3 extending inside, the plurality of first-type grooves 3 are arranged parallel to each other and at intervals, and the second-type groove 16 surrounds the first-type groove Slot 3 is set.
  • first-type grooves 3 are arranged parallel to each other, and the second-type grooves 16 surround and surround a plurality of first-type grooves 3 , for example, the direction shown in FIG. 1
  • first type of grooves 3 are arranged in parallel along the horizontal direction
  • the second type of grooves 16 are arranged in a ring shape
  • all the first type of grooves 3 are located in the ring shape of the second type of grooves 13
  • Figure 29 the schematic diagram of the positional relationship between the first type of groove 3 and the second type of groove 16 is shown in Figure 29. Two or more grooves 16 of the second type, and the plurality of grooves 16 of the second type are all arranged around.
  • the interior of part of the groove segments of each first-type trench 3 is completely filled with the first-type conductive polysilicon 5 , and the first-type conductive polysilicon 5 is connected to the first-type conductive type epitaxial layer 2
  • a field oxygen layer 6 made of an insulating medium is disposed between them, a second type insulating dielectric layer 12 is disposed above the first type trench 3, and a source metal 13 is disposed above the second type insulating dielectric layer 12, The source metal 13 is in ohmic contact with the first-type conductive polysilicon 5 in the first-type trench 3 through the first-type through hole 15 in the second-type insulating dielectric layer 12 .
  • the structure can be understood with reference to those shown in Figures 3 and 5, since the position of BB' is the central position of the device, the first type of through hole 15 is provided at the central position, and along the dotted line BB' The second type of through-holes 14 are provided on both sides. In addition, it can be seen from FIG. 5 that the interior of the first-type trench 3 below the first-type through hole 15 is completely filled with the first-type conductive polysilicon 5 .
  • the interior of part of the groove segment of each first-type trench 3 is filled with the first-type conductive polysilicon 5
  • the second-type conductive polysilicon 8 is filled above the first-type conductive polysilicon 5
  • a first-type insulating dielectric layer 7 is filled
  • between the second-type conductive polysilicon 8 and the first-type conductive epitaxial layer 2 is arranged Gate oxide layer 9, a second conductivity type body region 10 is provided on the upper surface of the first conductivity type epitaxial layer 2 between every two adjacent first type trenches 3, part of the second conductivity type body region 10
  • a first-conductivity-type source region 11 is provided on the upper surface, and a second-type insulating dielectric layer 12 is arranged above the first-type trench 3 and the first-conductivity-type source region 11, and part of the second-type insulating dielectric layer 12, the source metal 13 is provided
  • a first conductivity type well region 4 is provided in the first conductivity type epitaxial layer 2 , and the distribution area of the first conductivity type well region 4 includes the underside of the second type through hole 14 and Covering the side region and bottom region of the first type trench 3, the concentration of the first conductivity type impurity in the first conductivity type well region 4 is higher than that of the first conductivity type impurity in the first conductivity type epitaxial layer 2 the concentration of a conductivity type impurity; or,
  • the first conductivity type well region 4 is set in the first conductivity type epitaxial layer 2, and the distribution area of the first conductivity type well region 4 includes, in the first type trench 3 In the parallel direction, the side area and the bottom area of the first type of groove 3 between the second type of through hole 14 and the second type of groove 16 are adjacent to the second type of through hole 14 Between the side region and the bottom region of the first type trench 3, and the side region and the bottom region of the second type trench 16, the concentration of the first conductivity type impurity in the first conductivity type well region 4 lower than the concentration of the first conductivity type impurity in the first conductivity type epitaxial layer 2 .
  • the PN junction formed by the body region 10 of the second conductivity type and the epitaxial layer 2 of the first conductivity type and the PN junction formed by the body region 10 of the second conductivity type and the well region 4 of the first conductivity type have different breakdown characteristics. , through the setting of the first conductivity type well region structure as shown in Fig.
  • FIG. 25 It is a schematic diagram of the cross-sectional structure of a cell without a well region of the first conductivity type. As shown in FIG. 27, the cell structures in FIG. 25 and FIG. 26 are cut along the dotted line FF' and the dotted line EE' respectively during breakdown. In FIG.
  • the electric field on the PN junction composed of the body region 10 of the second conductivity type and the well region 4 of the first conductivity type is much higher than that of the body region 10 of the second conductivity type and the epitaxial layer 2 of the first conductivity type.
  • the PN junction which makes the device in the case of avalanche breakdown of a large current, most of the current will flow through the PN junction formed by the second conductivity type body region 10 and the first conductivity type well region 4, thereby protecting the transition region and the terminal region.
  • the PN junction formed by the body region 10 of the second conductivity type and the epitaxial layer 2 of the first conductivity type and the PN junction formed by the body region 10 of the second conductivity type and the well region 4 of the first conductivity type have different breakdown characteristics, as shown in FIG. 21 to the configuration of the first conductivity type well region structure shown in FIG.
  • the concentration of the impurity of the first conductivity type inside, when the avalanche breakdown occurs, the peak electric field intensity on the PN junction formed by the body region 10 of the second conductivity type and the epitaxial layer 2 of the first conductivity type will be obviously higher than that of the body region of the second conductivity type 10 and the peak electric field intensity on the PN junction composed of the well region 4 of the first conductivity type, which makes most of the current flow through the body region 10 of the second conductivity type and the epitaxial layer of the first conductivity type when the device undergoes avalanche breakdown of a large current.
  • the PN junction composed of layer 2 protects the transition region and the terminal region.
  • the power semiconductor device provided by the embodiment of the present invention, by setting the first conductivity type well region, avoids the accumulation of large current in the terminal and the transition region of the device, so that the terminal and the transition region are not damaged, thus improving the performance of the device.
  • the reliability in the short-circuit working mode improves the short-circuit capability of the device at the same time.
  • the first conductivity type well region 4 is provided in the first conductivity type epitaxial layer 2, and the distribution area of the first conductivity type well region 4 includes the The bottom area and the side area below the second type of through hole 14 and covering the first type of trench 3;
  • the boundary of the first conductivity type well region 4 along the direction parallel to the first type trench 3 is located below the second type through hole 14, and the first conductivity type epitaxial layer 2 is close to the The first conductivity type well region 4 is not distributed in the side region and bottom region of at least one of the first type trenches 3 parallel to the second type trench segment;
  • the concentration of the impurity of the first conductivity type in the well region 4 of the first conductivity type is 1.01 to 5 times the concentration of the impurity of the first conductivity type in the epitaxial layer of the first conductivity type.
  • the distribution of the well regions 4 of the first conductivity type can be understood as, along the direction parallel to the trenches 3 of the first type, they are mainly distributed under the via holes 14 of the second type, and include It can be seen from Fig. 2 and Fig. 4 that it covers the sides and bottom of the first type of groove 3.
  • the boundary of the well region 4 of the first conductivity type in this direction does not exceed both ends of the second-type through hole 14 , that is, the boundaries are all below the second-type through-hole 14 .
  • the distribution of the first conductivity type well region 4 is mainly at the bottom and side of the first type of trench 3, and close to the second type of trench 16 groove segment (The groove segment should be parallel to the first type of groove 3 , that is, the transverse groove segment portion shown in FIG. 29 ). At least one first type of groove 3 has no well region of the first conductivity type on the side and bottom.
  • the distribution area of the first conductivity type well region 4 includes, in the direction parallel to the first type trench 3, the The side area and bottom area of the first type of groove 3 between the second type of through hole 14 and the second type of groove 16, the first type of groove between adjacent second type of through holes 14 the side area and the bottom area of the groove 3, and the side area and the bottom area of the second type of groove 16;
  • the region of the well 4 of the first conductivity type extends along the boundary in a direction parallel to the trench 3 of the first type to a part of the region below the through hole 14 of the second type, and the epitaxial layer 2 of the first conductivity type
  • the side region and the bottom region of at least one of the first-type trenches 3 close to the second-type trench segment parallel to the first-type trench 3 are covered by the first-conductivity-type well region 4 ;
  • the concentration of the impurity of the first conductivity type in the epitaxial layer 2 of the first conductivity type is 1.01 to 5 times the concentration of the impurity of the first conductivity type in the well region 4 of the first conductivity type.
  • the distribution of the well regions 4 of the first conductivity type can be understood as, in the direction parallel to the first type trenches 3 , except for the first type trenches below the second type through holes 14
  • the bottom and sides of the first-type trenches 3 under other regions are provided with first-conductivity-type well regions 4, and in this direction, the boundary position of the first-conductivity-type well regions 4 can extend to the second-type trenches.
  • the bottom and side of the second type of groove 16 and the side and bottom of at least one first type of groove 3 close to the second type of groove 16 are all A first conductivity type well region 4 is provided.
  • a field oxygen layer 6 is arranged between the first conductive epitaxial layer 2, the second type insulating dielectric layer 12 is arranged above the second type trench 16, and a source is arranged above the second type insulating dielectric layer 12.
  • the first-type conductive polysilicon 5 in the second-type trench 16 is in ohmic contact with the source metal 13 through the first-type through hole 15 located in the second-type insulating dielectric layer 12 .
  • the surface of the epitaxial layer 2 of the first conductivity type between the groove segment of the second type of trench 16 parallel to the first type of trench 3 and the adjacent first type of trench 3 A second conductivity type body region 10 is provided, a second type insulating dielectric layer 12 is disposed above the second conductivity type body region 10, a source metal 13 is disposed above the second type insulation dielectric layer 12, and the source The metal 13 is in ohmic contact with the second conductivity type body region 10 through the second type through hole 14 located in the second type insulating dielectric layer 12 .
  • a second-type insulating dielectric layer 12 is arranged above each of the first-type trenches 3, and a gate is arranged above the second-type insulating dielectric layer 12.
  • the gate metal 17 is in ohmic contact with the second-type conductive polysilicon 8 through the third-type via hole 18 located in the second-type insulating dielectric layer 12 .
  • the power semiconductor device includes an N-type power semiconductor device and a P-type power semiconductor device.
  • the first conductivity type is N-type
  • the second conductivity type is N-type.
  • the type is P-type
  • the power semiconductor device is the P-type semiconductor device
  • the first conductivity type is P-type
  • the second conductivity type is N-type.
  • the power semiconductor device is the N-type power semiconductor device as an example for description.
  • the first conductivity type is N-type
  • the second conductivity type is P-type.
  • an N-type substrate 1 is included, and an N-type epitaxial layer 2 is arranged above the N-type substrate 1, as shown in Figure 1
  • a schematic top view of the device strip-shaped first-type trenches 3 parallel to each other and uniformly distributed are arranged on the surface of the N-type epitaxial layer 2, and the periphery of the first-type trenches 3 is surrounded by second-type trenches 16 surround.
  • FIG. 3 it is a schematic cross-sectional structure cut along the dotted line BB' in FIG.
  • the first-type conductive polysilicon 5 in the first-type trenches 3 is insulated from the N-type epitaxial layer 2 by the field oxygen layer 6, and the N-type epitaxial layer 2 between adjacent first-type trenches 3 is insulated from the first-type trenches.
  • the through hole 15 is in ohmic contact with the first type conductive polysilicon 5 in the first type trench 3; the second type trench 16 is filled with the first type conductive polysilicon 5, and the first type conductive polysilicon 5 in the second type trench 16 Conductive polysilicon 5 is insulated from N-type epitaxial layer 2 by field oxygen layer 6 .
  • a second type of insulating dielectric layer 12 is arranged above the second type of trench 16 parallel to the first type of trench 3, and a source is arranged above the second type of insulating dielectric layer 12.
  • An electrode metal 13 , the source metal 13 is in ohmic contact with the first type conductive polysilicon 5 in the second type trench 16 through the first type through hole 15 .
  • FIG 2 it is a schematic cross-sectional structure cut along the dotted line AA' in Figure 1.
  • the lower half of the first type of trench 3 is provided with the first type of conductive polysilicon 5, and the upper half is provided with the second type of conductive polysilicon.
  • first-type conductive polysilicon 5 and second-type conductive polysilicon 8 are insulated by first-type insulating dielectric layer 7
  • first-type conductive polysilicon 5 is insulated from N-type epitaxial layer 2 by field oxygen layer 6
  • second-type conductive polysilicon 8 is insulated from the N-type epitaxial layer 2 by the gate oxide layer 9
  • the surface of the N-type epitaxial layer 2 between adjacent first-type trenches 3 is provided with a P-type body region 10
  • An N-type source region 11 is provided
  • a second-type insulating dielectric layer 12 is arranged above the first-type trench 3 and the N-type source region 11, and a source metal layer is arranged above the second-type insulating dielectric layer 12.
  • the source metal 13 is in ohmic contact with the N-type source region 11 and the P-type body region 10 through the second-type through hole 14 in the second-type insulating dielectric layer 12;
  • a P-type body region 10 is provided on the surface of the N-type epitaxial layer 2 between the groove segment of the second-type trench 16 and the adjacent first-type trench 3, and a second-type insulating layer is arranged above the P-type body region 10.
  • the dielectric layer 12 is provided with a source metal 13 above the second-type insulating dielectric layer 12 , and the source metal 13 is in ohmic contact with the P-type body region 10 through the second-type through hole 14 .
  • FIG. 5 it is a schematic cross-sectional structure cut along the dotted line DD' in FIG. layer 12, a gate metal 17 is arranged above the second type insulating dielectric layer 12, and the gate metal 17 passes through the third type through hole 18 in the second type insulating dielectric layer 12 and the second type conductive polysilicon 8 ohm contacts.
  • FIG 4 it is a schematic cross-sectional structure cut along the dotted line CC' in Figure 1.
  • the side walls of the first type of trench 3 and the N-type near the bottom An N-type well region 4 is provided in the epitaxial layer 2, and the N-type well region 4 is provided only under the second type of through hole 14, and the edge of the N-type well region 4 does not cross the second type of through hole.
  • the end of the hole 14, and the edge of the N-type well region 4 is about 5 ⁇ m away from the end of the second type of through hole 14; the concentration of the N-type impurity in the N-type well region 4 is higher than that of the N-type impurities in the N-type epitaxial layer 2 concentration of impurities.
  • the N-type well region 4 is arranged like this because the PN junction formed by the P-type body region 10 and the N-type epitaxial layer 2, and the PN junction formed by the P-type body region 10 and the N-type well region 4 have different breakdown characteristics.
  • the doping concentration of the N-type well region 4 is greater than that of the epitaxial layer 2.
  • the peak electric field intensity on the PN junction composed of the P-type body region 10 and the epitaxial layer 2 will be significantly lower than that of the P-type body region 10 and the epitaxial layer 2.
  • FIG. 25 is a schematic cross-sectional structure diagram of a cell provided with a first conductivity type well region in this embodiment, and as shown in FIG. 26 is not shown in this embodiment.
  • Schematic diagram of the cross-sectional structure of a cell with a well region of the first conductivity type as shown in Figure 27, the electric field cut along the dotted line FF' and the dotted line EE' when the cell structure in Figure 25 and Figure 26 respectively breaks down
  • Distribution diagram, in Figure 25, the electric field on the PN junction composed of P-type body region 10 and N-type well region 4 is much higher than that of the PN junction composed of P-type body region 10 and epitaxial layer 2, which makes the device break down under high current avalanche At this time, most of the current will flow through the PN junction formed by the P-type body region 10 and the N-type well region 4, thereby protecting the transition region and the terminal region.
  • FIG. 21 to FIG. 24 it includes an N-type substrate 1, and an N-type epitaxial layer 2 is arranged on the N-type substrate 1, as shown in FIG. 1 is a schematic top view of the device provided by the present invention.
  • N-type epitaxial layer 2 On the surface of the N-type epitaxial layer 2, strip-shaped first-type trenches 3 parallel to each other and uniformly distributed are arranged. The periphery is surrounded by second-type grooves 16;
  • FIG. 22 it is a schematic cross-sectional structure cut along the dotted line BB' in FIG. 1.
  • the first-type trench 3 is filled with the first-type conductive polysilicon 5.
  • the first-type conductive polysilicon 5 in the first-type trenches 3 is insulated from the N-type epitaxial layer 2 by the field oxygen layer 6, and the N-type epitaxial layer 2 between adjacent first-type trenches 3 is insulated from the first-type trenches.
  • the conductive polysilicon 5 is insulated from the N-type epitaxial layer 2 by the field oxygen layer 6.
  • a second-type insulating dielectric layer is arranged above the second-type trench 16 parallel to the first-type trench 3 12.
  • a source metal 13 is provided above the second-type insulating dielectric layer 12, and the source metal 13 passes through the first-type through hole 15 and the first-type conductive polysilicon 5 ohm in the second-type trench 16 touch.
  • FIG 21 it is a schematic cross-sectional structure cut along the dotted line AA' in Figure 1.
  • the lower half of the first type of trench 3 is provided with the first type of conductive polysilicon 5, and the upper half is provided with the second type of conductive polysilicon 5.
  • first-type conductive polysilicon 5 and second-type conductive polysilicon 8 are insulated by first-type insulating dielectric layer 7
  • first-type conductive polysilicon 5 is insulated from N-type epitaxial layer 2 by field oxygen layer 6
  • second-type conductive polysilicon 8 is insulated from the N-type epitaxial layer 2 by the gate oxide layer 9
  • the surface of the N-type epitaxial layer 2 between adjacent first-type trenches 3 is provided with a P-type body region 10
  • An N-type source region 11 is provided
  • a second-type insulating dielectric layer 12 is arranged above the first-type trench 3 and the N-type source region 11, and a source metal layer is arranged above the second-type insulating dielectric layer 12.
  • the source metal 13 is in ohmic contact with the N-type source region 11 and the P-type body region 10 through the second-type through hole 14 in the second-type insulating dielectric layer 12;
  • a P-type body region 10 is provided on the surface of the N-type epitaxial layer 2 between the groove segment of the second-type trench 16 and the adjacent first-type trench 3, and a second-type insulating layer is arranged above the P-type body region 10.
  • the dielectric layer 12 is provided with a source metal 13 above the second-type insulating dielectric layer 12 , and the source metal 13 is in ohmic contact with the P-type body region 10 through the second-type through hole 14 .
  • FIG. 24 it is a schematic cross-sectional structure cut along the dotted line DD' in FIG. layer 12, a gate metal 17 is arranged above the second type insulating dielectric layer 12, and the gate metal 17 passes through the third type through hole 18 in the second type insulating dielectric layer 12 and the second type conductive polysilicon 8 ohm contacts.
  • N-type well region 4 is provided in the N-type epitaxial layer 2 near the sidewall and bottom of 3, and the edge of the N-type well region 4 crosses the end of the second type through hole 14, and partly enters the second type through hole 14.
  • an N-type well region 4 is arranged in the N-type epitaxial layer 2 near the sidewall and bottom of the second type trench 16; the concentration of N-type impurities in the N-type well region 4 is low The concentration of N-type impurities in the N-type epitaxial layer 2 .
  • the top view angle of the device, the N-type epitaxy near the sidewall and the bottom of the first first-type trench 3 near the second-type trench 16 N-type well region 4 is arranged in layer 2 .
  • the N-type well region 4 is arranged like this because the PN junction formed by the P-type body region 10 and the N-type epitaxial layer 2, and the PN junction formed by the P-type body region 10 and the N-type well region 4 have different breakdown characteristics.
  • the doping concentration of the N-type well region 4 is lower than that of the N-type epitaxial layer 2.
  • the peak electric field intensity on the PN junction composed of the P-type body region 10 and the N-type epitaxial layer 2 will be significantly higher than that of the P-type well region 10.
  • the peak electric field intensity on the PN junction formed by the body region 10 and the N-type well region 4 makes most of the current flow through the P-type body region 10 and the N-type epitaxial layer 2 when the device undergoes avalanche breakdown at a high current. PN junction, thus protecting the transition region and the terminal region.
  • a method for manufacturing a power semiconductor device as described above is provided, wherein, as shown in FIG. 28 , it includes:
  • the power semiconductor device includes an N-type power semiconductor device and a P-type power semiconductor device.
  • the first conductivity type is N-type
  • the second conductivity type is N-type.
  • the type is P-type
  • the power semiconductor device is the P-type semiconductor device
  • the first conductivity type is P-type
  • the second conductivity type is N-type.
  • the power semiconductor device is the N-type power semiconductor device as an example for description.
  • the first conductivity type is N-type
  • the second conductivity type is P-type.
  • an N-type substrate 1 is provided, and an N-type epitaxial layer 2 is grown on the N-type substrate 1 .
  • a thick oxide layer 19 is formed on the surface of the N-type epitaxial layer 2, and the thick oxide layer 19 and the N-type epitaxial layer 2 are selectively etched to form the first-type trench 3 and the second-type groove. Groove-like 16.
  • a part of the photoresist 20 is selectively retained, and then at a first angle a (in this embodiment, the first angle a shown in FIG. 8 can specifically be 17°) to implant N-type impurities into the sidewall and bottom of the first-type trench 3 to form an N-type well region 4 .
  • Impurities to form a well region of the first conductivity type including:
  • the photoresist After coating the photoresist, selectively retaining part of the photoresist, injecting impurities of the first conductivity type into the side region and the bottom region of the first type trench at a first angle to form a well region of the first conductivity type, the The distribution area of the well region of the first conductivity type includes the side region and the bottom region under the second type through hole and covering the trench of the first type, and the first conductivity type impurity in the well region of the first conductivity type The concentration is higher than the concentration of the first conductivity type impurity in the first conductivity type epitaxial layer; or,
  • the distribution region of the well region of the first conductivity type includes, in a direction parallel to the first type of trench, the first type of trench between the second type of through hole and the second type of trench.
  • the concentration of the impurity of the first conductivity type in the type well region is lower than the concentration of the impurity of the first conductivity type in the epitaxial layer of the first conductivity type.
  • N-type impurities are implanted into both the side region and the bottom region of the first-type trench 3 at a first angle a to form an N-type well region 4 .
  • the N-type well region 4 is distributed under the second-type through hole 14 and covers the side region and the bottom region of the first-type trench 3, and the N-type impurity in the N-type well region 4
  • the concentration is higher than the concentration of N-type impurities in the N-type epitaxial layer 2 .
  • the concentration of N-type impurities in the N-type well region 4 is 1.01 to 5 times the concentration of N-type impurities in the N-type epitaxial layer 2 .
  • P-type impurities are implanted in the side region and the bottom region of the first type trench 3 at a first angle a (it should be understood here that this method is achieved by implanting
  • the P-type impurity reduces the concentration of the N-type impurity by neutralizing the N-type impurity), forming an N-type well region 4, and the N-type well region 4 is distributed under the first type of through hole 15 and covers the The side area and the bottom area of the first type trench 3, and the side area and the bottom area distributed around the second type trench 16 and covering the second type trench 16, the N type
  • the concentration of the N-type impurity in the well region 4 is lower than the concentration of the first conductivity type impurity in the N-type epitaxial layer 2 .
  • the concentration of the impurity of the first conductivity type in the N-type epitaxial layer 2 is 1.01 to 5 times the concentration of the impurity of the first conductivity type in the well region 4 of the first conductivity type.
  • the value range of the first angle a is between 0° and 60°.
  • conductive polysilicon is deposited to fill up the first-type trench 3 and the second-type trench 16, and then the conductive polysilicon is etched, and the first-type trench 3 and the second-type trench 16 are etched.
  • the first type of conductive polysilicon 5 is formed in 16 .
  • the upper half of the conductive polysilicon in the first type trench 3 is selectively etched; as shown in FIG. 13, an insulating dielectric layer is deposited to fill the top half of the first type trench 3. half; as shown in Figure 14, remove the insulating dielectric layer above the N-type epitaxial layer 2; as shown in Figure 15, selectively etch part of the insulating dielectric layer in the first type of trench 3 to form the first type of insulating dielectric 7.
  • a gate oxide layer 9 is formed in the first type trench 3; as shown in FIG. 17, conductive polysilicon is deposited to fill the upper half of the first type trench 3, and then the The conductive polysilicon is etched to form the second type conductive polysilicon 8 in the upper half of the first type trench 3 .
  • P-type impurities are implanted on the surface of the device and annealed to form a P-type body region 10 , and then N-type impurities are selectively implanted to form an N-type source region 11 after activation.
  • an insulating medium is deposited to form a second type of insulating medium 12 on the surface of the device.
  • the second type of insulating dielectric 12, the N-type epitaxial layer 2, the first type of conductive polysilicon 5 and the second type of conductive polysilicon 8 are selectively etched to form the first type of through holes 15, The second type of through hole 14 and the third type of through hole 18 .
  • the metal is selectively etched to form source metal 13 and gate metal 17 .
  • the manufacturing method of the power semiconductor device provided by the embodiment of the present invention avoids the accumulation of large current in the position of the terminal and the transition region of the device by forming the well region of the first conductivity type, so that the terminal and the transition region are not damaged.
  • the reliability in the short-circuit working mode of the device is improved, and the short-circuit capability of the device is improved at the same time.
  • the manufacturing method provided by the embodiment of the present invention has the advantages of simple process, low cost, and compatibility with existing processes.

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  • Power Engineering (AREA)
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  • Ceramic Engineering (AREA)
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Abstract

La présente invention relève du domaine technique des semi-conducteurs. L'invention concerne spécifiquement un dispositif semi-conducteur de puissance. Le dispositif semi-conducteur de puissance comprend : un substrat de premier type de conductivité, sur lequel est disposée une couche épitaxiale de premier type de conductivité, des premières régions de puits de type à conductivité étant agencées dans la couche épitaxiale de premier type de conductivité, et étant réparties au-dessous de trous traversants de second type et de parties latérales de couvercle et de parties inférieures de tranchées de premier type, et la concentration d'impuretés dans les régions de puits de premier type de conductivité étant supérieure à la concentration d'impuretés dans la couche épitaxiale de premier type de conductivité ; ou, les premières régions de puits de type de conductivité étant réparties sur des parties latérales et des parties inférieures de tranchées de premier type entre les trous traversants de second type et les tranchées de second type, au niveau de parties latérales et de parties inférieures de tranchées de premier type entre des trous traversants de second type adjacents, et au niveau de parties latérales et de parties inférieures des tranchées de second type, et la concentration d'impuretés dans les régions de puits de premier type de conductivité étant inférieure à la concentration d'impuretés dans la couche épitaxiale de premier type de conductivité. La présente invention concerne en outre un procédé de fabrication d'un dispositif semi-conducteur de puissance. Au moyen du dispositif à semi-conducteur de puissance selon la présente invention, la fiabilité de fonctionnement de court-circuit du dispositif peut être améliorée.
PCT/CN2021/128397 2021-10-31 2021-11-03 Dispositif à semi-conducteurs de puissance et son procédé de fabrication WO2023070703A1 (fr)

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