WO2023070703A1 - Power semiconductor device and manufacturing method therefor - Google Patents

Power semiconductor device and manufacturing method therefor Download PDF

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Publication number
WO2023070703A1
WO2023070703A1 PCT/CN2021/128397 CN2021128397W WO2023070703A1 WO 2023070703 A1 WO2023070703 A1 WO 2023070703A1 CN 2021128397 W CN2021128397 W CN 2021128397W WO 2023070703 A1 WO2023070703 A1 WO 2023070703A1
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Prior art keywords
type
trench
conductivity type
conductivity
region
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PCT/CN2021/128397
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French (fr)
Chinese (zh)
Inventor
朱袁正
叶鹏
周锦程
杨卓
刘晶晶
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无锡新洁能股份有限公司
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Publication of WO2023070703A1 publication Critical patent/WO2023070703A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors

Definitions

  • the invention relates to the technical field of semiconductors, in particular to a power semiconductor device and a method for manufacturing the power semiconductor device.
  • the short-circuit mode In the short-circuit mode, a large amount of current flows through the shielded trench power device. When the short-circuit mode ends, the device is turned off. The parasitic inductance in the circuit causes the current to forcibly avalanche and break down the device, and the device will experience a very short period of time. High voltage and super high current state. Because the device has a breakdown weak point in the terminal and transition area, it will cause the current to concentrate and generate heat, and because the heat cannot be smoothly transferred to the active area due to the extremely short time, it will cause the device to have a burn point in the terminal or transition area.
  • the invention provides a power semiconductor device and a manufacturing method of the power semiconductor device, which solve the problem of low reliability in the short-circuit working mode existing in the related art.
  • a power semiconductor device including:
  • each first-type trench is completely filled with first-type conductive polysilicon, and a field oxygen layer composed of an insulating medium is arranged between the first-type conductive polysilicon and the first-conductivity-type epitaxial layer.
  • a second-type insulating dielectric layer is arranged above the first-type trenches, a source metal is arranged above the second-type insulating dielectric layer, and the source metal passes through the A first type of via hole is in ohmic contact with the first type of conductive polysilicon located in the first type of trench;
  • the inner part of part of the groove segment of each first-type trench is filled with the first-type conductive polysilicon, and the second-type conductive polysilicon is filled above the first-type conductive polysilicon, and the second-type conductive polysilicon and the first-type conductive polysilicon are filled.
  • a first-type insulating dielectric layer is filled between the conductive polysilicon, a gate oxide layer is provided between the second-type conductive polysilicon and the first-conductive-type epitaxial layer, and the first-type trench between every two adjacent first-type trenches
  • a second conductivity type body region is provided on the upper surface of one type of conductivity type epitaxial layer, and a first conductivity type source region is arranged on the upper surface of part of the second conductivity type body region, and the first type of trench and the first conductivity type
  • a second-type insulating dielectric layer is arranged above the source regions of the second type, and a source metal is arranged above part of the second-type insulating dielectric layer, and the source metal passes through the second-type insulating dielectric layer located in the second-type insulating dielectric layer.
  • the through holes are respectively in ohmic contact with the source region of the first conductivity type and the body region of the second conductivity type;
  • a first conductivity type well region is provided in the first conductivity type epitaxial layer, and the distribution area of the first conductivity type well region includes a side region below the second type through hole and covering the first type trench and the bottom region, the concentration of the first conductivity type impurity in the first conductivity type well region is higher than the concentration of the first conductivity type impurity in the first conductivity type epitaxial layer; or,
  • a first conductivity type well region is provided in the first conductivity type epitaxial layer, and the distribution area of the first conductivity type well region includes, in a direction parallel to the first type trench, the second type through hole the side region and the bottom region of the first-type trench between the second-type trench, the side region and the bottom region of the first-type trench between adjacent second-type through holes, and In the side region and the bottom region of the second type trench, the concentration of the first conductivity type impurity in the first conductivity type well region is lower than the concentration of the first conductivity type impurity in the first conductivity type epitaxial layer.
  • a first conductivity type well region is provided in the first conductivity type epitaxial layer, and the distribution area of the first conductivity type well region includes an area under the second type through hole and covering the first type trench bottom area as well as side area;
  • the boundaries of the first conductivity type well region along the direction parallel to the first type trenches are all located below the second type of through holes, and the first conductivity type epitaxial layer is close to the first type of trench.
  • the side region and the bottom region of at least one of the first-type trench segments of the second-type trench parallel to the similar-type trenches are not distributed with the first conductivity type well region;
  • the concentration of the impurity of the first conductivity type in the well region of the first conductivity type is 1.01 to 5 times the concentration of the impurity of the first conductivity type in the epitaxial layer of the first conductivity type.
  • the distribution region of the well region of the first conductivity type includes, in a direction parallel to the trench of the first type, the second hole between the through hole of the second type and the trench of the second type. the side area and the bottom area of the first type of trench, the side area and the bottom area of the first type of trench between the adjacent second type of through holes, and the side area and the bottom area of the second type of trench;
  • the well region of the first conductivity type extends along a boundary in a direction parallel to the trench of the first type to a partial region below the via hole of the second type, and the epitaxial layer of the first conductivity type is close to the The side region and the bottom region of at least one of the first-type trenches of the second-type trench segment parallel to the first-type trench are covered by the first-conductivity-type well region;
  • the concentration of the first conductivity type impurity in the first conductivity type epitaxial layer is 1.01 to 5 times the concentration of the first conductivity type impurity in the first conductivity type well region.
  • the inside of the second-type trench is filled with first-type conductive polysilicon, a field oxygen layer is set between the first-type conductive polysilicon and the first conductive epitaxial layer, and a field oxide layer is set above the second-type trench.
  • the second type of insulating dielectric layer, the source metal is arranged above the second type of insulating dielectric layer, the first type of conductive polysilicon in the second type of trench passes through the A first type of via is in ohmic contact with the source metal.
  • a body region of the second conductivity type is provided on the surface of the epitaxial layer of the first conductivity type between the segment of the trench of the second type parallel to the trench of the first type and the adjacent trench of the first type, and the A second-type insulating dielectric layer is disposed above the body region of the second conductivity type, and a source metal is disposed above the second-type insulating dielectric layer, and the source metal passes through the second insulating dielectric layer located in the second-type insulating dielectric layer.
  • the via-like hole is in ohmic contact with the second conductivity type body region.
  • a second type of insulating dielectric layer is disposed above each of the first type of trenches, and a gate metal is disposed above part of the second type of insulating dielectric layer, and the gate metal is positioned on the second type of trench.
  • the third type of through hole in the insulating dielectric layer is in ohmic contact with the second type of conductive polysilicon.
  • the power semiconductor device includes an N-type power semiconductor device and a P-type power semiconductor device.
  • the first conductivity type is N-type
  • the second conductivity type is P-type
  • the first conductivity type is P-type
  • the second conductivity type is N-type
  • a method for manufacturing a power semiconductor device as described above including:
  • a field oxide layer is formed on the surface of the epitaxial layer of the first conductivity type, the bottom region and side regions of the first type of trenches, and the bottom region and side regions of the second type of trenches ;
  • first-type conductive polysilicon in the first-type trench and the second-type trench respectively;
  • a first-type insulating dielectric layer is formed in the etched area
  • Impurities to form a well region of the first conductivity type including:
  • the photoresist After coating the photoresist, selectively retaining part of the photoresist, injecting impurities of the first conductivity type into the side region and the bottom region of the first type trench at a first angle to form a well region of the first conductivity type, the The distribution area of the well region of the first conductivity type includes the side region and the bottom region under the second type through hole and covering the trench of the first type, and the first conductivity type impurity in the well region of the first conductivity type The concentration is higher than the concentration of the first conductivity type impurity in the first conductivity type epitaxial layer; or,
  • the distribution region of the well region of the first conductivity type includes, in a direction parallel to the first type of trench, the first type of trench between the second type of through hole and the second type of trench.
  • the concentration of the impurity of the first conductivity type in the type well region is lower than the concentration of the impurity of the first conductivity type in the epitaxial layer of the first conductivity type.
  • the value range of the first angle is between 0° and 60°.
  • the device by setting the well region of the first conductivity type, it is avoided that the device has a large current gathering at the position of the terminal and the transition region, so that the terminal and the transition region are not damaged, thus improving the short-circuit working mode of the device. Reliability, while improving the short-circuit capability of the device.
  • FIG. 1 is a schematic top view of the metal and trenches of the device provided by the present invention.
  • Fig. 2 is a schematic cross-sectional structure cut along the dotted line AA' in Fig. 1 in an embodiment of the present invention.
  • Fig. 3 is a schematic cross-sectional structure cut along the dotted line BB' in Fig. 1 in an embodiment of the present invention.
  • Fig. 4 is a schematic cross-sectional structure cut along the dotted line CC' in Fig. 1 in an embodiment of the present invention.
  • Fig. 5 is a schematic cross-sectional structure cut along the dotted line DD' in Fig. 1 in an embodiment of the present invention.
  • FIG. 6 is a schematic cross-sectional structure diagram of growing a first conductivity type epitaxial layer on a first conductivity type substrate in an embodiment of the present invention.
  • FIG. 7 is a schematic cross-sectional structure diagram of forming a first-type trench and a second-type trench in an embodiment of the present invention.
  • FIG. 8 is a schematic cross-sectional structure diagram of forming a well region of the first conductivity type in an embodiment of the present invention.
  • FIG. 9 is a schematic diagram of a cross-sectional structure of removing photoresist and thick oxide layer in an embodiment of the present invention.
  • FIG. 10 is a schematic cross-sectional structure diagram of forming a field oxygen layer in an embodiment of the present invention.
  • FIG. 11 is a schematic cross-sectional structure diagram of forming the first type of conductive polysilicon in an embodiment of the present invention.
  • FIG. 12 is a schematic cross-sectional view of selectively etching the upper half of the conductive polysilicon in the first type of trench in an embodiment of the present invention.
  • FIG. 13 is a schematic cross-sectional view of the top half of the trench filled with an insulating dielectric layer deposited in an embodiment of the present invention.
  • FIG. 14 is a schematic cross-sectional structure diagram of removing the insulating dielectric layer above the epitaxial layer of the first conductivity type in an embodiment of the present invention.
  • FIG. 15 is a schematic cross-sectional structure diagram of forming a first type of insulating medium in an embodiment of the present invention.
  • FIG. 16 is a schematic cross-sectional structure diagram of forming a gate oxide layer in an embodiment of the present invention.
  • FIG. 17 is a schematic cross-sectional structure diagram of forming the second type of conductive polysilicon in an embodiment of the present invention.
  • FIG. 18 is a schematic cross-sectional structure diagram of forming a body region of the second conductivity type and a source region of the first conductivity type in an embodiment of the present invention.
  • FIG. 19 is a schematic cross-sectional structure diagram of forming a second type of insulating medium in an embodiment of the present invention.
  • 20 is a schematic cross-sectional structure diagram of forming the first type of through hole, the second type of through hole and the third type of through hole in the embodiment of the present invention.
  • Fig. 21 is a schematic cross-sectional structure diagram taken along the dotted line AA' in Fig. 1 in another embodiment of the present invention.
  • Fig. 22 is a schematic cross-sectional structure diagram taken along the dotted line BB' in Fig. 1 in another embodiment of the present invention.
  • Fig. 23 is a schematic cross-sectional structure diagram taken along the dotted line CC' in Fig. 1 in another embodiment of the present invention.
  • Fig. 24 is a schematic cross-sectional view taken along the dotted line DD' in Fig. 1 in another embodiment of the present invention.
  • FIG. 25 is a schematic cross-sectional structure diagram of a cell provided with a well region of the first conductivity type in an embodiment of the present invention.
  • FIG. 26 is a schematic cross-sectional structure diagram of a cell without a well region of the first conductivity type in an embodiment of the present invention.
  • Fig. 27 is a diagram of the electric field distribution cut along the dotted line FF' and the dotted line EE' when the cellular structures in Fig. 25 and Fig. 26 respectively break down.
  • Fig. 28 is a flow chart of the manufacturing method of the power semiconductor device provided by the present invention.
  • Fig. 29 is a schematic diagram of the positional relationship between the first type of groove and the second type of groove provided by the present invention.
  • FIG. 1 is a top view of a power semiconductor device provided according to an embodiment of the present invention.
  • FIG. 2 to FIG. The sectional views taken along CC' and dotted line DD', and Fig. 21 to Fig. 24 are the sectional views taken along dotted line AA', dotted line BB', dotted line CC' and dotted line DD' respectively in Fig. 1, including:
  • a first conductivity type substrate 1, a first conductivity type epitaxial layer 2 is disposed on the first conductivity type substrate 1, and the upper surface of the first conductivity type epitaxial layer 2 is disposed facing the first conductivity type epitaxial layer 2
  • At least one second-type groove 16 and a plurality of first-type grooves 3 extending inside, the plurality of first-type grooves 3 are arranged parallel to each other and at intervals, and the second-type groove 16 surrounds the first-type groove Slot 3 is set.
  • first-type grooves 3 are arranged parallel to each other, and the second-type grooves 16 surround and surround a plurality of first-type grooves 3 , for example, the direction shown in FIG. 1
  • first type of grooves 3 are arranged in parallel along the horizontal direction
  • the second type of grooves 16 are arranged in a ring shape
  • all the first type of grooves 3 are located in the ring shape of the second type of grooves 13
  • Figure 29 the schematic diagram of the positional relationship between the first type of groove 3 and the second type of groove 16 is shown in Figure 29. Two or more grooves 16 of the second type, and the plurality of grooves 16 of the second type are all arranged around.
  • the interior of part of the groove segments of each first-type trench 3 is completely filled with the first-type conductive polysilicon 5 , and the first-type conductive polysilicon 5 is connected to the first-type conductive type epitaxial layer 2
  • a field oxygen layer 6 made of an insulating medium is disposed between them, a second type insulating dielectric layer 12 is disposed above the first type trench 3, and a source metal 13 is disposed above the second type insulating dielectric layer 12, The source metal 13 is in ohmic contact with the first-type conductive polysilicon 5 in the first-type trench 3 through the first-type through hole 15 in the second-type insulating dielectric layer 12 .
  • the structure can be understood with reference to those shown in Figures 3 and 5, since the position of BB' is the central position of the device, the first type of through hole 15 is provided at the central position, and along the dotted line BB' The second type of through-holes 14 are provided on both sides. In addition, it can be seen from FIG. 5 that the interior of the first-type trench 3 below the first-type through hole 15 is completely filled with the first-type conductive polysilicon 5 .
  • the interior of part of the groove segment of each first-type trench 3 is filled with the first-type conductive polysilicon 5
  • the second-type conductive polysilicon 8 is filled above the first-type conductive polysilicon 5
  • a first-type insulating dielectric layer 7 is filled
  • between the second-type conductive polysilicon 8 and the first-type conductive epitaxial layer 2 is arranged Gate oxide layer 9, a second conductivity type body region 10 is provided on the upper surface of the first conductivity type epitaxial layer 2 between every two adjacent first type trenches 3, part of the second conductivity type body region 10
  • a first-conductivity-type source region 11 is provided on the upper surface, and a second-type insulating dielectric layer 12 is arranged above the first-type trench 3 and the first-conductivity-type source region 11, and part of the second-type insulating dielectric layer 12, the source metal 13 is provided
  • a first conductivity type well region 4 is provided in the first conductivity type epitaxial layer 2 , and the distribution area of the first conductivity type well region 4 includes the underside of the second type through hole 14 and Covering the side region and bottom region of the first type trench 3, the concentration of the first conductivity type impurity in the first conductivity type well region 4 is higher than that of the first conductivity type impurity in the first conductivity type epitaxial layer 2 the concentration of a conductivity type impurity; or,
  • the first conductivity type well region 4 is set in the first conductivity type epitaxial layer 2, and the distribution area of the first conductivity type well region 4 includes, in the first type trench 3 In the parallel direction, the side area and the bottom area of the first type of groove 3 between the second type of through hole 14 and the second type of groove 16 are adjacent to the second type of through hole 14 Between the side region and the bottom region of the first type trench 3, and the side region and the bottom region of the second type trench 16, the concentration of the first conductivity type impurity in the first conductivity type well region 4 lower than the concentration of the first conductivity type impurity in the first conductivity type epitaxial layer 2 .
  • the PN junction formed by the body region 10 of the second conductivity type and the epitaxial layer 2 of the first conductivity type and the PN junction formed by the body region 10 of the second conductivity type and the well region 4 of the first conductivity type have different breakdown characteristics. , through the setting of the first conductivity type well region structure as shown in Fig.
  • FIG. 25 It is a schematic diagram of the cross-sectional structure of a cell without a well region of the first conductivity type. As shown in FIG. 27, the cell structures in FIG. 25 and FIG. 26 are cut along the dotted line FF' and the dotted line EE' respectively during breakdown. In FIG.
  • the electric field on the PN junction composed of the body region 10 of the second conductivity type and the well region 4 of the first conductivity type is much higher than that of the body region 10 of the second conductivity type and the epitaxial layer 2 of the first conductivity type.
  • the PN junction which makes the device in the case of avalanche breakdown of a large current, most of the current will flow through the PN junction formed by the second conductivity type body region 10 and the first conductivity type well region 4, thereby protecting the transition region and the terminal region.
  • the PN junction formed by the body region 10 of the second conductivity type and the epitaxial layer 2 of the first conductivity type and the PN junction formed by the body region 10 of the second conductivity type and the well region 4 of the first conductivity type have different breakdown characteristics, as shown in FIG. 21 to the configuration of the first conductivity type well region structure shown in FIG.
  • the concentration of the impurity of the first conductivity type inside, when the avalanche breakdown occurs, the peak electric field intensity on the PN junction formed by the body region 10 of the second conductivity type and the epitaxial layer 2 of the first conductivity type will be obviously higher than that of the body region of the second conductivity type 10 and the peak electric field intensity on the PN junction composed of the well region 4 of the first conductivity type, which makes most of the current flow through the body region 10 of the second conductivity type and the epitaxial layer of the first conductivity type when the device undergoes avalanche breakdown of a large current.
  • the PN junction composed of layer 2 protects the transition region and the terminal region.
  • the power semiconductor device provided by the embodiment of the present invention, by setting the first conductivity type well region, avoids the accumulation of large current in the terminal and the transition region of the device, so that the terminal and the transition region are not damaged, thus improving the performance of the device.
  • the reliability in the short-circuit working mode improves the short-circuit capability of the device at the same time.
  • the first conductivity type well region 4 is provided in the first conductivity type epitaxial layer 2, and the distribution area of the first conductivity type well region 4 includes the The bottom area and the side area below the second type of through hole 14 and covering the first type of trench 3;
  • the boundary of the first conductivity type well region 4 along the direction parallel to the first type trench 3 is located below the second type through hole 14, and the first conductivity type epitaxial layer 2 is close to the The first conductivity type well region 4 is not distributed in the side region and bottom region of at least one of the first type trenches 3 parallel to the second type trench segment;
  • the concentration of the impurity of the first conductivity type in the well region 4 of the first conductivity type is 1.01 to 5 times the concentration of the impurity of the first conductivity type in the epitaxial layer of the first conductivity type.
  • the distribution of the well regions 4 of the first conductivity type can be understood as, along the direction parallel to the trenches 3 of the first type, they are mainly distributed under the via holes 14 of the second type, and include It can be seen from Fig. 2 and Fig. 4 that it covers the sides and bottom of the first type of groove 3.
  • the boundary of the well region 4 of the first conductivity type in this direction does not exceed both ends of the second-type through hole 14 , that is, the boundaries are all below the second-type through-hole 14 .
  • the distribution of the first conductivity type well region 4 is mainly at the bottom and side of the first type of trench 3, and close to the second type of trench 16 groove segment (The groove segment should be parallel to the first type of groove 3 , that is, the transverse groove segment portion shown in FIG. 29 ). At least one first type of groove 3 has no well region of the first conductivity type on the side and bottom.
  • the distribution area of the first conductivity type well region 4 includes, in the direction parallel to the first type trench 3, the The side area and bottom area of the first type of groove 3 between the second type of through hole 14 and the second type of groove 16, the first type of groove between adjacent second type of through holes 14 the side area and the bottom area of the groove 3, and the side area and the bottom area of the second type of groove 16;
  • the region of the well 4 of the first conductivity type extends along the boundary in a direction parallel to the trench 3 of the first type to a part of the region below the through hole 14 of the second type, and the epitaxial layer 2 of the first conductivity type
  • the side region and the bottom region of at least one of the first-type trenches 3 close to the second-type trench segment parallel to the first-type trench 3 are covered by the first-conductivity-type well region 4 ;
  • the concentration of the impurity of the first conductivity type in the epitaxial layer 2 of the first conductivity type is 1.01 to 5 times the concentration of the impurity of the first conductivity type in the well region 4 of the first conductivity type.
  • the distribution of the well regions 4 of the first conductivity type can be understood as, in the direction parallel to the first type trenches 3 , except for the first type trenches below the second type through holes 14
  • the bottom and sides of the first-type trenches 3 under other regions are provided with first-conductivity-type well regions 4, and in this direction, the boundary position of the first-conductivity-type well regions 4 can extend to the second-type trenches.
  • the bottom and side of the second type of groove 16 and the side and bottom of at least one first type of groove 3 close to the second type of groove 16 are all A first conductivity type well region 4 is provided.
  • a field oxygen layer 6 is arranged between the first conductive epitaxial layer 2, the second type insulating dielectric layer 12 is arranged above the second type trench 16, and a source is arranged above the second type insulating dielectric layer 12.
  • the first-type conductive polysilicon 5 in the second-type trench 16 is in ohmic contact with the source metal 13 through the first-type through hole 15 located in the second-type insulating dielectric layer 12 .
  • the surface of the epitaxial layer 2 of the first conductivity type between the groove segment of the second type of trench 16 parallel to the first type of trench 3 and the adjacent first type of trench 3 A second conductivity type body region 10 is provided, a second type insulating dielectric layer 12 is disposed above the second conductivity type body region 10, a source metal 13 is disposed above the second type insulation dielectric layer 12, and the source The metal 13 is in ohmic contact with the second conductivity type body region 10 through the second type through hole 14 located in the second type insulating dielectric layer 12 .
  • a second-type insulating dielectric layer 12 is arranged above each of the first-type trenches 3, and a gate is arranged above the second-type insulating dielectric layer 12.
  • the gate metal 17 is in ohmic contact with the second-type conductive polysilicon 8 through the third-type via hole 18 located in the second-type insulating dielectric layer 12 .
  • the power semiconductor device includes an N-type power semiconductor device and a P-type power semiconductor device.
  • the first conductivity type is N-type
  • the second conductivity type is N-type.
  • the type is P-type
  • the power semiconductor device is the P-type semiconductor device
  • the first conductivity type is P-type
  • the second conductivity type is N-type.
  • the power semiconductor device is the N-type power semiconductor device as an example for description.
  • the first conductivity type is N-type
  • the second conductivity type is P-type.
  • an N-type substrate 1 is included, and an N-type epitaxial layer 2 is arranged above the N-type substrate 1, as shown in Figure 1
  • a schematic top view of the device strip-shaped first-type trenches 3 parallel to each other and uniformly distributed are arranged on the surface of the N-type epitaxial layer 2, and the periphery of the first-type trenches 3 is surrounded by second-type trenches 16 surround.
  • FIG. 3 it is a schematic cross-sectional structure cut along the dotted line BB' in FIG.
  • the first-type conductive polysilicon 5 in the first-type trenches 3 is insulated from the N-type epitaxial layer 2 by the field oxygen layer 6, and the N-type epitaxial layer 2 between adjacent first-type trenches 3 is insulated from the first-type trenches.
  • the through hole 15 is in ohmic contact with the first type conductive polysilicon 5 in the first type trench 3; the second type trench 16 is filled with the first type conductive polysilicon 5, and the first type conductive polysilicon 5 in the second type trench 16 Conductive polysilicon 5 is insulated from N-type epitaxial layer 2 by field oxygen layer 6 .
  • a second type of insulating dielectric layer 12 is arranged above the second type of trench 16 parallel to the first type of trench 3, and a source is arranged above the second type of insulating dielectric layer 12.
  • An electrode metal 13 , the source metal 13 is in ohmic contact with the first type conductive polysilicon 5 in the second type trench 16 through the first type through hole 15 .
  • FIG 2 it is a schematic cross-sectional structure cut along the dotted line AA' in Figure 1.
  • the lower half of the first type of trench 3 is provided with the first type of conductive polysilicon 5, and the upper half is provided with the second type of conductive polysilicon.
  • first-type conductive polysilicon 5 and second-type conductive polysilicon 8 are insulated by first-type insulating dielectric layer 7
  • first-type conductive polysilicon 5 is insulated from N-type epitaxial layer 2 by field oxygen layer 6
  • second-type conductive polysilicon 8 is insulated from the N-type epitaxial layer 2 by the gate oxide layer 9
  • the surface of the N-type epitaxial layer 2 between adjacent first-type trenches 3 is provided with a P-type body region 10
  • An N-type source region 11 is provided
  • a second-type insulating dielectric layer 12 is arranged above the first-type trench 3 and the N-type source region 11, and a source metal layer is arranged above the second-type insulating dielectric layer 12.
  • the source metal 13 is in ohmic contact with the N-type source region 11 and the P-type body region 10 through the second-type through hole 14 in the second-type insulating dielectric layer 12;
  • a P-type body region 10 is provided on the surface of the N-type epitaxial layer 2 between the groove segment of the second-type trench 16 and the adjacent first-type trench 3, and a second-type insulating layer is arranged above the P-type body region 10.
  • the dielectric layer 12 is provided with a source metal 13 above the second-type insulating dielectric layer 12 , and the source metal 13 is in ohmic contact with the P-type body region 10 through the second-type through hole 14 .
  • FIG. 5 it is a schematic cross-sectional structure cut along the dotted line DD' in FIG. layer 12, a gate metal 17 is arranged above the second type insulating dielectric layer 12, and the gate metal 17 passes through the third type through hole 18 in the second type insulating dielectric layer 12 and the second type conductive polysilicon 8 ohm contacts.
  • FIG 4 it is a schematic cross-sectional structure cut along the dotted line CC' in Figure 1.
  • the side walls of the first type of trench 3 and the N-type near the bottom An N-type well region 4 is provided in the epitaxial layer 2, and the N-type well region 4 is provided only under the second type of through hole 14, and the edge of the N-type well region 4 does not cross the second type of through hole.
  • the end of the hole 14, and the edge of the N-type well region 4 is about 5 ⁇ m away from the end of the second type of through hole 14; the concentration of the N-type impurity in the N-type well region 4 is higher than that of the N-type impurities in the N-type epitaxial layer 2 concentration of impurities.
  • the N-type well region 4 is arranged like this because the PN junction formed by the P-type body region 10 and the N-type epitaxial layer 2, and the PN junction formed by the P-type body region 10 and the N-type well region 4 have different breakdown characteristics.
  • the doping concentration of the N-type well region 4 is greater than that of the epitaxial layer 2.
  • the peak electric field intensity on the PN junction composed of the P-type body region 10 and the epitaxial layer 2 will be significantly lower than that of the P-type body region 10 and the epitaxial layer 2.
  • FIG. 25 is a schematic cross-sectional structure diagram of a cell provided with a first conductivity type well region in this embodiment, and as shown in FIG. 26 is not shown in this embodiment.
  • Schematic diagram of the cross-sectional structure of a cell with a well region of the first conductivity type as shown in Figure 27, the electric field cut along the dotted line FF' and the dotted line EE' when the cell structure in Figure 25 and Figure 26 respectively breaks down
  • Distribution diagram, in Figure 25, the electric field on the PN junction composed of P-type body region 10 and N-type well region 4 is much higher than that of the PN junction composed of P-type body region 10 and epitaxial layer 2, which makes the device break down under high current avalanche At this time, most of the current will flow through the PN junction formed by the P-type body region 10 and the N-type well region 4, thereby protecting the transition region and the terminal region.
  • FIG. 21 to FIG. 24 it includes an N-type substrate 1, and an N-type epitaxial layer 2 is arranged on the N-type substrate 1, as shown in FIG. 1 is a schematic top view of the device provided by the present invention.
  • N-type epitaxial layer 2 On the surface of the N-type epitaxial layer 2, strip-shaped first-type trenches 3 parallel to each other and uniformly distributed are arranged. The periphery is surrounded by second-type grooves 16;
  • FIG. 22 it is a schematic cross-sectional structure cut along the dotted line BB' in FIG. 1.
  • the first-type trench 3 is filled with the first-type conductive polysilicon 5.
  • the first-type conductive polysilicon 5 in the first-type trenches 3 is insulated from the N-type epitaxial layer 2 by the field oxygen layer 6, and the N-type epitaxial layer 2 between adjacent first-type trenches 3 is insulated from the first-type trenches.
  • the conductive polysilicon 5 is insulated from the N-type epitaxial layer 2 by the field oxygen layer 6.
  • a second-type insulating dielectric layer is arranged above the second-type trench 16 parallel to the first-type trench 3 12.
  • a source metal 13 is provided above the second-type insulating dielectric layer 12, and the source metal 13 passes through the first-type through hole 15 and the first-type conductive polysilicon 5 ohm in the second-type trench 16 touch.
  • FIG 21 it is a schematic cross-sectional structure cut along the dotted line AA' in Figure 1.
  • the lower half of the first type of trench 3 is provided with the first type of conductive polysilicon 5, and the upper half is provided with the second type of conductive polysilicon 5.
  • first-type conductive polysilicon 5 and second-type conductive polysilicon 8 are insulated by first-type insulating dielectric layer 7
  • first-type conductive polysilicon 5 is insulated from N-type epitaxial layer 2 by field oxygen layer 6
  • second-type conductive polysilicon 8 is insulated from the N-type epitaxial layer 2 by the gate oxide layer 9
  • the surface of the N-type epitaxial layer 2 between adjacent first-type trenches 3 is provided with a P-type body region 10
  • An N-type source region 11 is provided
  • a second-type insulating dielectric layer 12 is arranged above the first-type trench 3 and the N-type source region 11, and a source metal layer is arranged above the second-type insulating dielectric layer 12.
  • the source metal 13 is in ohmic contact with the N-type source region 11 and the P-type body region 10 through the second-type through hole 14 in the second-type insulating dielectric layer 12;
  • a P-type body region 10 is provided on the surface of the N-type epitaxial layer 2 between the groove segment of the second-type trench 16 and the adjacent first-type trench 3, and a second-type insulating layer is arranged above the P-type body region 10.
  • the dielectric layer 12 is provided with a source metal 13 above the second-type insulating dielectric layer 12 , and the source metal 13 is in ohmic contact with the P-type body region 10 through the second-type through hole 14 .
  • FIG. 24 it is a schematic cross-sectional structure cut along the dotted line DD' in FIG. layer 12, a gate metal 17 is arranged above the second type insulating dielectric layer 12, and the gate metal 17 passes through the third type through hole 18 in the second type insulating dielectric layer 12 and the second type conductive polysilicon 8 ohm contacts.
  • N-type well region 4 is provided in the N-type epitaxial layer 2 near the sidewall and bottom of 3, and the edge of the N-type well region 4 crosses the end of the second type through hole 14, and partly enters the second type through hole 14.
  • an N-type well region 4 is arranged in the N-type epitaxial layer 2 near the sidewall and bottom of the second type trench 16; the concentration of N-type impurities in the N-type well region 4 is low The concentration of N-type impurities in the N-type epitaxial layer 2 .
  • the top view angle of the device, the N-type epitaxy near the sidewall and the bottom of the first first-type trench 3 near the second-type trench 16 N-type well region 4 is arranged in layer 2 .
  • the N-type well region 4 is arranged like this because the PN junction formed by the P-type body region 10 and the N-type epitaxial layer 2, and the PN junction formed by the P-type body region 10 and the N-type well region 4 have different breakdown characteristics.
  • the doping concentration of the N-type well region 4 is lower than that of the N-type epitaxial layer 2.
  • the peak electric field intensity on the PN junction composed of the P-type body region 10 and the N-type epitaxial layer 2 will be significantly higher than that of the P-type well region 10.
  • the peak electric field intensity on the PN junction formed by the body region 10 and the N-type well region 4 makes most of the current flow through the P-type body region 10 and the N-type epitaxial layer 2 when the device undergoes avalanche breakdown at a high current. PN junction, thus protecting the transition region and the terminal region.
  • a method for manufacturing a power semiconductor device as described above is provided, wherein, as shown in FIG. 28 , it includes:
  • the power semiconductor device includes an N-type power semiconductor device and a P-type power semiconductor device.
  • the first conductivity type is N-type
  • the second conductivity type is N-type.
  • the type is P-type
  • the power semiconductor device is the P-type semiconductor device
  • the first conductivity type is P-type
  • the second conductivity type is N-type.
  • the power semiconductor device is the N-type power semiconductor device as an example for description.
  • the first conductivity type is N-type
  • the second conductivity type is P-type.
  • an N-type substrate 1 is provided, and an N-type epitaxial layer 2 is grown on the N-type substrate 1 .
  • a thick oxide layer 19 is formed on the surface of the N-type epitaxial layer 2, and the thick oxide layer 19 and the N-type epitaxial layer 2 are selectively etched to form the first-type trench 3 and the second-type groove. Groove-like 16.
  • a part of the photoresist 20 is selectively retained, and then at a first angle a (in this embodiment, the first angle a shown in FIG. 8 can specifically be 17°) to implant N-type impurities into the sidewall and bottom of the first-type trench 3 to form an N-type well region 4 .
  • Impurities to form a well region of the first conductivity type including:
  • the photoresist After coating the photoresist, selectively retaining part of the photoresist, injecting impurities of the first conductivity type into the side region and the bottom region of the first type trench at a first angle to form a well region of the first conductivity type, the The distribution area of the well region of the first conductivity type includes the side region and the bottom region under the second type through hole and covering the trench of the first type, and the first conductivity type impurity in the well region of the first conductivity type The concentration is higher than the concentration of the first conductivity type impurity in the first conductivity type epitaxial layer; or,
  • the distribution region of the well region of the first conductivity type includes, in a direction parallel to the first type of trench, the first type of trench between the second type of through hole and the second type of trench.
  • the concentration of the impurity of the first conductivity type in the type well region is lower than the concentration of the impurity of the first conductivity type in the epitaxial layer of the first conductivity type.
  • N-type impurities are implanted into both the side region and the bottom region of the first-type trench 3 at a first angle a to form an N-type well region 4 .
  • the N-type well region 4 is distributed under the second-type through hole 14 and covers the side region and the bottom region of the first-type trench 3, and the N-type impurity in the N-type well region 4
  • the concentration is higher than the concentration of N-type impurities in the N-type epitaxial layer 2 .
  • the concentration of N-type impurities in the N-type well region 4 is 1.01 to 5 times the concentration of N-type impurities in the N-type epitaxial layer 2 .
  • P-type impurities are implanted in the side region and the bottom region of the first type trench 3 at a first angle a (it should be understood here that this method is achieved by implanting
  • the P-type impurity reduces the concentration of the N-type impurity by neutralizing the N-type impurity), forming an N-type well region 4, and the N-type well region 4 is distributed under the first type of through hole 15 and covers the The side area and the bottom area of the first type trench 3, and the side area and the bottom area distributed around the second type trench 16 and covering the second type trench 16, the N type
  • the concentration of the N-type impurity in the well region 4 is lower than the concentration of the first conductivity type impurity in the N-type epitaxial layer 2 .
  • the concentration of the impurity of the first conductivity type in the N-type epitaxial layer 2 is 1.01 to 5 times the concentration of the impurity of the first conductivity type in the well region 4 of the first conductivity type.
  • the value range of the first angle a is between 0° and 60°.
  • conductive polysilicon is deposited to fill up the first-type trench 3 and the second-type trench 16, and then the conductive polysilicon is etched, and the first-type trench 3 and the second-type trench 16 are etched.
  • the first type of conductive polysilicon 5 is formed in 16 .
  • the upper half of the conductive polysilicon in the first type trench 3 is selectively etched; as shown in FIG. 13, an insulating dielectric layer is deposited to fill the top half of the first type trench 3. half; as shown in Figure 14, remove the insulating dielectric layer above the N-type epitaxial layer 2; as shown in Figure 15, selectively etch part of the insulating dielectric layer in the first type of trench 3 to form the first type of insulating dielectric 7.
  • a gate oxide layer 9 is formed in the first type trench 3; as shown in FIG. 17, conductive polysilicon is deposited to fill the upper half of the first type trench 3, and then the The conductive polysilicon is etched to form the second type conductive polysilicon 8 in the upper half of the first type trench 3 .
  • P-type impurities are implanted on the surface of the device and annealed to form a P-type body region 10 , and then N-type impurities are selectively implanted to form an N-type source region 11 after activation.
  • an insulating medium is deposited to form a second type of insulating medium 12 on the surface of the device.
  • the second type of insulating dielectric 12, the N-type epitaxial layer 2, the first type of conductive polysilicon 5 and the second type of conductive polysilicon 8 are selectively etched to form the first type of through holes 15, The second type of through hole 14 and the third type of through hole 18 .
  • the metal is selectively etched to form source metal 13 and gate metal 17 .
  • the manufacturing method of the power semiconductor device provided by the embodiment of the present invention avoids the accumulation of large current in the position of the terminal and the transition region of the device by forming the well region of the first conductivity type, so that the terminal and the transition region are not damaged.
  • the reliability in the short-circuit working mode of the device is improved, and the short-circuit capability of the device is improved at the same time.
  • the manufacturing method provided by the embodiment of the present invention has the advantages of simple process, low cost, and compatibility with existing processes.

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Abstract

The present invention relates to the technical field of semiconductors. Specifically disclosed is a power semiconductor device. The power semiconductor device comprises: a first conductivity-type substrate, on which a first conductivity-type epitaxial layer is arranged, wherein first conductivity-type well regions are arranged in the first conductivity-type epitaxial layer, and are distributed below second-type through holes and cover side portions and bottom portions of first-type trenches, and the concentration of impurities in the first conductivity-type well regions is higher than the concentration of impurities in the first conductivity-type epitaxial layer; or, the first conductivity-type well regions are distributed at side portions and bottom portions of first-type trenches between the second-type through holes and second-type trenches, at side portions and bottom portions of first-type trenches between adjacent second-type through holes, and at side portions and bottom portions of the second-type trenches, and the concentration of impurities in the first conductivity-type well regions is lower than the concentration of impurities in the first conductivity-type epitaxial layer. Further disclosed in the present invention is a manufacturing method for a power semiconductor device. By means of the power semiconductor device provided in the present invention, the reliability of short-circuit operation of the device can be improved.

Description

一种功率半导体器件及其制作方法A kind of power semiconductor device and its manufacturing method 技术领域technical field
本发明涉及半导体技术领域，尤其涉及一种功率半导体器件及功率半导体器件的制作方法。The invention relates to the technical field of semiconductors, in particular to a power semiconductor device and a method for manufacturing the power semiconductor device.
背景技术Background technique
在短路工作模式下，有大量电流流过屏蔽栅沟槽功率器件，当短路工作模式结束的瞬间器件关断，电路中存在的寄生电感使得电流强行雪崩击穿器件，器件会经历一个极短时间的高压超大电流状态。由于器件在终端与过渡区存在击穿薄弱点，会导致电流的集中并发热，又由于时间极短使得热量无法顺利转移到有源区，进而导致器件在终端或过渡区出现烧毁点。In the short-circuit mode, a large amount of current flows through the shielded trench power device. When the short-circuit mode ends, the device is turned off. The parasitic inductance in the circuit causes the current to forcibly avalanche and break down the device, and the device will experience a very short period of time. High voltage and super high current state. Because the device has a breakdown weak point in the terminal and transition area, it will cause the current to concentrate and generate heat, and because the heat cannot be smoothly transferred to the active area due to the extremely short time, it will cause the device to have a burn point in the terminal or transition area.
因此，如何能够消除终端与过渡区的击穿薄弱点以提升功率半导体器件在短路工作模式下的可靠性成为本领域技术人员亟待解决的技术问题。Therefore, how to eliminate the breakdown weak point of the terminal and the transition region to improve the reliability of the power semiconductor device in the short-circuit mode has become a technical problem to be solved urgently by those skilled in the art.
发明内容Contents of the invention
本发明提供了一种功率半导体器件及功率半导体器件的制作方法，解决相关技术中存在的短路工作模式下可靠性低的问题。The invention provides a power semiconductor device and a manufacturing method of the power semiconductor device, which solve the problem of low reliability in the short-circuit working mode existing in the related art.
作为本发明的第一个方面，提供一种功率半导体器件，其中，包括：As a first aspect of the present invention, a power semiconductor device is provided, including:
第一导电类型衬底，所述第一导电类型衬底上设置第一导电类型外延层，所述第一导电类型外延层的上表面设置朝向所述第一导电类型外延层内部延伸的至少一条第二类沟槽和多条第一类沟槽，多条第一类沟槽之间相互平行且间隔设置，所述第二类沟槽环绕第一类沟槽的***设置；A first conductivity type substrate, a first conductivity type epitaxial layer is disposed on the first conductivity type substrate, and at least one strip extending toward the inside of the first conductivity type epitaxial layer is disposed on the upper surface of the first conductivity type epitaxial layer A second type of groove and a plurality of first type grooves, the plurality of first type grooves are arranged parallel to each other and spaced apart, and the second type of groove is arranged around the periphery of the first type of groove;
每条第一类沟槽的部分槽段的内部全部填充第一类导电多晶硅，所述第一类导电多晶硅与所述第一导电类型外延层之间设置由绝缘介质构成的场氧层，在所述第一类沟槽的上方均设置第二类绝缘介质层，所述第二类绝缘介质层的上方设置源极金属，所述源极金属通过位于所述第二类绝缘介质层内的第一类通孔与位于所述第一类沟槽内的所述第一类导电多晶硅欧姆接触；The interior of some groove segments of each first-type trench is completely filled with first-type conductive polysilicon, and a field oxygen layer composed of an insulating medium is arranged between the first-type conductive polysilicon and the first-conductivity-type epitaxial layer. A second-type insulating dielectric layer is arranged above the first-type trenches, a source metal is arranged above the second-type insulating dielectric layer, and the source metal passes through the A first type of via hole is in ohmic contact with the first type of conductive polysilicon located in the first type of trench;
每条第一类沟槽的部分槽段的内部部分填充第一类导电多晶硅，在所述第一类导电多晶硅的上方填充第二类导电多晶硅，所述第二类导电多晶硅与所述第一类导电多晶硅之间填充第一类绝缘介质层，所述第二类导电多晶硅与所述第一导电类型外延层之间设置栅氧层，每相邻两条第一类沟槽之间的第一类导电类型外延层的上表面设置第二导电类型体区，部分所述第二导电类型体区的上表面设置第一导电类型源区，所述第一类沟槽与所述第一导电类型源区的上方均设置第二类绝缘介质层，部分所述第二类绝缘介质层的上方设置源极金属，所述源极金属通过位于所述第二类绝缘介质层内的第二类通孔分别与所述第一导电类型源区和第二导电类型体区欧姆接触；The inner part of part of the groove segment of each first-type trench is filled with the first-type conductive polysilicon, and the second-type conductive polysilicon is filled above the first-type conductive polysilicon, and the second-type conductive polysilicon and the first-type conductive polysilicon are filled. A first-type insulating dielectric layer is filled between the conductive polysilicon, a gate oxide layer is provided between the second-type conductive polysilicon and the first-conductive-type epitaxial layer, and the first-type trench between every two adjacent first-type trenches A second conductivity type body region is provided on the upper surface of one type of conductivity type epitaxial layer, and a first conductivity type source region is arranged on the upper surface of part of the second conductivity type body region, and the first type of trench and the first conductivity type A second-type insulating dielectric layer is arranged above the source regions of the second type, and a source metal is arranged above part of the second-type insulating dielectric layer, and the source metal passes through the second-type insulating dielectric layer located in the second-type insulating dielectric layer. The through holes are respectively in ohmic contact with the source region of the first conductivity type and the body region of the second conductivity type;
所述第一导电类型外延层内设置第一导电类型阱区，所述第一导电类型阱区分布区域包括所述第二类通孔下方且包覆所述第一类沟槽的侧部区域和底部区域，所述第一导电类型阱区内的第一导电类型杂质的浓度高于所述第一导电 类型外延层内的第一导电类型杂质的浓度；或者，A first conductivity type well region is provided in the first conductivity type epitaxial layer, and the distribution area of the first conductivity type well region includes a side region below the second type through hole and covering the first type trench and the bottom region, the concentration of the first conductivity type impurity in the first conductivity type well region is higher than the concentration of the first conductivity type impurity in the first conductivity type epitaxial layer; or,
所述第一导电类型外延层内设置第一导电类型阱区，所述第一导电类型阱区分布区域包括，在与所述第一类沟槽平行的方向上，所述第二类通孔与所述第二类沟槽之间的所述第一类沟槽的侧部区域与底部区域，相邻第二类通孔之间的第一类沟槽的侧部区域与底部区域，以及第二类沟槽的侧部区域与底部区域，所述第一导电类型阱区内的第一导电类型杂质的浓度低于所述第一导电类型外延层内的第一导电类型杂质的浓度。A first conductivity type well region is provided in the first conductivity type epitaxial layer, and the distribution area of the first conductivity type well region includes, in a direction parallel to the first type trench, the second type through hole the side region and the bottom region of the first-type trench between the second-type trench, the side region and the bottom region of the first-type trench between adjacent second-type through holes, and In the side region and the bottom region of the second type trench, the concentration of the first conductivity type impurity in the first conductivity type well region is lower than the concentration of the first conductivity type impurity in the first conductivity type epitaxial layer.
进一步地，所述第一导电类型外延层内设置第一导电类型阱区，所述第一导电类型阱区分布区域包括所述第二类通孔下方且包覆所述第一类沟槽的底部区域以及侧部区域；Further, a first conductivity type well region is provided in the first conductivity type epitaxial layer, and the distribution area of the first conductivity type well region includes an area under the second type through hole and covering the first type trench bottom area as well as side area;
所述第一导电类型阱区沿与所述第一类沟槽平行的方向上的边界均位于所述第二类通孔的下方，所述第一导电类外延层中靠近与所述第一类沟槽平行的第二类沟槽槽段的至少一条所述第一类沟槽的侧部区域和底部区域未分布所述第一导电类型阱区；The boundaries of the first conductivity type well region along the direction parallel to the first type trenches are all located below the second type of through holes, and the first conductivity type epitaxial layer is close to the first type of trench. The side region and the bottom region of at least one of the first-type trench segments of the second-type trench parallel to the similar-type trenches are not distributed with the first conductivity type well region;
所述第一导电类型阱区内的第一导电类型杂质的浓度为所述第一导电类型外延层内的第一导电类型杂质的浓度的1.01倍至5倍。The concentration of the impurity of the first conductivity type in the well region of the first conductivity type is 1.01 to 5 times the concentration of the impurity of the first conductivity type in the epitaxial layer of the first conductivity type.
进一步地，所述第一导电类型阱区分布区域包括，在与所述第一类沟槽平行的方向上，所述第二类通孔与所述第二类沟槽之间的所述第一类沟槽的侧部区域与底部区域，相邻第二类通孔之间的第一类沟槽的侧部区域与底部区域，以及第二类沟槽的侧部区域与底部区域；Further, the distribution region of the well region of the first conductivity type includes, in a direction parallel to the trench of the first type, the second hole between the through hole of the second type and the trench of the second type. the side area and the bottom area of the first type of trench, the side area and the bottom area of the first type of trench between the adjacent second type of through holes, and the side area and the bottom area of the second type of trench;
所述第一导电类型阱区沿与所述第一类沟槽平行的方向上的边界延伸至所述第二类通孔的下方的部分区域，所述第一导电类型外延层中靠近与所述第一类沟槽平行的第二类沟槽槽段的至少一条所述第一类沟槽的侧部区域和底部区域被所述第一导电类型阱区包覆；The well region of the first conductivity type extends along a boundary in a direction parallel to the trench of the first type to a partial region below the via hole of the second type, and the epitaxial layer of the first conductivity type is close to the The side region and the bottom region of at least one of the first-type trenches of the second-type trench segment parallel to the first-type trench are covered by the first-conductivity-type well region;
所述第一导电类型外延层内的第一导电类型杂质的浓度为所述第一导电类型阱区内的第一导电类型杂质的浓度的1.01倍至5倍。The concentration of the first conductivity type impurity in the first conductivity type epitaxial layer is 1.01 to 5 times the concentration of the first conductivity type impurity in the first conductivity type well region.
进一步地，所述第二类沟槽的内部填充第一类导电多晶硅，所述第一类导电多晶硅与所述第一导电外延层之间设置场氧层，所述第二类沟槽上方设置所述第二类绝缘介质层，所述第二类绝缘介质层的上方设置源极金属，所述第二类沟槽内的第一类导电多晶硅通过位于所述第二类绝缘介质层内的第一类通孔与所述源极金属欧姆接触。Further, the inside of the second-type trench is filled with first-type conductive polysilicon, a field oxygen layer is set between the first-type conductive polysilicon and the first conductive epitaxial layer, and a field oxide layer is set above the second-type trench. The second type of insulating dielectric layer, the source metal is arranged above the second type of insulating dielectric layer, the first type of conductive polysilicon in the second type of trench passes through the A first type of via is in ohmic contact with the source metal.
进一步地，与所述第一类沟槽平行的第二类沟槽槽段与相邻的第一类沟槽之间的第一导电类型外延层的表面设置第二导电类型体区，所述第二导电类型体区的上方设置第二类绝缘介质层，所述第二类绝缘介质层的上方设置源极金属，所述源极金属通过位于所述第二类绝缘介质层内的第二类通孔与所述第二导电类型体区欧姆接触。Further, a body region of the second conductivity type is provided on the surface of the epitaxial layer of the first conductivity type between the segment of the trench of the second type parallel to the trench of the first type and the adjacent trench of the first type, and the A second-type insulating dielectric layer is disposed above the body region of the second conductivity type, and a source metal is disposed above the second-type insulating dielectric layer, and the source metal passes through the second insulating dielectric layer located in the second-type insulating dielectric layer. The via-like hole is in ohmic contact with the second conductivity type body region.
进一步地，每条所述第一类沟槽的上方设置第二类绝缘介质层，部分所述第二类绝缘介质层的上方设置栅极金属，所述栅极金属通过位于所述第二类绝缘介质层内的第三类通孔与所述第二类导电多晶硅欧姆接触。Further, a second type of insulating dielectric layer is disposed above each of the first type of trenches, and a gate metal is disposed above part of the second type of insulating dielectric layer, and the gate metal is positioned on the second type of trench The third type of through hole in the insulating dielectric layer is in ohmic contact with the second type of conductive polysilicon.
进一步地，所述功率半导体器件包括N型功率半导体器件和P型功率半导体器件，当所述功率半导体器件为所述N型功率半导体器件时，第一导电类型为N型，第二导电类型为P型，当所述功率半导体器件为所述P型半导体器件时，第一导电类型为P型，第二导电类型为N型。Further, the power semiconductor device includes an N-type power semiconductor device and a P-type power semiconductor device. When the power semiconductor device is the N-type power semiconductor device, the first conductivity type is N-type, and the second conductivity type is P-type, when the power semiconductor device is the P-type semiconductor device, the first conductivity type is P-type, and the second conductivity type is N-type.
作为本发明的另一个方面，提供一种如前文所述的功率半导体器件的制作方法，其中，包括：As another aspect of the present invention, a method for manufacturing a power semiconductor device as described above is provided, including:
提供第一导电类型衬底，在所述第一导电类型衬底上生长第一导电类型外延层；providing a first conductivity type substrate on which a first conductivity type epitaxial layer is grown;
在所述第一导电类型外延层的表面形成厚氧化层，选择性刻蚀厚氧化层与所述第一导电类型外延层后，形成第一类沟槽与第二类沟槽；forming a thick oxide layer on the surface of the first conductivity type epitaxial layer, and after selectively etching the thick oxide layer and the first conductivity type epitaxial layer, forming a first type trench and a second type trench;
涂覆光刻胶后选择性保留部分光刻胶，以第一角度在所述第一类沟槽的侧部区域与底部区域注入第一导电类型杂质或第二导电类型杂质，形成第一导电类型阱区；Selectively retain part of the photoresist after coating the photoresist, and inject first conductivity type impurities or second conductivity type impurities into the side region and bottom region of the first type of trench at a first angle to form a first conductivity type trench. type well area;
去除光刻胶与厚氧化层后，在第一导电类型外延层的表面、第一类沟槽的底部区域及侧部区域以及第二类沟槽的底部区域及侧部区域均形成场氧层；After removing the photoresist and the thick oxide layer, a field oxide layer is formed on the surface of the epitaxial layer of the first conductivity type, the bottom region and side regions of the first type of trenches, and the bottom region and side regions of the second type of trenches ;
分别在所述第一类沟槽与第二类沟槽内形成第一类导电多晶硅；forming first-type conductive polysilicon in the first-type trench and the second-type trench respectively;
选择性刻蚀第一类沟槽内的部分导电多晶硅后，在刻蚀后的区域内形成第一类绝缘介质层；After selectively etching part of the conductive polysilicon in the first-type trench, a first-type insulating dielectric layer is formed in the etched area;
在第一类沟槽内形成栅氧层，以及在第一类沟槽内的第一类绝缘介质层上形成第二类导电多晶硅；forming a gate oxide layer in the first type of trench, and forming a second type of conductive polysilicon on the first type of insulating dielectric layer in the first type of trench;
依次形成第二导电类型体区和第一导电类型源区；sequentially forming a body region of the second conductivity type and a source region of the first conductivity type;
淀积绝缘介质，形成第二类绝缘介质层；Depositing an insulating medium to form a second type insulating medium layer;
选择性刻蚀第二类绝缘介质层、第一导电类型源区、第二导电类型体区、第一类导电多晶硅与第二类导电多晶硅后，形成第一类通孔、第二类通孔和第三类通孔；After selectively etching the second-type insulating dielectric layer, the first-conductivity-type source region, the second-conductivity-type body region, the first-type conductive polysilicon and the second-type conductive polysilicon, the first-type via hole and the second-type through-hole are formed and the third type of through hole;
形成源极金属与栅极金属。Form source metal and gate metal.
进一步地，所述涂覆光刻胶后选择性保留部分光刻胶，以第一角度在所述第一类沟槽的侧部区域与底部区域均注入第一导电类型杂质或第二导电类型杂质，形成第一导电类型阱区，包括：Further, after the photoresist is coated, a part of the photoresist is selectively retained, and impurities of the first conductivity type or the second conductivity type are injected into the side region and the bottom region of the first type trench at a first angle. Impurities to form a well region of the first conductivity type, including:
涂覆光刻胶后选择性保留部分光刻胶，以第一角度在所述第一类沟槽的侧部区域与底部区域注入第一导电类型杂质，形成第一导电类型阱区，所述第一导电类型阱区分布区域包括所述第二类通孔下方且包覆所述第一类沟槽的侧部区域和底部区域，所述第一导电类型阱区内的第一导电类型杂质的浓度高于所述第一导电类型外延层内的第一导电类型杂质的浓度；或者，After coating the photoresist, selectively retaining part of the photoresist, injecting impurities of the first conductivity type into the side region and the bottom region of the first type trench at a first angle to form a well region of the first conductivity type, the The distribution area of the well region of the first conductivity type includes the side region and the bottom region under the second type through hole and covering the trench of the first type, and the first conductivity type impurity in the well region of the first conductivity type The concentration is higher than the concentration of the first conductivity type impurity in the first conductivity type epitaxial layer; or,
涂覆光刻胶后选择性保留部分光刻胶，以第一角度在所述第一类沟槽的侧部区域与底部区域均注入第二导电类型杂质，形成第一导电类型阱区，所述第一导电类型阱区分布区域包括，在与所述第一类沟槽平行的方向上，所述第二类通孔与所述第二类沟槽之间的所述第一类沟槽的侧部区域与底部区域，相邻第二类通孔之间的第一类沟槽的侧部区域与底部区域，以及第二类沟槽的侧部 区域与底部区域，所述第一导电类型阱区内的第一导电类型杂质的浓度低于所述第一导电类型外延层内的第一导电类型杂质的浓度。After coating the photoresist, selectively retaining part of the photoresist, injecting impurities of the second conductivity type into both the side region and the bottom region of the trench of the first type at a first angle to form a well region of the first conductivity type. The distribution region of the well region of the first conductivity type includes, in a direction parallel to the first type of trench, the first type of trench between the second type of through hole and the second type of trench The side area and the bottom area of the first type of trench between the adjacent second type of through hole, and the side area and the bottom area of the second type of trench, the first conductive The concentration of the impurity of the first conductivity type in the type well region is lower than the concentration of the impurity of the first conductivity type in the epitaxial layer of the first conductivity type.
进一步地，所述第一角度的取值范围在0°～60°之间。Further, the value range of the first angle is between 0° and 60°.
本发明提供的功率半导体器件，通过设置第一导电类型阱区，避免了器件在终端与过渡区位置有大电流的聚集，使得终端与过渡区不受伤害，这样提升了器件短路工作模式下的可靠性，同时提升了器件的短路能力。In the power semiconductor device provided by the present invention, by setting the well region of the first conductivity type, it is avoided that the device has a large current gathering at the position of the terminal and the transition region, so that the terminal and the transition region are not damaged, thus improving the short-circuit working mode of the device. Reliability, while improving the short-circuit capability of the device.
附图说明Description of drawings
附图是用来提供对本发明的进一步理解，并且构成说明书的一部分，与下面的具体实施方式一起用于解释本发明，但并不构成对本发明的限制。在附图中：The accompanying drawings are used to provide a further understanding of the present invention, and constitute a part of the description, together with the following specific embodiments, are used to explain the present invention, but do not constitute a limitation to the present invention. In the attached picture:
图1为本发明提供的器件的金属与沟槽的俯视示意图。FIG. 1 is a schematic top view of the metal and trenches of the device provided by the present invention.
图2为本发明一种实施例中沿着图1中的虚线AA’截得的剖面结构示意图。Fig. 2 is a schematic cross-sectional structure cut along the dotted line AA' in Fig. 1 in an embodiment of the present invention.
图3为本发明一种实施例中沿着图1中的虚线BB’截得的剖面结构示意图。Fig. 3 is a schematic cross-sectional structure cut along the dotted line BB' in Fig. 1 in an embodiment of the present invention.
图4为本发明一种实施例中沿着图1中的虚线CC’截得的剖面结构示意图。Fig. 4 is a schematic cross-sectional structure cut along the dotted line CC' in Fig. 1 in an embodiment of the present invention.
图5为本发明一种实施例中沿着图1中的虚线DD’截得的剖面结构示意图。Fig. 5 is a schematic cross-sectional structure cut along the dotted line DD' in Fig. 1 in an embodiment of the present invention.
图6为本发明实施例中在第一导电类型衬底上生长第一导电类型外延层的剖面结构示意图。6 is a schematic cross-sectional structure diagram of growing a first conductivity type epitaxial layer on a first conductivity type substrate in an embodiment of the present invention.
图7为本发明实施例中形成形成第一类沟槽与第二类沟槽的剖面结构示意图。FIG. 7 is a schematic cross-sectional structure diagram of forming a first-type trench and a second-type trench in an embodiment of the present invention.
图8为本发明实施例中形成第一导电类型阱区的剖面结构示意图。FIG. 8 is a schematic cross-sectional structure diagram of forming a well region of the first conductivity type in an embodiment of the present invention.
图9为本发明实施例中去除光刻胶与厚氧化层的剖面结构示意图。FIG. 9 is a schematic diagram of a cross-sectional structure of removing photoresist and thick oxide layer in an embodiment of the present invention.
图10为本发明实施例中形成场氧层的剖面结构示意图。FIG. 10 is a schematic cross-sectional structure diagram of forming a field oxygen layer in an embodiment of the present invention.
图11为本发明实施例中形成第一类导电多晶硅的剖面结构示意图。FIG. 11 is a schematic cross-sectional structure diagram of forming the first type of conductive polysilicon in an embodiment of the present invention.
图12为本发明实施例中选择性刻蚀第一类沟槽内的上半部分导电多晶硅的剖面结构示意图。FIG. 12 is a schematic cross-sectional view of selectively etching the upper half of the conductive polysilicon in the first type of trench in an embodiment of the present invention.
图13为本发明实施例中淀积绝缘介质层填充满第一类沟槽的上半部分的剖面结构示意图。FIG. 13 is a schematic cross-sectional view of the top half of the trench filled with an insulating dielectric layer deposited in an embodiment of the present invention.
图14为本发明实施例中去除第一导电类型外延层上方的绝缘介质层的剖面结构示意图。FIG. 14 is a schematic cross-sectional structure diagram of removing the insulating dielectric layer above the epitaxial layer of the first conductivity type in an embodiment of the present invention.
图15为本发明实施例中形成第一类绝缘介质的剖面结构示意图。FIG. 15 is a schematic cross-sectional structure diagram of forming a first type of insulating medium in an embodiment of the present invention.
图16为本发明实施例中形成栅氧层的剖面结构示意图。FIG. 16 is a schematic cross-sectional structure diagram of forming a gate oxide layer in an embodiment of the present invention.
图17为本发明实施例中形成第二类导电多晶硅的剖面结构示意图。FIG. 17 is a schematic cross-sectional structure diagram of forming the second type of conductive polysilicon in an embodiment of the present invention.
图18为本发明实施例中形成第二导电类型体区与第一导电类型源区的剖面结构示意图。18 is a schematic cross-sectional structure diagram of forming a body region of the second conductivity type and a source region of the first conductivity type in an embodiment of the present invention.
图19为本发明实施例中形成第二类绝缘介质的剖面结构示意图。FIG. 19 is a schematic cross-sectional structure diagram of forming a second type of insulating medium in an embodiment of the present invention.
图20为本发明实施例中形成第一类通孔、第二类通孔、第三类通孔的剖面结构示意图。20 is a schematic cross-sectional structure diagram of forming the first type of through hole, the second type of through hole and the third type of through hole in the embodiment of the present invention.
图21为本发明另一实施例中沿着图1中的虚线AA’截得的剖面结构示意图。Fig. 21 is a schematic cross-sectional structure diagram taken along the dotted line AA' in Fig. 1 in another embodiment of the present invention.
图22为本发明另一实施例中沿着图1中的虚线BB’截得的剖面结构示意图。Fig. 22 is a schematic cross-sectional structure diagram taken along the dotted line BB' in Fig. 1 in another embodiment of the present invention.
图23为本发明另一实施例中沿着图1中的虚线CC’截得的剖面结构示意图。Fig. 23 is a schematic cross-sectional structure diagram taken along the dotted line CC' in Fig. 1 in another embodiment of the present invention.
图24为本发明另一实施例中沿着图1中的虚线DD’截得的剖面结构示意图。Fig. 24 is a schematic cross-sectional view taken along the dotted line DD' in Fig. 1 in another embodiment of the present invention.
图25为本发明一种实施例中设有第一导电类型阱区的元胞的剖面结构示意图。FIG. 25 is a schematic cross-sectional structure diagram of a cell provided with a well region of the first conductivity type in an embodiment of the present invention.
图26为本发明一种实施例中不设有第一导电类型阱区的元胞的剖面结构示意图。FIG. 26 is a schematic cross-sectional structure diagram of a cell without a well region of the first conductivity type in an embodiment of the present invention.
图27为图25与图26中的元胞结构分别在击穿时沿着虚线FF’与虚线EE’截得的电场分布图。Fig. 27 is a diagram of the electric field distribution cut along the dotted line FF' and the dotted line EE' when the cellular structures in Fig. 25 and Fig. 26 respectively break down.
图28为本发明提供的功率半导体器件的制作方法的流程图。Fig. 28 is a flow chart of the manufacturing method of the power semiconductor device provided by the present invention.
图29为本发明提供的第一类沟槽与第二类沟槽的位置关系示意图。Fig. 29 is a schematic diagram of the positional relationship between the first type of groove and the second type of groove provided by the present invention.
具体实施方式Detailed ways
需要说明的是，在不冲突的情况下，本发明中的实施例及实施例中的特征可以相互结合。下面将参考附图并结合实施例来详细说明本发明。It should be noted that, in the case of no conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and examples.
为了使本领域技术人员更好地理解本发明方案，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分的实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都应当属于本发明保护的范围。In order to enable those skilled in the art to better understand the solutions of the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only Embodiments of some, but not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.
需要说明的是，本发明的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的本发明的实施例。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包括，例如，包含了一系列步骤或单元的过程、方法、***、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。It should be noted that the terms "first" and "second" in the description and claims of the present invention and the above drawings are used to distinguish similar objects, but not necessarily used to describe a specific sequence or sequence. It should be understood that the data so used may be interchanged under appropriate circumstances for the embodiments of the invention described herein. Furthermore, the terms "comprising" and "having", as well as any variations thereof, are intended to cover a non-exclusive inclusion, for example, a process, method, system, product, or device comprising a series of steps or elements that is not necessarily limited to the explicitly listed instead, may include other steps or elements not explicitly listed or inherent to the process, method, product or apparatus.
在本实施例中提供了一种功率半导体器件，图1是根据本发明实施例提供的功率半导体器件的俯视图，图2至图5分别为沿图1中的虚线AA'、虚线BB'、虚线CC'以及虚线DD'截得的剖视图，以及图21至图24分别为沿图1中的虚线AA'、虚线BB'、虚线CC'以及虚线DD'截得的剖视图，包括：In this embodiment, a power semiconductor device is provided. FIG. 1 is a top view of a power semiconductor device provided according to an embodiment of the present invention. FIG. 2 to FIG. The sectional views taken along CC' and dotted line DD', and Fig. 21 to Fig. 24 are the sectional views taken along dotted line AA', dotted line BB', dotted line CC' and dotted line DD' respectively in Fig. 1, including:
第一导电类型衬底1，所述第一导电类型衬底1上设置第一导电类型外延层2，所述第一导电类型外延层2的上表面设置朝向所述第一导电类型外延层2内部延伸的至少一条第二类沟槽16和多条第一类沟槽3，多条第一类沟槽3之间相互平行且间隔设置，所述第二类沟槽16环绕第一类沟槽3设置。A first conductivity type substrate 1, a first conductivity type epitaxial layer 2 is disposed on the first conductivity type substrate 1, and the upper surface of the first conductivity type epitaxial layer 2 is disposed facing the first conductivity type epitaxial layer 2 At least one second-type groove 16 and a plurality of first-type grooves 3 extending inside, the plurality of first-type grooves 3 are arranged parallel to each other and at intervals, and the second-type groove 16 surrounds the first-type groove Slot 3 is set.
此处应当理解的是，第一类沟槽3之间均相互平行设置，而第二类沟槽16将多条第一类沟槽3包围并环绕一圈设置，例如，图1所示方向为例，所述第 一类沟槽3均沿水平方向平行设置，所述第二类沟槽16呈环形设置，且所有第一类沟槽3均位于所述第二类沟槽13的环形区域内，具体如图29所示的第一类沟槽3与第二类沟槽16的位置关系示意图，图29所示结构仅以一条第二类沟槽16为例进行示意，还可以设置两条或者多条第二类沟槽16，多条第二类沟槽16均环绕设置。It should be understood here that the first-type grooves 3 are arranged parallel to each other, and the second-type grooves 16 surround and surround a plurality of first-type grooves 3 , for example, the direction shown in FIG. 1 For example, the first type of grooves 3 are arranged in parallel along the horizontal direction, the second type of grooves 16 are arranged in a ring shape, and all the first type of grooves 3 are located in the ring shape of the second type of grooves 13 In the area, the schematic diagram of the positional relationship between the first type of groove 3 and the second type of groove 16 is shown in Figure 29. Two or more grooves 16 of the second type, and the plurality of grooves 16 of the second type are all arranged around.
如图3或图22所示，每条第一类沟槽3的部分槽段的内部全部填充第一类导电多晶硅5，所述第一类导电多晶硅5与所述第一导电类型外延层2之间设置由绝缘介质构成的场氧层6，在所述第一类沟槽3的上方设置第二类绝缘介质层12，所述第二类绝缘介质层12的上方设置源极金属13，所述源极金属13通过位于所述第二类绝缘介质层12内的第一类通孔15与位于所述第一类沟槽3内的所述第一类导电多晶硅5欧姆接触。As shown in FIG. 3 or FIG. 22 , the interior of part of the groove segments of each first-type trench 3 is completely filled with the first-type conductive polysilicon 5 , and the first-type conductive polysilicon 5 is connected to the first-type conductive type epitaxial layer 2 A field oxygen layer 6 made of an insulating medium is disposed between them, a second type insulating dielectric layer 12 is disposed above the first type trench 3, and a source metal 13 is disposed above the second type insulating dielectric layer 12, The source metal 13 is in ohmic contact with the first-type conductive polysilicon 5 in the first-type trench 3 through the first-type through hole 15 in the second-type insulating dielectric layer 12 .
应当理解的是，该结构的理解可以参照图3和图5所示，由于BB'的位置为器件的中心位置，在该中心位置上均设置第一类通孔15，而沿着虚线BB'的两侧设置的则为第二类通孔14。另外，在图5可以看出，位于第一类通孔15下方的第一类沟槽3的槽段内部全部填充第一类导电多晶硅5。It should be understood that the structure can be understood with reference to those shown in Figures 3 and 5, since the position of BB' is the central position of the device, the first type of through hole 15 is provided at the central position, and along the dotted line BB' The second type of through-holes 14 are provided on both sides. In addition, it can be seen from FIG. 5 that the interior of the first-type trench 3 below the first-type through hole 15 is completely filled with the first-type conductive polysilicon 5 .
如图2或图21所示，每条第一类沟槽3的部分槽段的内部部分填充第一类导电多晶硅5，在所述第一类导电多晶硅5的上方填充第二类导电多晶硅8，所述第二类导电多晶硅8与所述第一类导电多晶硅5之间填充第一类绝缘介质层7，所述第二类导电多晶硅8与所述第一导电类型外延层2之间设置栅氧层9，每相邻两条第一类沟槽3之间的第一类导电类型外延层2的上表面设置第二导电类型体区10，部分所述第二导电类型体区10的上表面设置第一导电类型源区11，所述第一类沟槽3与所述第一导电类型源区11的上方均设置第二类绝缘介质层12，部分所述第二类绝缘介质层12的上方设置源极金属13，所述源极金属13通过位于所述第二类绝缘介质层12内的第二类通孔14分别与所述第一导电类型源区11和第二导电类型体区10欧姆接触。As shown in FIG. 2 or FIG. 21 , the interior of part of the groove segment of each first-type trench 3 is filled with the first-type conductive polysilicon 5 , and the second-type conductive polysilicon 8 is filled above the first-type conductive polysilicon 5 , between the second-type conductive polysilicon 8 and the first-type conductive polysilicon 5, a first-type insulating dielectric layer 7 is filled, and between the second-type conductive polysilicon 8 and the first-type conductive epitaxial layer 2 is arranged Gate oxide layer 9, a second conductivity type body region 10 is provided on the upper surface of the first conductivity type epitaxial layer 2 between every two adjacent first type trenches 3, part of the second conductivity type body region 10 A first-conductivity-type source region 11 is provided on the upper surface, and a second-type insulating dielectric layer 12 is arranged above the first-type trench 3 and the first-conductivity-type source region 11, and part of the second-type insulating dielectric layer 12, the source metal 13 is provided, and the source metal 13 is respectively connected to the source region 11 of the first conductivity type and the second conductivity type Body area 10 ohm contacts.
应当理解的是，如图5所示，在第一类沟槽3中除去前文所述的部分槽段全部填充第一类导电多晶硅5，其他部分槽段均是部分填充第一类导电多晶硅5，然后在第一类导电多晶硅5的上方填充第二类导电多晶硅8。It should be understood that, as shown in FIG. 5 , in the first type of trench 3, except for the above-mentioned part of the groove segments, all of them are filled with the first type of conductive polysilicon 5, and other parts of the groove segments are partially filled with the first type of conductive polysilicon 5. , and then the second type of conductive polysilicon 8 is filled above the first type of conductive polysilicon 5 .
如图2至图5所示，所述第一导电类型外延层2内设置第一导电类型阱区4，所述第一导电类型阱区4分布区域包括所述第二类通孔14下方且包覆所述第一类沟槽3的侧部区域和底部区域，所述第一导电类型阱区4内的第一导电类型杂质的浓度高于所述第一导电类型外延层2内的第一导电类型杂质的浓度；或者，As shown in FIG. 2 to FIG. 5 , a first conductivity type well region 4 is provided in the first conductivity type epitaxial layer 2 , and the distribution area of the first conductivity type well region 4 includes the underside of the second type through hole 14 and Covering the side region and bottom region of the first type trench 3, the concentration of the first conductivity type impurity in the first conductivity type well region 4 is higher than that of the first conductivity type impurity in the first conductivity type epitaxial layer 2 the concentration of a conductivity type impurity; or,
如图21至图24所示，所述第一导电类型外延层2内设置第一导电类型阱区4，所述第一导电类型阱区4分布区域包括，在与所述第一类沟槽3平行的方向上，所述第二类通孔14与所述第二类沟槽16之间的所述第一类沟槽3的侧部区域与底部区域，相邻第二类通孔14之间的第一类沟槽3的侧部区域与底部区域，以及第二类沟槽16的侧部区域与底部区域，所述第一导电类型阱区内4的第一导电类型杂质的浓度低于所述第一导电类型外延层2内的第一导电类型 杂质的浓度。As shown in Fig. 21 to Fig. 24, the first conductivity type well region 4 is set in the first conductivity type epitaxial layer 2, and the distribution area of the first conductivity type well region 4 includes, in the first type trench 3 In the parallel direction, the side area and the bottom area of the first type of groove 3 between the second type of through hole 14 and the second type of groove 16 are adjacent to the second type of through hole 14 Between the side region and the bottom region of the first type trench 3, and the side region and the bottom region of the second type trench 16, the concentration of the first conductivity type impurity in the first conductivity type well region 4 lower than the concentration of the first conductivity type impurity in the first conductivity type epitaxial layer 2 .
应当理解的是，第二导电类型体区10与第一导电类型外延层2组成的PN结以及第二导电类型体区10与第一导电类型阱区4组成的PN结具有不同的击穿特性，通过如图2至图5所示的第一导电类型阱区结构的设置，由于此方式中所述第一导电类型阱区内4的第一导电类型杂质的浓度高于所述第一导电类型外延层2内的第一导电类型杂质的浓度，在雪崩击穿时，第二导电类型体区10与第一导电类型外延层2组成的PN结上的峰值电场强度会明显低于第二导电类型体区10与第一导电类型阱区4组成的PN结上的峰值电场强度，如图25所示为设有第一导电类型阱区4的元胞的剖面结构示意图，如图26所示为未设第一导电类型阱区的元胞的剖面结构示意图，如图27所示为图25与图26中的元胞结构分别在击穿时沿着虚线FF’与虚线EE’截得的电场分布图，图25中第二导电类型体区10与第一导电类型阱区4组成的PN结上的电场远高于第二导电类型体区10与第一导电类型外延层2组成的PN结，这使得器件在大电流雪崩击穿时，绝大部分电流会流过第二导电类型体区10与第一导电类型阱区4组成的PN结，从而保护了过渡区与终端区。It should be understood that the PN junction formed by the body region 10 of the second conductivity type and the epitaxial layer 2 of the first conductivity type and the PN junction formed by the body region 10 of the second conductivity type and the well region 4 of the first conductivity type have different breakdown characteristics. , through the setting of the first conductivity type well region structure as shown in Fig. The concentration of the first conductivity type impurity in the epitaxial layer 2 of the second conductivity type, when the avalanche breakdown occurs, the peak electric field intensity on the PN junction formed by the body region 10 of the second conductivity type and the epitaxial layer 2 of the first conductivity type will be significantly lower than that of the second conductivity type The peak electric field intensity on the PN junction formed by the body region 10 of the conductivity type and the well region 4 of the first conductivity type is shown in FIG. It is a schematic diagram of the cross-sectional structure of a cell without a well region of the first conductivity type. As shown in FIG. 27, the cell structures in FIG. 25 and FIG. 26 are cut along the dotted line FF' and the dotted line EE' respectively during breakdown. In FIG. 25 , the electric field on the PN junction composed of the body region 10 of the second conductivity type and the well region 4 of the first conductivity type is much higher than that of the body region 10 of the second conductivity type and the epitaxial layer 2 of the first conductivity type. The PN junction, which makes the device in the case of avalanche breakdown of a large current, most of the current will flow through the PN junction formed by the second conductivity type body region 10 and the first conductivity type well region 4, thereby protecting the transition region and the terminal region.
另外，第二导电类型体区10与第一导电类型外延层2组成的PN结以及第二导电类型体区10与第一导电类型阱区4组成的PN结具有不同的击穿特性，通过图21至图24所示的第一导电类型阱区结构的设置，由于此方式中所述第一导电类型阱区内4的第一导电类型杂质的浓度低于所述第一导电类型外延层2内的第一导电类型杂质的浓度，在雪崩击穿时，第二导电类型体区10与第一导电类型外延层2组成的PN结上的峰值电场强度会明显高于第二导电类型体区10与第一导电类型阱区4组成的PN结上的峰值电场强度，这使得器件在大电流雪崩击穿时，绝大部分电流会流过第二导电类型体区10与第一导电类型外延层2组成的PN结，从而保护了过渡区与终端区。In addition, the PN junction formed by the body region 10 of the second conductivity type and the epitaxial layer 2 of the first conductivity type and the PN junction formed by the body region 10 of the second conductivity type and the well region 4 of the first conductivity type have different breakdown characteristics, as shown in FIG. 21 to the configuration of the first conductivity type well region structure shown in FIG. The concentration of the impurity of the first conductivity type inside, when the avalanche breakdown occurs, the peak electric field intensity on the PN junction formed by the body region 10 of the second conductivity type and the epitaxial layer 2 of the first conductivity type will be obviously higher than that of the body region of the second conductivity type 10 and the peak electric field intensity on the PN junction composed of the well region 4 of the first conductivity type, which makes most of the current flow through the body region 10 of the second conductivity type and the epitaxial layer of the first conductivity type when the device undergoes avalanche breakdown of a large current. The PN junction composed of layer 2 protects the transition region and the terminal region.
综上，本发明实施例提供的功率半导体器件，通过设置第一导电类型阱区，避免了器件在终端与过渡区位置有大电流的聚集，使得终端与过渡区不受伤害，这样提升了器件短路工作模式下的可靠性，同时提升了器件的短路能力。To sum up, the power semiconductor device provided by the embodiment of the present invention, by setting the first conductivity type well region, avoids the accumulation of large current in the terminal and the transition region of the device, so that the terminal and the transition region are not damaged, thus improving the performance of the device. The reliability in the short-circuit working mode improves the short-circuit capability of the device at the same time.
作为一种具体地实施方式，如图2至图5所示，所述第一导电类型外延层2内设置第一导电类型阱区4，所述第一导电类型阱区4分布区域包括所述第二类通孔14下方且包覆所述第一类沟槽3的底部区域以及侧部区域；As a specific implementation, as shown in Fig. 2 to Fig. 5, the first conductivity type well region 4 is provided in the first conductivity type epitaxial layer 2, and the distribution area of the first conductivity type well region 4 includes the The bottom area and the side area below the second type of through hole 14 and covering the first type of trench 3;
所述第一导电类型阱区4沿与所述第一类沟槽3平行的方向上的边界均位于所述第二类通孔14的下方，所述第一导电类外延层2中靠近与所述第一类沟槽3平行的第二类沟槽槽段的至少一条所述第一类沟槽3的侧部区域和底部区域未分布所述第一导电类型阱区4；The boundary of the first conductivity type well region 4 along the direction parallel to the first type trench 3 is located below the second type through hole 14, and the first conductivity type epitaxial layer 2 is close to the The first conductivity type well region 4 is not distributed in the side region and bottom region of at least one of the first type trenches 3 parallel to the second type trench segment;
所述第一导电类型阱区4内的第一导电类型杂质的浓度为所述第一导电类型外延层内的第一导电类型杂质的浓度的1.01倍至5倍。The concentration of the impurity of the first conductivity type in the well region 4 of the first conductivity type is 1.01 to 5 times the concentration of the impurity of the first conductivity type in the epitaxial layer of the first conductivity type.
在该实施方式中，第一导电类型阱区4的分布可以理解为，在沿与所述第一类沟槽3平行的方向上，其主要分布在第二类通孔14的下方，且包覆第一类沟槽3的侧部和底部，由图2和图4可以看出。另外，第一导电类型阱区4在 该方向上的边界均未超过所述第二类通孔14的两端，即边界均在第二类通孔14的下方。在沿与所述第一类沟槽3垂直的方向上，第一导电类型阱区4的分布主要是在第一类沟槽3的底部和侧部，且靠近第二类沟槽16槽段(该槽段应当为平行于第一类沟槽3，即如图29所示的横向槽段部分)的至少一条第一类沟槽3的侧部和底部未设置第一导电类型阱区。In this embodiment, the distribution of the well regions 4 of the first conductivity type can be understood as, along the direction parallel to the trenches 3 of the first type, they are mainly distributed under the via holes 14 of the second type, and include It can be seen from Fig. 2 and Fig. 4 that it covers the sides and bottom of the first type of groove 3. In addition, the boundary of the well region 4 of the first conductivity type in this direction does not exceed both ends of the second-type through hole 14 , that is, the boundaries are all below the second-type through-hole 14 . Along the direction perpendicular to the first type of trench 3, the distribution of the first conductivity type well region 4 is mainly at the bottom and side of the first type of trench 3, and close to the second type of trench 16 groove segment (The groove segment should be parallel to the first type of groove 3 , that is, the transverse groove segment portion shown in FIG. 29 ). At least one first type of groove 3 has no well region of the first conductivity type on the side and bottom.
作为另一种具体地实施方式，如图1、图21至图24所示，所述第一导电类型阱区4分布区域包括，在与所述第一类沟槽3平行的方向上，所述第二类通孔14与所述第二类沟槽16之间的所述第一类沟槽3的侧部区域与底部区域，相邻第二类通孔14之间的第一类沟槽3的侧部区域与底部区域，以及第二类沟槽16的侧部区域与底部区域；As another specific implementation, as shown in FIG. 1, FIG. 21 to FIG. 24, the distribution area of the first conductivity type well region 4 includes, in the direction parallel to the first type trench 3, the The side area and bottom area of the first type of groove 3 between the second type of through hole 14 and the second type of groove 16, the first type of groove between adjacent second type of through holes 14 the side area and the bottom area of the groove 3, and the side area and the bottom area of the second type of groove 16;
所述第一导电类型阱4区沿与所述第一类沟槽3平行的方向上的边界延伸至所述第二类通孔14的下方的部分区域，所述第一导电类型外延层2中靠近与所述第一类沟槽3平行的第二类沟槽槽段的至少一条所述第一类沟槽3的侧部区域和底部区域被所述第一导电类型阱区4包覆；The region of the well 4 of the first conductivity type extends along the boundary in a direction parallel to the trench 3 of the first type to a part of the region below the through hole 14 of the second type, and the epitaxial layer 2 of the first conductivity type The side region and the bottom region of at least one of the first-type trenches 3 close to the second-type trench segment parallel to the first-type trench 3 are covered by the first-conductivity-type well region 4 ;
所述第一导电类型外延层2内的第一导电类型杂质的浓度为所述第一导电类型阱区4内的第一导电类型杂质的浓度的1.01倍至5倍。The concentration of the impurity of the first conductivity type in the epitaxial layer 2 of the first conductivity type is 1.01 to 5 times the concentration of the impurity of the first conductivity type in the well region 4 of the first conductivity type.
在该实施方式中，第一导电类型阱区4的分布可以理解为，在沿与所述第一类沟槽3平行的方向上，除了第二类通孔14的下方的第一类沟槽外，其他区域下方的第一类沟槽3的底部和侧部均设置有第一导电类型阱区4，且在该方向上，第一导电类型阱区4的边界位置可以延伸至第二类通孔14的下方。在与所述第一类沟槽3垂直的方向上，第二类沟槽16的底部和侧部，以及靠近第二类沟槽16的至少一条第一类沟槽3的侧部和底部均设置第一导电类型阱区4。In this embodiment, the distribution of the well regions 4 of the first conductivity type can be understood as, in the direction parallel to the first type trenches 3 , except for the first type trenches below the second type through holes 14 In addition, the bottom and sides of the first-type trenches 3 under other regions are provided with first-conductivity-type well regions 4, and in this direction, the boundary position of the first-conductivity-type well regions 4 can extend to the second-type trenches. Below the through hole 14. In the direction perpendicular to the first type of groove 3, the bottom and side of the second type of groove 16, and the side and bottom of at least one first type of groove 3 close to the second type of groove 16 are all A first conductivity type well region 4 is provided.
在前述实施方式的基础上，如图3和图4，以及图22和图23所示，所述第二类沟槽16的内部填充第一类导电多晶硅5，所述第一类导电多晶硅5与所述第一导电外延层2之间设置场氧层6，所述第二类沟槽16上方设置所述第二类绝缘介质层12，所述第二类绝缘介质层12的上方设置源极金属13，所述第二类沟槽16内的第一类导电多晶硅5通过位于所述第二类绝缘介质层12内的第一类通孔15与所述源极金属13欧姆接触。On the basis of the aforementioned embodiments, as shown in FIGS. 3 and 4, and FIGS. A field oxygen layer 6 is arranged between the first conductive epitaxial layer 2, the second type insulating dielectric layer 12 is arranged above the second type trench 16, and a source is arranged above the second type insulating dielectric layer 12. The first-type conductive polysilicon 5 in the second-type trench 16 is in ohmic contact with the source metal 13 through the first-type through hole 15 located in the second-type insulating dielectric layer 12 .
如图2和图21所示，与所述第一类沟槽3平行的第二类沟槽16槽段与相邻的第一类沟槽3之间的第一导电类型外延层2的表面设置第二导电类型体区10，所述第二导电类型体区10的上方设置第二类绝缘介质层12，所述第二类绝缘介质层12的上方设置源极金属13，所述源极金属13通过位于所述第二类绝缘介质层12内的第二类通孔14与所述第二导电类型体区10欧姆接触。As shown in Figure 2 and Figure 21, the surface of the epitaxial layer 2 of the first conductivity type between the groove segment of the second type of trench 16 parallel to the first type of trench 3 and the adjacent first type of trench 3 A second conductivity type body region 10 is provided, a second type insulating dielectric layer 12 is disposed above the second conductivity type body region 10, a source metal 13 is disposed above the second type insulation dielectric layer 12, and the source The metal 13 is in ohmic contact with the second conductivity type body region 10 through the second type through hole 14 located in the second type insulating dielectric layer 12 .
如图4和图5，以及图23和图24所示，每条所述第一类沟槽3的上方设置第二类绝缘介质层12，所述第二类绝缘介质层12的上方设置栅极金属17，所述栅极金属17通过位于所述第二类绝缘介质层12内的第三类通孔18与所述第二类导电多晶硅8欧姆接触。As shown in Figures 4 and 5, and Figures 23 and 24, a second-type insulating dielectric layer 12 is arranged above each of the first-type trenches 3, and a gate is arranged above the second-type insulating dielectric layer 12. The gate metal 17 is in ohmic contact with the second-type conductive polysilicon 8 through the third-type via hole 18 located in the second-type insulating dielectric layer 12 .
应当理解的是，所述功率半导体器件包括N型功率半导体器件和P型功率半导体器件，当所述功率半导体器件为所述N型功率半导体器件时，第一导电 类型为N型，第二导电类型为P型，当所述功率半导体器件为所述P型半导体器件时，第一导电类型为P型，第二导电类型为N型。It should be understood that the power semiconductor device includes an N-type power semiconductor device and a P-type power semiconductor device. When the power semiconductor device is the N-type power semiconductor device, the first conductivity type is N-type, and the second conductivity type is N-type. The type is P-type, and when the power semiconductor device is the P-type semiconductor device, the first conductivity type is P-type, and the second conductivity type is N-type.
在本发明实施例中，均以功率半导体器件为所述N型功率半导体器件为例进行说明，此时第一导电类型为N型，第二导电类型为P型。In the embodiments of the present invention, the power semiconductor device is the N-type power semiconductor device as an example for description. At this time, the first conductivity type is N-type, and the second conductivity type is P-type.
作为本发明的一种具体地实施例，如图1至图5所示，包括N型衬底1，在所述N型衬底1上方设有N型外延层2，如图1所示为器件的俯视示意图，在所述N型外延层2的表面设置条形的互相平行且均匀分布的第一类沟槽3，在所述第一类沟槽3的***被第二类沟槽16环绕。As a specific embodiment of the present invention, as shown in Figures 1 to 5, an N-type substrate 1 is included, and an N-type epitaxial layer 2 is arranged above the N-type substrate 1, as shown in Figure 1 A schematic top view of the device, strip-shaped first-type trenches 3 parallel to each other and uniformly distributed are arranged on the surface of the N-type epitaxial layer 2, and the periphery of the first-type trenches 3 is surrounded by second-type trenches 16 surround.
如图3所示为沿着图1中的虚线BB’截得的剖面结构示意图，在第一类沟槽3的中部位置，第一类沟槽3内填充满了第一类导电多晶硅5，第一类沟槽3内的第一类导电多晶硅5通过场氧层6与N型外延层2绝缘，相邻的第一类沟槽3之间的N型外延层2与第一类沟槽3的上方设有第二类绝缘介质层12，在所述第二类绝缘介质层12的上方设有源极金属13，所述源极金属13通过第二类绝缘介质层12内的第一类通孔15与第一类沟槽3内的第一类导电多晶硅5欧姆接触；第二类沟槽16内填充满了第一类导电多晶硅5，第二类沟槽16内的第一类导电多晶硅5通过场氧层6与N型外延层2绝缘。由器件的俯视角度，与第一类沟槽3平行的第二类沟槽16槽段的上方设有第二类绝缘介质层12，在所述第二类绝缘介质层12的上方设有源极金属13，所述源极金属13通过第一类通孔15与第二类沟槽16内的第一类导电多晶硅5欧姆接触。As shown in FIG. 3, it is a schematic cross-sectional structure cut along the dotted line BB' in FIG. The first-type conductive polysilicon 5 in the first-type trenches 3 is insulated from the N-type epitaxial layer 2 by the field oxygen layer 6, and the N-type epitaxial layer 2 between adjacent first-type trenches 3 is insulated from the first-type trenches. 3 is provided with a second-type insulating dielectric layer 12, and a source metal 13 is provided above the second-type insulating dielectric layer 12, and the source metal 13 passes through the first The through hole 15 is in ohmic contact with the first type conductive polysilicon 5 in the first type trench 3; the second type trench 16 is filled with the first type conductive polysilicon 5, and the first type conductive polysilicon 5 in the second type trench 16 Conductive polysilicon 5 is insulated from N-type epitaxial layer 2 by field oxygen layer 6 . From the top view angle of the device, a second type of insulating dielectric layer 12 is arranged above the second type of trench 16 parallel to the first type of trench 3, and a source is arranged above the second type of insulating dielectric layer 12. An electrode metal 13 , the source metal 13 is in ohmic contact with the first type conductive polysilicon 5 in the second type trench 16 through the first type through hole 15 .
如图2所示为沿着图1中的虚线AA’截得的剖面结构示意图，第一类沟槽3的下半段设有第一类导电多晶硅5，上半段设有第二类导电多晶硅8，第一类导电多晶硅5与第二类导电多晶硅8通过第一类绝缘介质层7绝缘，第一类导电多晶硅5通过场氧层6与N型外延层2绝缘，第二类导电多晶硅8通过栅氧层9与N型外延层2绝缘，相邻的第一类沟槽3之间的N型外延层2的表面设有P型体区10，在该P型体区10的表面设有N型源区11，在第一类沟槽3与N型源区11的上方设有第二类绝缘介质层12，在所述第二类绝缘介质层12的上方设有源极金属13，所述源极金属13通过第二类绝缘介质层12内的第二类通孔14分别与N型源区11以及P型体区10欧姆接触；与第一类沟槽3平行的第二类沟槽16槽段与相邻的第一类沟槽3之间的N型外延层2的表面设有P型体区10，在该P型体区10的上方设有第二类绝缘介质层12，在所述第二类绝缘介质层12的上方设有源极金属13，所述源极金属13通过第二类通孔14与该P型体区10欧姆接触。As shown in Figure 2, it is a schematic cross-sectional structure cut along the dotted line AA' in Figure 1. The lower half of the first type of trench 3 is provided with the first type of conductive polysilicon 5, and the upper half is provided with the second type of conductive polysilicon. Polysilicon 8, first-type conductive polysilicon 5 and second-type conductive polysilicon 8 are insulated by first-type insulating dielectric layer 7, first-type conductive polysilicon 5 is insulated from N-type epitaxial layer 2 by field oxygen layer 6, second-type conductive polysilicon 8 is insulated from the N-type epitaxial layer 2 by the gate oxide layer 9, and the surface of the N-type epitaxial layer 2 between adjacent first-type trenches 3 is provided with a P-type body region 10, and on the surface of the P-type body region 10 An N-type source region 11 is provided, a second-type insulating dielectric layer 12 is arranged above the first-type trench 3 and the N-type source region 11, and a source metal layer is arranged above the second-type insulating dielectric layer 12. 13. The source metal 13 is in ohmic contact with the N-type source region 11 and the P-type body region 10 through the second-type through hole 14 in the second-type insulating dielectric layer 12; A P-type body region 10 is provided on the surface of the N-type epitaxial layer 2 between the groove segment of the second-type trench 16 and the adjacent first-type trench 3, and a second-type insulating layer is arranged above the P-type body region 10. The dielectric layer 12 is provided with a source metal 13 above the second-type insulating dielectric layer 12 , and the source metal 13 is in ohmic contact with the P-type body region 10 through the second-type through hole 14 .
如图5所示为沿着图1中的虚线DD’截得的剖面结构示意图，在第一类沟槽3的两端的尽头以及在第一类沟槽3的上方设有第二类绝缘介质层12，在所述第二类绝缘介质层12的上方设有栅极金属17，所述栅极金属17通过第二类绝缘介质层12内的第三类通孔18与第二类导电多晶硅8欧姆接触。As shown in FIG. 5, it is a schematic cross-sectional structure cut along the dotted line DD' in FIG. layer 12, a gate metal 17 is arranged above the second type insulating dielectric layer 12, and the gate metal 17 passes through the third type through hole 18 in the second type insulating dielectric layer 12 and the second type conductive polysilicon 8 ohm contacts.
如图4所示为沿着图1中的虚线CC’截得的剖面结构示意图，在与第一类沟槽3平行的方向上，第一类沟槽3的侧壁与底部附近的N型外延层2内设有N型阱区4，只有第二类通孔14的下方才设有所述N型阱区4，且所述N型阱 区4的边缘不越过所述第二类通孔14的尽头，且N型阱区4的边缘距离第二类通孔14的尽头约5μm；所述N型阱区4内的N型杂质的浓度高于N型外延层2内的N型杂质的浓度。As shown in Figure 4, it is a schematic cross-sectional structure cut along the dotted line CC' in Figure 1. In the direction parallel to the first type of trench 3, the side walls of the first type of trench 3 and the N-type near the bottom An N-type well region 4 is provided in the epitaxial layer 2, and the N-type well region 4 is provided only under the second type of through hole 14, and the edge of the N-type well region 4 does not cross the second type of through hole. The end of the hole 14, and the edge of the N-type well region 4 is about 5 μm away from the end of the second type of through hole 14; the concentration of the N-type impurity in the N-type well region 4 is higher than that of the N-type impurities in the N-type epitaxial layer 2 concentration of impurities.
如图2所示，与第一类沟槽3垂直的方向上，靠近第二类沟槽16的第一条第一类沟槽3的侧壁与底部附近的N型外延层2内，不设有N型阱区4。As shown in FIG. 2 , in the direction perpendicular to the first-type trench 3 , in the N-type epitaxial layer 2 near the sidewall and bottom of the first first-type trench 3 close to the second-type trench 16 , there is no An N-type well region 4 is provided.
这样设置N型阱区4是因为P型体区10与N型外延层2组成的PN结、P型体区10与N型阱区4组成的PN结具有不同的击穿特性，由于本实施例中N型阱区4的掺杂浓度大于外延层2，在雪崩击穿时，P型体区10与外延层2组成的PN结上的峰值电场强度会明显低于P型体区10与N型阱区4组成的PN结上的峰值电场强度，如图25所示为本实施例设有第一导电类型阱区的元胞的剖面结构示意图，如图26所示为本实施例不设有第一导电类型阱区的元胞的剖面结构示意图，如图27所示为图25与图26中的元胞结构分别在击穿时沿着虚线FF’与虚线EE’截得的电场分布图，图25中P型体区10与N型阱区4组成的PN结上的电场远高于P型体区10与外延层2组成的PN结，这使得器件在大电流雪崩击穿时，绝大部分电流会流过P型体区10与N型阱区4组成的PN结，从而保护了过渡区与终端区。The N-type well region 4 is arranged like this because the PN junction formed by the P-type body region 10 and the N-type epitaxial layer 2, and the PN junction formed by the P-type body region 10 and the N-type well region 4 have different breakdown characteristics. In the example, the doping concentration of the N-type well region 4 is greater than that of the epitaxial layer 2. During avalanche breakdown, the peak electric field intensity on the PN junction composed of the P-type body region 10 and the epitaxial layer 2 will be significantly lower than that of the P-type body region 10 and the epitaxial layer 2. The peak electric field intensity on the PN junction formed by the N-type well region 4, as shown in FIG. 25 is a schematic cross-sectional structure diagram of a cell provided with a first conductivity type well region in this embodiment, and as shown in FIG. 26 is not shown in this embodiment. Schematic diagram of the cross-sectional structure of a cell with a well region of the first conductivity type, as shown in Figure 27, the electric field cut along the dotted line FF' and the dotted line EE' when the cell structure in Figure 25 and Figure 26 respectively breaks down Distribution diagram, in Figure 25, the electric field on the PN junction composed of P-type body region 10 and N-type well region 4 is much higher than that of the PN junction composed of P-type body region 10 and epitaxial layer 2, which makes the device break down under high current avalanche At this time, most of the current will flow through the PN junction formed by the P-type body region 10 and the N-type well region 4, thereby protecting the transition region and the terminal region.
作为本发明的另一种具体地实施例，如图1、图21至图24所示，包括N型衬底1，在所述N型衬底1上方设有N型外延层2，如图1所示为本发明提供的器件的俯视示意图，在所述N型外延层2的表面设置条形的互相平行且均匀分布的第一类沟槽3，在所述第一类沟槽3的***被第二类沟槽16环绕；As another specific embodiment of the present invention, as shown in FIG. 1, FIG. 21 to FIG. 24, it includes an N-type substrate 1, and an N-type epitaxial layer 2 is arranged on the N-type substrate 1, as shown in FIG. 1 is a schematic top view of the device provided by the present invention. On the surface of the N-type epitaxial layer 2, strip-shaped first-type trenches 3 parallel to each other and uniformly distributed are arranged. The periphery is surrounded by second-type grooves 16;
如图22所示为沿着图1中的虚线BB’截得的剖面结构示意图，在第一类沟槽3的中部位置，第一类沟槽3内填充满了第一类导电多晶硅5，第一类沟槽3内的第一类导电多晶硅5通过场氧层6与N型外延层2绝缘，相邻的第一类沟槽3之间的N型外延层2与第一类沟槽3的上方设有第二类绝缘介质层12，在所述第二类绝缘介质层12的上方设有源极金属13，所述源极金属13通过第二类绝缘介质层12内的第一类通孔15与第一类沟槽3内的第一类导电多晶硅5欧姆接触；第二类沟槽16内填充满了第一类导电多晶硅5，第二类沟槽16内的第一类导电多晶硅5通过场氧层6与N型外延层2绝缘，由器件的俯视角度理解，与第一类沟槽3平行的第二类沟槽16槽段的上方设有第二类绝缘介质层12，在所述第二类绝缘介质层12的上方设有源极金属13，所述源极金属13通过第一类通孔15与第二类沟槽16内的第一类导电多晶硅5欧姆接触。As shown in FIG. 22, it is a schematic cross-sectional structure cut along the dotted line BB' in FIG. 1. In the middle of the first-type trench 3, the first-type trench 3 is filled with the first-type conductive polysilicon 5. The first-type conductive polysilicon 5 in the first-type trenches 3 is insulated from the N-type epitaxial layer 2 by the field oxygen layer 6, and the N-type epitaxial layer 2 between adjacent first-type trenches 3 is insulated from the first-type trenches. 3 is provided with a second-type insulating dielectric layer 12, and a source metal 13 is provided above the second-type insulating dielectric layer 12, and the source metal 13 passes through the first The through hole 15 is in ohmic contact with the first type conductive polysilicon 5 in the first type trench 3; the second type trench 16 is filled with the first type conductive polysilicon 5, and the first type conductive polysilicon 5 in the second type trench 16 The conductive polysilicon 5 is insulated from the N-type epitaxial layer 2 by the field oxygen layer 6. From the perspective of the device, a second-type insulating dielectric layer is arranged above the second-type trench 16 parallel to the first-type trench 3 12. A source metal 13 is provided above the second-type insulating dielectric layer 12, and the source metal 13 passes through the first-type through hole 15 and the first-type conductive polysilicon 5 ohm in the second-type trench 16 touch.
如图21所示为沿着图1中的虚线AA’截得的剖面结构示意图，第一类沟槽3的下半段设有第一类导电多晶硅5，上半段设有第二类导电多晶硅8，第一类导电多晶硅5与第二类导电多晶硅8通过第一类绝缘介质层7绝缘，第一类导电多晶硅5通过场氧层6与N型外延层2绝缘，第二类导电多晶硅8通过栅氧层9与N型外延层2绝缘，相邻的第一类沟槽3之间的N型外延层2的表面设有P型体区10，在该P型体区10的表面设有N型源区11，在第一类沟槽3与N型源区11的上方设有第二类绝缘介质层12，在所述第二类绝缘介质层12的上方设有源极金属13，所述源极金属13通过第二类绝缘介质层12内的第二 类通孔14分别与N型源区11以及P型体区10欧姆接触；与第一类沟槽3平行的第二类沟槽16槽段与相邻的第一类沟槽3之间的N型外延层2的表面设有P型体区10，在该P型体区10的上方设有第二类绝缘介质层12，在所述第二类绝缘介质层12的上方设有源极金属13，所述源极金属13通过第二类通孔14与该P型体区10欧姆接触。As shown in Figure 21, it is a schematic cross-sectional structure cut along the dotted line AA' in Figure 1. The lower half of the first type of trench 3 is provided with the first type of conductive polysilicon 5, and the upper half is provided with the second type of conductive polysilicon 5. Polysilicon 8, first-type conductive polysilicon 5 and second-type conductive polysilicon 8 are insulated by first-type insulating dielectric layer 7, first-type conductive polysilicon 5 is insulated from N-type epitaxial layer 2 by field oxygen layer 6, second-type conductive polysilicon 8 is insulated from the N-type epitaxial layer 2 by the gate oxide layer 9, and the surface of the N-type epitaxial layer 2 between adjacent first-type trenches 3 is provided with a P-type body region 10, and on the surface of the P-type body region 10 An N-type source region 11 is provided, a second-type insulating dielectric layer 12 is arranged above the first-type trench 3 and the N-type source region 11, and a source metal layer is arranged above the second-type insulating dielectric layer 12. 13. The source metal 13 is in ohmic contact with the N-type source region 11 and the P-type body region 10 through the second-type through hole 14 in the second-type insulating dielectric layer 12; A P-type body region 10 is provided on the surface of the N-type epitaxial layer 2 between the groove segment of the second-type trench 16 and the adjacent first-type trench 3, and a second-type insulating layer is arranged above the P-type body region 10. The dielectric layer 12 is provided with a source metal 13 above the second-type insulating dielectric layer 12 , and the source metal 13 is in ohmic contact with the P-type body region 10 through the second-type through hole 14 .
如图24所示为沿着图1中的虚线DD’截得的剖面结构示意图，在第一类沟槽3的两端的尽头，在第一类沟槽3的上方设有第二类绝缘介质层12，在所述第二类绝缘介质层12的上方设有栅极金属17，所述栅极金属17通过第二类绝缘介质层12内的第三类通孔18与第二类导电多晶硅8欧姆接触。As shown in FIG. 24, it is a schematic cross-sectional structure cut along the dotted line DD' in FIG. layer 12, a gate metal 17 is arranged above the second type insulating dielectric layer 12, and the gate metal 17 passes through the third type through hole 18 in the second type insulating dielectric layer 12 and the second type conductive polysilicon 8 ohm contacts.
如图23所示为沿着图1中的虚线CC’截得的剖面结构示意图，在与第一类沟槽3平行的方向上，除了第二类通孔14的下方，第一类沟槽3的侧壁与底部附近的N型外延层2内都设有N型阱区4，且所述N型阱区4的边缘越过所述第二类通孔14的尽头，部分进入第二类通孔14的下方，所述第二类沟槽16的侧壁与底部附近的N型外延层2内设有N型阱区4；所述N型阱区4内的N型杂质的浓度低于N型外延层2内的N型杂质的浓度。As shown in FIG. 23 , it is a schematic cross-sectional structure diagram taken along the dotted line CC' in FIG. N-type well region 4 is provided in the N-type epitaxial layer 2 near the sidewall and bottom of 3, and the edge of the N-type well region 4 crosses the end of the second type through hole 14, and partly enters the second type through hole 14. Below the through hole 14, an N-type well region 4 is arranged in the N-type epitaxial layer 2 near the sidewall and bottom of the second type trench 16; the concentration of N-type impurities in the N-type well region 4 is low The concentration of N-type impurities in the N-type epitaxial layer 2 .
如图21所示，与第一类沟槽3垂直的方向上，器件的俯视角度，靠近第二类沟槽16的第一条第一类沟槽3的侧壁与底部附近的N型外延层2内设有N型阱区4。As shown in FIG. 21 , in the direction perpendicular to the first-type trench 3 , the top view angle of the device, the N-type epitaxy near the sidewall and the bottom of the first first-type trench 3 near the second-type trench 16 N-type well region 4 is arranged in layer 2 .
这样设置N型阱区4是因为P型体区10与N型外延层2组成的PN结、P型体区10与N型阱区4组成的PN结具有不同的击穿特性，由于本实施例中N型阱区4的掺杂浓度小于N型外延层2，在雪崩击穿时，P型体区10与N型外延层2组成的PN结上的峰值电场强度会明显高于P型体区10与N型阱区4组成的PN结上的峰值电场强度，这使得器件在大电流雪崩击穿时，绝大部分电流会流过P型体区10与N型外延层2组成的PN结，从而保护了过渡区与终端区。The N-type well region 4 is arranged like this because the PN junction formed by the P-type body region 10 and the N-type epitaxial layer 2, and the PN junction formed by the P-type body region 10 and the N-type well region 4 have different breakdown characteristics. In the example, the doping concentration of the N-type well region 4 is lower than that of the N-type epitaxial layer 2. When the avalanche breakdown occurs, the peak electric field intensity on the PN junction composed of the P-type body region 10 and the N-type epitaxial layer 2 will be significantly higher than that of the P-type well region 10. The peak electric field intensity on the PN junction formed by the body region 10 and the N-type well region 4 makes most of the current flow through the P-type body region 10 and the N-type epitaxial layer 2 when the device undergoes avalanche breakdown at a high current. PN junction, thus protecting the transition region and the terminal region.
作为本发明的另一实施例，提供一种如前文所述的功率半导体器件的制作方法，其中，如图28所示，包括：As another embodiment of the present invention, a method for manufacturing a power semiconductor device as described above is provided, wherein, as shown in FIG. 28 , it includes:
S110、提供第一导电类型衬底，在所述第一导电类型衬底上生长第一导电类型外延层；S110, providing a first conductivity type substrate, and growing a first conductivity type epitaxial layer on the first conductivity type substrate;
需要说明的是，所述功率半导体器件包括N型功率半导体器件和P型功率半导体器件，当所述功率半导体器件为所述N型功率半导体器件时，第一导电类型为N型，第二导电类型为P型，当所述功率半导体器件为所述P型半导体器件时，第一导电类型为P型，第二导电类型为N型。It should be noted that the power semiconductor device includes an N-type power semiconductor device and a P-type power semiconductor device. When the power semiconductor device is the N-type power semiconductor device, the first conductivity type is N-type, and the second conductivity type is N-type. The type is P-type, and when the power semiconductor device is the P-type semiconductor device, the first conductivity type is P-type, and the second conductivity type is N-type.
在本发明实施例中，均以功率半导体器件为所述N型功率半导体器件为例进行说明，此时第一导电类型为N型，第二导电类型为P型。In the embodiments of the present invention, the power semiconductor device is the N-type power semiconductor device as an example for description. At this time, the first conductivity type is N-type, and the second conductivity type is P-type.
在该步骤中，如图6所示，提供N型衬底1，在所述N型衬底1上生长N型外延层2。In this step, as shown in FIG. 6 , an N-type substrate 1 is provided, and an N-type epitaxial layer 2 is grown on the N-type substrate 1 .
S120、在所述第一导电类型外延层的表面形成厚氧化层，选择性刻蚀厚氧化层与所述第一导电类型外延层后，形成第一类沟槽与第二类沟槽；S120, forming a thick oxide layer on the surface of the first conductivity type epitaxial layer, and after selectively etching the thick oxide layer and the first conductivity type epitaxial layer, forming a first type trench and a second type trench;
在该步骤中，如图7所示，在N型外延层2的表面形成厚氧化层19，选择 性刻蚀厚氧化层19与N型外延层2，形成第一类沟槽3与第二类沟槽16。In this step, as shown in FIG. 7, a thick oxide layer 19 is formed on the surface of the N-type epitaxial layer 2, and the thick oxide layer 19 and the N-type epitaxial layer 2 are selectively etched to form the first-type trench 3 and the second-type groove. Groove-like 16.
S130、涂覆光刻胶后选择性保留部分光刻胶，以第一角度在所述第一类沟槽的侧部区域与底部区域注入第一导电类型杂质或第二导电类型杂质，形成第一导电类型阱区；S130. Selectively retain part of the photoresist after coating the photoresist, and inject impurities of the first conductivity type or impurities of the second conductivity type into the side region and the bottom region of the trench of the first type at a first angle to form a second type of trench. a conductivity type well region;
在该步骤中，如图8所示，涂覆光刻胶后选择性保留部分光刻胶20，然后以第一角度a(该实施例中，图8所示的第一角度a具体可以为17°)的角度在第一类沟槽3的侧壁与底部注入N型杂质，形成N型阱区4。In this step, as shown in FIG. 8 , after coating the photoresist, a part of the photoresist 20 is selectively retained, and then at a first angle a (in this embodiment, the first angle a shown in FIG. 8 can specifically be 17°) to implant N-type impurities into the sidewall and bottom of the first-type trench 3 to form an N-type well region 4 .
具体地，所述涂覆光刻胶后选择性保留部分光刻胶，以第一角度在所述第一类沟槽的侧部区域与底部区域均注入第一导电类型杂质或第二导电类型杂质，形成第一导电类型阱区，包括：Specifically, after the coating of the photoresist, a part of the photoresist is selectively retained, and impurities of the first conductivity type or the second conductivity type are injected into the side region and the bottom region of the first type trench at a first angle. Impurities to form a well region of the first conductivity type, including:
涂覆光刻胶后选择性保留部分光刻胶，以第一角度在所述第一类沟槽的侧部区域与底部区域注入第一导电类型杂质，形成第一导电类型阱区，所述第一导电类型阱区分布区域包括所述第二类通孔下方且包覆所述第一类沟槽的侧部区域和底部区域，所述第一导电类型阱区内的第一导电类型杂质的浓度高于所述第一导电类型外延层内的第一导电类型杂质的浓度；或者，After coating the photoresist, selectively retaining part of the photoresist, injecting impurities of the first conductivity type into the side region and the bottom region of the first type trench at a first angle to form a well region of the first conductivity type, the The distribution area of the well region of the first conductivity type includes the side region and the bottom region under the second type through hole and covering the trench of the first type, and the first conductivity type impurity in the well region of the first conductivity type The concentration is higher than the concentration of the first conductivity type impurity in the first conductivity type epitaxial layer; or,
涂覆光刻胶后选择性保留部分光刻胶，以第一角度在所述第一类沟槽的侧部区域与底部区域均注入第二导电类型杂质，形成第一导电类型阱区，所述第一导电类型阱区分布区域包括，在与所述第一类沟槽平行的方向上，所述第二类通孔与所述第二类沟槽之间的所述第一类沟槽的侧部区域与底部区域，相邻第二类通孔之间的第一类沟槽的侧部区域与底部区域，以及第二类沟槽的侧部区域与底部区域，所述第一导电类型阱区内的第一导电类型杂质的浓度低于所述第一导电类型外延层内的第一导电类型杂质的浓度。After coating the photoresist, selectively retaining part of the photoresist, injecting impurities of the second conductivity type into both the side region and the bottom region of the trench of the first type at a first angle to form a well region of the first conductivity type. The distribution region of the well region of the first conductivity type includes, in a direction parallel to the first type of trench, the first type of trench between the second type of through hole and the second type of trench The side area and the bottom area of the first type of trench between the adjacent second type of through hole, and the side area and the bottom area of the second type of trench, the first conductive The concentration of the impurity of the first conductivity type in the type well region is lower than the concentration of the impurity of the first conductivity type in the epitaxial layer of the first conductivity type.
应当理解的是，为了形成图2至图5所示结构，以第一角度a在所述第一类沟槽3的侧部区域与底部区域均注入N型杂质，形成N型阱区4，所述N型阱区4分布在所述第二类通孔14下方且包覆所述第一类沟槽3的侧部区域和底部区域，所述N型阱区4内的N型杂质的浓度高于所述N型外延层2内的N型杂质的浓度。优选地，所述N型阱区4内的N型杂质的浓度为所述N型外延层2内的N型杂质的浓度的1.01倍至5倍。It should be understood that, in order to form the structures shown in FIGS. 2 to 5 , N-type impurities are implanted into both the side region and the bottom region of the first-type trench 3 at a first angle a to form an N-type well region 4 , The N-type well region 4 is distributed under the second-type through hole 14 and covers the side region and the bottom region of the first-type trench 3, and the N-type impurity in the N-type well region 4 The concentration is higher than the concentration of N-type impurities in the N-type epitaxial layer 2 . Preferably, the concentration of N-type impurities in the N-type well region 4 is 1.01 to 5 times the concentration of N-type impurities in the N-type epitaxial layer 2 .
为了形成图21至图24所示结构，以第一角度a在所述第一类沟槽3的侧部区域与底部区域均注入P型杂质(此处应当理解的是，该方式是通过注入P型杂质以中和N型杂质的方式来降低N型杂质的浓度)，形成N型阱区4，所述N型阱区4分布在所述第一类通孔15下方且包覆所述第一类沟槽3的侧部区域和底部区域，以及分布在所述第二类沟槽16的周围且包覆所述第二类沟槽16的侧部区域和底部区域，所述N型阱区4内的N型杂质的浓度低于所述N型外延层2内的第一导电类型杂质的浓度。优选地，所述N型外延层2内的第一导电类型杂质的浓度为所述第一导电类型阱区4内的第一导电类型杂质的浓度的1.01倍至5倍。In order to form the structures shown in Figures 21 to 24, P-type impurities are implanted in the side region and the bottom region of the first type trench 3 at a first angle a (it should be understood here that this method is achieved by implanting The P-type impurity reduces the concentration of the N-type impurity by neutralizing the N-type impurity), forming an N-type well region 4, and the N-type well region 4 is distributed under the first type of through hole 15 and covers the The side area and the bottom area of the first type trench 3, and the side area and the bottom area distributed around the second type trench 16 and covering the second type trench 16, the N type The concentration of the N-type impurity in the well region 4 is lower than the concentration of the first conductivity type impurity in the N-type epitaxial layer 2 . Preferably, the concentration of the impurity of the first conductivity type in the N-type epitaxial layer 2 is 1.01 to 5 times the concentration of the impurity of the first conductivity type in the well region 4 of the first conductivity type.
优选地，所述第一角度a的取值范围在0°～60°之间。Preferably, the value range of the first angle a is between 0° and 60°.
S140、去除光刻胶与厚氧化层后，在第一导电类型外延层的表面、第一类 沟槽的底部区域及侧部区域以及第二类沟槽的底部区域及侧部区域均形成场氧层；S140. After removing the photoresist and the thick oxide layer, a field is formed on the surface of the epitaxial layer of the first conductivity type, the bottom region and the side region of the first type trench, and the bottom region and side region of the second type trench Oxygen layer;
在该步骤中，如图9所示，去除光刻胶20与厚氧化层19；如图10所示，在N型外延层2的表面、第一类沟槽3与第二类沟槽16的底部与侧壁形成场氧层6。In this step, as shown in FIG. 9, the photoresist 20 and the thick oxide layer 19 are removed; as shown in FIG. The bottom and sidewalls form the field oxygen layer 6.
S150、分别在所述第一类沟槽与第二类沟槽内形成第一类导电多晶硅；S150, forming a first type of conductive polysilicon in the first type of trench and the second type of trench respectively;
在该步骤中，如图11所示，淀积导电多晶硅填满第一类沟槽3与第二类沟槽16，然后刻蚀导电多晶硅，在第一类沟槽3与第二类沟槽16内形成第一类导电多晶硅5。In this step, as shown in FIG. 11, conductive polysilicon is deposited to fill up the first-type trench 3 and the second-type trench 16, and then the conductive polysilicon is etched, and the first-type trench 3 and the second-type trench 16 are etched. The first type of conductive polysilicon 5 is formed in 16 .
S160、选择性刻蚀第一类沟槽内的部分导电多晶硅后，在刻蚀后的区域内形成第一类绝缘介质层；S160. After selectively etching part of the conductive polysilicon in the first-type trench, a first-type insulating dielectric layer is formed in the etched area;
在该步骤中，如图12所示，选择性刻蚀第一类沟槽3内的上半部分导电多晶硅；如图13所示，淀积绝缘介质层填充满第一类沟槽3的上半部分；如图14所示，去除N型外延层2上方的绝缘介质层；如图15所示，选择性刻蚀第一类沟槽3内的部分绝缘介质层，形成第一类绝缘介质7。In this step, as shown in FIG. 12, the upper half of the conductive polysilicon in the first type trench 3 is selectively etched; as shown in FIG. 13, an insulating dielectric layer is deposited to fill the top half of the first type trench 3. half; as shown in Figure 14, remove the insulating dielectric layer above the N-type epitaxial layer 2; as shown in Figure 15, selectively etch part of the insulating dielectric layer in the first type of trench 3 to form the first type of insulating dielectric 7.
S170、在第一类沟槽内形成栅氧层，以及在第一类沟槽内的第一类绝缘介质层上形成第二类导电多晶硅；S170, forming a gate oxide layer in the first type of trench, and forming a second type of conductive polysilicon on the first type of insulating dielectric layer in the first type of trench;
在该步骤中，如图16所示，在第一类沟槽3内形成栅氧层9；如图17所示，淀积导电多晶硅填充满第一类沟槽3的上半部分，然后刻蚀导电多晶硅，在第一类沟槽3的上半部分形成第二类导电多晶硅8。In this step, as shown in FIG. 16, a gate oxide layer 9 is formed in the first type trench 3; as shown in FIG. 17, conductive polysilicon is deposited to fill the upper half of the first type trench 3, and then the The conductive polysilicon is etched to form the second type conductive polysilicon 8 in the upper half of the first type trench 3 .
S180、依次形成第二导电类型体区和第一导电类型源区；S180, sequentially forming a body region of the second conductivity type and a source region of the first conductivity type;
在该步骤中，如图18所示，在器件表面注入P型杂质后退火形成P型体区10，然后选择性注入N型杂质，激活后形成N型源区11。In this step, as shown in FIG. 18 , P-type impurities are implanted on the surface of the device and annealed to form a P-type body region 10 , and then N-type impurities are selectively implanted to form an N-type source region 11 after activation.
S190、淀积绝缘介质，形成第二类绝缘介质层；S190, depositing an insulating medium to form a second type insulating medium layer;
在该步骤中，如图19所示，淀积绝缘介质，在器件表面形成第二类绝缘介质12。In this step, as shown in FIG. 19 , an insulating medium is deposited to form a second type of insulating medium 12 on the surface of the device.
S200、选择性刻蚀第二类绝缘介质层、第一导电类型源区、第二导电类型体区、第一类导电多晶硅与第二类导电多晶硅后，形成第一类通孔、第二类通孔和第三类通孔；S200. After selectively etching the second-type insulating dielectric layer, the first-conductivity-type source region, the second-conductivity-type body region, the first-type conductive polysilicon, and the second-type conductive polysilicon, form a first-type via hole and a second-type through hole. Through-holes and third-type through-holes;
在该步骤中，如图20所示，选择性刻蚀第二类绝缘介质12、N型外延层2、第一类导电多晶硅5与第二类导电多晶硅8，形成第一类通孔15、第二类通孔14和第三类通孔18。In this step, as shown in FIG. 20, the second type of insulating dielectric 12, the N-type epitaxial layer 2, the first type of conductive polysilicon 5 and the second type of conductive polysilicon 8 are selectively etched to form the first type of through holes 15, The second type of through hole 14 and the third type of through hole 18 .
S210、形成源极金属与栅极金属。S210 , forming a source metal and a gate metal.
在该步骤中，如图2、图5、图21和图24所示，在器件表面淀积金属后，选择性刻蚀金属形成源极金属13与栅极金属17。In this step, as shown in FIG. 2 , FIG. 5 , FIG. 21 and FIG. 24 , after depositing metal on the surface of the device, the metal is selectively etched to form source metal 13 and gate metal 17 .
综上，本发明实施例提供的功率半导体器件的制作方法，通过形成第一导电类型阱区，避免了器件在终端与过渡区位置有大电流的聚集，使得终端与过渡区不受伤害，这样提升了器件短路工作模式下的可靠性，同时提升了器件的短路能力。另外，本发明实施例提供的制作方法还具有工艺简单、成本低廉， 且与现有工艺兼容的优势。To sum up, the manufacturing method of the power semiconductor device provided by the embodiment of the present invention avoids the accumulation of large current in the position of the terminal and the transition region of the device by forming the well region of the first conductivity type, so that the terminal and the transition region are not damaged. The reliability in the short-circuit working mode of the device is improved, and the short-circuit capability of the device is improved at the same time. In addition, the manufacturing method provided by the embodiment of the present invention has the advantages of simple process, low cost, and compatibility with existing processes.
关于本发明实施例提供的功率半导体器件的制作方法的原理可以参照前文的功率半导体器件的描述，此处不再赘述。For the principle of the manufacturing method of the power semiconductor device provided by the embodiment of the present invention, reference may be made to the foregoing description of the power semiconductor device, which will not be repeated here.
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。It can be understood that, the above embodiments are only exemplary embodiments adopted for illustrating the principle of the present invention, but the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also regarded as the protection scope of the present invention.

Claims (10)

  1. 一种功率半导体器件，其特征在于，包括：A power semiconductor device, characterized in that it comprises:
    第一导电类型衬底，所述第一导电类型衬底上设置第一导电类型外延层，所述第一导电类型外延层的上表面设置朝向所述第一导电类型外延层内部延伸的至少一条第二类沟槽和多条第一类沟槽，多条第一类沟槽之间相互平行且间隔设置，所述第二类沟槽环绕第一类沟槽设置；A first conductivity type substrate, a first conductivity type epitaxial layer is disposed on the first conductivity type substrate, and at least one strip extending toward the inside of the first conductivity type epitaxial layer is disposed on the upper surface of the first conductivity type epitaxial layer a second type of groove and a plurality of first type grooves, the plurality of first type grooves are arranged parallel to each other and at intervals, and the second type of groove is arranged around the first type of groove;
    每条第一类沟槽的部分槽段的内部全部填充第一类导电多晶硅，所述第一类导电多晶硅与所述第一导电类型外延层之间设置由绝缘介质构成的场氧层，在所述第一类沟槽的上方均设置第二类绝缘介质层，所述第二类绝缘介质层的上方设置源极金属，所述源极金属通过位于所述第二类绝缘介质层内的第一类通孔与位于所述第一类沟槽内的所述第一类导电多晶硅欧姆接触；The interior of some groove segments of each first-type trench is completely filled with first-type conductive polysilicon, and a field oxygen layer composed of an insulating medium is arranged between the first-type conductive polysilicon and the first-conductivity-type epitaxial layer. A second-type insulating dielectric layer is arranged above the first-type trenches, a source metal is arranged above the second-type insulating dielectric layer, and the source metal passes through the A first type of via hole is in ohmic contact with the first type of conductive polysilicon located in the first type of trench;
    每条第一类沟槽的部分槽段的内部部分填充第一类导电多晶硅，在所述第一类导电多晶硅的上方填充第二类导电多晶硅，所述第二类导电多晶硅与所述第一类导电多晶硅之间填充第一类绝缘介质层，所述第二类导电多晶硅与所述第一导电类型外延层之间设置栅氧层，每相邻两条第一类沟槽之间的第一类导电类型外延层的上表面设置第二导电类型体区，部分所述第二导电类型体区的上表面设置第一导电类型源区，所述第一类沟槽与所述第一导电类型源区的上方均设置第二类绝缘介质层，部分所述第二类绝缘介质层的上方设置源极金属，所述源极金属通过位于所述第二类绝缘介质层内的第二类通孔分别与所述第一导电类型源区和第二导电类型体区欧姆接触；The inner part of part of the groove segment of each first-type trench is filled with the first-type conductive polysilicon, and the second-type conductive polysilicon is filled above the first-type conductive polysilicon, and the second-type conductive polysilicon and the first-type conductive polysilicon are filled. A first-type insulating dielectric layer is filled between the conductive polysilicon, a gate oxide layer is provided between the second-type conductive polysilicon and the first-conductive-type epitaxial layer, and the first-type trench between every two adjacent first-type trenches A second conductivity type body region is provided on the upper surface of one type of conductivity type epitaxial layer, and a first conductivity type source region is arranged on the upper surface of part of the second conductivity type body region, and the first type of trench and the first conductivity type A second-type insulating dielectric layer is arranged above the source regions of the second type, and a source metal is arranged above part of the second-type insulating dielectric layer, and the source metal passes through the second-type insulating dielectric layer located in the second-type insulating dielectric layer. The through holes are respectively in ohmic contact with the source region of the first conductivity type and the body region of the second conductivity type;
    所述第一导电类型外延层内设置第一导电类型阱区，所述第一导电类型阱区分布区域包括所述第二类通孔下方且包覆所述第一类沟槽的侧部区域和底部区域，所述第一导电类型阱区内的第一导电类型杂质的浓度高于所述第一导电类型外延层内的第一导电类型杂质的浓度；或者，A first conductivity type well region is provided in the first conductivity type epitaxial layer, and the distribution area of the first conductivity type well region includes a side region below the second type through hole and covering the first type trench and the bottom region, the concentration of the first conductivity type impurity in the first conductivity type well region is higher than the concentration of the first conductivity type impurity in the first conductivity type epitaxial layer; or,
    所述第一导电类型外延层内设置第一导电类型阱区，所述第一导电类型阱区分布区域包括，在与所述第一类沟槽平行的方向上，所述第二类通孔与所述第二类沟槽之间的所述第一类沟槽的侧部区域与底部区域，相邻第二类通孔之间的第一类沟槽的侧部区域与底部区域，以及第二类沟槽的侧部区域与底部区域，所述第一导电类型阱区内的第一导电类型杂质的浓度低于所述第一导电类型外延层内的第一导电类型杂质的浓度。A first conductivity type well region is provided in the first conductivity type epitaxial layer, and the distribution area of the first conductivity type well region includes, in a direction parallel to the first type trench, the second type through hole the side region and the bottom region of the first-type trench between the second-type trench, the side region and the bottom region of the first-type trench between adjacent second-type through holes, and In the side region and the bottom region of the second type trench, the concentration of the first conductivity type impurity in the first conductivity type well region is lower than the concentration of the first conductivity type impurity in the first conductivity type epitaxial layer.
  2. 根据权利要求1所述的功率半导体器件，其特征在于，所述第一导电类型外延层内设置第一导电类型阱区，所述第一导电类型阱区分布区域包括所述第二类通孔下方且包覆所述第一类沟槽的底部区域以及侧部区域；The power semiconductor device according to claim 1, wherein a well region of a first conductivity type is provided in the epitaxial layer of the first conductivity type, and the distribution area of the well region of the first conductivity type includes the through hole of the second type below and covering the bottom region and the side region of the first type of trench;
    所述第一导电类型阱区沿与所述第一类沟槽平行的方向上的边界均位于所述第二类通孔的下方，所述第一导电类外延层中靠近与所述第一类沟槽平行的第二类沟槽槽段的至少一条所述第一类沟槽的侧部区域和底部区域未分布所述第一导电类型阱区；The boundaries of the first conductivity type well region along the direction parallel to the first type trenches are all located below the second type of through holes, and the first conductivity type epitaxial layer is close to the first type of trench. The side region and the bottom region of at least one of the first-type trench segments of the second-type trench parallel to the similar-type trenches are not distributed with the first conductivity type well region;
    所述第一导电类型阱区内的第一导电类型杂质的浓度为所述第一导电类型 外延层内的第一导电类型杂质的浓度的1.01倍至5倍。The concentration of the impurity of the first conductivity type in the well region of the first conductivity type is 1.01 to 5 times the concentration of the impurity of the first conductivity type in the epitaxial layer of the first conductivity type.
  3. 根据权利要求1所述的功率半导体器件，其特征在于，所述第一导电类型阱区分布区域包括，在与所述第一类沟槽平行的方向上，所述第二类通孔与所述第二类沟槽之间的所述第一类沟槽的侧部区域与底部区域，相邻第二类通孔之间的第一类沟槽的侧部区域与底部区域，以及第二类沟槽的侧部区域与底部区域；The power semiconductor device according to claim 1, wherein the distribution region of the well region of the first conductivity type comprises, in a direction parallel to the trench of the first type, the through hole of the second type is connected to the through hole of the second type. The side region and the bottom region of the first type of groove between the second type of grooves, the side region and the bottom region of the first type of groove between the adjacent second type of through holes, and the second The side area and the bottom area of the groove-like;
    所述第一导电类型阱区沿与所述第一类沟槽平行的方向上的边界延伸至所述第二类通孔的下方的部分区域，所述第一导电类型外延层中靠近与所述第一类沟槽平行的第二类沟槽槽段的至少一条所述第一类沟槽的侧部区域和底部区域被所述第一导电类型阱区包覆；The well region of the first conductivity type extends along a boundary in a direction parallel to the trench of the first type to a partial region below the via hole of the second type, and the epitaxial layer of the first conductivity type is close to the The side region and the bottom region of at least one of the first-type trenches of the second-type trench segment parallel to the first-type trench are covered by the first-conductivity-type well region;
    所述第一导电类型外延层内的第一导电类型杂质的浓度为所述第一导电类型阱区内的第一导电类型杂质的浓度的1.01倍至5倍。The concentration of the first conductivity type impurity in the first conductivity type epitaxial layer is 1.01 to 5 times the concentration of the first conductivity type impurity in the first conductivity type well region.
  4. 根据权利要求1至3中任意一项所述的功率半导体器件，其特征在于，The power semiconductor device according to any one of claims 1 to 3, characterized in that,
    所述第二类沟槽的内部填充第一类导电多晶硅，所述第一类导电多晶硅与所述第一导电外延层之间设置场氧层，所述第二类沟槽上方设置所述第二类绝缘介质层，所述第二类绝缘介质层的上方设置源极金属，所述第二类沟槽内的第一类导电多晶硅通过位于所述第二类绝缘介质层内的第一类通孔与所述源极金属欧姆接触。The inside of the second-type trench is filled with first-type conductive polysilicon, a field oxygen layer is set between the first-type conductive polysilicon and the first conductive epitaxial layer, and the first-type conductive polysilicon is set above the second-type trench. The second type of insulating dielectric layer, the source metal is arranged above the second type of insulating dielectric layer, the first type of conductive polysilicon in the second type of trench passes through the first type of conductive polysilicon located in the second type of insulating dielectric layer A via is in ohmic contact with the source metal.
  5. 根据权利要求1至3中任意一项所述的功率半导体器件，其特征在于，与所述第一类沟槽平行的第二类沟槽槽段与相邻的第一类沟槽之间的第一导电类型外延层的表面设置第二导电类型体区，所述第二导电类型体区的上方设置第二类绝缘介质层，所述第二类绝缘介质层的上方设置源极金属，所述源极金属通过位于所述第二类绝缘介质层内的第二类通孔与所述第二导电类型体区欧姆接触。The power semiconductor device according to any one of claims 1 to 3, characterized in that, the distance between the second-type trench segment parallel to the first-type trench and the adjacent first-type trench A body region of a second conductivity type is provided on the surface of the epitaxial layer of the first conductivity type, a second-type insulating dielectric layer is arranged above the body region of the second conductivity type, and a source metal is arranged above the second-type insulating dielectric layer, so that The source metal is in ohmic contact with the body region of the second conductivity type through a second-type via hole located in the second-type insulating dielectric layer.
  6. 根据权利要求1至3中任意一项所述的功率半导体器件，其特征在于，每条所述第一类沟槽的上方设置第二类绝缘介质层，部分所述第二类绝缘介质层的上方设置栅极金属，所述栅极金属通过位于所述第二类绝缘介质层内的第三类通孔与所述第二类导电多晶硅欧姆接触。The power semiconductor device according to any one of claims 1 to 3, wherein a second-type insulating dielectric layer is arranged above each of the first-type trenches, and part of the second-type insulating dielectric layer A gate metal is arranged above, and the gate metal is in ohmic contact with the second-type conductive polysilicon through a third-type through hole located in the second-type insulating dielectric layer.
  7. 根据权利要求1至3中任意一项所述的功率半导体器件，其特征在于，所述功率半导体器件包括N型功率半导体器件和P型功率半导体器件，当所述功率半导体器件为所述N型功率半导体器件时，第一导电类型为N型，第二导电类型为P型，当所述功率半导体器件为所述P型半导体器件时，第一导电类型为P型，第二导电类型为N型。The power semiconductor device according to any one of claims 1 to 3, wherein the power semiconductor device includes an N-type power semiconductor device and a P-type power semiconductor device, and when the power semiconductor device is the N-type For a power semiconductor device, the first conductivity type is N-type, and the second conductivity type is P-type. When the power semiconductor device is the P-type semiconductor device, the first conductivity type is P-type, and the second conductivity type is N-type. type.
  8. 一种如权利要求1至7中任意一项所述的功率半导体器件的制作方法，其特征在于，包括：A method for manufacturing a power semiconductor device according to any one of claims 1 to 7, characterized in that it comprises:
    提供第一导电类型衬底，在所述第一导电类型衬底上生长第一导电类型外延层；providing a first conductivity type substrate on which a first conductivity type epitaxial layer is grown;
    在所述第一导电类型外延层的表面形成厚氧化层，选择性刻蚀厚氧化层与所述第一导电类型外延层后，形成第一类沟槽与第二类沟槽；forming a thick oxide layer on the surface of the first conductivity type epitaxial layer, and after selectively etching the thick oxide layer and the first conductivity type epitaxial layer, forming a first type trench and a second type trench;
    涂覆光刻胶后选择性保留部分光刻胶，以第一角度在所述第一类沟槽的侧部区域与底部区域注入第一导电类型杂质或第二导电类型杂质，形成第一导电类型阱区；Selectively retain part of the photoresist after coating the photoresist, and inject first conductivity type impurities or second conductivity type impurities into the side region and bottom region of the first type of trench at a first angle to form a first conductivity type trench. type well area;
    去除光刻胶与厚氧化层后，在第一导电类型外延层的表面、第一类沟槽的底部区域及侧部区域以及第二类沟槽的底部区域及侧部区域均形成场氧层；After removing the photoresist and the thick oxide layer, a field oxide layer is formed on the surface of the epitaxial layer of the first conductivity type, the bottom region and side regions of the first type of trenches, and the bottom region and side regions of the second type of trenches ;
    分别在所述第一类沟槽与第二类沟槽内形成第一类导电多晶硅；forming first-type conductive polysilicon in the first-type trench and the second-type trench respectively;
    选择性刻蚀第一类沟槽内的部分导电多晶硅后，在刻蚀后的区域内形成第一类绝缘介质层；After selectively etching part of the conductive polysilicon in the first-type trench, a first-type insulating dielectric layer is formed in the etched area;
    在第一类沟槽内形成栅氧层，以及在第一类沟槽内的第一类绝缘介质层上形成第二类导电多晶硅；forming a gate oxide layer in the first type of trench, and forming a second type of conductive polysilicon on the first type of insulating dielectric layer in the first type of trench;
    依次形成第二导电类型体区和第一导电类型源区；sequentially forming a body region of the second conductivity type and a source region of the first conductivity type;
    淀积绝缘介质，形成第二类绝缘介质层；Depositing an insulating medium to form a second type insulating medium layer;
    选择性刻蚀第二类绝缘介质层、第一导电类型源区、第二导电类型体区、第一类导电多晶硅与第二类导电多晶硅后，形成第一类通孔、第二类通孔和第三类通孔；After selectively etching the second-type insulating dielectric layer, the first-conductivity-type source region, the second-conductivity-type body region, the first-type conductive polysilicon and the second-type conductive polysilicon, the first-type via hole and the second-type through-hole are formed and the third type of through-hole;
    形成源极金属与栅极金属。Form source metal and gate metal.
  9. 根据权利要求8所述的制作方法，其特征在于，所述涂覆光刻胶后选择性保留部分光刻胶，以第一角度在所述第一类沟槽的侧部区域与底部区域注入第一导电类型杂质或第二导电类型杂质，形成第一导电类型阱区，包括：The manufacturing method according to claim 8, characterized in that, after the coating of the photoresist, a part of the photoresist is selectively retained, and injected into the side region and the bottom region of the first type of trench at a first angle. Impurities of the first conductivity type or impurities of the second conductivity type form a well region of the first conductivity type, including:
    涂覆光刻胶后选择性保留部分光刻胶，以第一角度在所述第一类沟槽的侧部区域与底部区域注入第一导电类型杂质，形成第一导电类型阱区，所述第一导电类型阱区分布区域包括所述第二类通孔下方且包覆所述第一类沟槽的侧部区域和底部区域，所述第一导电类型阱区内的第一导电类型杂质的浓度高于所述第一导电类型外延层内的第一导电类型杂质的浓度；或者，After coating the photoresist, selectively retaining part of the photoresist, injecting impurities of the first conductivity type into the side region and the bottom region of the first type trench at a first angle to form a well region of the first conductivity type, the The distribution area of the well region of the first conductivity type includes the side region and the bottom region under the second type through hole and covering the trench of the first type, and the first conductivity type impurity in the well region of the first conductivity type The concentration is higher than the concentration of the first conductivity type impurity in the first conductivity type epitaxial layer; or,
    涂覆光刻胶后选择性保留部分光刻胶，以第一角度在所述第一类沟槽的侧部区域与底部区域均注入第二导电类型杂质，形成第一导电类型阱区，所述第一导电类型阱区分布区域包括，在与所述第一类沟槽平行的方向上，所述第二类通孔与所述第二类沟槽之间的所述第一类沟槽的侧部区域与底部区域，相邻第二类通孔之间的第一类沟槽的侧部区域与底部区域，以及第二类沟槽的侧部区域与底部区域，，所述第一导电类型阱区内的第一导电类型杂质的浓度低于所述第一导电类型外延层内的第一导电类型杂质的浓度。After coating the photoresist, selectively retaining part of the photoresist, injecting impurities of the second conductivity type into both the side region and the bottom region of the trench of the first type at a first angle to form a well region of the first conductivity type. The distribution region of the well region of the first conductivity type includes, in a direction parallel to the first type of trench, the first type of trench between the second type of through hole and the second type of trench The side area and the bottom area of the first type of trench between the adjacent second type of through hole, and the side area and the bottom area of the second type of trench, the first The concentration of the first conductivity type impurity in the conductivity type well region is lower than the concentration of the first conductivity type impurity in the first conductivity type epitaxial layer.
  10. 根据权利要求8或9所述的制作方法，其特征在于，所述第一角度的取值范围在0°～60°之间。The manufacturing method according to claim 8 or 9, characterized in that, the value range of the first angle is between 0°-60°.
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