WO2023065672A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2023065672A1
WO2023065672A1 PCT/CN2022/095717 CN2022095717W WO2023065672A1 WO 2023065672 A1 WO2023065672 A1 WO 2023065672A1 CN 2022095717 W CN2022095717 W CN 2022095717W WO 2023065672 A1 WO2023065672 A1 WO 2023065672A1
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Prior art keywords
substrate
electrode layer
pixel circuit
display panel
transistor
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PCT/CN2022/095717
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English (en)
French (fr)
Inventor
许传志
谢正芳
王向前
Original Assignee
合肥维信诺科技有限公司
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Application filed by 合肥维信诺科技有限公司 filed Critical 合肥维信诺科技有限公司
Priority to KR1020237026106A priority Critical patent/KR20230121155A/ko
Publication of WO2023065672A1 publication Critical patent/WO2023065672A1/zh
Priority to US18/356,375 priority patent/US20240021148A1/en

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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10OLED displays
    • H10K59/12Active-matrix OLED [AMOLED] displays
    • H10K59/121Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10OLED displays
    • H10K59/12Active-matrix OLED [AMOLED] displays
    • H10K59/121Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10OLED displays
    • H10K59/12Active-matrix OLED [AMOLED] displays
    • H10K59/122Pixel-defining structures or layers, e.g. banks
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10OLED displays
    • H10K59/12Active-matrix OLED [AMOLED] displays
    • H10K59/131Interconnections, e.g. wiring lines or terminals
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30Devices specially adapted for multicolour light emission
    • H10K59/35Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H10K59/65OLEDs integrated with inorganic image sensors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80Constructional details
    • H10K59/805Electrodes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80Constructional details
    • H10K59/805Electrodes
    • H10K59/8051Anodes
    • H10K59/80515Anodes characterised by their shape
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00Aspects of the constitution of display devices
    • G09G2300/04Structural and physical details of display devices
    • G09G2300/0421Structural details of the set of electrodes
    • G09G2300/0426Layout of electrodes and connections
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element

Definitions

  • the present application belongs to the field of display technology, and in particular relates to a display panel and a display device.
  • a light-transmitting display area can be provided on the display panel, and a photosensitive component can be arranged on the back of the light-transmitting display area.
  • Embodiments of the present application provide a display panel and a display device, which can improve the light transmittance of the light transmittance display area.
  • an embodiment of the present application provides a display panel.
  • the display panel has a first display area and a second display area.
  • the light transmittance of the first display area is higher than the light transmittance of the second display area.
  • the display panel includes: The substrate includes the substrate and the first pixel circuit arranged in the first display area, the first pixel circuit includes more than two driving elements; the light emitting device layer is arranged on the substrate, and the light emitting device layer includes the first pixel circuit arranged in the first display area A sub-pixel, the first sub-pixel includes a first electrode layer, a first light-emitting layer and a second electrode layer; at least part of the first pixel circuit is used to drive more than two first sub-pixels, two of the first pixel circuit
  • the driving elements above are scattered and distributed in the area covered by at least part of the first sub-pixel driven by the first pixel circuit, and the orthographic projection of the first electrode layer on the substrate covers the orthographic projection of the driving element on the substrate.
  • an embodiment of the present application provides a display device, including the display panel of the first aspect.
  • Embodiments of the present application provide a display panel and a display device.
  • the display panel has a first display area and a second display area.
  • the driving elements in the first pixel circuit for driving the first sub-pixel in the first display area may be scattered and distributed in the area covered by at least part of the first sub-pixel driven by the first pixel circuit, and the first sub-pixel of the first sub-pixel
  • the orthographic projection of an electrode layer on the substrate covers the orthographic projection of the driving element on the substrate, so as to avoid the shading of the light by the driving element in the first pixel circuit, reduce the light-shielding area of the first display area, and improve the first display
  • the area is the light transmittance of the light-transmitting display area.
  • FIG. 1 is a schematic top view of a display panel provided by an embodiment of the present application.
  • FIG. 2 is a schematic top view of a display panel provided by another embodiment of the present application.
  • Fig. 3 is a simple sectional view of an example of A-A direction in Fig. 1;
  • FIG. 4 is a schematic structural diagram of an example of a first pixel circuit in an embodiment of the present application.
  • Fig. 5 is a simple schematic diagram of partial enlargement of an example of the Q1 region in Fig. 1;
  • Fig. 6 is a simplified schematic diagram of partial enlargement of another example of the Q1 region in Fig. 1;
  • FIG. 7 is a partially enlarged schematic diagram of an example of the area Q3 in FIG. 6 .
  • a light-transmitting display area can be provided on the display panel, and the above-mentioned photosensitive component is arranged on the back of the light-transmitting display area, so that the full-screen display of the display panel can be realized on the basis of ensuring the normal operation of the photosensitive component.
  • the light-transmitting display area needs to have good light-transmitting performance.
  • the pixel circuits of the sub-pixels in the light-transmitting display area will adversely affect the light-transmitting properties of the light-transmitting display area, thereby adversely affecting the functions of the light-transmitting display area, thereby reducing the performance of the display panel.
  • the embodiment of the present application provides a display panel and a display device, which can improve the light transmittance of the light-transmitting display area when the pixel circuits of the sub-pixels in the light-transmitting display area are arranged in the light-transmitting display area, so as to ensure the display panel performance.
  • FIG. 1 is a schematic top view of a display panel provided by an embodiment of the present application.
  • the display panel has a display area AA and a non-display area NA.
  • the display area AA includes a first display area AA1 and a second display area AA2, that is, the display panel has a first display area AA1 and a second display area AA2.
  • the second display area AA2 surrounds at least part of the first display area AA1.
  • the light transmittance of the first display area AA1 is higher than the light transmittance of the second display area AA2, and the first display area AA1 is a light-transmissive display area.
  • the light transmittance of the first display area AA1 may be greater than or equal to 15%, even greater than 40%, or have a higher light transmittance.
  • the light transmittance of the first display area AA1 is greater than the light transmittance of the second display area AA2, so that the display panel can integrate photosensitive components on the back of the first display area AA1, and at the same time, the first display area AA1 can also display pictures, improving the display panel.
  • the screen-to-body ratio realizes the full-screen design of the display panel.
  • the first display area in the above embodiments may include a first area and a second area.
  • FIG. 2 is a schematic top view of a display panel provided by another embodiment of the present application.
  • the second display area AA2 may include a first area AA21 and a second area AA22 .
  • the first area AA21 is located between the second area AA22 and the first display area AA1.
  • the second area AA22 may surround at least a portion of the first area AA21.
  • the light transmittance of the first area AA21 is higher than that of the second area AA22.
  • the structure of the Q2 region shown in FIG. 2 is consistent with the structure of the Q1 region shown in FIG. 1 , and will not be repeated here.
  • FIG. 3 is a simplified cross-sectional view of an example along the direction A-A in FIG. 1 .
  • the display panel may include a substrate 11 and a light emitting device layer 12 .
  • the substrate 11 includes a substrate 111 and a first pixel circuit disposed in the first display area.
  • the layer where the first pixel circuit is located is marked as 112 in FIG. 3 .
  • the first pixel circuit can be used to drive the sub-pixels of the first display area.
  • the first pixel circuit includes more than two driving elements.
  • the driving element may include components such as transistors and capacitors, which are not limited herein.
  • the light emitting device layer 12 is disposed on the substrate 11 .
  • the light emitting device layer 12 includes first sub-pixels disposed in the first display area.
  • the first sub-pixel may include a red sub-pixel R, a green sub-pixel G and a blue sub-pixel B, which is not limited herein.
  • the first sub-pixel includes a first electrode layer 121 , a first light emitting layer 122 and a second electrode layer 123 .
  • the first electrode layer may include a pixel anode
  • the second electrode layer may include a pixel cathode.
  • the above-mentioned first pixel circuit can be used to drive the first sub-pixel.
  • at least part of the first pixel circuits can be used to drive more than two first sub-pixels, and the number of pixel circuits capable of driving more than two first sub-pixels is not limited here.
  • all first pixel circuits in the first display area can be used to drive more than two first sub-pixels.
  • a part of the first pixel circuits in the first display area is used to drive more than two first sub-pixels, and another part of the first pixel circuits is used to drive one first sub-pixel.
  • More than two driving elements of the first pixel circuit are scattered and distributed in the area covered by at least part of the first sub-pixel driven by the first pixel circuit, and the orthographic projection of the first electrode layer on the substrate covers the area of the driving element on the substrate. orthographic projection.
  • the driving element is distributed in the area covered by the first sub-pixel, and the orthographic projection of the first electrode layer on the substrate covers the orthographic projection of the driving element on the substrate, which can prevent the driving element of the first pixel circuit from blocking light, thereby improving the second pixel circuit.
  • the circuit structure of the first pixel circuit is not limited here.
  • the first pixel circuit may include any one of a 2T1C circuit, a 7T1C circuit, a 7T2C circuit, a 9T1C circuit and the like.
  • “2T1C circuit” refers to the pixel circuit including 2 thin film transistors (T) and 1 capacitor (C) in the pixel circuit, other "7T1C circuit”, “7T2C circuit”, “9T1C circuit” and so on.
  • FIG. 4 is a schematic structural diagram of an example of a first pixel circuit in an embodiment of the present application.
  • the driving elements in the first pixel circuit include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and The first capacitor C1.
  • the connection relationship between transistors and capacitors can be seen in FIG. 4 , which will not be repeated here.
  • the first end of the second transistor T2 is connected to the data signal line Data.
  • the control terminal of the second transistor T2 and the control terminal of the third transistor T3 are connected to the first scanning signal line S1.
  • the control end of the fourth transistor T4 is connected to the second scanning signal line S2.
  • the first terminal of the fifth transistor T5 and one terminal of the first capacitor C1 are connected to the power supply signal line VDD.
  • the control terminal of the fifth transistor T5 and the control terminal of the sixth transistor T6 are connected to the light emitting control signal line EM.
  • the control end of the seventh transistor T7 is connected to the third scanning signal line S3.
  • the first end of the seventh transistor T7 and the second end of the fourth transistor T4 are connected to the initialization signal line Vref.
  • FIG. 5 is a simplified schematic diagram of an example of a partially enlarged area of Q1 in FIG. 1 .
  • the structure of the first pixel circuit in the Q1 area is shown in FIG. 2 . It should be noted that what is shown in FIG. 5 is an emphasis on the description of the embodiment of the present application, and structures such as connecting wires are omitted.
  • the Q1 region may also have other structures, which are not limited here.
  • each first pixel circuit can drive six first sub-pixels, and the seven transistors and one capacitor in the first pixel circuit are scattered and distributed in the area covered by the six first sub-pixels driven by the first pixel circuit.
  • the Q1 area includes a plurality of first sub-pixels, and the first sub-pixels may include blue sub-pixels, red sub-pixels and green sub-pixels.
  • FIG. 5 shows a blue sub-pixel B, a red sub-pixel R, and a green sub-pixel G.
  • the first electrode layer E4 , the first electrode layer E5 , and the first electrode layer E6 correspond to the green sub-pixel G.
  • the first electrode layer E2 and the first electrode layer E3 correspond to the blue sub-pixel B.
  • the first electrode layer E1 corresponds to the red sub-pixel R.
  • the driving elements of the first pixel circuit include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and a A capacitor C1.
  • the first transistor T1 may be located between the first electrode layer E1 and the substrate and covered by the first electrode layer E1, that is, the orthographic projection of the first electrode layer E1 on the substrate covers the orthographic projection of the first transistor T1 on the substrate. projection.
  • the second transistor T2 can be located between the first electrode layer E2 and the substrate, and is covered by the first electrode layer E2, that is, the orthographic projection of the first electrode layer E2 on the substrate covers the orthographic projection of the second transistor T2 on the substrate. projection.
  • the third transistor T3 may be located between the first electrode layer E3 and the substrate and covered by the first electrode layer E3, that is, the orthographic projection of the first electrode layer E3 on the substrate covers the orthographic projection of the third transistor T3 on the substrate. projection.
  • the fourth transistor T4 and the seventh transistor T7 may be located between the first electrode layer E4 and the substrate and covered by the first electrode layer E4, that is, the orthographic projection of the first electrode layer E4 on the substrate covers the fourth transistor T4 and the seventh transistor T7. Orthographic projection of the seventh transistor T7 on the substrate.
  • the fifth transistor T5 and the sixth transistor T6 may be located between the first electrode layer E5 and the substrate and covered by the first electrode layer E5, that is, the orthographic projection of the first electrode layer E5 on the substrate covers the fifth transistor T5 and the sixth transistor T6. Orthographic projection of the sixth transistor T6 on the substrate.
  • the first capacitor C1 can be located between the first electrode layer E6 and the substrate, and is covered by the first electrode layer E6, that is, the orthographic projection of the first electrode layer E6 on the substrate covers the orthographic projection of the first capacitor C1 on the substrate. projection.
  • FIG. 6 is a partially enlarged schematic diagram of another example of the Q1 region in FIG. 1 .
  • the structure of the first pixel circuit in the Q1 area is shown in FIG. 3 . It should be noted that what is shown in FIG. 6 is the emphatic part of the embodiment of the present application, and structures such as connecting wires are omitted.
  • the Q1 region may also have other structures, which are not limited here.
  • each first pixel circuit can drive six first sub-pixels, and the seven transistors and one capacitor in the first pixel circuit are scattered and distributed in the area covered by the four first sub-pixels driven by the first pixel circuit.
  • the Q1 area includes a plurality of first sub-pixels, and the first sub-pixels may include blue sub-pixels, red sub-pixels and green sub-pixels.
  • FIG. 6 shows a blue sub-pixel B, a red sub-pixel R, and a green sub-pixel G.
  • the third electrode layer E3 and the fifth electrode layer E5 correspond to the green sub-pixel G.
  • the second electrode layer E2 and the fourth electrode layer E4 correspond to the blue sub-pixel B.
  • the first electrode layer E1 and the sixth electrode layer E6 correspond to the red sub-pixel R.
  • the first transistor T1, the second transistor T2, the third transistor T3 and the first capacitor C1 can be located between the first electrode layer E1 and the substrate, and covered by the first electrode layer E1, that is, the first electrode layer E1 is on the substrate
  • the fourth transistor T4 and the seventh transistor T7 may be located between the first electrode layer E3 and the substrate and covered by the first electrode layer E3, that is, the orthographic projection of the first electrode layer E3 on the substrate covers the fourth transistor T4 and the seventh transistor T7. Orthographic projection of the seventh transistor T7 on the substrate.
  • the fifth transistor T5 and the sixth transistor T6 may be located between the first electrode layer E4 and the substrate and covered by the first electrode layer E4, that is, the orthographic projection of the first electrode layer E4 on the substrate covers the fifth transistor T5 and the sixth transistor T6. Orthographic projection of the sixth transistor T6 on the substrate. No driving element is provided between the first electrode layer E2 and the substrate, between the first electrode layer E5 and the substrate, and between the first electrode layer E6 and the substrate.
  • the display panel has a first display area and a second display area.
  • the driving elements in the first pixel circuit for driving the first sub-pixel in the first display area may be scattered and distributed in the area covered by at least part of the first sub-pixel driven by the first pixel circuit, and the first sub-pixel of the first sub-pixel.
  • the orthographic projection of an electrode layer on the substrate covers the orthographic projection of the driving element on the substrate, so as to avoid the shading of the light by the driving element in the first pixel circuit, reduce the light-shielding area of the first display area, and improve the first display Transparency of the area.
  • the light transmittance of the first display area is improved, which can ensure the performance of the display panel with a full screen.
  • the orthographic projection of the first electrode layer of the first sub-pixel on the substrate covers the orthographic projection of the driving element on the substrate, the diffraction caused by the driving element of the first pixel circuit can also be reduced or even avoided, and the performance of the display panel can be improved. Show performance.
  • the driving elements in the above-mentioned first pixel circuit can be divided into M element groups, where M is an integer greater than 1.
  • the element group includes at least one drive element.
  • the number of driving elements in different element groups may be the same or different, which is not limited here.
  • the M element groups are provided in one-to-one correspondence with the M first electrode layers in the two or more first sub-pixels driven by the first pixel circuit. Specifically, the orthographic projection of an element group on the substrate is covered by the orthographic projection of a first electrode layer corresponding to the element group on the substrate.
  • the first transistor T1 forms an element group by itself
  • the second transistor T2 forms an element group by itself
  • the third transistor T3 forms an element group by itself
  • the fourth transistor T4 and the The seven transistors T7 jointly form an element group
  • the fifth transistor T5 and the sixth transistor T6 jointly form an element group
  • the first capacitor C1 forms an element group by itself.
  • the first transistor T1, the second transistor T2, the third transistor T3 and the first capacitor C1 together form an element group, and the fourth transistor T4 and the seventh transistor T7 jointly form an element group.
  • the fifth transistor T5 and the sixth transistor T6 jointly form an element group.
  • the driving element in the first pixel circuit includes a driving transistor.
  • the first transistor T1 in FIG. 4 is the driving transistor. Due to the large size of the driving transistor, in order to improve the light transmittance of the first display area and reduce the diffraction caused by the first pixel circuit, it is required that the orthographic projections of all the driving elements in the first pixel circuit on the substrate can be captured by the first pixel circuit.
  • the driving transistor can be separately arranged between a first electrode layer and the substrate, and drive the first pixel circuit
  • Other driving elements other than transistors are arranged between other first electrode layers and the substrate; or, small-sized devices such as driving transistors and capacitors are separately arranged between one first electrode layer and the substrate, and the first pixel Other driving elements in the circuit except small-scale devices such as driving transistors and capacitors are arranged between other first electrode layers and the substrate.
  • the drive transistor is located between the first target electrode layer and the substrate, and the orthographic projection of the first target electrode layer on the substrate covers the orthographic projection of the drive transistor on the substrate, where the first target electrode layer is the first
  • the driving element includes a driving transistor and a capacitor, the driving transistor and more than one capacitor are located between the second target electrode layer and the substrate, and the orthographic projection of the second target electrode layer on the substrate covers the driving transistor and the more than one capacitor
  • the second target electrode layer here is the first electrode layer of any one of the two or more first sub-pixels driven by the first pixel circuit, except for the driving transistor and the
  • the driving elements other than the one or more capacitors are located between other first electrode layers except the second target electrode layer and the substrate in the two or more first sub-pixels driven by the first pixel circuit.
  • the quantity of the capacitance between the second target electrode layer and the substrate with the driving transistor is set according to the structure of the first pixel circuit, the size of the device and the size of the first electrode layer, and is not limited here.
  • the driving elements connected to the same signal line in the first pixel circuit can be divided into the same element group. That is, one element group may include driving elements connected to the same signal line in the first pixel circuit.
  • the signal line is used to provide a signal for driving the first pixel circuit.
  • the signal lines may include one or more of the following: data signal lines, power supply signal lines, control light emitting signal lines, scanning signal lines, and initialization signal lines.
  • Data signal lines may be used to provide data signals.
  • the power supply signal line can be used to provide a power supply signal.
  • the control lighting signal line may be used to provide a control lighting signal.
  • Scanning signal lines may be used to provide scanning signals.
  • the initialization signal line may be used to provide an initialization signal.
  • the second transistor T2 and the third transistor T3 connected to the first scanning signal line S1 can be divided into an element group; the fifth transistor T5 and the sixth transistor T6 connected to the control light emitting signal line EM It can be divided into an element group; the fourth transistor T4 and the seventh transistor T7 connected to the initialization signal line Vref can be divided into an element group.
  • the driving elements connected to the same signal line are divided into one element group and arranged in the area covered by the same first sub-pixel, which is convenient for design and manufacture, and can simplify the difficulty of design and manufacture.
  • the display panel further includes connecting wires.
  • the connecting lines are located in the first display area.
  • the connecting wires can be used to connect different driving elements in the first pixel circuit, that is, the wirings electrically connected to the driving elements in the first pixel circuit belong to the connecting wires.
  • different drive elements do not mean different types of drive elements, but drive elements that are not the same drive element.
  • the first pixel circuit is shown in Figure 4, the second transistor T2 and the third transistor T3 in the same first pixel circuit are different driving elements, the third transistor T3 and the first capacitor C1 in the same first pixel circuit are different driving elements, and the two second transistors T2 in different first pixel circuits are also different driving elements.
  • the connecting wire can also be used to connect the driving element and the signal wire, that is, the wiring electrically connecting the driving element and the signal wire belongs to the connecting wire.
  • the connection line can also be used to connect the driving element and the first electrode layer, so as to transmit the driving signal generated by the first pixel circuit to the first electrode layer, and drive the first sub-pixel, that is, the wiring that electrically connects the driving element to the first electrode layer belongs to the connection line.
  • the above connecting wires may be metal wires or transparent wires, or may be partly metal wires and partly transparent wires, which are not limited herein.
  • the transparent traces may include but not limited to indium tin oxide traces, ie ITO traces.
  • connecting lines made of transparent materials can be used.
  • connection wire can be arranged on the same layer as the structure connected by the connection wire, or it can not be arranged on the same layer, and the electrical connection is realized through the via hole, which is not limited here.
  • the connecting lines may be arranged in three layers.
  • the driving element includes a transistor, and the connection line connected to the gate of the transistor can be arranged on the same layer as the gate of the transistor.
  • the connection wires connected to the signal wires may be arranged on the same layer as the signal wires.
  • some connection lines may be arranged on the same layer as data signal lines and power supply signal lines.
  • the connection wires connected to the first electrode layer may be provided on the same layer as the first electrode layer.
  • the connection line is arranged on the same layer as the structure connected by the connection line, which can further simplify the design and manufacture and reduce the difficulty of design and manufacture.
  • the connecting lines may include a first connecting line segment and a second connecting line segment.
  • the first connecting line segment is electrically connected to the second connecting line segment.
  • the orthographic projection of the first connecting line segment on the substrate is located within the orthographic projection of the first electrode layer on the substrate, and the orthographic projection of the second connecting line segment on the substrate is located outside the orthographic projection of the first electrode layer on the substrate. That is, the first connecting line segment may be within the area covered by the first sub-pixel, and the second connecting line segment may be outside the area covered by the first sub-pixel.
  • the orthographic projection of the first connecting line segment on the substrate is located within the orthographic projection of the first electrode layer on the substrate, which basically does not cause diffraction that affects the performance of the first display area, and the specific path of the first connecting line segment is not limited here. line, shape, etc.
  • the orthographic projection of the second connecting line segment on the substrate is outside the orthographic projection of the first electrode layer on the substrate.
  • the second connecting line segment can be set as an S-shaped trace.
  • the second connecting line segment can also be set as a transparent routing, so as to improve the light transmittance of the first display area and reduce the diffraction caused by the second connecting line segment.
  • the signal lines may include a first signal line segment and a second signal line segment.
  • the first signal line segment is electrically connected to the second signal line segment.
  • the orthographic projection of the first signal line segment on the substrate is located within the orthographic projection of the first electrode layer on the substrate, and the orthographic projection of the second signal line segment on the substrate is located outside the orthographic projection of the first electrode layer on the substrate. That is, the first signal line segment may be within the area covered by the first sub-pixel, and the second signal line segment may be outside the area covered by the first sub-pixel.
  • the orthographic projection of the first signal line segment on the substrate is located within the orthographic projection of the first electrode layer on the substrate, which basically does not cause diffraction that affects the performance of the first display area.
  • the specific path of the first signal line segment is not limited here. line, shape, etc.
  • the orthographic projection of the second signal line segment on the substrate is outside the orthographic projection of the first electrode layer on the substrate.
  • the second signal line segment can be set as an S-shaped trace.
  • the second signal line segment can also be set as a transparent line, so as to improve the light transmittance of the first display area and reduce the diffraction caused by the second signal line segment.
  • connection lines and signal lines can be located in the area covered by the first sub-pixel as much as possible.
  • signal lines may also be considered connection lines.
  • the signal line is connected to the driving elements in different first pixel circuits, that is, the signal line can be regarded as a connection line between different driving elements in different first pixel circuits.
  • connection lines between the signal lines can be regarded as the connection lines between the driving elements in different first pixel circuits.
  • FIG. 7 is a partially enlarged schematic diagram of an example of the area Q3 in FIG. 6 .
  • FIG. 7 shows the first transistor T1 to the seventh transistor T7 in two pixel circuits, and the first capacitor C1 , where T1 & C1 represent the first transistor T1 and the first capacitor C1 .
  • Figure 7 also shows the signal lines, which include data signal lines Data, power supply signal lines VDD, control light emission signal lines EM, scanning signal lines S1 to S3, and initialization signal lines Vref, wherein S2 & S3 represent scanning signal lines S2 and scanning Signal line S3.
  • FIG. 7 also shows the connection line 14 .
  • the connection line 14 can be connected to driving elements in different first pixel circuits, and can also be connected to different driving elements in the same pixel circuit.
  • the connecting line 14 may include a first connecting line segment 141 and a second connecting line segment 142, the orthographic projection of the first connecting line segment 141 on the substrate is located within the orthographic projection of the first electrode layer on the substrate, and the second connecting line segment 142 is located on the substrate.
  • the orthographic projection on the base lies outside the orthographic projection of the first electrode layer on the substrate.
  • the first connecting line segment 141 may be a straight line, an S-shaped line or other shaped lines, which is not limited herein.
  • the second connection line segment 142 can be an S-shaped line, so as to reduce or even eliminate the diffraction occurring in the first display area.
  • the present application also provides a display device.
  • the display device includes the display panel in the above-mentioned embodiments.
  • the display device may specifically be a mobile phone, a computer, a tablet computer, a TV, an electronic paper, and other devices with a display function, which are not limited herein.

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Abstract

本申请公开了一种显示面板及显示装置,属于显示技术领域。显示面板具有第一显示区和第二显示区,第一显示区的透光率高于第二显示区的透光率,显示面板包括:基板,包括衬底和设置于第一显示区的第一像素电路,第一像素电路包括两个以上的驱动元件;发光器件层,设置于基板,发光器件层包括设置于第一显示区的第一子像素,第一子像素包括第一电极层、第一发光层和第二电极层;至少部分的第一像素电路用于驱动两个以上的第一子像素,第一像素电路的两个以上驱动元件分散分布于第一像素电路驱动的至少部分第一子像素覆盖的区域,且第一电极层在衬底上的正投影覆盖驱动元件在衬底上的正投影。

Description

显示面板及显示装置
相关申请的交叉引用
本申请要求享有于2021年10月22日提交的名称为“显示面板及显示装置”的中国专利申请202111234915.5的优先权,该申请的全部内容通过引用并入本文中。
技术领域
本申请属于显示技术领域,尤其涉及一种显示面板及显示装置。
背景技术
随着显示技术的发展,显示面板的功能也随之增多。为了实现显示、拍摄、感光等功能,需要在显示面板集成摄像头、红外感光元件等感光组件。为了提高占屏比,可在显示面板上设置透光显示区,将感光组件设置在透光显示区背面。
为了保证感光组件能够正常工作,需要透光显示区的透光性更好,因此亟需一种能够提高透光显示区的透光性的显示面板。
发明内容
本申请实施例提供一种显示面板及显示装置,能够提高透光显示区的透光性。
第一方面,本申请实施例提供一种显示面板,显示面板具有第一显示区和第二显示区,第一显示区的透光率高于第二显示区的透光率,显示面板包括:基板,包括衬底和设置于第一显示区的第一像素电路,第一像素电路包括两个以上的驱动元件;发光器件层,设置于基板,发光器件层包括设置于第一显示区的第一子像素,第一子像素包括第一电极层、第一发光层和第二电极层;至少部分的第一像素电路用于驱动两个以上的第一子 像素,第一像素电路的两个以上驱动元件分散分布于第一像素电路驱动的至少部分第一子像素覆盖的区域,且第一电极层在衬底上的正投影覆盖驱动元件在衬底上的正投影。
第二方面,本申请实施例提供一种显示装置,包括第一方面的显示面板。
本申请实施例提供一种显示面板及显示装置,显示面板具有第一显示区和第二显示区。用于驱动第一显示区中第一子像素的第一像素电路中的驱动元件,可分散分布于该第一像素电路驱动的至少部分第一子像素覆盖的区域,且第一子像素的第一电极层在衬底上的正投影覆盖驱动元件在衬底上的正投影,以避免第一像素电路中的驱动元件对光线的遮挡,减小第一显示区的遮光面积,提高第一显示区即透光显示区的透光性。
附图说明
为了更清楚地说明本申请实施例的技术方案,下面将对本申请实施例中所需要使用的附图作简单的介绍,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1为本申请一实施例提供的显示面板的俯视示意图;
图2为本申请另一实施例提供的显示面板的俯视示意图;
图3为图1中A-A向的一示例的简易剖面图;
图4为本申请实施例中第一像素电路的一示例的结构示意图;
图5为图1中Q1区域的一示例的局部放大的简易示意图;
图6为图1中Q1区域的另一示例的局部放大的简易示意图;
图7为图6中Q3区域的一示例的局部放大的示意图。
具体实施方式
下面将详细描述本申请的各个方面的特征和示例性实施例,为了使本申请的目的、技术方案及优点更加清楚明白,以下结合附图及具体实施例,对本申请进行进一步详细描述。应理解,此处所描述的具体实施例仅意在解释本申请,而不是限定本申请。对于本领域技术人员来说,本申请 可以在不需要这些具体细节中的一些细节的情况下实施。下面对实施例的描述仅仅是为了通过示出本申请的示例来提供对本申请更好的理解。
随着显示技术的发展,用户对显示面板的屏占比要求越来越高。在诸如手机、平板电脑等显示装置上,需要在显示面板的一侧集成如前置摄像头、红外光传感器、接近光传感器等感光组件。可在显示面板上设置透光显示区,将上述感光组件设置在透光显示区背面,从而能够在保证感光组件正常工作的基础上,实现显示面板的全面屏显示。
为了保证感光组件能够正常工作,需要透光显示区具有良好的透光性能。而透光显示区内的子像素的像素电路会对透光显示区的透光性产生不良影响,从而对透光显示区的功能造成不良影响,进而降低了显示面板的性能。
本申请实施例提供一种显示面板及显示装置,能够在透光显示区内的子像素的像素电路设置在透光显示区内的情况下,提高透光显示区的透光性,以保证显示面板的性能。
图1为本申请一实施例提供的显示面板的俯视示意图。如图1所示,显示面板具有显示区AA和非显示区NA。显示区AA包括第一显示区AA1和第二显示区AA2,即显示面板具有第一显示区AA1和第二显示区AA2。
第二显示区AA2围绕第一显示区AA1的至少部分。第一显示区AA1的透光率高于第二显示区AA2的透光率,第一显示区AA1即为透光显示区。例如,第一显示区AA1的透光率可大于等于15%,甚至大于40%,或具有更高的透光率。第一显示区AA1的透光率大于第二显示区AA2的透光率,使得显示面板在第一显示区AA1的背面可以集成感光组件,同时第一显示区AA1还能够显示画面,提高显示面板的屏占比,实现显示面板的全面屏设计。
在一些示例中,上述实施例中的第一显示区可包括第一区域和第二区域。图2为本申请另一实施例提供的显示面板的俯视示意图。如图2所示,第二显示区AA2可包括第一区域AA21和第二区域AA22。第一区域AA21位于第二区域AA22和第一显示区AA1之间。第二区域AA22可包 围第一区域AA21的至少部分。第一区域AA21的透光率高于第二区域AA22的透光率。图2所示的Q2区域的结构与图1所示的Q1区域的结构一致,在此不再赘述。
图3为图1中A-A向的一示例的简易剖面图。如图3所示,显示面板可包括基板11和发光器件层12。
基板11包括衬底111和设置于第一显示区的第一像素电路。为了便于标示,第一像素电路所在的层在图3中标示为112。第一像素电路可用于驱动第一显示区的子像素。第一像素电路包括两个以上的驱动元件。在一些示例中,驱动元件可包括晶体管、电容等元器件,在此并不限定。
发光器件层12设置于基板11。发光器件层12包括设置于第一显示区的第一子像素。第一子像素可包括红色子像素R、绿色子像素G和蓝色子像素B,在此并不限定。第一子像素包括第一电极层121、第一发光层122和第二电极层123。在一些示例中,第一电极层可包括像素阳极,第二电极层可包括像素阴极。
上述第一像素电路可用于驱动第一子像素。在本申请实施例中,至少部分的第一像素电路可用于驱动两个以上的第一子像素,能够驱动两个以上的第一子像素的像素电路的数量在此并不限定。例如,第一显示区内的所有第一像素电路均可用于驱动两个以上的第一子像素。又例如,第一显示区内的一部分第一像素电路用于驱动两个以上的第一子像素,另一部分第一像素电路用于驱动一个第一子像素。
第一像素电路的两个以上的驱动元件分散分布于第一像素电路驱动的至少部分第一子像素覆盖的区域,且第一电极层在衬底上的正投影覆盖驱动元件在衬底上的正投影。驱动元件分布在第一子像素覆盖的区域,且第一电极层在衬底上的正投影覆盖驱动元件在衬底上的正投影,能够避免第一像素电路的驱动元件遮挡光线,从而提高第一显示区的透光性。
在此并不限定第一像素电路的电路结构。在一些示例中,第一像素电路可包括2T1C电路、7T1C电路、7T2C电路、9T1C电路等电路中的任意一种。其中,“2T1C电路”指像素电路中包括2个薄膜晶体管(T)和1个电容(C)的像素电路,其它“7T1C电路”、“7T2C电路”、“9T1C 电路”等依次类推。
为了便于理解,下面以第一像素电路为7T1C电路为例进行说明。图4为本申请实施例中第一像素电路的一示例的结构示意图。如图4所示,第一像素电路中的驱动元件包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7和第一电容C1。各晶体管和电容之间的连接关系可参见图4,在此不再赘述。
第二晶体管T2的第一端与数据信号线Data连接。第二晶体管T2的控制端、第三晶体管T3的控制端与第一扫描信号线S1连接。第四晶体管T4的控制端与第二扫描信号线S2连接。第五晶体管T5的第一端和第一电容C1的一端与供电信号线VDD连接。第五晶体管T5的控制端、第六晶体管T6的控制端与控制发光信号线EM连接。第七晶体管T7的控制端与第三扫描信号线S3连接。第七晶体管T7的第一端、第四晶体管T4的第二端与初始化信号线Vref连接。
在一些示例中,可将第一像素电路中的驱动元件分散分布在第一像素电路驱动的所有第一子像素覆盖的区域。图5为图1中Q1区域的一示例的局部放大的简易示意图。Q1区域中第一像素电路的结构如图2所示。需要说明的是,图5中示出的是本申请实施例着重说明的部分,省略了连接线等结构,Q1区域中还可具有其他结构,在此并不限定。这里以每个第一像素电路可驱动六个第一子像素,且第一像素电路中的七个晶体管和一个电容分散分布在该第一像素电路驱动的六个第一子像素覆盖的区域为例进行说明。Q1区域包括多个第一子像素,第一子像素可包括蓝色子像素、红色子像素和绿色子像素。图5示出了蓝色子像素B、红色子像素R和绿色子像素G。第一电极层E4、第一电极层E5、第一电极层E6与绿色子像素G对应。第一电极层E2和第一电极层E3与蓝色子像素B对应。第一电极层E1与红色子像素R对应。
如图5所示,第一像素电路的驱动元件包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7和第一电容C1。
第一晶体管T1可位于第一电极层E1与衬底之间,且被第一电极层E1覆盖,即第一电极层E1在衬底上的正投影覆盖第一晶体管T1在衬底上的正投影。第二晶体管T2可位于第一电极层E2与衬底之间,且被第一电极层E2覆盖,即第一电极层E2在衬底上的正投影覆盖第二晶体管T2在衬底上的正投影。第三晶体管T3可位于第一电极层E3与衬底之间,且被第一电极层E3覆盖,即第一电极层E3在衬底上的正投影覆盖第三晶体管T3在衬底上的正投影。第四晶体管T4和第七晶体管T7可位于第一电极层E4与衬底之间,且被第一电极层E4覆盖,即第一电极层E4在衬底上的正投影覆盖第四晶体管T4和第七晶体管T7在衬底上的正投影。第五晶体管T5和第六晶体管T6可位于第一电极层E5与衬底之间,且被第一电极层E5覆盖,即第一电极层E5在衬底上的正投影覆盖第五晶体管T5和第六晶体管T6在衬底上的正投影。第一电容C1可位于第一电极层E6与衬底之间,且被第一电极层E6覆盖,即第一电极层E6在衬底上的正投影覆盖第一电容C1在衬底上的正投影。
在另一些示例中,可将第一像素电路中的驱动元件分散分布在第一像素电路驱动的部分第一子像素覆盖的区域。图6为图1中Q1区域的另一示例的局部放大的简易示意图。Q1区域中第一像素电路的结构如图3所示。需要说明的是,图6中示出的是本申请实施例着重说明的部分,省略了连接线等结构,Q1区域中还可具有其他结构,在此并不限定。这里以每个第一像素电路可驱动六个第一子像素,且第一像素电路中的七个晶体管和一个电容分散分布在该第一像素电路驱动的四个第一子像素覆盖的区域为例进行说明。Q1区域包括多个第一子像素,第一子像素可包括蓝色子像素、红色子像素和绿色子像素。图6示出了蓝色子像素B、红色子像素R和绿色子像素G。第三电极层E3和第五电极层E5与绿色子像素G对应。第二电极层E2和第四电极层E4与蓝色子像素B对应。第一电极层E1和第六电极层E6与红色子像素R对应。
第一晶体管T1、第二晶体管T2、第三晶体管T3和第一电容C1可位于第一电极层E1与衬底之间,且被第一电极层E1覆盖,即第一电极层E1在衬底上的正投影覆盖第一晶体管T1、第二晶体管T2、第三晶体管T3 和第一电容C1在衬底上的正投影。第四晶体管T4和第七晶体管T7可位于第一电极层E3与衬底之间,且被第一电极层E3覆盖,即第一电极层E3在衬底上的正投影覆盖第四晶体管T4和第七晶体管T7在衬底上的正投影。第五晶体管T5和第六晶体管T6可位于第一电极层E4与衬底之间,且被第一电极层E4覆盖,即第一电极层E4在衬底上的正投影覆盖第五晶体管T5和第六晶体管T6在衬底上的正投影。第一电极层E2与衬底之间、第一电极层E5与衬底之间以及第一电极层E6与衬底之间并未设置驱动元件。
在本申请实施例中,显示面板具有第一显示区和第二显示区。用于驱动第一显示区中第一子像素的第一像素电路中的驱动元件,可分散分布于该第一像素电路驱动的至少部分第一子像素覆盖的区域,且第一子像素的第一电极层在衬底上的正投影覆盖驱动元件在衬底上的正投影,以避免第一像素电路中的驱动元件对光线的遮挡,减小第一显示区的遮光面积,提高第一显示区的透光性。第一显示区的透光性得到提高,能够保证全面屏的显示面板的性能。而且,由于第一子像素的第一电极层在衬底上的正投影覆盖驱动元件在衬底上的正投影,也能够减轻甚至避免第一像素电路的驱动元件引起的衍射,提高显示面板的显示性能。
在一些实施例中,上述第一像素电路中的驱动元件可划分为M个元件组,M为大于1的整数。元件组包括至少一个驱动元件。不同的元件组中的驱动元件的数量可以相同,也可以不同,在此并不限定。M个元件组与第一像素电路驱动的两个以上的第一子像素中的M个第一电极层一一对应设置。具体地,一个元件组在衬底上的正投影被该元件组对应的一个第一电极层在衬底上的正投影覆盖。
例如,在图5所示的第一像素电路中,第一晶体管T1自成一个元件组,第二晶体管T2自成一个元件组,第三晶体管T3自成一个元件组,第四晶体管T4和第七晶体管T7共同组成一个元件组,第五晶体管T5和第六晶体管T6共同组成一个元件组,第一电容C1自成一个元件组。
又例如,在图6所示的第一像素电路中,第一晶体管T1、第二晶体管T2、第三晶体管T3和第一电容C1共同组成一个元件组,第四晶体管T4 和第七晶体管T7共同组成一个元件组,第五晶体管T5和第六晶体管T6共同组成一个元件组。
在上述实施例中,第一像素电路中的驱动元件包括驱动晶体管。例如,图4中的第一晶体管T1即为驱动晶体管。由于驱动晶体管的尺寸较大,为了提高第一显示区的透光性,减轻第一像素电路带来的衍射,需要第一像素电路中所有驱动元件在衬底上的正投影均能被该第一像素电路驱动的第一子像素的第一电极层在衬底上的正投影覆盖,可将该驱动晶体管单独设置于一个第一电极层与衬底之间,将第一像素电路中除驱动晶体管之外的其他驱动元件设置于其他的第一电极层与衬底之间;或者,将驱动晶体管与电容等小尺寸器件单独设置于一个第一电极层与衬底之间,将第一像素电路中除驱动晶体管和电容等小尺寸器件之外的其他驱动元件设置于其他的第一电极层与衬底之间。
例如,驱动晶体管位于第一目标电极层与衬底之间,且第一目标电极层在衬底上的正投影覆盖驱动晶体管在衬底上的正投影,这里的第一目标电极层为第一像素电路驱动的两个以上的第一子像素中任意一个的第一电极层,第一像素电路中除驱动晶体管之外的其他驱动元件,位于第一像素电路驱动的两个以上的第一子像素中除第一目标电极层之外的其他第一电极层与衬底之间。或者,驱动元件包括驱动晶体管和电容,驱动晶体管和一个以上的电容位于第二目标电极层与衬底之间,且第二目标电极层在衬底上的正投影覆盖驱动晶体管和一个以上的电容在衬底上的正投影,这里的第二目标电极层为第一像素电路驱动的两个以上的第一子像素中的任意一个的第一电极层,第一像素电路中除驱动晶体管和这一个以上的电容之外的其他驱动元件,位于第一像素电路驱动的两个以上的第一子像素中除第二目标电极层之外的其他第一电极层与衬底之间。与驱动晶体管位于第二目标电极层与衬底之间的电容的数量根据第一像素电路结构、器件尺寸和第一电极层尺寸等设定,在此并不限定。
为了便于设计及制作,可将第一像素电路中与同一信号线连接的驱动元件划分至同一个元件组。即一个元件组可包括第一像素电路中与同一信号线连接的驱动元件。
信号线用于提供驱动第一像素电路的信号。在一些示例中,信号线可包括以下一项或两项以上:数据信号线、供电信号线、控制发光信号线、扫描信号线、初始化信号线。
数据信号线可用于提供数据信号。供电信号线可用于提供供电信号。控制发光信号线可用于提供控制发光信号。扫描信号线可用于提供扫描信号。初始化信号线可用于提供初始化信号。例如,如图4所示,与第一扫描信号线S1连接的第二晶体管T2和第三晶体管T3可划分为一个元件组;与控制发光信号线EM连接的第五晶体管T5和第六晶体管T6可划分为一个元件组;与初始化信号线Vref连接的第四晶体管T4和第七晶体管T7可划分为一个元件组。
与同一信号线连接的驱动元件划分为一个元件组,设置在同一第一子像素覆盖的区域,便于设计及制作,能够简化设计和制作难度。
在上述实施例中,显示面板还包括连接线。连接线位于第一显示区。连接线可用于连接第一像素电路中不同的驱动元件,即第一像素电路中驱动元件电连接的走线属于连接线。这里“不同的驱动元件”并不是指不同类型的驱动元件,而是指不是同一驱动元件的驱动元件。例如,第一像素电路如图4所示,同一第一像素电路中的第二晶体管T2与第三晶体管T3为不同的驱动元件,同一第一像素电路中的第三晶体管T3与第一电容C1为不同的驱动元件,不同第一像素电路中的两个第二晶体管T2也为不同的驱动元件。连接线还可用于连接驱动元件与信号线,即驱动元件与信号线电连接的走线属于连接线。连接线还可用于连接驱动元件与第一电极层,以将第一像素电路产生的驱动信号传输至第一电极层,驱动第一子像素,即驱动元件与第一电极层电连接的走线属于连接线。
上述连接线可为金属走线,也可为透明走线,也可部分为金属走线,部分为透明走线,在此并不限定。透明走线可包括但不限于氧化铟锡走线即ITO走线。为了进一步提高第一显示区的透光性,可采用透明材质的连接线。
连接线可与该连接线所连接的结构同层设置,也可非同层设置,通过过孔实现电连接,在此并不限定。
在一些示例中,连接线可分三层设置。驱动元件包括晶体管,与晶体管的栅极连接的连接线可与晶体管的栅极同层设置。与信号线连接的连接线可与该信号线同层设置。例如,部分连接线可与数据信号线、供电信号线同层设置。与第一电极层连接的连接线可与第一电极层同层设置。连接线与该连接线所连接的结构同层设置,可进一步简化设计和制作,降低设计和制作难度。
在一些实施例中,上述至少部分连接线可包括第一连接线段和第二连接线段。第一连接线段与第二连接线段电连接。第一连接线段在衬底上的正投影位于第一电极层在衬底上的正投影内,第二连接线段在衬底上的正投影位于第一电极层在衬底上的正投影外。即第一连接线段可在第一子像素覆盖的区域内,第二连接线段可在第一子像素覆盖的区域外。
第一连接线段在衬底上的正投影位于第一电极层在衬底上的正投影内,基本不会造成影响第一显示区性能的衍射,在此并不限定第一连接线段的具体走线方式、形状等。第二连接线段在在衬底上的正投影位于第一电极层在衬底上的正投影外,为了减轻因第二连接线段产生的衍射,可将第二连接线段设置为S型走线。进一步地,还可将第二连接线段设置为透明走线,以提高第一显示区的透光性以及减轻因第二连接线段产生的衍射。
在上述实施例中,上述至少部分信号线可包括第一信号线段和第二信号线段。第一信号线段与第二信号线段电连接。第一信号线段在衬底上的正投影位于第一电极层在衬底上的正投影内,第二信号线段在衬底上的正投影位于第一电极层在衬底上的正投影外。即第一信号线段可在第一子像素覆盖的区域内,第二信号线段可在第一子像素覆盖的区域外。
第一信号线段在衬底上的正投影位于第一电极层在衬底上的正投影内,基本不会造成影响第一显示区性能的衍射,在此并不限定第一信号线段的具体走线方式、形状等。第二信号线段在在衬底上的正投影位于第一电极层在衬底上的正投影外,为了减轻因第二信号线段产生的衍射,可将第二信号线段设置为S型走线。进一步地,还可将第二信号线段设置为透明走线,以提高第一显示区的透光性以及减轻因第二信号线段产生的衍 射。
为了尽量提高第一显示区的透光性以及减轻甚至消除第一显示区中出现的衍射,可尽量使连接线和信号线位于第一子像素覆盖的区域内。
在一些示例中,信号线也可视为连接线。例如,信号线与不同第一像素电路中的驱动元件连接,即该信号线可视为不同第一像素电路中不同驱动元件之间的连接线。
在另一些示例中,信号线之间的连接线可视为不同的第一像素电路中的驱动元件之间的连接线。例如,图7为图6中Q3区域的一示例的局部放大的示意图。图7示出了两个像素电路中的第一晶体管T1至第七晶体管T7,以及第一电容C1,其中,T1&C1表示第一晶体管T1和第一电容C1。图7还示出了信号线,信号线包括数据信号线Data、供电信号线VDD、控制发光信号线EM、扫描信号线S1至S3、初始化信号线Vref,其中,S2&S3表示扫描信号线S2和扫描信号线S3。图7还示出了连接线14。连接线14可连接不同第一像素电路中的驱动元件,也可连接同一像素电路中的不同驱动元件。连接线14可包括第一连接线段141和第二连接线段142,第一连接线段141在衬底上的正投影位于第一电极层在衬底上的正投影内,第二连接线段142在衬底上的正投影位于第一电极层在衬底上的正投影外。第一连接线段141可为直线走线、S型走线或其他形状的走线,在此并不限定。第二连接线段142可为S型走线,以减轻甚至消除第一显示区中出现的衍射。
本申请还提供一种显示装置。该显示装置包括上述实施例中的显示面板。关于显示面板的具体内容可参见上述实施例中的相关说明,能够实现上述实施例中显示面板的效果,在此不再赘述。显示装置具体可为手机、计算机、平板电脑、电视、电子纸等具有显示功能的装置,在此并不限定。
需要明确的是,本说明书中的各个实施例均采用递进的方式描述,各个实施例之间相同或相似的部分互相参见即可,每个实施例重点说明的都是与其他实施例的不同之处。对于显示装置实施例而言,相关之处可以参见显示面板实施例的说明部分。本申请并不局限于上文所描述并在图中示 出的特定结构。本领域的技术人员可以在领会本申请的精神之后,作出各种改变、修改和添加。并且,为了简明起见,这里省略对已知技术的详细描述。
本领域技术人员应能理解,上述实施例均是示例性而非限制性的。在不同实施例中出现的不同技术特征可以进行组合,以取得有益效果。本领域技术人员在研究附图、说明书及权利要求书的基础上,应能理解并实现所揭示的实施例的其他变化的实施例。在权利要求书中,术语“包括”并不排除其他装置或步骤;数量词“一个”不排除多个;术语“第一”、“第二”用于标示名称而非用于表示任何特定的顺序。权利要求中的任何附图标记均不应被理解为对保护范围的限制。权利要求中出现的多个部分的功能可以由一个单独的硬件或软件模块来实现。某些技术特征出现在不同的从属权利要求中并不意味着不能将这些技术特征进行组合以取得有益效果。

Claims (17)

  1. 一种显示面板,所述显示面板具有第一显示区和第二显示区,所述第一显示区的透光率高于所述第二显示区的透光率,所述显示面板包括:
    基板,包括衬底和设置于所述第一显示区的第一像素电路,所述第一像素电路包括两个以上的驱动元件;
    发光器件层,设置于所述基板,所述发光器件层包括设置于所述第一显示区的第一子像素,所述第一子像素包括第一电极层、第一发光层和第二电极层;
    至少部分的所述第一像素电路用于驱动两个以上的所述第一子像素,所述第一像素电路的所述两个以上的驱动元件分散分布于所述第一像素电路驱动的至少部分所述第一子像素覆盖的区域,且所述第一电极层在所述衬底上的正投影覆盖所述驱动元件在所述衬底上的正投影。
  2. 根据权利要求1所述的显示面板,其中,
    所述第一像素电路中的驱动元件划分为M个元件组,所述元件组包括至少一个驱动元件,M为大于1的整数;
    M个所述元件组与所述第一像素电路驱动的两个以上的所述第一子像素中的M个所述第一电极层一一对应设置。
  3. 根据权利要求1所述的显示面板,其中,
    所述驱动元件包括驱动晶体管,所述驱动晶体管位于第一目标电极层与所述衬底之间,且所述第一目标电极层在所述衬底上的正投影覆盖所述驱动晶体管在所述衬底上的正投影,所述第一目标电极层为所述第一像素电路驱动的两个以上的所述第一子像素中的任意一个的所述第一电极层;所述第一像素电路中除所述驱动晶体管之外的其他所述驱动元件,位于所述第一像素电路驱动的两个以上的所述第一子像素中除所述第一目标电极层之外的其他所述第一电极层与所述衬底之间。
  4. 根据权利要求1所述的显示面板,其中,
    所述驱动元件包括驱动晶体管和电容,所述驱动晶体管和一个以上的 所述电容位于第二目标电极层与所述衬底之间,且所述第二目标电极层在所述衬底上的正投影覆盖所述驱动晶体管和一个以上的所述电容在所述衬底上的正投影,所述第二目标电极层为所述第一像素电路驱动的两个以上的所述第一子像素中的任意一个的所述第一电极层;所述第一像素电路中除所述驱动晶体管和一个以上的所述电容之外的其他所述驱动元件,位于所述第一像素电路驱动的两个以上的所述第一子像素中除所述第二目标电极层之外的其他所述第一电极层与所述衬底之间。
  5. 根据权利要求2所述的显示面板,其中,一个所述元件组包括所述第一像素电路中与同一信号线连接的所述驱动元件,所述信号线用于提供驱动所述第一像素电路的信号。
  6. 根据权利要求1所述的显示面板,其中,所述显示面板还包括:
    连接线,位于所述第一显示区,用于连接所述第一像素电路中的不同的所述驱动元件,以及,用于连接所述驱动元件与信号线,以及,用于连接所述驱动元件与所述第一电极层,所述信号线用于提供驱动所述第一像素电路的信号。
  7. 根据权利要求6所述的显示面板,其中,
    所述驱动元件包括晶体管,与所述晶体管的栅极连接的所述连接线与所述晶体管的栅极同层设置。
  8. 根据权利要求6所述的显示面板,其中,
    与所述信号线连接的所述连接线与所述信号线同层设置。
  9. 根据权利要求6所述的显示面板,其中,
    与所述第一电极层连接的所述连接线与所述第一电极层同层设置。
  10. 根据权利要求6所述的显示面板,其中,
    所述连接线包括第一连接线段和第二连接线段,所述第一连接线段与所述第二连接线段电连接,所述第一连接线段在所述衬底上的正投影位于所述第一电极层在所述衬底上的正投影内,所述第二连接线段在所述衬底上的正投影位于所述第一电极层在所述衬底上的正投影外;
    所述第二连接线段为S型走线。
  11. 根据权利要求10所述的显示面板,其中,所述第二连接线段为 透明走线。
  12. 根据权利要求6所述的显示面板,其中,
    所述信号线包括第一信号线段和第二信号线段,所述第一信号线段与所述第二信号线段电连接,所述第一信号线段在所述衬底上的正投影位于所述第一电极层在所述衬底上的正投影内,所述第二信号线段在所述衬底上的正投影位于所述第一电极层在所述衬底上的正投影外;
    所述第二信号线段为S型走线。
  13. 根据权利要求12所述的显示面板,其中,所述第二信号线段为透明走线。
  14. 根据权利要求5所述的显示面板,其中,所述信号线包括以下一项或两项以上:
    数据信号线、供电信号线、控制发光信号线、扫描信号线、初始化信号线。
  15. 根据权利要求6所述的显示面板,其中,所述信号线包括以下一项或两项以上:
    数据信号线、供电信号线、控制发光信号线、扫描信号线、初始化信号线。
  16. 根据权利要求1所述的显示面板,其中,
    所述第二显示区包括第一区域和第二区域,所述第一区域位于所述第二区域和所述第一显示区之间,所述第一区域的透光率高于所述第二区域的透光率。
  17. 一种显示装置,包括如权利要求1至16中任意一项所述的显示面板。
PCT/CN2022/095717 2021-10-22 2022-05-27 显示面板及显示装置 WO2023065672A1 (zh)

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