WO2021238490A1 - 显示基板和显示装置 - Google Patents

显示基板和显示装置 Download PDF

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Publication number
WO2021238490A1
WO2021238490A1 PCT/CN2021/087545 CN2021087545W WO2021238490A1 WO 2021238490 A1 WO2021238490 A1 WO 2021238490A1 CN 2021087545 W CN2021087545 W CN 2021087545W WO 2021238490 A1 WO2021238490 A1 WO 2021238490A1
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WIPO (PCT)
Prior art keywords
light
display area
display
sub
layer
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PCT/CN2021/087545
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English (en)
French (fr)
Inventor
石博
黄炜赟
孙开鹏
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/626,149 priority Critical patent/US20220352285A1/en
Publication of WO2021238490A1 publication Critical patent/WO2021238490A1/zh
Priority to US17/857,257 priority patent/US20220344432A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/87—Arrangements for heating or cooling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
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    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
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    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
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    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
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    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H10K59/30—Devices specially adapted for multicolour light emission
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H10K59/65—OLEDs integrated with inorganic image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H10K59/80—Constructional details
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Definitions

  • the embodiment of the present disclosure relates to a display substrate and a display device.
  • the industry has proposed a solution called "under-screen camera” that combines a camera and a display panel into a display device.
  • the display device includes a display panel and a camera located below the display panel.
  • the area of the display device with the under-screen camera can emit light and display like other areas, and has a camera function at the same time.
  • At least one embodiment of the present disclosure provides a display substrate having a first side for display and a second side opposite to the first side, the display substrate including a display area, wherein the display area Comprising a first display area and a second display area at least partially surrounding the first display area, the first display area allowing light from the first side to be at least partially transmitted to the second side; the first The display area includes a plurality of first sub-pixels arranged in an array, each of the first sub-pixels includes a first light-emitting device, the second display area includes a plurality of first pixel circuits, and the plurality of first pixel circuits are respectively connected to The plurality of first light-emitting devices of the plurality of first sub-pixels are electrically connected to respectively drive the plurality of first light-emitting devices; wherein, the display area further includes a first light-shielding layer, which is perpendicular to the display substrate In the direction of the board surface, the first light shielding layer at least partially overlaps the second display area,
  • the display substrate provided by at least one embodiment of the present disclosure further includes a power line and a reset voltage line, wherein the first light shielding layer is electrically connected to the power line or the reset voltage line.
  • each of the plurality of first pixel circuits includes a first thin film transistor, and the first thin film transistor includes a first active layer, a first gate, and The first source and drain electrodes; the first light-shielding layer and the first source and drain electrodes are arranged in the same layer.
  • the second display area includes a first sub-area at least partially surrounding the first display area and a second sub-area at least partially surrounding the first sub-area ,
  • the first light-shielding layer is arranged in the first sub-region, and the plurality of first pixel circuits are arranged in the second sub-region.
  • the display substrate provided by at least one embodiment of the present disclosure further includes a plurality of signal lines respectively electrically connected to the plurality of first pixel circuits, the plurality of signal lines extend through the first sub-region, and the first
  • the pixel circuit also includes a first storage capacitor.
  • the first storage capacitor includes a first capacitor plate and a second capacitor plate.
  • the first capacitor plate and the first gate are arranged in the same layer.
  • the signal line is arranged in the same layer as the first capacitor plate or the second capacitor plate.
  • the display substrate provided by at least one embodiment of the present disclosure further includes a base substrate and a second light-shielding layer, wherein the plurality of first sub-pixels are disposed on the base substrate, and the second light-shielding layer is disposed on the base substrate.
  • the first light-shielding layer and the second light-shielding layer are arranged in the same layer.
  • the first light-shielding layer and the second light-shielding layer are integrated film layers continuously arranged, and the integrated film layer has The opening is opened so that in a direction perpendicular to the surface of the display substrate, the first light shielding layer does not overlap with the first display area.
  • the display substrate provided by at least one embodiment of the present disclosure further includes a base substrate and a heat dissipation layer, wherein the plurality of first sub-pixels are disposed on the first side of the base substrate, and the heat dissipation layer is disposed on the base substrate.
  • the first side and the second side are opposite; the first light shielding layer and the heat dissipation layer are provided in the same layer.
  • the first light-shielding layer and the heat dissipation layer are an integrated film layer continuously arranged, and the integrated film layer has an opening in the first display area, So that in a direction perpendicular to the surface of the display substrate, the first light shielding layer does not overlap with the first display area.
  • the second display area further includes a plurality of second sub-pixels, and each second sub-pixel includes a second light-emitting device and is electrically connected to the second light-emitting device.
  • the second pixel circuit is configured to drive the second light-emitting device, in the second display area, the plurality of second pixel circuits are arranged in a first array, and the plurality The first pixel circuit is arranged in the gap of the first array, and is arranged integrally with the plurality of second pixel circuits into a second array.
  • the first pixel circuit includes a first thin film transistor, and the first thin film transistor includes a first active layer, a first gate, and a first source and drain electrode
  • the first light-emitting device includes a first electrode, a second electrode, and a first light-emitting layer between the first electrode and the second electrode.
  • the first source and drain electrodes are electrically connected;
  • the second pixel circuit includes a second thin film transistor, and the second thin film transistor includes a second active layer, a second gate, and a second source and drain electrode.
  • the light-emitting device includes a first electrode, a second electrode, and a second light-emitting layer between the first electrode and the second electrode.
  • the source and drain electrodes are electrically connected; in the plane where the display substrate is located, the shortest distance between the first via hole and the light-emitting area of the first light-emitting layer is smaller than the light emission between the second via hole and the second light-emitting layer The shortest distance of the area.
  • the orthographic projection of the first via hole in the plane of the display substrate and the light-emitting area of the first light-emitting layer in the plane of the display substrate overlap at least partially.
  • the display area includes a third display area that at least partially surrounds the second display area, and the third display area includes a plurality of third sub-elements arranged in an array. Pixel, wherein the arrangement density of the plurality of third sub-pixels in the third display area is greater than the arrangement density of the plurality of first sub-pixels in the first display area, and is also greater than the arrangement density of the second sub-pixels in the first display area. The arrangement density of the plurality of second sub-pixels in the display area.
  • the arrangement density of the plurality of first sub-pixels in the first display area is equal to that of the plurality of second sub-pixels in the second display area. Arrangement density.
  • the display substrate provided by at least one embodiment of the present disclosure further includes a first scan driving circuit and a second scan driving circuit respectively located on opposite sides of the display area, wherein the first scan driving circuit and the second scan driving circuit
  • the circuits collectively provide electrical signals for a plurality of third sub-pixels in the third display area;
  • the first scan driving circuit is also a first scan driving circuit located on the side of the first display area close to the first scan driving circuit
  • the plurality of second sub-pixels and the plurality of first pixel circuits in the second display area provide electrical signals
  • the second scan driving circuit is also a second scan driving circuit located on the side of the first display area close to the second scan driving circuit.
  • the plurality of second sub-pixels and the plurality of first pixel circuits in the second display area provide electrical signals.
  • At least one embodiment of the present disclosure provides a display device including any one of the above-mentioned display substrates and a sensor, wherein the sensor is disposed on a second side of the display substrate, and the sensor is configured as Receive light from the first side.
  • the senor in a direction perpendicular to the surface of the display substrate, the sensor at least partially overlaps the first display area of the display substrate.
  • Fig. 1A is a schematic plan view of a display substrate
  • Fig. 1B is a partial enlarged schematic diagram of a display substrate
  • FIG. 2 is a schematic cross-sectional view of the display substrate in FIG. 1B along the line A-A;
  • FIG. 3 is a schematic plan view of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 4A is a partial enlarged schematic diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • 4B is a schematic diagram of an arrangement of sub-pixels in a first display area and a second display area in a display substrate provided by at least one embodiment of the present disclosure
  • FIG. 5 is a schematic plan view of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 6 is a schematic cross-sectional view of the display substrate in FIG. 5 along the line C-C;
  • FIG. 7 is a schematic plan view of a first display area and a part of a second display area in a display substrate provided by at least one embodiment of the present disclosure
  • FIG. 8 is another schematic plan view of the first display area and a part of the second display area in the display substrate provided by at least one embodiment of the present disclosure
  • FIG. 9 is a schematic cross-sectional view of the display substrate in FIG. 3 along the line B-B;
  • Fig. 10 is another schematic cross-sectional view of the display substrate in Fig. 3 along the line B-B;
  • FIG. 11 is a schematic plan view of a first light-shielding layer in a display substrate provided by at least one embodiment of the present disclosure
  • Fig. 12 is another schematic cross-sectional view of the display substrate in Fig. 3 along the line B-B;
  • FIG. 13 is a schematic cross-sectional view of a second display area in a display substrate provided by at least one embodiment of the present disclosure
  • FIG. 14 is a schematic diagram of an arrangement of seed pixels in a first display area in a display substrate provided by at least one embodiment of the present disclosure
  • 15 is a schematic diagram of an arrangement of seed pixels in a second display area in a display substrate provided by at least one embodiment of the present disclosure
  • 16 is a schematic plan view of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 17 is a pixel circuit diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • 18A is a schematic cross-sectional view of a display device provided by at least one embodiment of the present disclosure.
  • 18B is a schematic cross-sectional view of another display device provided by at least one embodiment of the present disclosure.
  • 19A and 19B are respectively a point spread function simulation diagram of a point light source imaging when the display device has no first light shielding layer and when there is a first light shielding layer;
  • 20A and 20B are two modulation transfer function diagrams of point light source imaging when the display device has no first light shielding layer and when there is a first light shielding layer;
  • 21A and 21B are real glare photos of the point light source imaging when the display device does not have the first light-shielding layer and has the first light-shielding layer, respectively.
  • the display panel in order to allow more light to enter the camera located below the display panel, the display panel can be designed to have a high pixel density area and a low pixel density area, and the camera is set to allow More light penetrates below the low pixel density area.
  • FIG. 1A shows a schematic plan view of a display substrate
  • FIG. 1B is a partial enlarged schematic view of the display substrate shown in FIG. 1A
  • FIG. 2 shows a schematic cross-sectional view of the display substrate in FIG. 1B along the line A-A.
  • the display area of the display substrate includes a light-transmitting display area 1, a peripheral display area 2 and a main body display area 3 arranged side by side.
  • the main display area 3 is the main display area and has a higher resolution (PPI, Pixel Per Inch), that is, the main display area 3 is arranged with a higher density of sub-pixels for display.
  • Each sub-pixel includes a light-emitting device and a pixel circuit that drives the light-emitting device.
  • the light-transmitting display area 1 may allow light incident from the display side of the display substrate to pass through the display substrate to reach the back side of the display substrate, so as to be used for normal operation of components such as sensors (such as image sensors) disposed on the back side of the display substrate.
  • the light-transmitting display area 1 and the peripheral display area 2 also include a plurality of sub-pixels for display.
  • the pixel circuit of the sub-pixel includes metal traces, metal electrodes, and active layers, it is usually at least partially opaque, or its light permeability cannot meet the requirements of the light-transmitting display area 1.
  • the pixel circuits of the sub-pixels in the light-transmitting display area 1 can be arranged in the peripheral display area 2, such as the peripheral The gray box in the display area 2 is shown, so it occupies a part of the space of the peripheral display area 2.
  • the remaining space of the peripheral display area 2 is used to set the sub-pixels of the peripheral display area 2 itself, for example, each white box in the peripheral display area 2 represents a sub-pixel.
  • each white box in the peripheral display area 2 represents a sub-pixel.
  • the sub-pixels of the peripheral display area 2 (white boxes in FIG. 1B) and the pixel circuits of the sub-pixels in the light-transmitting display area 1 (gray boxes in FIG. 1B) are all in the peripheral display area 2.
  • the light-emitting device 4 of a sub-pixel in the light-transmitting display area 1 includes an anode 4A, a cathode 4C, and a light-emitting layer 4B between the anode 4A and the cathode 4C.
  • the anode 4A is connected to the peripheral display through a wire 6.
  • the pixel circuit 5 in the area 2 and thus the light-emitting device 4 is controlled and driven by the pixel circuit 5.
  • the pixel circuit 5 includes one or more thin film transistors, capacitors and other structures. In the plane of the display substrate, there are certain gaps between the layers of these structures, that is, many narrow gaps are formed.
  • the light on the display side of the display substrate It may enter the peripheral display area 2 obliquely through the light-transmitting display area 1, and enter the sensor (such as an image sensor) provided on the back side of the display substrate through the slit in the peripheral display area 2, which is equivalent to that the light has passed through the aperture ratio.
  • a low grating therefore, will produce a strong diffraction phenomenon, leading to aggravation of the glare phenomenon of the sensor during imaging, and a decrease in resolution, thereby affecting the normal function of the sensor.
  • At least one embodiment of the present disclosure provides a display substrate and a display device.
  • the display substrate has a first side for display and a second side opposite to the first side.
  • the display substrate includes a display area, and the display area includes a first display. Area and a second display area at least partially surrounding the first display area, the first display area allows light from the first side to be at least partially transmitted to the second side;
  • the first display area includes a plurality of first sub-pixels arranged in an array, Each first sub-pixel includes a first light-emitting device, and the second display area includes a plurality of first pixel circuits, and the plurality of first pixel circuits are respectively electrically connected to the plurality of first light-emitting devices of the plurality of first sub-pixels to respectively Drive a plurality of first light-emitting devices;
  • the display area further includes a first light-shielding layer, in a direction perpendicular to the surface of the display substrate, the first light-shielding layer and the
  • the first light-shielding layer can block the light entering the second display area, so as to prevent the light from entering the sensor provided on the second side of the display substrate through the second display area, thereby improving the performance of the sensor. Sensing effect.
  • FIG. 3 shows a schematic plan view of the display substrate.
  • the display substrate has a first side for display (ie, a display side) and a second side (ie, a non-display side, also called a back side) opposite to the first side.
  • the display substrate includes a display area including a first display area 10 and a second display area 20 at least partially surrounding the first display area 10.
  • the first display area 10 allows light from the first side to be at least partially transmitted to the second display area.
  • Side that is, the first display area 10 is a transparent display area. Light can pass from the display side of the display substrate to the non-display side through the transparent display area.
  • the light transmitted from the first display area 10 to the non-display side is used for sensing work, such as imaging.
  • FIG. 4A shows a schematic diagram of the arrangement of sub-pixels in the display area.
  • the first display area 10 includes a plurality of first sub-pixels P1 arranged in an array, each first sub-pixel P1 includes a first light-emitting device EM1, and the plurality of first light-emitting devices EM1 are arranged in an array;
  • the second display area 20 includes a plurality of first pixel circuits D1, and the plurality of first pixel circuits D1 are respectively electrically connected to the plurality of first light-emitting devices EM1 of the plurality of first sub-pixels P1 to drive the plurality of first light-emitting devices EM1 respectively .
  • the pixel circuits of the plurality of first sub-pixels P1 in the first display area 10 are arranged in the second display area 20, thereby avoiding too many structures or opaque structures in the first display area 10. Ensuring the light transmittance of the first display area 10 is beneficial to transmit more light for being sensed by the sensor and improve the sensing quality.
  • the second display area 20 further includes a plurality of second sub-pixels P2, and each second sub-pixel P2 includes a second light-emitting device EM2 and a second pixel circuit D2 electrically connected to the second light-emitting device EM2. D2 is configured to drive the second light emitting device EM2.
  • the plurality of second pixel circuits D2 are arranged in a first array, and the plurality of first pixel circuits D1 are arranged in the gaps of the first array and are arranged integrally with the plurality of second pixel circuits D2
  • the first array is a sub-array of the second array.
  • a plurality of first light-emitting devices EM1 and a plurality of second sub-pixels P2 are arranged uniformly in the first display area 10 and the second display area 20, respectively, so that the first The display area 10 and the second display area 20 emit light and display uniformly as a whole.
  • FIG. 4B shows a specific schematic diagram of the arrangement of sub-pixels in the first display area and the second display area.
  • the left side of the arc-shaped dashed line is the second display area 20
  • the right side of the arc-shaped dashed line is the first display area 10.
  • the second pixel circuits D2 of the plurality of second sub-pixels P2 are arranged in a first array
  • the plurality of first pixel circuits D1 are arranged in the gaps of the first array, for example, arranged in a dashed circle frame.
  • the second pixel circuits D2 are arranged in a second array as a whole, whereby the first light-emitting devices EM1 of the plurality of sub-pixels P1 and the plurality of second sub-pixels P2 (ie, the plurality of second light-emitting devices EM1)
  • the devices EM2) are arranged uniformly in the first display area 10 and the second display area 20, respectively.
  • the display area further includes a first light-shielding layer.
  • the first light-shielding layer and the second display area 20 at least partially overlap, and the first light-shielding layer does not overlap with the first display area 10 .
  • the first light shielding layer can shield the light that enters the second display area 20 and passes through the slits between the various traces, electrodes or active layers in the second display area 20, so as to prevent the light from passing through the second display area 20. It reaches the second side of the display substrate, so that the sensing quality of the sensor can be improved, for example, the shooting quality of the under-screen camera can be improved.
  • FIG. 5 shows a schematic plan view of a display substrate provided by at least one embodiment of the present disclosure
  • FIG. 6 shows a schematic cross-sectional view of the display substrate along the line C-C.
  • each of the plurality of first pixel circuits includes a first thin film transistor 12, and the first thin film transistor 12 includes a first active layer 121, a first gate 122, and a first source and drain electrode.
  • Structures such as 123 and 124; for example, the first light-shielding layer S1 can be provided in the same layer as the first source and drain electrodes 123 and 124, thereby simplifying the manufacturing process of the display substrate.
  • “same-layer arrangement” means that two functional layers or structural layers are formed in the same layer and with the same material in the hierarchical structure of the display substrate.
  • the two The functional layer or the structure layer can be formed of the same material layer, and the required pattern and structure can be formed through the same patterning process.
  • the second display area 20 includes a first sub-area 20A at least partially surrounding the first display area 10 and a second sub-area 20A at least partially surrounding the first sub-area 20A.
  • the area 20B that is, the second sub-area 20B is farther away from the first display area 10 than the first sub-area 20A.
  • the first light-shielding layer S1 is disposed in the first sub-region 20A, and a plurality of first pixel circuits are disposed in the second sub-region 20B.
  • the first light shielding layer S1 at least partially covers the first sub-region 20A.
  • the first light shielding layer S1 completely covers the first sub-region 20A, thereby completely shielding light entering the second sub-region 20B.
  • the display substrate further includes a plurality of signal lines L, which extend in the vertical direction in the figure in the display area, in order to avoid crossing the first display area 10 in the extension direction.
  • the multiple signal lines L are bent and extend through the first sub-region 20A, thereby bypassing the first display area 10, in the first sub-region 20A, the multiple signal lines L extend parallel to each other, for example, with slits therebetween .
  • the multiple signal lines L may also extend in the horizontal direction in the figure in the display area. In order to avoid crossing the first display area 10 in the extension direction, the multiple signal lines L are bent and extend through the first sub-region.
  • the first pixel circuit further includes a first storage capacitor 13.
  • the first storage capacitor 13 includes a first capacitor plate 131 and a second capacitor plate 132, and the first capacitor plate 131 and the first gate 122 They are arranged in the same layer, and multiple signal lines L are arranged in the same layer as the first capacitor plate 131 or the second capacitor plate 132.
  • the plurality of signal lines L may be data lines, scan lines (for example, gate lines, reset lines, light-emitting control lines, etc.), power supply voltage lines, and the like.
  • the orthographic projection of the first light-shielding layer S1 on the plane of the display substrate completely covers the multiple signal lines L routed in the first sub-region 20A on the plane of the display substrate.
  • the first display area 10 may be a suitable shape such as a circle, a rectangle, a racetrack, etc., and a circle is shown as an example in the figure.
  • the size D of the first display area 10 may be 3 mm-4 mm, such as 3.2 mm, 3.4 mm, 3.6 mm, etc., so as to transmit enough light, for example, for imaging.
  • the size of the first display area 10 may be a diameter of a circle, a diagonal of a square or a rectangle, or the like.
  • the width A of the first sub-region 20A that is, the arrangement width of the first light-shielding layer S1 may be 0.1 mm-0.3 mm, such as 0.1 mm or 0.2 mm, etc., so as to achieve a certain light-shielding effect without affecting the display area. normal display.
  • the display substrate further includes a power line and a reset voltage line (detailed later), and the first light shielding layer S1 is electrically connected to the power line or the reset voltage line.
  • a certain direct current signal can be input to the first light shielding layer S1 to avoid the first light shielding layer S1 from appearing in a floating state, thereby avoiding the influence on the signal transmission on the display substrate.
  • the first light-shielding layer S1 may also be disposed on other positions of the display substrate.
  • FIG. 9 is a schematic cross-sectional view of the display substrate in FIG. 3 along the line B-B.
  • the display substrate further includes a base substrate 14 and a second light-shielding layer S2.
  • a plurality of first sub-pixels are arranged on the base substrate 14, and the second light-shielding layer S2 is arranged on the plurality of first pixel circuits and the liner. Between the base substrates 14, at least part of the circuit structures of the plurality of first pixel circuits or at least part of the circuit structures of the plurality of second pixel circuits is blocked.
  • the second light shielding layer S2 at least shields the active layer 121 of the first thin film transistor 12 to prevent light from entering the active layer 121 from the second side of the display substrate to affect the normal operation of the first thin film transistor 12.
  • the second light-shielding layer S2 is covered with an insulating layer 14A to be spaced apart from the plurality of first pixel circuits; for another example, the second light-shielding layer S2 at least shields the gaps between different electrodes of the first pixel circuit or the second pixel circuit. Slits, or slits between electrodes and signal lines (e.g., gate lines, data lines, power lines), etc.
  • the first light-shielding layer S1 and the second light-shielding layer S2 are provided in the same layer.
  • the first light shielding layer S1 is disposed in the first sub-region 20A as in the above-mentioned embodiment, so as to shield one or more slits between the plurality of signal lines L.
  • a blocking B here means that the orthographic projection of B on the plane where the display substrate is located is in the orthographic projection of A on the plane where the display substrate is located.
  • the first light-shielding layer S1 and the second light-shielding layer S2 may be arranged at intervals, or, in some embodiments, as shown in FIG. 10, the first light-shielding layer S1 and the second light-shielding layer S2 are continuous
  • the integrated film layer is provided, and the integrated film layer has an opening in the first display area 10 so that the first light shielding layer S1 and the first display area 10 do not overlap in the direction perpendicular to the surface of the display substrate.
  • the integrated film layer of the first light-shielding layer S1 and the second light-shielding layer S2 can completely cover the display area except the first display area 10 to fully achieve the light-shielding effect.
  • the first light-shielding layer S1 and the second light-shielding layer S2 can be made of metal materials or alloy materials with good light-shielding properties, such as copper (Cu), aluminum (Al), and titanium (Ti).
  • the display substrate further includes a base substrate 14 and a heat dissipation layer SCF, and a plurality of first sub-pixels are arranged on the first side of the base substrate 14 (shown in the figure as The upper side of the base substrate 14), the heat dissipation layer SCF is disposed on the second side of the base substrate 14 (shown as the lower side of the base substrate 14 in the figure), and the first side and the second side are opposite.
  • the first light shielding layer S1 and the heat dissipation layer SCF are provided in the same layer.
  • the first light shielding layer S1 is disposed in the first sub-region 20A as in the above-mentioned embodiment, so as to shield one or more slits between the plurality of signal lines L.
  • the first light-shielding layer S1 and the heat dissipation layer SCF may be arranged at intervals, or, referring to FIG. 11 and FIG. 12, the first light-shielding layer S1 and the heat dissipation layer SCF may be a continuous integrated film layer.
  • a display area 10 has an opening so that in a direction perpendicular to the surface of the display substrate, the first light shielding layer S1 does not overlap with the first display area 10.
  • the first light-shielding layer S1 and the heat dissipation layer SCF may be metal layers such as copper foil to have good light-shielding effect and heat dissipation effect at the same time.
  • a copper foil with a certain shape and size (such as the shape and size shown in FIG. 11) can be formed by cutting, and then attached to the second side of the base substrate 14 to simultaneously Realize good shading effect and heat dissipation effect.
  • the first light-shielding layer S1 and the second light-shielding layer S2 are arranged as a continuous integrated film layer or the first light-shielding layer S1 and the heat dissipation layer SCF are arranged as a continuous integrated film.
  • the chemical film layer can achieve the technical effect of completely shielding the second display area 20, thereby achieving a more sufficient light shielding effect, and improving the working quality of the under-screen sensor, for example, improving the photographing effect of the under-screen camera.
  • different first light shielding layers S1 may be used at the same time, for example, any two or more of the first light shielding layers S1 shown in FIG. 6, FIG. 9, FIG. 10, and FIG. 12 may be used. Use at the same time to further improve the shading effect.
  • the first light shielding layer S1 shown in FIGS. 10 and 11 may be used at the same time, or the first light shielding layer S1 shown in FIGS. 6 and 11 may be used at the same time, or the first light shielding layer S1 shown in FIGS. 6 and 11 may be used at the same time.
  • the first light-shielding layer S1, or the first light-shielding layer S1 shown in FIG. 9 and FIG. 11, etc. are used at the same time, that is, the display substrate has two or more first light-shielding layers S1 at the same time to further improve the light-shielding effect.
  • the first pixel circuit includes a first thin film transistor 12, and the first thin film transistor 12 includes a first active layer 121 and a first gate.
  • the first light-emitting device 11 includes a first electrode 111, a second electrode 113, and a first light-emitting layer 112 between the first electrode 111 and the second electrode 113, and the first light-emitting device
  • the first electrode 111 of 11 is electrically connected to the first source/drain electrode 124 through the first via hole V1.
  • the first electrode 111 of the first light emitting device 11 is first electrically connected to the transparent connection electrode 15 through the first via hole V1, and then electrically connected to the first source/drain electrode 124 through the transparent connection electrode 15.
  • the transparent connecting electrode 15 may be made of a transparent conductive material, such as a transparent metal oxide, such as indium tin oxide (ITO), etc., to have good light transmittance.
  • a transparent metal oxide such as indium tin oxide (ITO), etc.
  • ITO indium tin oxide
  • the transparent connecting electrode 15 has better light transmittance than the first electrode 111. Therefore, the transparent connecting electrode 15 is used to electrically connect the first electrode 111 and the first source/drain electrode 124 to further increase the light transmittance of the first display area 10. sex.
  • the second pixel circuit includes a second thin film transistor 22, the second thin film transistor 22 includes a second active layer 221, a second gate 222, and second source and drain electrodes 223 and 224, and the second light emitting device 21 It includes a first electrode 211, a second electrode 213, and a second light-emitting layer 212 between the first electrode 211 and the second electrode 213.
  • the first electrode 211 of the second light-emitting device 21 is drained from the second source through the second via hole V2. Pole 223 is electrically connected.
  • the display substrate further includes a first gate insulating layer 141, a second gate insulating layer 142, an interlayer insulating layer 143, a first planarization layer 144, a second planarization layer 145, and a pixel defining layer.
  • the structure of the layer 146 and the encapsulation layer 147, etc., the embodiment of the present disclosure does not specifically limit other structures of the display substrate.
  • the above-mentioned active layers may use amorphous silicon layers, polysilicon layers or metal oxide semiconductor materials.
  • the polysilicon may be high temperature polysilicon or low temperature polysilicon
  • the oxide semiconductor may be indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), zinc oxide (ZnO), gallium zinc oxide (GZO), or the like.
  • Each gate can be made of copper (Cu), aluminum (Al), titanium (Ti) or other metal materials or alloy materials, for example, formed into a single-layer metal layer structure or a multi-layer metal layer structure, such as multiple layers of titanium/aluminum/titanium Metal layer structure.
  • Each of the drain electrodes can be made of copper (Cu), aluminum (Al), titanium (Ti) and other metal materials or alloy materials, for example, formed into a single-layer metal layer structure or a multi-layer metal layer structure, such as titanium/aluminum/titanium, etc. Layer metal layer structure.
  • the material of the first electrode of each light-emitting device may be a transparent metal oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), gallium zinc oxide (GZO), and the material of the second electrode may be lithium (Li) , Aluminum (Al), Magnesium (Mg), Silver (Ag) and other metal materials.
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • GZO gallium zinc oxide
  • the material of the second electrode may be lithium (Li) , Aluminum (Al), Magnesium (Mg), Silver (Ag) and other metal materials.
  • the base substrate 14 may be a rigid base substrate such as glass, quartz, or a flexible base substrate such as polyimide.
  • the first gate insulating layer 141, the second gate insulating layer 142, and the interlayer insulating layer 143 may be silicon oxide, nitrogen, etc.
  • Inorganic insulating materials such as silicon or silicon oxynitride, the first planarization layer 144, the second planarization layer 145, and the pixel defining layer 146 can be made of organic insulating materials such as polyimide or resin.
  • the encapsulation layer 147 may include a stack of a plurality of organic encapsulation layers and inorganic encapsulation layers.
  • the embodiments of the present disclosure do not specifically limit the material and structure of each functional layer of the display substrate.
  • each light-emitting layer may be an organic light-emitting layer or a quantum dot light-emitting layer, etc.
  • the display substrate may be realized as an organic light-emitting diode (OLED) display substrate or a quantum dot light-emitting diode (QLED) display substrate, etc.
  • OLED organic light-emitting diode
  • QLED quantum dot light-emitting diode
  • the type of display substrate is not specifically limited.
  • the first via hole V1 and the light-emitting area of the first light-emitting layer 112 (that is, the first light-emitting layer 112 is directly opposite to the first
  • the shortest distance between the electrode 111 and the second electrode 113) is smaller than the second via hole V2 and the light-emitting area of the second light-emitting layer 212 (that is, the second light-emitting layer 212 is directly opposite to the first electrode 211 and the second electrode 211).
  • the area between the electrodes 213) is the shortest distance.
  • FIG. 14 shows a schematic plan view of the light-emitting area and the first electrode via of the light-emitting device of four sub-pixels in the first display area 10, and the four sub-pixels constitute one pixel unit in the first display area 10.
  • the four sub-pixels include one red sub-pixel R, one blue sub-pixel B, and two green sub-pixels G.
  • FIG. 15 shows a schematic plan view of the light-emitting area and the first electrode via of the light-emitting device of four sub-pixels in the second display area 20, and the four sub-pixels constitute one pixel unit in the second display area 00.
  • the four sub-pixels include one red sub-pixel R, one blue sub-pixel B, and two green sub-pixels G.
  • the shortest distance between the first via hole V1 and the light-emitting area R1 of the first light-emitting layer 112 is smaller than the light-emitting area of the second via hole V2 and the second light-emitting layer 212
  • the shortest distance d of R2 is smaller than the light-emitting area of the second via hole V2 and the second light-emitting layer 212
  • the orthographic projection of the first via hole V1 in the plane of the display substrate and the orthographic projection of the light-emitting area R1 of the first light-emitting layer 112 in the plane of the display substrate At least partially overlapped. At this time, the shortest distance between the first via hole V1 and the light-emitting region R1 of the first light-emitting layer 112 is zero. As shown in FIGS.
  • the orthographic projection of the second via hole V2 in the plane of the display substrate and the orthographic projection of the light-emitting area R2 of the second light-emitting layer 212 in the plane of the display substrate do not overlap, and the second via hole
  • the shortest distance between V2 and the light-emitting region R2 of the first light-emitting layer 112 is d, and d is greater than zero.
  • the distance between the first via hole V1 and the light-emitting area R1 of the first light-emitting layer 112 is closer, which can prevent the extension of the first electrode 111 from being too long and affecting the first display area 10. Transparency.
  • the display area further includes a third display area 30 at least partially surrounding the second display area 20, and the third display area 30 includes a plurality of third display areas arranged in an array.
  • Sub-pixel P3 the arrangement density of the plurality of third sub-pixels P3 in the third display area 30 is greater than the arrangement density of the plurality of first sub-pixels P1 in the first display area 10, and is also greater than the arrangement density of the plurality of second sub-pixels P1 in the second display area 20.
  • the arrangement density of the sub-pixels P2 is such that the third display area 30 has a higher resolution than the first display area 10 and the second display area 20.
  • the area occupied by the third display area 30 is larger than the areas occupied by the first display area 10 and the second display area 20, and the third display area 30 is implemented as the main display area of the display substrate.
  • the arrangement density of the plurality of first sub-pixels P1 in the first display area 10 is equal to the arrangement density of the plurality of second sub-pixels P2 in the second display area 20.
  • the arrangement density of the plurality of third sub-pixels P3 in the third display area 30 is twice the arrangement density of the plurality of first sub-pixels P1 in the first display area 10.
  • each third sub-pixel P3 in the third display area 30 includes a third pixel circuit and a third light-emitting device.
  • the specific structures of the third pixel circuit and the third light-emitting device are similar to those of the second pixel circuit and the second light-emitting device.
  • the mechanism is similar, please refer to Figure 13 for details, which will not be repeated here.
  • the display substrate further includes a first scan drive circuit (Gate on Array) GOA1 and a second scan drive circuit GOA2 located on opposite sides of the display area, and the first scan drive circuit GOA1 and the second scan driving circuit GOA2 jointly provide electrical signals for a plurality of third sub-pixels in the third display area 30, that is, in the third display area 30, the GOA driving circuit adopts a double-side driving method, and the third display area 30
  • the scan driving circuits on the left and right sides are connected to each other.
  • the first scan driving circuit GOA1 also provides electrical signals for the plurality of second sub-pixels and the plurality of first pixel circuits in the second display area 20 located on the side of the first display area 10 close to the first scan driving circuit GOA1.
  • electrical signals are provided for a plurality of second sub-pixels and a plurality of first pixel circuits in the second display area 20 on the left side of the dotted line in FIG.
  • the second scan driving circuit GOA2 is also located near the second display area 10
  • the plurality of second sub-pixels and the plurality of first pixel circuits in the second display area 20 on the side of the scan driving circuit GOA2 provide electrical signals, for example, for the plurality of second sub-pixels in the second display area 20 on the right side of the dotted line in FIG.
  • the two sub-pixels and the plurality of first pixel circuits provide electrical signals. That is, for the first display area 10 and the second display area 20, the GOA driving circuit adopts a unilateral driving method, and the two sides of the first display area 10 and the second display area 20 are used for the first display area 10 and the second display area 20.
  • the scan driving circuits that provide electrical signals in the display area 20 are not connected to each other.
  • the display substrate further includes a power line and a reset voltage line
  • the first light shielding layer S1 is electrically connected to the power line or the reset voltage line to prevent the first light shielding layer S1 from being suspended.
  • the driving circuit of the display substrate and the connection relationship between the power supply line and the reset voltage line will be exemplarily introduced with reference to the accompanying drawings.
  • the first pixel circuit, the second pixel circuit, and the third pixel circuit in the display substrate may use 2T1C, 7T1C and other pixel driving circuits.
  • FIG. 17 shows a circuit diagram of a 7T1C pixel circuit.
  • the pixel circuit includes a driving transistor T1, a data writing transistor T2, a compensation transistor T3, a storage capacitor C, a first light-emission control transistor T4, a second light-emission control transistor T5, a first reset transistor T6, and a second Reset transistor T7.
  • the driving transistor T1 includes a control terminal, a first terminal, and a second terminal, which are configured to control the driving current flowing through the light emitting device EM, and the control terminal of the driving transistor T1 is connected to the first node N1, and the first terminal of the driving transistor T1 The terminal is connected to the second node N2, and the second terminal of the driving transistor T1 is connected to the third node N3.
  • the data writing transistor T2 includes a control terminal, a first terminal, and a second terminal.
  • the control terminal is configured to receive the first scan signal Ga1, the first terminal is configured to receive the data signal, and the second terminal is connected to the first terminal of the driving transistor T1.
  • the terminal (the second node N2) is connected and configured to write the data signal to the first terminal of the driving transistor T1 in response to the first scan signal Ga1.
  • the first terminal of the data writing transistor T2 is connected to the data line to receive the data signal, and the control terminal is connected to the scan line to receive the first scan signal Ga1.
  • the data writing transistor T2 can be turned on in response to the first scan signal Ga1, so that the data signal can be written to the first end (the second node N2) of the driving transistor T1, and the data signal can be stored In the storage capacitor C, a driving current for driving the light-emitting device EM to emit light can be generated according to the data signal during, for example, the light-emitting phase.
  • the compensation transistor T3 includes a control terminal, a first terminal, and a second terminal.
  • the control terminal is configured to receive the second scan signal Ga2.
  • the first terminal and the second terminal are electrically connected to the control terminal and the second terminal of the driving transistor T1.
  • the compensation circuit is configured to perform threshold compensation in response to the second scan signal.
  • the storage capacitor C is electrically connected to the control terminal of the driving transistor T1 and the first voltage terminal VDD, and is configured to store the data signal written by the data writing transistor T2.
  • the compensation transistor T3 can be turned on in response to the second scan signal Ga2, so that the data signal written by the data writing transistor T2 can be stored in the storage capacitor C.
  • the compensation transistor T3 can electrically connect the control terminal and the second terminal of the driving transistor T1, so that the information related to the threshold voltage of the driving transistor T1 can be correspondingly stored in the storage circuit.
  • the stored data signal and the threshold voltage can be used to control the driving transistor T1 during the light-emitting phase, so that the output of the driving transistor T1 is compensated.
  • the first light-emitting control transistor T4 is connected to the first terminal (the second node N2) of the driving transistor T1 and the first voltage terminal VDD, and is configured to turn the first power source of the first voltage terminal VDD in response to the first light-emitting control signal.
  • the voltage is applied to the first terminal of the driving transistor T1.
  • the first light emission control transistor T4 is connected to the first light emission control terminal Em1, the first voltage terminal VDD, and the second node N2.
  • the second light emitting control transistor T5 and the second light emitting control terminal Em2 the first terminal of the light emitting device EM, and the second terminal of the driving transistor T1 are connected, and are configured to respond to the second light emitting control signal so that the driving current can be applied to Light-emitting device EM.
  • the second light-emission control transistor T5 is turned on in response to the second light-emission control signal provided by the second light-emission control terminal Em2, so that the driving transistor T1 can apply a driving current to the light-emitting device EM through the second light-emission control transistor T5
  • the second light-emitting control transistor T5 is turned off in response to the second light-emitting control signal, so as to avoid current flowing through the light-emitting device EM to cause it to emit light, which can improve the contrast of the corresponding display device.
  • the second light-emission control transistor T5 can also be turned on in response to the second light-emission control signal, so that the reset circuit can be combined to perform a reset operation on the driving transistor T1 and the light-emitting device EM.
  • the second light emission control signal Em2 can be the same as or different from the first light emission control signal Em1, for example, the two can be connected to the same or different signal output terminals.
  • the first reset transistor T6 is configured to apply the first reset voltage Vini1 to the first node N1 in response to the first reset signal Rst1
  • the second reset transistor T7 is configured to apply the second reset voltage Vini2 in response to the second reset signal Rst2.
  • the fourth node N4 Applied to the fourth node N4.
  • the first reset transistor T6 and the second reset transistor T7 can be turned on in response to the reset signal, so that the reset voltage can be applied to the first end of the light emitting device EM and the first node N1, so that the driving transistor can be T1, the compensation transistor T3, and the light-emitting device EM perform a reset operation to eliminate the influence of the previous light-emitting stage.
  • the light emitting device EM includes a first terminal and a second terminal, the first terminal of the light emitting device EM is configured to receive a driving current from the second terminal of the driving transistor T1, and the second terminal of the light emitting device EM is configured to be connected to the second voltage terminal VSS. connect.
  • the first end of the light emitting device EM may be connected to the third node N3.
  • the first node N1, the second node N2, the third node N3, and the fourth node N4 do not necessarily represent actual components, but rather represent the junction of related circuit connections in the circuit diagram.
  • the symbol Vd can represent both the data signal terminal and the level of the data signal.
  • Ga1 and Ga2 can represent the first scan signal, the second scan signal, or the first scan signal terminal and the second scan signal.
  • Terminal, Rst can represent both the reset control terminal and the reset signal
  • the symbol Vinit can represent both the reset voltage terminal and the reset voltage
  • the symbol VDD can represent both the first voltage terminal and the first power supply voltage
  • the symbol VSS can either It means that the second voltage terminal can also indicate the second power supply voltage.
  • the second voltage terminal can be grounded, that is, VSS can be 0V.
  • the first light shielding layer S1 may be electrically connected to a power line that transmits the first power supply voltage VDD or the second power supply voltage VSS, or is electrically connected to a reset voltage line that transmits the reset voltage Vini1 or Vini2.
  • the first light-shielding layer S1 when the first light-shielding layer S1 is arranged in the same layer as the power line or the reset voltage line, the first light-shielding layer S1 can be directly electrically connected to the power line or the reset voltage line through the connecting wire, or when the first light-shielding layer S1 When it is arranged in a different layer from the power line or the reset voltage line, the first light shielding layer S1 may be electrically connected to the power line or the reset voltage line through a via hole.
  • a via can be directly formed between the first light-shielding layer S1 and the power line or the reset voltage line. So that the first light shielding layer S1 is electrically connected to the power line or the reset voltage line through the via hole.
  • the light-shielding layer S1 may be extended to a position overlapping with the power line or the reset voltage line, and then A via is formed between the two, and an electrical connection is made; or, the power line or the reset voltage line is extended to a position overlapping the first light shielding layer S1, and then a via is formed between the two, and the electrical connection is made .
  • the power line or the reset voltage line may also be introduced into a position overlapping with the first light shielding layer S1 by using a connecting wire, and then a via is formed between the connecting wire and the first light shielding layer S1 and electrically connected.
  • the first light shielding layer S1 can be electrically connected to the power line or the reset voltage line in any suitable manner.
  • the embodiment of the present disclosure electrically connects the first light shielding layer S1 to the power line or the reset voltage line.
  • the method is not specifically limited. Therefore, the first light-shielding layer S1 can be transmitted with a certain power supply voltage or reset voltage, which can prevent the first light-shielding layer S1 from appearing in a floating state and affecting the signal transmission on the display substrate.
  • the first light-shielding layer can effectively block at least part of the light entering the second display area, so as to prevent the light from entering the under-screen sensor, such as a camera, through the second display area. Thereby improving the sensing effect, such as improving the shooting quality of the camera under the screen.
  • the first light shielding layer can be input with a certain electrical signal, so as not to affect the normal operation of the driving circuit in the display substrate.
  • the first light-shielding layer can be arranged in the same layer as some existing functional layers in the display substrate, so that the same material can be used in the preparation process to be formed through the same process, which can also simplify the preparation process of the display substrate. That is, without increasing the difficulty of preparing the display substrate, the working fluid quality of the under-screen sensor of the display substrate, such as a camera, is improved, and the narrow frame design of the display substrate is also realized.
  • the display device includes any of the above-mentioned display substrates (shown in FIG. 18A as the display substrate in FIG. 6 as an example) and a sensor 19.
  • the sensor 19 is provided on the second side (non-display side) of the display substrate, and the sensor is configured to receive light from the first side (display side).
  • the sensor 19 may be any type of sensor such as a camera or an infrared sensor.
  • FIG. 18B shows a schematic cross-sectional view of another display device provided by at least one embodiment of the present disclosure.
  • the first light-shielding layer S1 and the heat dissipation layer SCF in the display device are arranged in the same layer, for example, the arrangement of the first light-shielding layer S1 in the display substrate shown in FIG. 12 is adopted.
  • the first electrode 111 of the first light emitting device is directly electrically connected to the first source and drain 124 through the via hole exposing the source and drain 124, thereby saving transparency.
  • the connection electrode 15 and the second planarization layer 145 simplify the film structure of the display substrate.
  • the sensor 19 in a direction perpendicular to the surface of the display substrate, the sensor 19 at least partially overlaps the first display area 10 of the display substrate, so that the light from the first side can be fully received and based on the light working. Since the display substrate has a first light-shielding layer that shields the second display area, the sensor 19 only receives light transmitted through the first display area, which can prevent the light-transmissive second display area from reaching the sensor 19 and affecting the sensor 19 Therefore, the sensor 19 of the display device has a higher working quality. For example, when the sensor 19 is a camera, the camera has a higher photographing quality.
  • the display device provided by at least one embodiment of the present disclosure may be any product or component with display function, such as a display substrate, a display panel, an electronic paper, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.
  • a display substrate such as a liquid crystal display (LCD)
  • a display panel such as a liquid crystal display (LCD)
  • an electronic paper such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.
  • the embodiment of the present disclosure does not limit this.
  • FIG. 19A and FIG. 19B respectively show the point spread function simulation diagram of the point light source imaging when the display device has no first light shielding layer and the first light shielding layer.
  • the energy distribution state on the imaging surface that is, the dispersion distribution of energy in various directions (embodied in XY coordinates) such as up, down, left, and right, which can intuitively characterize the glare of the point light source.
  • Figure 19A when the first light-shielding layer is not provided in the second display area, under the oblique field angle, the light passes through the second display area, which is similar to passing through a grating with a small aperture ratio.
  • the center of the point light source imaging is The peak energy is only 10.5, and point light source glare is serious.
  • FIG. 19B after the first light-shielding layer is provided in the second display area, light can only pass through the first display area under the oblique field angle, and the central energy peak of the point light source imaging is greater than 11, and the point light source glare phenomenon is significantly improved.
  • 20A and 20B show the modulation transfer function (Moduation Transfer Function) diagram of the point light source imaged on the meridian and arcuate surfaces when the display device has no first light-shielding layer and a first light-shielding layer, the abscissa values in the figure Represents the spatial frequency (that is, the spatial line pair per millimeter, the unit is lp/mm), and the ordinate is the MTF value, which is used to characterize the resolution under different spatial frequencies. At the same spatial frequency, the higher the MTF value, the higher the imaging resolution.
  • Moduation Transfer Function Moduation Transfer Function
  • the F0 curve is the modulation transfer function curve of the point light source imaging when the display device does not have the first light shielding layer
  • the F1 curve is the modulation transfer function curve of the point light source imaging after the display device is provided with the first light shielding layer. It can be seen that under the same spatial frequency, the MTF value of the F1 curve is higher than the MTF value of the F0 curve, that is, after the first light shielding layer is provided, the resolution of the point light source imaging of the display device is significantly improved.
  • FIG. 21A shows a real glare photo taken by a point light source when the display device has no first light shielding layer
  • Figure 21B shows a real glare photo taken by a point light source after the display device is provided with the first light shielding layer. Comparing FIGS. 21A and 21B, it can be seen that after the first light shielding layer is provided, the glare phenomenon of the point light source imaging of the display device is significantly improved.

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Abstract

一种显示基板和显示装置。该显示基板具有第一侧和第二侧，显示基板包括显示区域，该显示区域包括第一显示区域（10）以及第二显示区域（20），第一显示区域（10）允许来自第一侧的光至少部分透射至第二侧；第一显示区域（10）包括阵列排布的多个第一子像素（P1），每个第一子像素（P1）包括第一发光器件（EM1），第二显示区域（20）包括多个第一像素电路（D1），多个第一像素电路（D1）分别与多个第一发光器件（EM1）电连接；显示区域还包括第一遮光层（S1），在垂直于显示基板的板面的方向上，第一遮光层（S1）与第二显示区域（20）至少部分重叠，第一遮光层（S1）与第一显示区域（10）不重叠。由此，第一遮光层（S1）可以遮挡进入第二显示区域（20）的光，以避免光线经过第二显示区域（20）射入屏下传感器，例如屏下摄像头，从而提高屏下摄像头的拍摄质量。

Description

显示基板和显示装置
本申请要求于2020年5月29日递交的中国专利申请第202010479765.3号的优先权，出于所有目的，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种显示基板和显示装置。
背景技术
随着手机等显示电子产品的发展，显示屏的屏占比的提升成为一种产品趋势，前置摄像头等手机必备的功能元件成为制约屏占比提升的一大因素。针对这个问题，业界提出了将摄像头与显示面板结合到一显示装置中的被称为“屏下摄像头”的方案。在这样的方案中，显示装置包括显示面板和位于该显示面板下方的摄像头。显示装置的具有屏下摄像头的区域可以与其他区域一样发光并进行显示，并同时具有摄像功能。
发明内容
本公开至少一实施例提供一种显示基板，该显示基板具有用于显示的第一侧和与所述第一侧相对的第二侧，所述显示基板包括显示区域，其中，所述显示区域包括第一显示区域以及至少部分围绕所述第一显示区域的第二显示区域，所述第一显示区域允许来自所述第一侧的光至少部分透射至所述第二侧；所述第一显示区域包括阵列排布的多个第一子像素，每个第一子像素包括第一发光器件，所述第二显示区域包括多个第一像素电路，所述多个第一像素电路分别与所述多个第一子像素的多个第一发光器件电连接，以分别驱动所述多个第一发光器件；其中，所述显示区域还包括第一遮光层，在垂直于所述显示基板的板面的方向上，所述第一遮光层与所述第二显示区域至少部分重叠，所述第一遮光层与所述第一显示区域不重叠。
例如，本公开至少一实施例提供的显示基板还包括电源线和复位电压线，其中，所述第一遮光层与所述电源线或者所述复位电压线电连接。
例如，本公开至少一实施例提供的显示基板中，所述多个第一像素电路中的每个包括第一薄膜晶体管，所述第一薄膜晶体管包括第一有源层、第一栅极和第一源漏电极；所述第一遮光层与所述第一源漏电极同层设置。
例如，本公开至少一实施例提供的显示基板中，所述第二显示区域包括至少部分围绕所述第一显示区域的第一子区以及至少部分围绕所述第一子区的第二子区，所述第一遮光层设置在所述第一子区中，所述多个第一像素电路设置在所述第二子区中。
例如，本公开至少一实施例提供的显示基板还包括分别电连接所述多个第一像素电 路的多条信号线，所述多条信号线延伸经过所述第一子区，所述第一像素电路还包括第一存储电容，所述第一存储电容包括第一电容极板和第二电容极板，所述第一电容极板与所述第一栅极同层设置，所述多条信号线与所述第一电容极板或者所述第二电容极板同层设置。
例如，本公开至少一实施例提供的显示基板还包括衬底基板和第二遮光层，其中，所述多个第一子像素设置在所述衬底基板上，所述第二遮光层设置在所述多个第一像素电路与所述衬底基板之间，以遮挡至少部分所述多个第一像素电路的电路结构；所述第一遮光层与所述第二遮光层同层设置。
例如，本公开至少一实施例提供的显示基板中，所述第一遮光层与所述第二遮光层为连续设置的一体化膜层，所述一体化膜层在所述第一显示区域具有开口，以使得在垂直于所述显示基板的板面的方向上，所述第一遮光层与所述第一显示区域不重叠。
例如，本公开至少一实施例提供的显示基板还包括衬底基板和散热层，其中，所述多个第一子像素设置在所述衬底基板的第一侧，所述散热层设置在所述衬底基板的第二侧，所述第一侧和所述第二侧相对；所述第一遮光层与所述散热层同层设置。
例如，本公开至少一实施例提供的显示基板中，所述第一遮光层与所述散热层为连续设置的一体化膜层，所述一体化膜层在所述第一显示区域具有开口，以使得在垂直于所述显示基板的板面的方向上，所述第一遮光层与所述第一显示区域不重叠。
例如，本公开至少一实施例提供的显示基板中，所述第二显示区域还包括多个第二子像素，每个第二子像素包括第二发光器件以及与所述第二发光器件电连接的第二像素电路，所述第二像素电路配置为驱动所述第二发光器件，在所述第二显示区域中，所述多个第二像素电路呈第一阵列排布，所述多个第一像素电路设置在所述第一阵列的间隙中，并与所述多个第二像素电路整体排布为第二阵列。
例如，本公开至少一实施例提供的显示基板中，所述第一像素电路包括第一薄膜晶体管，所述第一薄膜晶体管包括第一有源层、第一栅极和第一源漏电极，所述第一发光器件包括第一电极、第二电极以及所述第一电极和所述第二电极之间的第一发光层，所述第一发光器件的第一电极通过第一过孔与所述第一源漏电极电连接；所述第二像素电路包括第二薄膜晶体管，所述第二薄膜晶体管包括第二有源层、第二栅极和第二源漏电极，所述第二发光器件包括第一电极、第二电极以及所述第一电极和所述第二电极之间的第二发光层，所述第二发光器件的第一电极通过第二过孔与所述第二源漏电极电连接；在所述显示基板所在平面内，所述第一过孔与所述第一发光层的发光区域的最短距离小于所述第二过孔与所述第二发光层的发光区域的最短距离。
例如，本公开至少一实施例提供的显示基板中，所述第一过孔在所述显示基板所在平面内的正投影与所述第一发光层的发光区域在所述显示基板所在平面内的正投影至少部分重叠。
例如，本公开至少一实施例提供的显示基板中，所述显示区域包括至少部分围绕所述第二显示区域的第三显示区域，所述第三显示区域包括阵列排布的多个第三子像素， 其中，所述第三显示区域中所述多个第三子像素的排布密度大于所述第一显示区域中所述多个第一子像素的排布密度，也大于所述第二显示区域中所述多个第二子像素的排布密度。
例如，本公开至少一实施例提供的显示基板中，所述第一显示区域中所述多个第一子像素的排布密度等于所述第二显示区域中所述多个第二子像素的排布密度。
例如，本公开至少一实施例提供的显示基板还包括分别位于所述显示区域相对两侧的第一扫描驱动电路和第二扫描驱动电路，其中，所述第一扫描驱动电路和第二扫描驱动电路共同为在所述第三显示区域中的多个第三子像素提供电信号；所述第一扫描驱动电路还为位于所述第一显示区域靠近所述第一扫描驱动电路一侧的第二显示区域中的多个第二子像素和多个第一像素电路提供电信号，所述第二扫描驱动电路还为位于所述第一显示区域靠近所述第二扫描驱动电路一侧的第二显示区域中的多个第二子像素和多个第一像素电路提供电信号。
本公开至少一实施例提供一种显示装置，该显示装置包括上述任一所述的显示基板，以及传感器，其中，所述传感器设置于所述显示基板的第二侧，且所述传感器配置为接收来自所述第一侧的光。
例如，本公开至少一实施例提供的显示装置中，在垂直于所述显示基板的板面的方向上，所述传感器与所述显示基板的第一显示区域至少部分重叠。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1A为一种显示基板的平面示意图；
图1B为一种显示基板的局部放大示意图；
图2为图1B中的显示基板沿A-A线的截面示意图；
图3为本公开至少一实施例提供的一种显示基板的平面示意图；
图4A为本公开至少一实施例提供的一种显示基板的局部放大示意图；
图4B为本公开至少一实施例提供的一种显示基板中第一显示区域和第二显示区域中子像素的排列示意图；
图5为本公开至少一实施例提供的一种显示基板的平面示意图；
图6为图5中的显示基板沿C-C线的截面示意图；
图7为本公开至少一实施例提供的显示基板中第一显示区域和部分第二显示区域的平面示意图；
图8为本公开至少一实施例提供的显示基板中第一显示区域和部分第二显示区域的另一平面示意图；
图9为图3中的显示基板沿B-B线的截面示意图；
图10为图3中的显示基板沿B-B线的另一截面示意图；
图11本公开至少一实施例提供的显示基板中的第一遮光层的平面示意图；
图12为图3中的显示基板沿B-B线的另一截面示意图；
图13为本公开至少一实施例提供的显示基板中第二显示区域的截面示意图；
图14为本公开至少一实施例提供的显示基板中第一显示区域种子像素的排列示意图；
图15为本公开至少一实施例提供的显示基板中第二显示区域种子像素的排列示意图；
图16为本公开至少一实施例提供的一种显示基板的平面示意图；
图17为本公开至少一实施例提供的一种显示基板的像素电路图；
图18A为本公开至少一实施例提供的一种显示装置的截面示意图；
图18B为本公开至少一实施例提供的另一种显示装置的截面示意图；
图19A和图19B分别为显示装置在没有第一遮光层和有第一遮光层时点光源成像的点扩散函数仿真图；
图20A和图20B为显示装置在没有第一遮光层和有第一遮光层时点光源成像的两种调制传递函数图；以及
图21A和图21B分别为显示装置在没有第一遮光层和有第一遮光层时点光源成像的眩光实拍照片。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在“屏下摄像头”的设计方案中，为了使得更多的光能够进入位于显示面板下方的摄像头中，可以将显示面板设计为具有高像素密度区域和低像素密度区域，摄像头则设置在能够允许更多的光透过的低像素密度区域下方。
例如，图1A示出了一种显示基板的平面示意图，图1B为图1A示出的的显示基板 的局部放大示意图，图2示出了图1B中的显示基板沿A-A线的截面示意图。
如图1A、图1B和图2所示，该显示基板的显示区包括并列布置的透光显示区1、周边显示区2以及主体显示区3。
例如，主体显示区3为主要的显示区域，具有较高的分辨率(PPI，Pixel Per Inch)，即主体显示区3内排布有密度较高的用于显示的子像素。每个子像素包括发光器件以及驱动发光器件的像素电路。透光显示区1可以允许从显示基板显示侧射入的光透过显示基板而到达显示基板的背侧，从而用于位于显示基板背侧设置的传感器(例如图像传感器)等部件的正常工作。
透光显示区1和周边显示区2也包括多个子像素，以用于显示。但是，由于子像素的像素电路包括金属走线、金属电极以及有源层等，因此通常至少部分是不透光的，或者说其透光性不能满足透光显示区1的需求。为了保证透光显示区1的透光性，透光显示区1中子像素(例如图1B中透光显示区1内的方框所示)的像素电路可以设置在周边显示区2，如周边显示区2中的灰色方框所示，因此占据了周边显示区2的部分空间。周边显示区2的剩余空间用于设置周边显示区2自身的子像素，例如周边显示区2中的每一个白色方框代表一个子像素。此时，例如，周边显示区2的子像素(图1B中的白色方框)以及透光显示区1中子像素的像素电路(图1B中的灰色方框)整体上在周边显示区2中排布为阵列。由此，透光显示区1和周边显示区2的分辨率低于主体显示区3的分辨率，即透光显示区1和周边显示区2内排布的用于显示的子像素的密度小于主体显示区3的子像素密度。
如图2所示，透光显示区1中的一个子像素的发光器件4包括阳极4A、阴极4C以及在阳极4A和阴极4C之间的发光层4B，阳极4A通过走线6连接至周边显示区2中的像素电路5，由此发光器件4由像素电路5控制、驱动。像素电路5包括一个或多个薄膜晶体管、电容等结构，在显示基板的平面中，这些结构的各膜层之间具有一定的间隙，即形成许多狭窄的缝隙，在显示基板的显示侧的光线可能通过透光显示区1斜向射入周边显示区2，并经过周边显示区2中的狭缝进入显示基板的背侧设置的传感器(例如图像传感器)中，相当于光线通过了开口率很低的光栅，因此会产生强烈的衍射现象，导致传感器例如在成像时的眩光现象加重，解析度降低，由此影响传感器的正常功能。
本公开至少一实施例提供一种显示基板和显示装置，该显示基板具有用于显示的第一侧和与第一侧相对的第二侧，显示基板包括显示区域，该显示区域包括第一显示区域以及至少部分围绕第一显示区域的第二显示区域，第一显示区域允许来自第一侧的光至少部分透射至第二侧；第一显示区域包括阵列排布的多个第一子像素，每个第一子像素包括第一发光器件，第二显示区域包括多个第一像素电路，多个第一像素电路分别与多个第一子像素的多个第一发光器件电连接，以分别驱动多个第一发光器件；该显示区域还包括第一遮光层，在垂直于显示基板的板面的方向上，第一遮光层与第二显示区域至少部分重叠，第一遮光层与第一显示区域不重叠。由此，在该实施例中，第一遮光层可以遮挡进入第二显示区域的光，以避免光线经过第二显示区域射入设置在显示基板的第 二侧的传感器中，从而提高该传感器的感测效果。
下面通过几个具体的实施例对本公开的显示基板和显示装置进行示例性说明。
本公开至少一实施例提供一种显示基板，图3示出了该显示基板的平面示意图。如图3所示，该显示基板具有用于显示的第一侧(即显示侧)和与第一侧相对的第二侧(即非显示侧，又可称为背侧)。该显示基板包括显示区域，该显示区域包括第一显示区域10以及至少部分围绕第一显示区域10的第二显示区域20，第一显示区域10允许来自第一侧的光至少部分透射至第二侧，也即第一显示区域10为透明显示区域，光线可从显示基板的显示侧通过透明显示区域到达非显示侧，非显示侧例如可以设置摄像头、红外感应装置等传感器，该传感器可采集并利用从第一显示区域10透射至非显示侧的光进行感测工作，例如进行成像等。
例如，图4A示出了显示区域中子像素的排布示意图。如图4A所示，第一显示区域10包括阵列排布的多个第一子像素P1，每个第一子像素P1包括第一发光器件EM1，多个第一发光器件EM1排列为阵列；第二显示区域20包括多个第一像素电路D1，多个第一像素电路D1分别与多个第一子像素P1的多个第一发光器件EM1电连接，以分别驱动多个第一发光器件EM1。即，第一显示区域10中的多个第一子像素P1的像素电路设置在第二显示区域20，由此可避免第一显示区域10中设置的结构过多或者具有不透光结构，从而保证第一显示区域10的透光性，有利于透射更多的用于被传感器感测的光，改善感测质量。例如，第二显示区域20还包括多个第二子像素P2，每个第二子像素P2包括第二发光器件EM2以及与第二发光器件EM2电连接的第二像素电路D2，第二像素电路D2配置为驱动第二发光器件EM2。在第二显示区域20中，多个第二像素电路D2呈第一阵列排布，多个第一像素电路D1设置在第一阵列的间隙中，并与多个第二像素电路D2整体排布为第二阵列，即，第一阵列为第二阵列的一个子阵列。例如，多个第一发光器件EM1和多个第二子像素P2(即多个第二发光器件EM2)分别在第一显示区域10和第二显示区域20中排列均匀，由此可以实现第一显示区域10和第二显示区域20整体上均匀发光与显示。
例如，图4B示出了一种具体的第一显示区域和第二显示区域中的子像素的排布示意图。如图4B所示，弧形虚线左侧为第二显示区域20，弧形虚线右侧为第一显示区域10。在第二显示区域20中，多个第二子像素P2的第二像素电路D2呈第一阵列排布，多个第一像素电路D1设置在第一阵列的间隙中，例如设置在虚线圈框出的部分，从而与多个第二像素电路D2整体排布为第二阵列，由此多个子像素P1的多个第一发光器件EM1和多个第二子像素P2(即多个第二发光器件EM2)分别在第一显示区域10和第二显示区域20中排列均匀。
例如，该显示区域还包括第一遮光层，在垂直于显示基板的板面的方向上，第一遮光层与第二显示区域20至少部分重叠，第一遮光层与第一显示区域10不重叠。由此，第一遮光层可以遮挡进入第二显示区域20且经过第二显示区域20中各种走线、电极或有源层之间的狭缝的光，以避免光线经过第二显示区域20到达显示基板的第二侧，从而 可以改善传感器的感测质量，例如提高屏下摄像头的拍摄质量。
例如，图5示出了本公开至少一实施例提供的一种显示基板的平面示意图，图6示出了该显示基板沿C-C线的截面示意图。如图5和图6所示，多个第一像素电路中的每个包括第一薄膜晶体管12，第一薄膜晶体管12包括第一有源层121、第一栅极122和第一源漏电极123和124等结构；例如，第一遮光层S1可以与第一源漏电极123和124同层设置，由此可以简化显示基板的制备工艺。
需要注意的是，在本公开的实施例中，“同层设置”为两个功能层或结构层在显示基板的层级结构中同层且同材料形成，例如，在制备工艺中，该两个功能层或结构层可以由同一个材料层形成，且可以通过同一构图工艺形成所需要的图案和结构。
例如，在一些实施例中，如图5和图6所示，第二显示区域20包括至少部分围绕第一显示区域10的第一子区20A以及至少部分围绕第一子区20A的第二子区20B，也即，第二子区20B相比于第一子区20A更远离第一显示区域10。第一遮光层S1设置在第一子区20A中，多个第一像素电路设置在第二子区20B中。例如，第一遮光层S1至少部分覆盖第一子区20A，例如，在一些示例中，第一遮光层S1完全覆盖第一子区20A，由此可以完全遮挡进入第二子区20B的光线。
例如，如图7所示，显示基板还包括多条信号线L，该多条信号线L在显示区域中沿图中的竖直方向延伸，在延伸方向上为了避免与第一显示区域10交叉，多条信号线L弯折并延伸经过第一子区20A，从而绕过第一显示区域10，在该第一子区20A中该多条信号线L例如彼此平行延伸且之间具有狭缝。又例如，该多条信号线L也可以在显示区域中沿图中的水平方向延伸，在延伸方向上为了避免与第一显示区域10交叉，多条信号线L弯折并延伸经过第一子区20A，从而绕过第一显示区域10，在该第一子区20A中该多条信号线L例如彼此平行延伸且之间具有狭缝。如图6所示，第一像素电路还包括第一存储电容13，第一存储电容13包括第一电容极板131和第二电容极板132，第一电容极板131与第一栅极122同层设置，多条信号线L与第一电容极板131或者第二电容极板132同层设置。例如，多条信号线L可以为数据线、扫描线(例如栅线、复位线、发光控制线等)、电源电压线等。
例如，在一些实施例中，如图8所示，第一遮光层S1在显示基板所在平面上的正投影完全覆盖第一子区20A中走线的多条信号线L在显示基板所在平面上的正投影，或者完全覆盖第一子区20A本身在显示基板所在平面上的正投影，从而在垂直于显示基板的板面的方向上，第一遮光层S1与多条信号线L重叠，由此遮挡了这些信号线L之间的一个或多个狭缝。
例如，在一些示例中，第一显示区域10可以为圆形、矩形、跑道形等合适的图形，图中示出为圆形作为示例。例如，第一显示区域10的尺寸D可以为3毫米-4毫米，例如3.2毫米、3.4毫米、3.6毫米等，从而可透过足够的光，例如用于成像。例如，上述第一显示区域10的尺寸可以为圆形的直径、正方形或者长方形的对角线等。例如，第一子区20A的宽度A，也即第一遮光层S1的设置宽度可以为0.1毫米-0.3毫米，例如0.1毫 米或者0.2毫米等，从而达到一定的遮光效果，且不影响显示区域的正常显示。
例如，在一些实施例中，显示基板还包括电源线和复位电压线(稍后详述)，第一遮光层S1与电源线或者复位电压线电连接。由此，第一遮光层S1中可被输入一定的直流电信号，以避免第一遮光层S1出现悬空状态，从而避免对显示基板上的信号传输造成影响。
例如，在另一些实施例中，第一遮光层S1也可以设置在显示基板的其他位置。
例如，图9是图3中的显示基板沿B-B线的截面示意图。如图9所示，显示基板还包括衬底基板14和第二遮光层S2，多个第一子像素设置在衬底基板14上，第二遮光层S2设置在多个第一像素电路与衬底基板14之间，以遮挡至少部分多个第一像素电路的电路结构，或者遮挡至少部分多个第二像素电路的电路结构。例如，第二遮光层S2至少遮挡第一薄膜晶体管12的有源层121，以避免光线从显示基板的第二侧射入有源层121而影响第一薄膜晶体管12的正常工作。例如，第二遮光层S2上覆盖有绝缘层14A，以与多个第一像素电路间隔；又例如，第二遮光层S2至少遮挡第一像素电路或第二像素电路的不同电极之间的狭缝，或者电极与信号线(例如栅线、数据线、电源线)之间的狭缝等。例如，第一遮光层S1与第二遮光层S2同层设置。例如，第一遮光层S1如上述实施例设置在第一子区20A，从而遮挡多条信号线L之间的一个或多个狭缝。注意，这里的A遮挡B指代的是B在显示基板所在平面上的正投影位于A在显示基板所在平面上的正投影之中。
例如，如图9所示，第一遮光层S1与第二遮光层S2可以间隔设置，或者，在一些实施例中，如图10所示，第一遮光层S1与第二遮光层S2为连续设置的一体化膜层，该一体化膜层在第一显示区域10具有开口，以使得在垂直于显示基板的板面的方向上，第一遮光层S1与第一显示区域10不重叠。
例如，如图11所示，第一遮光层S1与第二遮光层S2的一体化膜层可以完全覆盖除第一显示区域10以外的显示区域，以充分达到遮光作用。
例如，该示例中，第一遮光层S1与第二遮光层S2可以采用铜(Cu)、铝(Al)、钛(Ti)等具有良好遮光性的金属材料或者合金材料。
例如，在另一些实施例中，如图12所示，显示基板还包括衬底基板14和散热层SCF，多个第一子像素设置在衬底基板14的第一侧(图中示出为衬底基板14的上侧)，散热层SCF设置在衬底基板14的第二侧(图中示出为衬底基板14的下侧)，第一侧和第二侧相对。例如，第一遮光层S1与散热层SCF同层设置。例如，第一遮光层S1如上述实施例设置在第一子区20A，从而遮挡多条信号线L之间的一个或多个狭缝。
例如，第一遮光层S1与散热层SCF可以间隔设置，或者，参考图11和图12，第一遮光层S1与散热层SCF可以为连续设置的一体化膜层，该一体化膜层在第一显示区域10具有开口，以使得在垂直于显示基板的板面的方向上，第一遮光层S1与第一显示区域10不重叠。
例如，该示例中，第一遮光层S1与散热层SCF可以采用铜箔等金属层，以同时具 有良好的遮光效果和散热效果。例如，在显示基板的制备过程中，可以通过剪切形成具有一定形状与尺寸(例如图11所示的形状和尺寸)的铜箔，然后贴附在衬底基板14的第二侧，以同时实现良好的遮光效果和散热效果。
在本公开的实施例中，如图11所示，将第一遮光层S1与第二遮光层S2设置为连续的一体化膜层或者将第一遮光层S1与散热层SCF设置为连续的一体化膜层，可以达到完全遮挡第二显示区域20的技术效果，进而达到更加充分的遮光作用，提高屏下传感器的工作质量，例如提高屏下摄像头的拍照效果。
例如，在一些实施例中，不同的第一遮光层S1可以同时使用，例如图6、图9、图10以及图12中所示的第一遮光层S1中的任意两个或两个以上可以同时使用，以进一步提高遮光效果。例如，在一些实施例中，可以同时使用图10和图11所示的第一遮光层S1，或者同时使用图6和图11所示的第一遮光层S1，或者同时使用图6和图10第一遮光层S1，或者同时使用图9和图11所示的第一遮光层S1等，也即显示基板同时具有两个或两个以上第一遮光层S1，以进一步提高遮光效果。
例如，在一些实施例中，如图6、图9、图10以及图12所示，第一像素电路包括第一薄膜晶体管12，第一薄膜晶体管12包括第一有源层121、第一栅极122和第一源漏电极123和124，第一发光器件11包括第一电极111、第二电极113以及第一电极111和第二电极113之间的第一发光层112，第一发光器件11的第一电极111通过第一过孔V1与第一源漏电极124电连接。例如，第一发光器件11的第一电极111首先通过第一过孔V1与透明连接电极15电连接，再通过透明连接电极15与第一源漏电极124电连接。
例如，透明连接电极15可以采用透明导电材料，例如透明金属氧化物，例如氧化铟锡(ITO)等，以具有良好的透光性。通常，透明连接电极15比第一电极111具有更好的透光性，因此采用透明连接电极15将第一电极111与第一源漏电极124电连接可以进一步提高第一显示区域10的透光性。
如图13所示，第二像素电路包括第二薄膜晶体管22，第二薄膜晶体管22包括第二有源层221、第二栅极222和第二源漏电极223和224，第二发光器件21包括第一电极211、第二电极213以及第一电极211和第二电极213之间的第二发光层212，第二发光器件21的第一电极211通过第二过孔V2与第二源漏电极223电连接。
例如，在本公开的实施例中，显示基板还包括第一栅绝缘层141、第二栅绝缘层142、层间绝缘层143、第一平坦化层144、第二平坦化层145、像素界定层146以及封装层147等结构，本公开的实施例对显示基板的其他结构不做具体限定。
例如，上述各有源层可以采用非晶硅层、多晶硅层或金属氧化物半导体材料。例如，多晶硅可以为高温多晶硅或低温多晶硅，氧化物半导体可以为氧化铟镓锌(IGZO)、氧化铟锌(IZO)、氧化锌(ZnO)或氧化镓锌(GZO)等。各栅极可以采用铜(Cu)、铝(Al)、钛(Ti)等金属材料或者合金材料，例如形成为单层金属层结构或者多层金属层结构，例如钛/铝/钛等多层金属层结构。各有漏极可以采用铜(Cu)、铝(Al)、钛(Ti)等金属材料或者合金材料，例如形成为单层金属层结构或者多层金属层结构，例如钛/铝/钛等多 层金属层结构。
例如，各发光器件的第一电极的材料可以为氧化铟锡(ITO)、氧化铟锌(IZO)、氧化镓锌(GZO)等透明金属氧化物，第二电极的材料可以为锂(Li)、铝(Al)、镁(Mg)、银(Ag)等金属材料。
衬底基板14可以为玻璃、石英等刚性衬底基板或者聚酰亚胺等柔性衬底基板，第一栅绝缘层141、第二栅绝缘层142和层间绝缘层143可以采用氧化硅、氮化硅或者氮氧化硅等无机绝缘材料，第一平坦化层144、第二平坦化层145和像素界定层146可以采用聚酰亚胺、树脂等有机绝缘材料。
封装层147可以包括多个有机封装层和无机封装层的叠层。本公开的实施例对显示基板各功能层的材料和结构不做具体限定。
例如，各发光层可以为有机发光层或者量子点发光层等，由此，显示基板可以实现为有机发光二极管(OLED)显示基板或者量子点发光二极管(QLED)显示基板等，本公开的实施例对显示基板的种类不做具体限定。
例如，在显示基板所在平面内，即在平行于衬底基板14的平面内，第一过孔V1与第一发光层112的发光区域(即第一发光层112的正对夹置在第一电极111和第二电极113之间的区域)的最短距离小于第二过孔V2与第二发光层212的发光区域(即第二发光层212的正对夹置在第一电极211和第二电极213之间的区域)的最短距离。由此缩小第一显示区域10中第一电极111与其经过的过孔V1之间的距离，从而尽量减小第一电极111所占据的空间，增加第一显示区域10的光透过率。
例如，图14示出了第一显示区域10中的四个子像素的发光器件的发光区域和第一电极过孔的平面示意图，该四个子像素组成第一显示区域10中的一个像素单元。例如，该四个子像素包括一个红色子像素R、一个蓝色子像素B和两个绿色子像素G。例如，图15示出了第二显示区域20中的四个子像素的发光器件的发光区域和第一电极过孔的平面示意图，该四个子像素组成一个第二显示区域00中的一个像素单元。例如，该四个子像素包括一个红色子像素R、一个蓝色子像素B和两个绿色子像素G。
例如，以红色子像素R为例，结合图12-图15，第一过孔V1与第一发光层112的发光区域R1的最短距离小于第二过孔V2与第二发光层212的发光区域R2的最短距离d。
例如，在一些实施例中，如图12和图14所示，第一过孔V1在显示基板所在平面内的正投影与第一发光层112的发光区域R1在显示基板所在平面内的正投影至少部分重叠，此时，第一过孔V1与第一发光层112的发光区域R1的最短距离为0。如图13和图15所示，第二过孔V2在显示基板所在平面内的正投影与第二发光层212的发光区域R2在显示基板所在平面内的正投影不重叠，且第二过孔V2与第一发光层112的发光区域R2的最短距离为d，d大于0。
由此，在第一显示区域10中，第一过孔V1与第一发光层112的发光区域R1的距离更近，可避免第一电极111的延伸长度过长而影响第一显示区域10的透光性。
例如，在一些实施例中，如图3和图4A所示，显示区域还包括至少部分围绕第二显 示区域20的第三显示区域30，第三显示区域30包括阵列排布的多个第三子像素P3。例如，第三显示区域30中多个第三子像素P3的排布密度大于第一显示区域10中多个第一子像素P1的排布密度，也大于第二显示区域20中多个第二子像素P2的排布密度，从而第三显示区域30具有高于第一显示区域10和第二显示区域20的分辨率。并且，第三显示区域30所占据的面积大于第一显示区域10和第二显示区域20所占据的面积，第三显示区域30实现为显示基板的主体显示区域。
例如，在一些示例中，第一显示区域10中多个第一子像素P1的排布密度等于第二显示区域20中多个第二子像素P2的排布密度。例如，在一个示例中，第三显示区域30中所述多个第三子像素P3的排布密度为第一显示区域10中多个第一子像素P1的排布密度的二倍。
例如，第三显示区域30中的每个第三子像素P3包括第三像素电路和第三发光器件，第三像素电路和第三发光器件的具体结构与第二像素电路和第二发光器件的机构相似，具体可参见图13，这里不再赘述。
例如，在一些实施例中，如图16所示，显示基板还包括分别位于显示区域相对两侧的第一扫描驱动电路(Gate on Array)GOA1和第二扫描驱动电路GOA2，第一扫描驱动电路GOA1和第二扫描驱动电路GOA2共同为在第三显示区域30中的多个第三子像素提供电信号，即在第三显示区域30中，GOA驱动电路采用双边驱动方式，第三显示区域30左右两侧扫描驱动电路相互连通。
例如，第一扫描驱动电路GOA1还为位于第一显示区域10靠近第一扫描驱动电路GOA1一侧的第二显示区域20中的多个第二子像素以及多个第一像素电路提供电信号，例如为图8中虚线左侧的第二显示区域20中的多个第二子像素以及多个第一像素电路提供电信号；第二扫描驱动电路GOA2还为位于第一显示区域10靠近第二扫描驱动电路GOA2一侧的第二显示区域20中的多个第二子像素以及多个第一像素电路提供电信号，例如为图8中虚线右侧的第二显示区域20中的多个第二子像素以及多个第一像素电路提供电信号。也即，对于第一显示区域10和第二显示区域20,GOA驱动电路采用单边驱动方式，第一显示区域10和第二显示区域20两侧的用于为第一显示区域10和第二显示区域20提供电信号的扫描驱动电路不相互连通。
例如，如上所述，显示基板还包括电源线和复位电压线，第一遮光层S1与电源线或者复位电压线电连接，以避免第一遮光层S1出现悬空状态。下面，结合附图示例性介绍显示基板的驱动电路以及电源线和复位电压线的连接关系。
例如，在一些示例中，显示基板中的第一像素电路、第二像素电路、第三像素电路可以采用2T1C、7T1C等像素驱动电路。例如，图17示出了一种7T1C像素电路的电路图。如图17所示，该像素电路包括驱动晶体管T1、数据写入晶体管T2、补偿晶体管T3、存储电容C、第一发光控制晶体管T4、第二发光控制晶体管T5、第一复位晶体管T6和第二复位晶体管T7。
例如，驱动晶体管T1包括控制端、第一端和第二端，其配置为控制流经发光器件 EM的驱动电流，且驱动晶体管T1的控制端和第一节点N1连接，驱动晶体管T1的第一端和第二节点N2连接，驱动晶体管T1的第二端和第三节点N3连接。
例如，数据写入晶体管T2包括控制端、第一端和第二端，其控制端配置为接收第一扫描信号Ga1，第一端配置为接收数据信号，第二端与驱动晶体管T1的第一端(第二节点N2)连接，且配置为响应于该第一扫描信号Ga1将该数据信号写入驱动晶体管T1的第一端。例如，数据写入晶体管T2的第一端与数据线连接以接收该数据信号，控制端与扫描线连接以接收该第一扫描信号Ga1。
例如，在数据写入阶段，数据写入晶体管T2可以响应于第一扫描信号Ga1而开启，从而可以将数据信号写入驱动晶体管T1的第一端(第二节点N2)，并将数据信号存储在存储电容C中，以在例如发光阶段时可以根据该数据信号生成驱动发光器件EM发光的驱动电流。
例如，补偿晶体管T3包括控制端、第一端和第二端，其控制端配置为接收第二扫描信号Ga2，其第一端和第二端分别与驱动晶体管T1的控制端和第二端电连接，该补偿电路配置为响应于该第二扫描信号进行阈值补偿。
例如，存储电容C与驱动晶体管T1的控制端及第一电压端VDD电连接，配置为存储数据写入晶体管T2写入的数据信号。例如，在数据写入和补偿阶段，补偿晶体管T3可以响应于该第二扫描信号Ga2而开启，从而可以将数据写入晶体管T2写入的数据信号存储在该存储电容C中。例如，同时在数据写入和补偿阶段，补偿晶体管T3可以将驱动晶体管T1的控制端和第二端电连接，从而可以使驱动晶体管T1的阈值电压的相关信息也相应地存储在该存储电路中，从而例如在发光阶段可以利用存储的数据信号以及阈值电压对驱动晶体管T1进行控制，使得驱动晶体管T1的输出得到补偿。
例如，第一发光控制晶体管T4与驱动晶体管T1的第一端(第二节点N2)以及第一电压端VDD连接，且配置为响应于第一发光控制信号将第一电压端VDD的第一电源电压施加至驱动晶体管T1的第一端。例如，第一发光控制晶体管T4和第一发光控制端Em1、第一电压端VDD以及第二节点N2连接。
例如，第二发光控制晶体管T5和第二发光控制端Em2、发光器件EM的第一端以及驱动晶体管T1的第二端连接，且配置为响应于第二发光控制信号使得驱动电流可被施加至发光器件EM。
例如，在发光阶段，第二发光控制晶体管T5响应于第二发光控制端Em2提供的第二发光控制信号而开启，从而驱动晶体管T1可以通过第二发光控制晶体管T5将驱动电流施加至发光器件EM以使其发光；而在非发光阶段，第二发光控制晶体管T5响应于第二发光控制信号而截止，从而避免有电流流过发光器件EM而使其发光，可以提高相应的显示装置的对比度。
又例如，在初始化阶段，第二发光控制晶体管T5也可以响应于第二发光控制信号而开启，从而可以结合复位电路以对驱动晶体管T1以及发光器件EM进行复位操作。
例如，第二发光控制信号Em2可以与第一发光控制信号Em1相同或不同，例如二 者可以连接到相同或不同的信号输出端。
例如，第一复位晶体管T6配置为响应于第一复位信号Rst1将第一复位电压Vini1施加到第一节点N1，该第二复位晶体管T7配置为响应于第二复位信号Rst2将第二复位电压Vini2施加到第四节点N4。例如，在初始化阶段，第一复位晶体管T6和第二复位晶体管T7可以响应于复位信号而开启，从而可以将复位电压施加至发光器件EM的第一端及第一节点N1，从而可以对驱动晶体管T1、补偿晶体管T3以及发光器件EM进行复位操作，消除之前的发光阶段的影响。
例如，发光器件EM包括第一端和第二端，发光器件EM的第一端配置为从驱动晶体管T1的第二端接收驱动电流，发光器件EM的第二端配置为与第二电压端VSS连接。例如，发光器件EM的第一端可以连接至第三节点N3。
需要注意的是，第一节点N1、第二节点N2、第三节点N3和第四节点N4并非一定表示实际存在的部件，而是表示电路图中相关电路连接的汇合点。符号Vd既可以表示数据信号端又可以表示数据信号的电平，同样地，符合Ga1、Ga2既可以表示第一扫描信号、第二扫描信号，也可以表示第一扫描信号端和第二扫描信号端，Rst既可以表示复位控制端又可以表示复位信号，符号Vinit既可以表示复位电压端又可以表示复位电压，符号VDD既可以表示第一电压端又可以表示第一电源电压，符号VSS既可以表示第二电压端又可以表示第二电源电压。以下各实施例与此相同，不再赘述。例如，在一些是来自红，第二电压端可以接地，即VSS可以为0V。
例如，第一遮光层S1可以与传输上述第一电源电压VDD或者第二电源电压VSS的电源线电连接，或者与传输复位电压Vini1或Vini2的复位电压线电连接。例如，当第一遮光层S1与电源线或者复位电压线同层设置时，该第一遮光层S1可以通过连接走线直接与电源线或者复位电压线电连接，或者，当第一遮光层S1与电源线或者复位电压线不同层设置时，该第一遮光层S1可以通过过孔与电源线或者复位电压线电连接。
例如，当第一遮光层S1与电源线或者复位电压线在垂直于显示基板的板面的方向交叠时，可以直接在第一遮光层S1与电源线或者复位电压线之间形成过孔，以使第一遮光层S1通过该过孔与电源线或者复位电压线电连接。或者，当第一遮光层S1与电源线或者复位电压线在垂直于显示基板的板面的方向不交叠时，可以将遮光层S1延伸至与电源线或者复位电压线交叠的位置，进而在二者之间形成过孔，并进行电连接；或者，将电源线或者复位电压线延伸至与第一遮光层S1交叠的位置，进而在二者之间形成过孔，并进行电连接。例如，也可以采用连接走线将电源线或者复位电压线引入到与第一遮光层S1交叠的位置，进而在连接走线与第一遮光层S1之间形成过孔，并进行电连接。在本公开的实施例中，可以通过任意合适的方式将第一遮光层S1与电源线或者复位电压线电连接，本公开的实施例对第一遮光层S1与电源线或者复位电压线电连接的方式不做具体限定。由此第一遮光层S1可被传输一定的电源电压或者复位电压，可避免第一遮光层S1出现悬空状态而对显示基板上的信号传输造成影响。
综上，本公开的至少一个实施例提供的显示基板中，第一遮光层可以有效遮挡至少 部分进入第二显示区域的光，以避免光线经过第二显示区域射入屏下传感器，例如摄像头，从而改善感测效果，例如提高屏下摄像头的拍摄质量。并且，该第一遮光层可被输入一定的电信号，从而不会影响显示基板中的驱动电路的正常工作。另外，该第一遮光层可以与显示基板中现有的某些功能层同层设置，从而在制备工艺中可以采用相同的材料通过相同的工艺形成，由此还可以简化显示基板的制备工艺，即在不增加显示基板制备难度的情况下，提高了显示基板的屏下传感器，例如摄像头的工质质量，并且还实现了显示基板的窄边框设计。
本公开至少一实施例还提供一种显示装置，如图18A所示，该显示装置包括上述任一的显示基板(图18A中示出为图6中的显示基板作为示例)以及传感器19。传感器19设置于显示基板的第二侧(非显示侧)，且传感器配置为接收来自第一侧(显示侧)的光。例如，传感器19可以为摄像头、红外传感器等任意形式的传感器。
例如，图18B示出了本公开至少一实施例提供的另一种显示装置的截面示意图。如图18B所示，该显示装置中的第一遮光层S1与散热层SCF同层设置，例如采用与图12所示的显示基板中第一遮光层S1的设置方式。与图12所示的显示基板不同的是，在图18B中，第一发光器件的第一电极111直接通过暴露源漏极124的过孔与第一源漏极124电连接，从而节省了透明连接电极15以及第二平坦化层145，简化了显示基板的膜层结构。
例如，在一些实施例中，在垂直于显示基板的板面的方向上，传感器19与显示基板的第一显示区域10至少部分重叠，从而可充分接受来自第一侧的光，并基于该光进行工作。由于该显示基板中具有遮挡第二显示区域的第一遮光层，因此该传感器19只接受到从第一显示区域透过的光，可避免光透光第二显示区域达到传感器19而对传感器19的工作造成影响，因此该显示装置的传感器19具有较高的工作质量，例如当传感器19为摄像头时，该摄像头具有较高的拍照质量。
例如，本公开至少一实施例提供的显示装置可以为显示基板、显示面板、电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，本公开的实施例对此不作限制。
例如，图19A和图19B分别示出了显示装置在没有第一遮光层和有第一遮光层时点光源成像的点扩散函数仿真图，该仿真图描述的是屏下摄像头通过点光源成像后，在成像面的能量分布状态，即能量在上下左右等各个方向(体现在XY坐标中)的弥散分布，由此可以直观地表征点光源眩光情况。如图19A所示，在第二显示区域没有设置第一遮光层时，斜视场角下，光线穿过第二显示区域，类似于通过开口率很小的光栅，此时，点光源成像的中心能量峰值仅10.5，点光源眩光现象严重。如图19B所示，在第二显示区域设置第一遮光层后，斜视场角下，光线只能通过第一显示区域，点光源成像的中心能量峰值大于11，点光源眩光现象得到显著改善。
图20A和图20B示出了显示装置在没有第一遮光层和有第一遮光层时点光源成像在子午面和弧氏面的调制传递函数(Moduation transfer function)图，图中的横坐标数值代 表空间频率(即每毫米的空间线对，单位为lp/mm)，纵坐标是MTF值，用来表征不同空间频率下的解析度。在相同的空间频率下，MTF值越高，成像解析度越高。在图19A和图19B中，F0曲线为显示装置在没有第一遮光层时点光源成像的调制传递函数曲线，F1曲线为显示装置在设置第一遮光层后点光源成像的调制传递函数曲线，可见，相同的空间频率下，F1曲线的MTF值均高于F0曲线的MTF值，即设置第一遮光层后，显示装置点光源成像的解析度显著提升。
例如，图21A示出了显示装置在没有第一遮光层时点光源成像的眩光实拍照片，图21B示出了显示装置在设置有第一遮光层后点光源成像的眩光实拍照片，通过对比图21A和图21B看出，在设置第一遮光层后，显示装置点光源成像的眩光现象得到明显改善。
还有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大或缩小，即这些附图并非按照实际的比例绘制。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”或者可以存在中间元件。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以权利要求的保护范围为准。

Claims (17)

  1. 一种显示基板，具有用于显示的第一侧和与所述第一侧相对的第二侧，所述显示基板包括显示区域，
    其中，所述显示区域包括第一显示区域以及至少部分围绕所述第一显示区域的第二显示区域，所述第一显示区域允许来自所述第一侧的光至少部分透射至所述第二侧；
    所述第一显示区域包括阵列排布的多个第一子像素，每个第一子像素包括第一发光器件，
    所述第二显示区域包括多个第一像素电路，所述多个第一像素电路分别与所述多个第一子像素的多个第一发光器件电连接，以分别驱动所述多个第一发光器件；
    其中，所述显示区域还包括第一遮光层，在垂直于所述显示基板的板面的方向上，所述第一遮光层与所述第二显示区域至少部分重叠，所述第一遮光层与所述第一显示区域不重叠。
  2. 根据权利要求1所述的显示基板，还包括电源线和复位电压线，
    其中，所述第一遮光层与所述电源线或者所述复位电压线电连接。
  3. 根据权利要求1或2所述的显示基板，其中，所述多个第一像素电路中的每个包括第一薄膜晶体管，所述第一薄膜晶体管包括第一有源层、第一栅极和第一源漏电极；
    所述第一遮光层与所述第一源漏电极同层设置。
  4. 根据权利要求3所述的显示基板，其中，所述第二显示区域包括至少部分围绕所述第一显示区域的第一子区以及至少部分围绕所述第一子区的第二子区，
    所述第一遮光层设置在所述第一子区中，所述多个第一像素电路设置在所述第二子区中。
  5. 根据权利要求4所述的显示基板，还包括分别电连接所述多个第一像素电路的多条信号线，所述多条信号线延伸经过所述第一子区，
    所述第一像素电路还包括第一存储电容，所述第一存储电容包括第一电容极板和第二电容极板，
    所述第一电容极板与所述第一栅极同层设置，所述多条信号线与所述第一电容极板或者所述第二电容极板同层设置。
  6. 根据权利要求1或2所述的显示基板，还包括衬底基板和第二遮光层，其中，所述多个第一子像素设置在所述衬底基板上，所述第二遮光层设置在所述多个第一像素电路与所述衬底基板之间，以遮挡至少部分所述多个第一像素电路的电路结构；
    所述第一遮光层与所述第二遮光层同层设置。
  7. 根据权利要求6所述的显示基板，其中，所述第一遮光层与所述第二遮光层为连续设置的一体化膜层，所述一体化膜层在所述第一显示区域具有开口，以使得在垂直于所述显示基板的板面的方向上，所述第一遮光层与所述第一显示区域不重叠。
  8. 根据权利要求1或2所述的显示基板，还包括衬底基板和散热层，其中，所述多 个第一子像素设置在所述衬底基板的第一侧，所述散热层设置在所述衬底基板的第二侧，所述第一侧和所述第二侧相对；
    所述第一遮光层与所述散热层同层设置。
  9. 根据权利要求8所述的显示基板，其中，所述第一遮光层与所述散热层为连续设置的一体化膜层，所述一体化膜层在所述第一显示区域具有开口，以使得在垂直于所述显示基板的板面的方向上，所述第一遮光层与所述第一显示区域不重叠。
  10. 根据权利要求1-9任一所述的显示基板，其中，所述第二显示区域还包括多个第二子像素，每个第二子像素包括第二发光器件以及与所述第二发光器件电连接的第二像素电路，所述第二像素电路配置为驱动所述第二发光器件，
    在所述第二显示区域中，所述多个第二像素电路呈第一阵列排布，所述多个第一像素电路设置在所述第一阵列的间隙中，并与所述多个第二像素电路整体排布为第二阵列。
  11. 根据权利要求10所述的显示基板，其中，所述第一像素电路包括第一薄膜晶体管，所述第一薄膜晶体管包括第一有源层、第一栅极和第一源漏电极，所述第一发光器件包括第一电极、第二电极以及所述第一电极和所述第二电极之间的第一发光层，所述第一发光器件的第一电极通过第一过孔与所述第一源漏电极电连接；
    所述第二像素电路包括第二薄膜晶体管，所述第二薄膜晶体管包括第二有源层、第二栅极和第二源漏电极，所述第二发光器件包括第一电极、第二电极以及所述第一电极和所述第二电极之间的第二发光层，所述第二发光器件的第一电极通过第二过孔与所述第二源漏电极电连接；
    在所述显示基板所在平面内，所述第一过孔与所述第一发光层的发光区域的最短距离小于所述第二过孔与所述第二发光层的发光区域的最短距离。
  12. 根据权利要求11所述的显示基板，其中，所述第一过孔在所述显示基板所在平面内的正投影与所述第一发光层的发光区域在所述显示基板所在平面内的正投影至少部分重叠。
  13. 根据权利要求1-12任一所述的显示基板，其中，所述显示区域包括至少部分围绕所述第二显示区域的第三显示区域，所述第三显示区域包括阵列排布的多个第三子像素，
    其中，所述第三显示区域中所述多个第三子像素的排布密度大于所述第一显示区域中所述多个第一子像素的排布密度，也大于所述第二显示区域中所述多个第二子像素的排布密度。
  14. 根据权利要求13所述的显示基板，其中，所述第一显示区域中所述多个第一子像素的排布密度等于所述第二显示区域中所述多个第二子像素的排布密度。
  15. 根据权利要求13或14所述的显示基板，还包括分别位于所述显示区域相对两侧的第一扫描驱动电路和第二扫描驱动电路，其中，
    所述第一扫描驱动电路和第二扫描驱动电路共同为在所述第三显示区域中的多个第三子像素提供电信号；
    所述第一扫描驱动电路还为位于所述第一显示区域靠近所述第一扫描驱动电路一侧的第二显示区域中的多个第二子像素和多个第一像素电路提供电信号，所述第二扫描驱动电路还为位于所述第一显示区域靠近所述第二扫描驱动电路一侧的第二显示区域中的多个第二子像素和多个第一像素电路提供电信号。
  16. 一种显示装置，包括：
    权利要求1-15任一所述的显示基板，以及
    传感器，
    其中，所述传感器设置于所述显示基板的第二侧，且所述传感器配置为接收来自所述第一侧的光。
  17. 根据权利要求16所述的显示装置，其中，在垂直于所述显示基板的板面的方向上，所述传感器与所述显示基板的第一显示区域至少部分重叠。
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