WO2022227478A1 - 一种显示基板及其制作方法、显示装置 - Google Patents

一种显示基板及其制作方法、显示装置 Download PDF

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Publication number
WO2022227478A1
WO2022227478A1 PCT/CN2021/129212 CN2021129212W WO2022227478A1 WO 2022227478 A1 WO2022227478 A1 WO 2022227478A1 CN 2021129212 W CN2021129212 W CN 2021129212W WO 2022227478 A1 WO2022227478 A1 WO 2022227478A1
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Prior art keywords
transistor
capacitor
electrically connected
electrode
plate
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PCT/CN2021/129212
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English (en)
French (fr)
Inventor
代俊秀
白露
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Publication of WO2022227478A1 publication Critical patent/WO2022227478A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]

Definitions

  • the embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and in particular, relate to a display substrate, a manufacturing method thereof, and a display device.
  • OLED Organic Light Emitting Diode
  • the driving circuit is an important auxiliary circuit in OLED.
  • the present disclosure provides a display substrate, comprising: a display area and a non-display area, including: a base substrate, a driving circuit and a first power supply line disposed on the base substrate and located in the non-display area , the drive circuit at least includes: a first capacitor, a second capacitor and a third capacitor; the first capacitor and the third capacitor are arranged along the first direction, and the second capacitor and the third capacitor are respectively are located on both sides of the first capacitor, the second capacitor is located on the side of the first capacitor close to the display area, and a pole plate of the third capacitor is electrically connected to the first power line;
  • the first power line extends along a first direction, and the orthographic projection of the first capacitor on the base substrate at least partially overlaps the orthographic projection of the first power line on the base substrate.
  • the orthographic projection of the third capacitor on the base substrate at least partially overlaps the orthographic projection of the first power line on the base substrate.
  • the display substrate further includes: a second power supply line, an initial signal line, a first clock signal line and a second clock signal line, which are disposed on the base substrate and located in the non-display area. ;
  • the second power line is located on the side of the drive circuit close to the display area and extends in the first direction
  • the initial signal line is located on the side of the first power line away from the display area and extends in the first direction
  • a clock signal line is located between the first power supply line and the initial signal line and extends in a first direction
  • the second clock signal line is located between the first clock signal line and the initial signal line , and extends along the first direction;
  • the width of the second power line is smaller than or equal to the width of the first power line, and/or the width of the initial signal line is smaller than the width of the first power line, and/or the first clock
  • the width of the signal line is smaller than the width of the first power line and larger than the width of the initial signal line, and/or the width of the second clock signal line is smaller than the width of the first power line and larger than the initial signal line width.
  • the driving circuit includes: a plurality of shift registers arranged along the first direction, each shift register includes: a first transistor to a tenth transistor, a first capacitor to a third capacitor, a signal input terminal, a signal output terminal, a first clock signal terminal, a second clock signal terminal, a first power supply terminal and a second power supply terminal;
  • the gate electrode of the first transistor is electrically connected to the first clock signal terminal, the source electrode of the first transistor is electrically connected to the signal input terminal, and the drain electrode of the first transistor is electrically connected to the first node;
  • the gate electrode of the second transistor is electrically connected to the first node, the source electrode of the second transistor is electrically connected to the first clock signal terminal, and the second electrode of the second transistor is electrically connected to the second node;
  • the gate electrode of the third transistor is electrically connected to the first clock signal terminal, the source electrode of the third transistor is electrically connected to the second power supply terminal, and the second pole of the third transistor is electrically connected to the second node;
  • the gate electrode of the fourth transistor is electrically connected to the second clock signal terminal, the source electrode of the fourth transistor is electrically connected to the first node, and the drain electrode of the fourth transistor is electrically connected to the source electrode of the fifth transistor. connect;
  • the gate electrode of the fifth transistor is electrically connected to the second node, and the drain electrode of the fifth transistor is electrically connected to the first power supply terminal;
  • the gate electrode of the sixth transistor is electrically connected to the second node, the source electrode of the sixth transistor is electrically connected to the second clock signal terminal, and the drain electrode of the sixth transistor is electrically connected to the third node;
  • the gate electrode of the seventh transistor is electrically connected to the second clock signal terminal, the source electrode of the seventh transistor is electrically connected to the third node, and the drain electrode of the seventh transistor is electrically connected to the fourth node;
  • the gate electrode of the eighth transistor is electrically connected to the first node, the source electrode of the eighth transistor is electrically connected to the first power supply terminal, and the drain electrode of the eighth transistor is electrically connected to the fourth node;
  • the gate electrode of the ninth transistor is electrically connected to the fourth node, the source electrode of the ninth transistor is electrically connected to the signal output terminal, and the drain electrode of the ninth transistor is electrically connected to the first power supply terminal;
  • the gate electrode of the tenth transistor is electrically connected to the first node, the source electrode of the tenth transistor is electrically connected to the second power supply terminal, and the drain electrode of the tenth transistor is electrically connected to the signal output terminal;
  • the first plate of the first capacitor is electrically connected to the second node, and the second plate of the first capacitor is electrically connected to the third node;
  • the first plate of the second capacitor is electrically connected to the first node, and the second plate of the second capacitor is electrically connected to the second clock signal terminal;
  • the first plate of the third capacitor is electrically connected to the fourth node, and the second plate of the third capacitor is electrically connected to the first power supply terminal.
  • the first electrode plate of the first capacitor is located on a side of the second electrode plate of the first capacitor close to the substrate, and the first electrode plate of the first capacitor is on the substrate
  • the orthographic projection on the base substrate covers the orthographic projection of the second electrode plate of the first capacitor on the base substrate;
  • the first electrode plate of the second capacitor is located on the side of the second electrode plate of the second capacitor close to the base substrate, and the orthographic projection of the first electrode plate of the second capacitor on the base substrate covers the entire surface. the orthographic projection of the second pole plate of the second capacitor on the base substrate;
  • the first electrode plate of the third capacitor is located on the side of the second electrode plate of the third capacitor close to the base substrate, and the orthographic projection of the first electrode plate of the third capacitor on the base substrate covers all parts. the orthographic projection of the second pole plate of the third capacitor on the base substrate;
  • the area of the overlapping portion of the first plate of the first capacitor and the first power line is positively correlated with the area of the first plate of the first capacitor, and the first plate of the third capacitor
  • the area of the overlapping portion with the first power line is positively correlated with the area of the first plate of the third capacitor;
  • the area of the overlapping portion of the first electrode plate of the first capacitor and the first power supply line is smaller than the area of the overlapping portion of the first electrode plate of the third capacitor and the first power supply line.
  • a plurality of shift registers in the driving circuit are cascaded, the signal input terminal of the first stage shift register is electrically connected to the initial signal line, and the signal output of the i-1th stage shift register is The terminal is electrically connected to the signal input terminal of the i-th stage shift register, the first power supply terminal of all shift registers is electrically connected to the first power supply line, the second power supply terminal of the shift register is electrically connected to the second power supply line, The first clock signal terminal of the odd-numbered shift registers is electrically connected to the first clock signal line, the second clock signal terminal of the odd-numbered shift registers is electrically connected to the second clock signal line, and the first clock signal of the even-numbered shift registers The terminal is electrically connected to the second clock signal line, and the second clock signal terminal of the even-numbered shift register is electrically connected to the first clock signal line, wherein i is a positive integer greater than or equal to 2.
  • the display substrate further includes: sub-pixels arranged on the base substrate and arranged in an array in the display area;
  • the signal output terminal of the shift register of the i-th stage is electrically connected with the sub-pixels in the 2i-1th row and the sub-pixels in the 2i-th row.
  • each shift register includes: connection electrodes and output signal lines arranged in different layers;
  • the output signal line is electrically connected to the signal output end of the shift register of the current stage, and the orthographic projection of the connection electrode on the base substrate at least partially overlaps the orthographic projection of the output signal line on the base substrate;
  • connection electrodes are respectively electrically connected to the signal output end of the shift register of the current stage and the signal input end of the shift register of the next stage.
  • the display substrate includes: a semiconductor layer, a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, a third an insulating layer and a third metal layer;
  • the semiconductor layer includes: active layers of a plurality of transistors, and the first metal layer includes: gate electrodes of the plurality of transistors, a first electrode plate of a first capacitor, a first electrode plate of a second capacitor, and a third capacitor
  • the first electrode plate, the second metal layer includes: the second electrode plate of the first capacitor, the second electrode plate of the second capacitor, the second electrode plate of the third capacitor and the output signal line
  • the third metal layer includes: source electrodes of a plurality of transistors, drain electrodes of a plurality of transistors, a first power supply line, a second power supply line, a first clock signal line, a second clock signal line, an initial signal line, and a connection electrode;
  • the resistance of the third metal layer is smaller than the resistance of the first metal layer and is smaller than the resistance of the second metal layer.
  • the active layers of all transistors include: a channel region and source and drain connections on both sides of the channel region, and the source electrodes of the transistors are connected to The source connecting part is electrically connected, and the drain electrode of the transistor is electrically connected with the drain connecting part;
  • the drain connection part of the active layer of the fourth transistor is multiplexed as a drain electrode
  • the source connection part of the active layer of the fifth transistor is multiplexed as a source electrode
  • the drain connection part of the active layer of the fourth transistor is multiplexed with the source electrode.
  • the source connections of the active layers of the five transistors are electrically connected.
  • the gate electrode of the second transistor, the gate electrode of the tenth transistor, the gate electrode of the eighth transistor, and the first electrode plate of the second capacitor are integrally formed into a structure,
  • the gate electrode of the fifth transistor, the gate electrode of the sixth transistor and the first plate of the first capacitor are integrally formed, and the gate electrode of the ninth transistor and the first plate of the third capacitor are integrally formed;
  • the drain electrode of the first transistor and the source electrode of the fourth transistor are integrally formed, the drain electrode of the second transistor and the drain electrode of the third transistor are integrally formed, and the source electrode of the third transistor, the source electrode of the tenth transistor and the drain electrode of the third transistor are integrally formed.
  • Two power lines are integrally formed, the drain electrode of the sixth transistor and the source electrode of the seventh transistor are integrally formed, the drain electrode of the seventh transistor and the drain electrode of the eighth transistor are integrally formed, the source electrode of the eighth transistor,
  • the drain electrode of the ninth transistor, the drain electrode of the fifth transistor and the first power supply line are integrally formed.
  • the first transistor, the second transistor, the third transistor, the fourth transistor and the fifth transistor are located at a distance from the first capacitor away from the third capacitor one side of the second capacitor close to the first power line; the sixth transistor is located on the side of the first capacitor close to the second power line, and located on one side of the second capacitor close to the third capacitor On the side, the seventh transistor and the eighth transistor are located between the first capacitor and the third capacitor, and the ninth transistor and the tenth transistor are located at a part of the second capacitor close to the second power line side.
  • the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor The active layers of the transistor, the seventh transistor, the ninth transistor, and the tenth transistor extend along the first direction, the active layer of the eighth transistor extends along the second direction, and the sixth transistor extends along the second direction.
  • the source electrode and the drain electrode are arranged along the first direction;
  • the first direction and the second direction intersect.
  • the distance between the first power line and the edge of the first capacitor close to the second power line is smaller than the distance between the first power line and the source electrode of the sixth transistor.
  • the output signal line in each shift register includes: a first connection part, a second connection part, a third connection part and a fourth connection part that are integrally formed;
  • the orthographic projection of the first connection portion on the base substrate at least partially overlaps with the orthographic projection of the source electrode of the ninth transistor on the base substrate, and at least partially overlaps with the orthographic projection of the drain electrode of the tenth transistor on the base substrate. partially overlapping, the first connecting portion extends along the first direction;
  • the second connection portion, the third connection portion, and the fourth connection portion extend along the second direction, and the second connection portion and the third connection portion are located at the first connection portion away from the first power source one side of the line, the fourth connection part is located on the side of the first connection part close to the first power line;
  • connection part is electrically connected with the sub-pixels in the 2i-1 row
  • third connection part is electrically connected with the sub-pixels in the 2i row
  • fourth connection part is electrically connected with the signal input terminal of the next stage shift register. connect
  • connection electrode on the base substrate at least partially overlaps with the orthographic projection of the fourth connection portion on the base substrate, and the fourth connection portion is input with the signal of the next-stage shift register through the connection electrode terminal electrical connection.
  • the display substrate further includes: a first through hole to a first through hole penetrating the first insulating layer, the second insulating layer and the third insulating layer ten vias;
  • the first via hole exposes the active layer of the first transistor
  • the second via hole exposes the active layer of the second transistor
  • the third via hole exposes the active layer of the third transistor
  • the The fourth via exposes the active layer of the fourth transistor
  • the fifth via exposes the active layer of the fifth transistor
  • the sixth via exposes the active layer of the sixth transistor
  • the seventh via exposes the active layer of the sixth transistor.
  • the via hole exposes the active layer of the seventh transistor
  • the eighth via hole exposes the active layer of the eighth transistor
  • the ninth via hole exposes the active layer of the ninth transistor
  • the tenth via hole exposing the active layer of the tenth transistor;
  • the source electrode and the drain electrode of the first transistor are electrically connected to the active layer of the first transistor through the first via hole
  • the source electrode and the drain electrode of the second transistor are electrically connected to the active layer of the second transistor through the second via hole
  • the source electrode and the drain electrode of the third transistor are electrically connected to the active layer of the third transistor through the third via hole
  • the source electrode and the drain electrode of the fourth transistor are electrically connected to the active layer of the fourth transistor through the fourth via hole
  • the source electrode and the drain electrode of the fifth transistor are electrically connected to the active layer of the fifth transistor through the fifth via hole
  • the source electrode and the drain electrode of the sixth transistor are electrically connected to the active layer of the sixth transistor through the sixth via hole
  • the source electrode and the drain electrode of the seventh transistor are electrically connected to the active layer of the seventh transistor through the seventh via hole
  • the source electrode and the drain electrode of the eighth transistor are electrically connected to the active layer of the eighth transistor through the eighth via hole
  • the source electrode and the drain electrode of the ninth transistor are electrically
  • the display substrate further includes: eleventh to sixteenth via holes penetrating the second insulating layer and the third insulating layer;
  • the eleventh via hole exposes the gate electrode of the first transistor
  • the twelfth via hole exposes the gate electrode of the second transistor
  • the thirteenth via hole exposes the gate electrode of the fourth transistor
  • the The fourteenth via hole exposes the gate electrode of the fifth transistor
  • the sixteenth via hole exposes the first plate of the third capacitor
  • the source electrode of the second transistor is electrically connected to the gate electrode of the first transistor through the eleventh via hole
  • the drain electrode of the first transistor is electrically connected to the gate electrode of the second transistor through the twelfth via hole
  • the source electrode of the sixth transistor is electrically connected
  • the electrode is electrically connected to the gate electrode of the fourth transistor through the thirteenth via hole
  • the drain electrode of the third transistor is electrically connected to the gate electrode of the fifth transistor through the fourteenth via hole
  • the drain electrode of the seventh transistor is electrically connected to the gate electrode of the fifth transistor through the sixteenth through hole.
  • the hole is electrically connected to the first plate of the third capacitor.
  • the display substrate further includes: seventeenth via holes to twenty-first via holes disposed on the third insulating layer;
  • the seventeenth via hole exposes the second electrode plate of the first capacitor
  • the eighteenth via hole exposes the second electrode plate of the second capacitor
  • the nineteenth via hole exposes the first electrode plate of the third capacitor.
  • Diode plate, the twentieth via hole exposes the first connection portion of the signal output end, and the twenty-first via hole exposes the fourth connection portion of the signal output end;
  • the drain electrode of the sixth transistor is electrically connected to the second plate of the first capacitor through the seventeenth via hole, the source electrode of the sixth transistor is electrically connected to the second plate of the second capacitor through the eighteenth through hole, and the ninth The drain electrode of the transistor is electrically connected to the second plate of the third capacitor through the nineteenth via hole, the source electrode of the ninth transistor and the drain electrode of the tenth transistor are electrically connected to the signal output terminal through the twentieth via hole, and the connection electrodes is electrically connected to the signal output terminal through the twenty-first via hole;
  • the number of the seventeenth via holes is multiple, and the multiple seventeenth via holes are arranged along the first direction;
  • the number of the eighteenth via holes is multiple, and the multiple eighteenth via holes are arranged along the first direction;
  • the number of the nineteenth via holes is multiple, and the multiple nineteenth via holes are arranged along the second direction.
  • the number of the twentieth via holes is multiple, and the multiple twentieth via holes are arranged along the first direction.
  • the present disclosure also provides a display device including the above-mentioned display substrate.
  • the present disclosure also provides a method for fabricating a display substrate, which is configured to fabricate the above-mentioned display substrate, and the method includes:
  • a drive circuit and a first power supply line located in the non-display area are formed on the base substrate;
  • the drive circuit includes: a first capacitor, a second capacitor and a third capacitor; the first capacitor and the third capacitor are Arranged in one direction, the second capacitor and the third capacitor are located on two sides of the first capacitor respectively, the second capacitor is located on the side of the first capacitor close to the display area, and the third capacitor A pole plate is electrically connected with the first power line;
  • the first power line extends along a first direction, and the orthographic projection of the first capacitor on the base substrate at least partially overlaps the orthographic projection of the first power line on the base substrate.
  • the driving circuit includes: a plurality of shift registers, each shift register includes: a plurality of transistors and first to third capacitors, the non-display capacitors are formed on the base substrate
  • the driver circuit and the first power line of the district include:
  • a semiconductor layer is formed on the base substrate, and the semiconductor layer includes: an active layer of a plurality of transistors;
  • a first insulating layer and a first metal layer are sequentially formed on the semiconductor layer, and the first metal layer includes: gate electrodes of a plurality of transistors, a first electrode plate of a first capacitor, a first electrode plate and a second electrode plate of the second capacitor. The first plate of the three capacitors;
  • a second insulating layer and a second metal layer are sequentially formed on the first metal layer, and the second metal layer includes: a second electrode plate of the first capacitor, a second electrode plate of the second capacitor, and a second electrode plate of the third capacitor. Plate and output signal line;
  • a third insulating layer and a third metal layer are sequentially formed on the second metal layer, and the third metal layer includes: source electrodes of a plurality of transistors, drain electrodes of a plurality of transistors, a first power supply line, a second power supply line, A first clock signal line, a second clock signal line, an initial signal line, and a connection electrode.
  • FIG. 1 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure
  • FIG. 2 is a top view of a driving circuit provided by an embodiment of the present disclosure
  • FIG. 3 is a schematic cross-sectional structure diagram of a display substrate
  • FIG. 4 is a schematic structural diagram of a driving circuit provided by an exemplary embodiment
  • 5 is an equivalent circuit diagram of a shift register provided by an exemplary embodiment
  • FIG. 6 is a working timing diagram of a shift register provided by an exemplary embodiment
  • FIG. 7 is a timing diagram of a driving circuit provided by an exemplary embodiment
  • FIG. 8 is a schematic structural diagram of a semiconductor layer provided by an exemplary embodiment
  • FIG. 9 is a schematic structural diagram of a first metal layer provided by an exemplary embodiment.
  • FIG. 10 is a schematic structural diagram of a second metal layer provided by an exemplary embodiment
  • FIG. 11 is a schematic structural diagram of a third metal layer provided by an exemplary embodiment
  • FIG. 12 is a schematic diagram of the disclosed display substrate after the semiconductor layer pattern is formed
  • FIG. 13 is a schematic diagram of the display substrate after the first metal layer pattern is formed
  • FIG. 14 is a schematic diagram of the display substrate after forming the second metal layer pattern
  • FIG. 15 is a schematic diagram of the display substrate after the third insulating layer pattern is formed.
  • FIG. 16 is a schematic diagram of a display substrate in an exemplary embodiment of the disclosure.
  • the terms “installed”, “connected” and “connected” should be construed in a broad sense unless otherwise expressly specified and limited. For example, it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • installed may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • electrically connected includes a case where constituent elements are connected together by an element having a certain electrical effect.
  • the "element having a certain electrical effect” is not particularly limited as long as it can transmit and receive electrical signals between the connected constituent elements.
  • Examples of “elements having a certain electrical effect” include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having various functions, and the like.
  • the transistors used in all the embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics.
  • the thin film transistor may be an oxide semiconductor thin film transistor, a low temperature polysilicon thin film transistor, an amorphous silicon thin film transistor, or a microcrystalline silicon thin film transistor.
  • As the thin film transistor a thin film transistor with a bottom gate structure or a thin film transistor with a top gate structure may be selected, as long as the switching function can be realized. Since the source and drain of the transistor used here are symmetrical, the source and drain can be interchanged.
  • parallel refers to a state where the angle formed by two straight lines is -10° or more and 10° or less, and therefore includes a state where the angle is -5° or more and 5° or less.
  • perpendicular refers to the state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore includes the state where the angle is 85° or more and 95° or less.
  • parallel refers to a state where the angle formed by two straight lines is -10° or more and 10° or less, and therefore includes a state where the angle is -5° or more and 5° or less.
  • perpendicular refers to the state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore includes the state where the angle is 85° or more and 95° or less.
  • film and “layer” are interchangeable.
  • conductive layer may be replaced by “conductive film” in some cases.
  • insulating film may be replaced with “insulating layer” in some cases.
  • FIG. 1 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure
  • FIG. 2 is a top view of a driving circuit provided by an embodiment of the present disclosure
  • the display substrate provided by the embodiments of the present disclosure may include: a display area and a non-display area located around the display area.
  • the display substrate may include: a base substrate, a driving circuit 10 and a first power supply line VGH disposed on the base substrate and located in the non-display area, and the driving circuit may at least include: a first capacitor C1, a second capacitor C2 and a third Capacitor C3.
  • the first capacitor C1 and the third capacitor C3 are arranged along the first direction, the second capacitor C2 and the third capacitor C3 are located on both sides of the first capacitor C1 respectively, and the second capacitor C2 is located on the side of the first capacitor C1 close to the display area , a pole plate of the third capacitor C3 is electrically connected to the first power line VGH.
  • the first power line VGH extends in the first direction.
  • the orthographic projection of the first capacitor C1 on the base substrate at least partially overlaps the orthographic projection of the first power line VGH on the base substrate.
  • the base substrate may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be, but not limited to, one or more of glass and metal foil; the flexible substrate may be, but not limited to, a poly ethylene terephthalate, ethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, One or more of polyethylene and textile fibers.
  • the first power line VGH may be located on a side of the second capacitor C2 away from the display area.
  • the first power line VGH may continuously provide a high-level DC signal.
  • the width of the first power line VGH may be about 6 micrometers to 12 micrometers.
  • the number of the first capacitor C1 , the second capacitor C2 and the third capacitor C3 is multiple, which is determined according to the actual demand of the display substrate, which is not limited in the present disclosure.
  • the display area may be provided with a plurality of sub-pixels PA regularly arranged, a plurality of first signal lines (eg, including scan lines G, control signal lines and light emission control lines) extending along the second direction line E), a plurality of second signal lines (eg, including data lines DL) extending along the first direction.
  • first signal lines eg, including scan lines G, control signal lines and light emission control lines
  • second signal lines eg, including data lines DL
  • At least one first signal line may extend along the second direction, and a plurality of first signal lines may be sequentially arranged along the first direction.
  • At least one second signal line may extend along the first direction, and the plurality of second signal lines may be sequentially arranged in the second direction.
  • At least one sub-pixel PA among the plurality of sub-pixels may include a light-emitting element and a pixel driving circuit for driving the light-emitting element to emit light.
  • the pixel drive circuit can be designed in 3T1C, 5T1C or 7T1C.
  • the intersection of the first direction and the second direction means that the included angle between the first direction and the second direction is about 70 degrees to 90 degrees.
  • the first direction and the second direction may lie in the same plane.
  • the first direction may be the row direction, which is parallel to the extension direction of the scan lines; the second direction may be the column direction, which is parallel to the extension direction of the data lines.
  • m rows of scan lines G1 to Gm are arranged along the first direction
  • m rows of light-emitting signal lines E1 to Em are arranged along the first direction
  • m rows are arranged along the second direction with The n columns of data lines DL1 to DLn.
  • the scanning lines and the data lines are insulated from each other, and the light-emitting signal lines and the data lines are insulated from each other.
  • m and n are both integers greater than 0.
  • the sub-pixels PA may be distributed at the intersections of m rows of scan lines and n columns of data lines.
  • the plurality of sub-pixels PA are regularly arranged in a matrix.
  • the sub-pixel may be any one of a red (R) sub-pixel, a green (G) sub-pixel, a blue (B) sub-pixel, and a white sub-pixel, which is not limited in the present disclosure.
  • the three sub-pixels can be arranged in a horizontal parallel, vertical parallel or fringe manner.
  • the display panel includes red (R) sub-pixels, green (G) sub-pixels, blue (B) sub-pixels and white sub-pixels
  • the four sub-pixels can be arranged in a horizontal parallel, vertical parallel or array manner. This is not limited.
  • FIG. 3 is a schematic cross-sectional structure diagram of a display substrate, illustrating the structure of three sub-pixels of the display substrate.
  • the display substrate may include a driving circuit layer 102 disposed on a base 101 , a light emitting device 103 disposed on a side of the driving circuit layer 102 away from the base substrate 101 , and a light emitting device 103 disposed away from the base 101
  • the encapsulation layer 104 on one side.
  • the display substrate may include other film layers, such as spacer columns, etc., which are not limited in the present disclosure.
  • the substrate 101 may be a flexible substrate, or it may be a rigid substrate.
  • the driving circuit layer 102 of each sub-pixel may include a plurality of transistors and storage capacitors constituting the pixel driving circuit, and each sub-pixel in FIG. 3 shows only one transistor 101 and one storage capacitor 101A as an example.
  • the light-emitting device 103 may include an anode 301, a pixel definition layer 302, an organic light-emitting layer 303, and a cathode 304.
  • the anode 301 is connected to the drain electrode of the driving transistor 210 through a via hole
  • the organic light-emitting layer 303 is connected to the anode 301
  • the cathode 304 is connected to the organic light-emitting layer.
  • the encapsulation layer 104 may include a stacked first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403.
  • the first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials, and the second encapsulation layer 402 may be made of organic materials.
  • the second encapsulation layer 402 is disposed between the first encapsulation layer 401 and the third encapsulation layer 403 to ensure that the outside water vapor cannot enter the light-emitting device 103 .
  • the organic light-emitting layer 303 may include a stacked hole injection layer (Hole Injection Layer, HIL for short), a hole transport layer (Hole Transport Layer, HTL for short), an electron blocking layer (Electron Block Layer, EBL), Emitting Layer (EML), Hole Block Layer (HBL), Electron Transport Layer (ETL) and Electron Injection Layer (EIL) .
  • HIL Hole Injection Layer
  • HTL Hole Transport Layer
  • EBL Electron Block Layer
  • EML Electron Transport Layer
  • EIL Electron Injection Layer
  • the hole injection layers of all subpixels may be a common layer connected together
  • the electron injection layers of all subpixels may be a common layer connected together
  • the hole transport layers of all subpixels may be A common layer connected together
  • the electron transport layer of all subpixels can be a common layer connected together
  • the hole blocking layer of all subpixels can be a common layer connected together
  • the light emitting layers of adjacent subpixels can have a small amount of The electron blocking layers of adjacent sub-pixels may overlap slightly, or may be isolated.
  • the light emitting structure may be an organic electroluminescent diode (OLED) including a stacked first electrode (anode), an organic light emitting layer and a second electrode (cathode).
  • OLED organic electroluminescent diode
  • the driving circuit may be a scanning driving circuit and/or a lighting driving circuit, which is not limited in the present disclosure.
  • the non-display area may also be provided with a timing controller 20 and a data driving circuit (not shown in the figure).
  • the driving circuit 20 may be arranged on the left or right side of the display area, and the timing controller and the data driving circuit may be arranged on the upper side or the lower side of the display area.
  • the data driving circuit may provide data signals to the sub-pixels of the plurality of columns through the plurality of data lines DL.
  • the scan driving circuit can provide scan signals to multiple rows of sub-pixels through multiple scan lines G.
  • the scan drive circuit can also generate at least one control signal in synchronization with the scan signal by row, and provide the control signal to multiple rows of sub-pixels in the display area.
  • the light-emitting driving circuit may provide light-emitting control signals to a plurality of rows of sub-pixels through a plurality of light-emitting control lines E.
  • the timing controller may provide grayscale values and control signals suitable for the specification of the data driving circuit to the data driving circuit, and may provide the clock signal, scan start and scanning start suitable for the specification of the scan driving circuit to the data driving circuit Signals and the like are supplied to the scan drive circuit, and a clock signal, an emission stop signal, and the like suitable for the specifications of the light emission drive circuit can be supplied to the light emission drive circuit.
  • the data driving circuit may generate data voltages to be supplied to the data lines using the grayscale values and control signals received from the timing controller.
  • the scan driving circuit may generate scan signals to be supplied to scan lines by receiving a clock signal, a scan start signal, and the like from a timing controller.
  • the scan driving circuit may sequentially supply the scan signals to the scan signals.
  • the scan driving circuit may be composed of a plurality of cascaded shift registers, and each shift register may sequentially generate scan signals under the control of a clock signal.
  • the light emission driving circuit may generate the light emission signal to be supplied to the light emission signal line by receiving a clock signal, an emission stop signal, and the like from the timing controller.
  • the lighting driving circuit may sequentially supply lighting signals to the lighting signal lines.
  • the light-emitting driving circuit may be composed of a plurality of cascaded shift registers, and each shift register may sequentially generate light-emitting signals under the control of a clock signal.
  • the first capacitor C1 along the first direction As the length becomes longer, the length along the second direction becomes narrower, and the length along the first direction of the third capacitor C3 becomes longer and the length along the second direction becomes narrower.
  • the display substrate provided by the embodiment of the present disclosure includes: a base substrate, a driving circuit and a first power supply line disposed on the base substrate and located in a non-display area, the driving circuit at least comprising: a first capacitor, a second capacitor and a third capacitor capacitor; the first capacitor and the third capacitor are arranged along the first direction, the second capacitor and the third capacitor are located on both sides of the first capacitor, the second capacitor is located on the side of the first capacitor close to the display area, and the third capacitor is located on the side of the display area.
  • a pole plate is electrically connected with the first power supply line; the first power supply line is located on the side of the second capacitor away from the display area and extends along the first direction, and the orthographic projection of the first capacitor on the substrate is at the first power supply line.
  • the orthographic projection on the base substrate at least partially overlaps, and the orthographic projection of the third capacitor on the base substrate at least partially overlaps the orthographic projection of the first power line on the base substrate.
  • the orthographic projection of the first capacitor on the base substrate and the orthographic projection of the first power line on the base substrate at least partially overlap, thereby reducing the area occupied by the driving circuit and reducing the amount of space occupied by the non-display area of the display substrate. Width to achieve narrow borders for displaying products.
  • the orthographic projection of the third capacitor C3 on the base substrate at least partially overlaps with the orthographic projection of the first power line VGH on the base substrate.
  • the orthographic projection of the third capacitor on the base substrate at least partially overlaps the orthographic projection of the first power line on the base substrate, which reduces the area occupied by the driving circuit, reduces the width of the non-display area in the display substrate, and realizes display products. narrow borders.
  • the display substrate may further include: a second power supply line VGL, an initial signal line ESTV, and a first clock signal line disposed on the base substrate and located in the non-display area ECK and the second clock signal line ECB.
  • the second power line VGL is located on one side of the driving circuit 10 close to the display area and extends along the first direction.
  • the initial signal line ESTV is located on a side of the first power line VGH away from the display area, and extends along the first direction.
  • the first clock signal line ECK is located between the first power supply line VGH and the initial signal line ESTV and extends in the first direction.
  • the second clock signal line ECB is located between the first clock signal line ECK and the initial signal line ESTV, and extends in the first direction.
  • the second power line VGL may continuously provide a low-level DC signal.
  • the initial signal line ESTV can provide a pulse signal.
  • the first clock signal line ECK may provide periodic pulse signals
  • the second clock signal line ECB may provide periodic pulse signals.
  • the first clock signal line ECK and the second clock signal line ECB are not simultaneously active level signals.
  • the width of the second power supply line VGL may be smaller than or equal to the width of the first power supply line VGH, and/or the width of the initial signal line ESTV may be smaller than the width of the first power supply line VGH, and/or Or, the width of the first clock signal line ECK may be smaller than the width of the first power supply line VGH, and may be greater than the width of the initial signal line ESTV, and/or the width of the second clock signal line ECB may be smaller than the width of the first power supply line VGH width, and may be greater than the width of the initial signal line ESTV.
  • the width of the second power supply line VGL is less than or equal to the width of the first power supply line VGH, which can reduce the width of the non-display area of the display substrate and realize a narrow frame.
  • the width of the second power line VGL may be about 6 to 12 microns.
  • the width of the initial signal line ESTV is smaller than the width of the first power supply line VGH, which can reduce the width of the non-display area of the display substrate and realize a narrow frame.
  • the width of the initial signal line ESTV may be about 5 micrometers to 10 micrometers.
  • the width of the first clock signal line ECK is smaller than the width of the first power supply line VGH, which can reduce the width of the non-display area of the display substrate and realize a narrow frame.
  • the width of the first clock signal line ECK may be about 6 micrometers to 20 micrometers.
  • the width of the second clock signal line ECB is smaller than the width of the first power supply line VGH, which can reduce the width of the non-display area of the display substrate and realize a narrow frame.
  • the width of the second clock signal line ECB may be about 6 to 20 microns.
  • FIG. 4 is a schematic structural diagram of a driving circuit provided by an exemplary embodiment
  • FIG. 5 is an equivalent circuit diagram of a shift register provided by an exemplary embodiment
  • FIG. 4 illustrates an example in which the driving circuit is a light-emitting driving circuit.
  • Each shift register EOA includes: a first transistor T1 to a tenth transistor T10, a first capacitor C1 to a third capacitor C3, a signal input terminal EIN, a signal output terminal EOUT, a first clock signal terminal CK1, and a second clock signal terminal.
  • CK2 the first power supply terminal VL1 and the second power supply terminal VL2.
  • the gate electrode of the first transistor T1 is electrically connected to the first clock signal terminal CK1, the source electrode of the first transistor T1 is electrically connected to the signal input terminal EIN, and the drain electrode of the first transistor T1 is electrically connected to the first node N1.
  • the gate electrode of the second transistor T2 is electrically connected to the first node N1, the source electrode of the second transistor T2 is electrically connected to the first clock signal terminal CK1, and the second electrode of the second transistor T2 is electrically connected to the second node N2.
  • the gate electrode of the third transistor T3 is electrically connected to the first clock signal terminal CK1, the source electrode of the third transistor T3 is electrically connected to the second power supply terminal VL2, and the second electrode of the third transistor T3 is electrically connected to the second node N2.
  • the gate electrode of the fourth transistor T4 is electrically connected to the second clock signal terminal CK2, the source electrode of the fourth transistor T4 is electrically connected to the first node N1, and the drain electrode of the fourth transistor T4 is electrically connected to the source electrode of the fifth transistor.
  • the gate electrode of the fifth transistor T5 is electrically connected to the second node N2, and the drain electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VL1.
  • the gate electrode of the sixth transistor T6 is electrically connected to the second node N2, the source electrode of the sixth transistor T6 is electrically connected to the second clock signal terminal CK2, and the drain electrode of the sixth transistor T6 is electrically connected to the third node N3.
  • the gate electrode of the seventh transistor T7 is electrically connected to the second clock signal terminal CK2, the source electrode of the seventh transistor T7 is electrically connected to the third node N3, and the drain electrode of the seventh transistor T7 is electrically connected to the fourth node N4.
  • the gate electrode of the eighth transistor T8 is electrically connected to the first node N1, the source electrode of the eighth transistor T8 is electrically connected to the first power supply terminal VL1, and the drain electrode of the eighth transistor T8 is electrically connected to the fourth node N4.
  • the gate electrode of the ninth transistor T9 is electrically connected to the fourth node N4, the source electrode of the ninth transistor T9 is electrically connected to the signal output terminal EOUT, and the drain electrode of the ninth transistor T9 is electrically connected to the first power supply terminal VL1.
  • the gate electrode of the tenth transistor T10 is electrically connected to the first node N1, the source electrode of the tenth transistor T10 is electrically connected to the second power supply terminal VL2, and the drain electrode of the tenth transistor T10 is electrically connected to the signal output terminal EOUT.
  • the first plate C11 of the first capacitor C1 is electrically connected to the second node N2, and the second plate C12 of the first capacitor C1 is electrically connected to the third node N3.
  • the first plate C21 of the second capacitor C2 is electrically connected to the first node N1, and the second plate C22 of the second capacitor C2 is electrically connected to the second clock signal terminal CK2.
  • the first plate C31 of the third capacitor C3 is electrically connected to the fourth node N4, and the second plate C32 of the third capacitor C3 is electrically connected to the first power terminal VL1.
  • the first clock signal terminal CK1 and the second clock signal terminal CK2 are continuously switched between high and low levels, respectively.
  • the first power supply terminal VL1 continuously outputs a high-level signal
  • the second power supply terminal VL2 continuously outputs a low-level signal
  • the first capacitor C1 is set to maintain the potential of the second node N2.
  • the second capacitor C2 is set to maintain the potential of the first node N1.
  • the third capacitor C3 is set to maintain the potential of the fourth node N4.
  • the first to tenth transistors T1 to T10 may employ low temperature polysilicon thin film transistors, or may employ oxide thin film transistors, or may employ both low temperature polysilicon thin film transistors and oxide thin film transistors.
  • the active layer of the low temperature polysilicon thin film transistor adopts low temperature polysilicon (Low Temperature Poly-Silicon, LTPS for short), and the active layer of the oxide thin film transistor adopts oxide (Oxide).
  • Low temperature polysilicon thin film transistors have the advantages of high mobility and fast charging, and oxide thin film transistors have the advantages of low leakage current.
  • a low temperature polycrystalline silicon thin film transistor and an oxide thin film transistor can be integrated on a display substrate to form a low temperature polycrystalline oxide (Low Temperature Polycrystalline Oxide, LTPO for short) display substrate, and the advantages of both can be utilized, It can achieve high resolution (Pixel Per Inch, PPI for short), low frequency drive, reduce power consumption, and improve display quality.
  • LTPO Low Temperature Polycrystalline Oxide
  • the first to tenth transistors T1 to T10 may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the product yield.
  • the first to tenth transistors T1 to T10 may include P-type transistors and N-type transistors.
  • the clock signal is a signal that periodically switches between two different levels, and these two levels are usually used to turn the transistor on and off respectively, so the higher of the two is usually referred to as A high level, and a lower level is called a low level.
  • the first transistor T1 may be a P-type transistor.
  • the first transistor T1 When the signal at the first clock signal terminal CK1 is at a low level, the first transistor T1 is in a conducting state, and when the signal at the first clock signal terminal CK1 is at a low level When it is at a high level, the first transistor T1 is in an off state.
  • the second transistor T2 may be a P-type transistor. When the signal of the first node N1 is at a low level, the second transistor T2 is in an on state, and when the signal at the first node N1 is at a high level, the second transistor T2 is in an off state .
  • the third transistor T3 may be a P-type transistor.
  • the fourth transistor T4 may be a P-type transistor.
  • the fourth transistor T4 is in a conducting state.
  • the fourth transistor T4 is at a high level.
  • T4 is off.
  • the fifth transistor T5 may be a P-type transistor.
  • the sixth transistor T6 may be a P-type transistor.
  • the seventh transistor T7 may be a P-type transistor.
  • the eighth transistor T8 may be a P-type transistor.
  • the ninth transistor T9 may be a P-type transistor.
  • the tenth transistor T10 may be a P-type transistor. When the signal of the first node N1 is at a low level, the tenth transistor T10 is in an on state, and when the signal at the first node N1 is at a high level, the tenth transistor T10 is in an off state .
  • the first electrode plate C11 of the first capacitor C1 is located on the side of the second electrode plate C12 of the first capacitor C1 close to the base substrate, and the first electrode plate C11 of the first capacitor C1 is located on the side of the substrate.
  • the orthographic projection on the base substrate covers the orthographic projection of the second electrode plate C12 of the first capacitor C1 on the base substrate.
  • the area of the first capacitor C1 may be about 200 square micrometers to 300 square micrometers.
  • the first electrode plate C21 of the second capacitor C2 is located on the side of the second electrode plate C22 of the second capacitor C2 close to the base substrate, and the first electrode plate C21 of the second capacitor C2 is located on the side of the second electrode plate C22 of the second capacitor C2 close to the substrate.
  • the orthographic projection on the base substrate covers the orthographic projection of the second electrode plate C22 of the second capacitor C2 on the base substrate.
  • the area of the second capacitor C2 may be about 300 square micrometers to 500 square micrometers.
  • the first electrode plate C31 of the third capacitor C3 is located on the side of the second electrode plate C32 of the third capacitor C3 close to the base substrate, and the first electrode plate C31 of the third capacitor C3 is located on the side of the second electrode plate C32 of the third capacitor C3 close to the substrate.
  • the orthographic projection on the base substrate covers the orthographic projection of the second electrode plate C32 of the third capacitor C3 on the base substrate.
  • the area of the third capacitor C3 may be about 300 square micrometers to 500 square micrometers.
  • the orthographic projection of the first electrode plate of the first capacitor C1 on the base substrate overlaps with the orthographic projection of the first power line VGH on the base substrate.
  • the area is positively related to the area of the first plate of the first capacitor, that is, the larger the area of the first capacitor, the orthographic projection of the first capacitor C1 on the substrate and the orthographic projection of the first power line VGH on the substrate The larger the area of the overlapping area.
  • the orthographic projection of the first electrode plate of the third capacitor C3 on the base substrate overlaps with the orthographic projection of the first power line VGH on the base substrate.
  • the area is positively related to the area of the first plate of the first capacitor, that is, the larger the area of the first capacitor, the orthographic projection of the third capacitor C3 on the substrate and the orthographic projection of the first power line VGH on the substrate The larger the area of the overlapping area.
  • the width of the overlapping portion of the first plate of the third capacitor C3 and the first power supply line VGH may be equal to the width of the first power supply line VGH.
  • the area of the overlapping portion of the first electrode plate of the first capacitor and the first power supply line may be smaller than the area of the overlapping portion of the first electrode plate of the third capacitor and the first power supply line.
  • the shift register provided by an exemplary embodiment is described below through the working process of the shift register.
  • FIG. 6 is a working timing diagram of the shift register provided by an exemplary embodiment.
  • a shift register involved in an exemplary embodiment includes: 10 switch transistors (T1 to T10), 3 capacitor units (C1 to C3), 3 signal input terminals (CK1, CK2 and EIN), 1 signal output terminal (EOUT), 2 power supply terminals (V1 and V2).
  • a working process of the shift register provided by an exemplary embodiment may include: a first stage P1 to an eighth stage P8.
  • the signal at the signal input terminal EIN is a high-level signal
  • the signal at the first clock signal terminal CK1 is a low-level signal
  • the first transistor T1 and the third transistor T3 are turned on
  • the signal at the signal input terminal EIN is turned on.
  • the signal of the second power supply terminal VL2 is written into the second node N2, at this time, the second node N2 is at a low level. Since the first node N1 is at a high level, the second transistor T2, the eighth transistor T8 and the tenth transistor T10 are turned off.
  • the signal of the second clock signal terminal CK2 is a high level signal, and the fourth transistor T4 and the seventh transistor T7 are turned off. Since the second node N2 is at a low level, the fifth transistor T5 and the sixth transistor T6 are turned on, and the signal of the second clock signal terminal CK2 is written to the third node N3. Since the voltage across the capacitor does not change abruptly, the fourth node N4 maintains the high level of the previous frame, the ninth transistor T9 is turned off, and the output signal of the signal output terminal EOUT maintains the low level of the previous frame.
  • the signal of the signal input terminal EIN and the signal of the first clock signal terminal CK1 are high-level signals
  • the first transistor T1 and the third transistor T3 are turned off
  • the first node N1 maintains a high level
  • the second transistor T2 , the eighth transistor T8 and the tenth transistor T10 are turned off
  • the second node N2 is kept at a low level
  • the fifth transistor T5 and the sixth transistor T6 are turned on, because the signal of the second clock signal terminal CK2 is a low level signal
  • the fourth The transistor T4 and the seventh transistor T7 are turned on
  • the signal of the second clock signal terminal CK2 is written into the third node N3
  • the third node N3 changes from high level to low level
  • the signal of the third node N3 is written into the fourth The node N4 and the fourth node N4 are at a low level
  • the ninth transistor T9 is turned on
  • the signal output terminal EOUT outputs a high level signal of the first power supply terminal VL1.
  • the signal at the signal input terminal EIN is a high level signal
  • the signal at the first clock signal terminal CK1 is a low level signal
  • the first transistor T1 and the third transistor T3 are turned on
  • the first node N1 is at a high level flat
  • the second transistor T2 the eighth transistor T8 and the tenth transistor T10 are turned off
  • the second node N2 is kept at a low level
  • the fifth transistor T5 and the sixth transistor T6 are turned on
  • the signal of the second clock signal terminal CK2 is written into the first Three nodes N3, since the signal of the second clock signal terminal CK2 is a high level signal, the third node N3 changes from the low level of the previous stage to the high level, the fourth transistor T4 and the seventh transistor T7 are turned off, and the fourth transistor T4 and the seventh transistor T7 are turned off.
  • the node N4 is kept at a low level
  • the ninth transistor T9 is turned on
  • the signal output terminal EOUT outputs a high level signal of the first
  • the signal at the signal input terminal EIN is a low-level signal
  • the signal at the first clock signal terminal CK1 is a high-level signal
  • the first transistor T1 and the third transistor T3 are turned off, and the first node N1 remains at a high level
  • the second transistor T2, the eighth transistor T8 and the tenth transistor T10 are turned off
  • the second node N2 is kept at a low level
  • the fifth transistor T5 and the sixth transistor T6 are turned on
  • the signal of the second clock signal terminal CK2 is written into the third Node N3, since the signal of the second clock signal terminal CK2 is a low level signal
  • the third node N3 changes from the high level of the previous stage to the low level
  • the fourth transistor T4 and the seventh transistor T7 are turned on
  • the third node N3 is turned on.
  • the signal of the node N3 is written into the fourth node N4, the fourth node N4 maintains a low level
  • the ninth transistor T9 is turned on
  • the signal of the signal input terminal EIN and the signal of the first clock signal terminal CK1 are low-level signals
  • the first transistor T1 and the third transistor T3 are turned on
  • the first node N1 changes from high level to low level.
  • the second transistor T2, the eighth transistor T8 and the tenth transistor T10 are turned on
  • the second node N2 is kept at a low level
  • the fifth transistor T5 and the sixth transistor T6 are turned on
  • the signal of the second clock signal terminal CK2 is written
  • the third node N3 since the signal of the second clock signal terminal CK2 is a high level signal
  • the third node N3 changes from the low level in the previous stage to the high level
  • the fourth transistor T4 and the seventh transistor T7 are turned off.
  • the eighth transistor T8 is turned on, the high level signal of the first power supply terminal VL1 is written into the fourth node N4, the fourth node N4 becomes a high level, and the ninth transistor T9 is turned off. Since the tenth transistor T10 is turned on, the The low-level signal of the two power supply terminals VL2 is written into the signal output terminal EOUT, and the signal output terminal EOUT outputs a low-level signal.
  • the signal of the signal input terminal EIN is a low-level signal
  • the signal of the first clock signal terminal CK1 is a high-level signal
  • the first transistor T1 and the third transistor T3 are turned off, and the first node N1 is kept at a low level
  • the second transistor T2 the eighth transistor T8 and the tenth transistor T10 are turned on
  • the signal of the first clock signal terminal CK1 is written into the second node N2
  • the second node N2 changes from low level to high level
  • the fifth transistor T5 and the sixth transistor T6 are turned off
  • the third node N3 is kept at a high level.
  • the fourth transistor T4 and the seventh transistor T7 are turned on, and the signal of the third node N3 Write the fourth node N4, the fourth node N4 keeps the high level, the ninth transistor T9 is turned off, because the tenth transistor T10 is turned on, the low level signal of the second power supply terminal VL2 is written to the signal output terminal EOUT, the signal output terminal EOUT outputs a low level signal.
  • the signal of the signal input terminal EIN is a low-level signal
  • the signal of the first clock signal terminal CK1 is a low-level signal
  • the first transistor T1 and the third transistor T3 are turned on
  • the first node N1 remains low.
  • the second transistor T2 the eighth transistor T8 and the tenth transistor T10 are turned on
  • the signal of the first clock signal terminal CK1 is written into the second node N2
  • the second node N2 is low level
  • the transistor T6 is turned on
  • the signal of the second clock signal terminal CK2 is written into the third node N3.
  • the fourth transistor T4 and the seventh transistor T7 are turned off, and the fourth node N4 Keeping the high level, the ninth transistor T9 is turned off. Since the tenth transistor T10 is turned on, the low-level signal of the second power supply terminal VL2 is written into the signal output terminal EOUT, and the signal output terminal EOUT outputs a low-level signal.
  • the signal at the signal input terminal EIN is a low-level signal
  • the signal at the first clock signal terminal CK1 is a high-level signal
  • the first transistor T1 and the third transistor T3 are turned off, and the first node N1 remains at a low level
  • the second transistor T2 the eighth transistor T8 and the tenth transistor T10 are turned on
  • the signal of the first clock signal terminal CK1 is written into the second node N2
  • the second node N2 changes from low level to high level
  • the fifth transistor T5 and the sixth transistor T6 are turned off
  • the third node N3 is kept at a high level.
  • the fourth transistor T4 and the seventh transistor T7 are turned on, and the signal of the third node N3 Write the fourth node N4, the fourth node N4 keeps the high level, the ninth transistor T9 is turned off, because the tenth transistor T10 is turned on, the low level signal of the second power supply terminal VL2 is written to the signal output terminal EOUT, the signal output terminal EOUT outputs a low level signal.
  • the eighth transistor T8 is continuously turned on, the ninth transistor T9 is turned off, the first transistor T1 periodically charges the second capacitor C2, and the first node N1 keeps a low level, the tenth transistor T10 is continuously turned on, and the signal output terminal EOUT outputs a low level signal until the pulse of the signal input terminal EIN of the next frame enters.
  • FIG. 7 is a timing diagram of a driving circuit provided by an exemplary embodiment.
  • EOUTi is the signal output terminal of the i-th stage shift register EOA(i)
  • EINi is the signal input terminal of the i-th stage shift register EOA(i).
  • the signal input terminal of the first stage shift register EOA(1) is electrically connected to the initial signal line ESTV
  • the signal output terminal of the i-1th stage shift register is electrically connected to the ith stage shift register.
  • the signal input terminals of all shift registers are electrically connected, the first power supply terminals VL1 of all shift registers are electrically connected to the first power supply line VGH, the second power supply terminals VL2 of all shift registers are electrically connected to the second power supply line VGL, and the odd-numbered stage shift registers are electrically connected to the second power supply line VGL.
  • the first clock signal terminal CK1 is electrically connected to the first clock signal line ECK
  • the second clock signal terminal CK2 of the odd-numbered shift registers is electrically connected to the second clock signal line ECB
  • the first clock signal terminal of the even-numbered shift registers CK1 is electrically connected to the second clock signal line ECB
  • the second clock signal terminal CK2 of the even-numbered shift registers is electrically connected to the first clock signal line ECK, wherein i is a positive integer greater than or equal to 2.
  • the signal output terminal of the i-th stage shift register is electrically connected to the 2i-1th row of sub-pixels and the 2i-th row of sub-pixels.
  • the signal output end of the i-th stage shift register is electrically connected to the sub-pixels in the 2i-1 row through the 2i-1 row light-emitting signal line, and is electrically connected to the 2i-row sub-pixels through the 2i-th row light-emitting signal line.
  • each shift register includes a connection electrode 40 .
  • the orthographic projection of the connection electrode 10 on the base substrate at least partially overlaps the orthographic projection of the signal output terminal EOUT on the base substrate.
  • the connection electrodes are respectively electrically connected to the signal output end of the shift register of the current stage and the signal input end of the shift register of the next stage.
  • the first transistor T1 , the second transistor T2 , the third transistor T3 , the fourth transistor T4 and the fifth transistor T5 are located at the position where the first capacitor C1 is far from the third capacitor C3 one side, and is located on the side of the second capacitor C2 close to the first power line VGH.
  • the sixth transistor T6 is located on the side of the first capacitor C1 close to the second power supply line VGL, and located on the side of the second capacitor C2 close to the third capacitor C3 .
  • the sixth transistor T6 is located on the side of the first capacitor C1 close to the second power supply line VGL, and located on the side of the second capacitor C2 close to the third capacitor C3, which can reduce the space occupied by the sixth crystal in the first direction, and can realize display Narrow bezels for products.
  • the seventh transistor T7 and the eighth transistor T8 are located between the first capacitor C1 and the third capacitor C3.
  • the ninth transistor T9 and the tenth transistor T10 are located on the side of the second capacitor C2 close to the second power supply line VGL.
  • FIG. 8 is a schematic structural diagram of a semiconductor layer provided by an exemplary embodiment
  • FIG. 9 is a schematic structural diagram of a first metal layer provided by an exemplary embodiment
  • FIG. 10 is a second metal layer provided by an exemplary embodiment.
  • FIG. 11 is a schematic diagram of the structure of the third metal layer provided by an exemplary embodiment.
  • a display substrate provided by an exemplary embodiment includes: a semiconductor layer, a first insulating layer, a first metal layer, a second insulating layer, a semiconductor layer, a first insulating layer, a first metal layer, a second insulating layer, The second metal layer, the third insulating layer and the third metal layer.
  • the semiconductor layer includes an active layer of a plurality of transistors.
  • the active layers of the plurality of transistors include: the active layer 11 of the first transistor T1, the active layer 21 of the second transistor T2, the active layer 31 of the third transistor T3, and the active layer 41 of the fourth transistor T4 , the active layer 51 of the fifth transistor T5, the active layer 61 of the sixth transistor T6, the active layer 71 of the seventh transistor T7, the active layer 81 of the eighth transistor T8, and the active layer 91 of the ninth transistor T9 and the active layer 110 of the tenth transistor T10.
  • the active layer 11 of the first transistor T1, the active layer 21 of the second transistor T2, the active layer 31 of the third transistor T3, and the active layer of the fourth transistor T4 The active layer 41, the active layer 51 of the fifth transistor T5, the active layer 61 of the sixth transistor T6, the active layer 71 of the seventh transistor T7, the active layer 91 of the ninth transistor T9, and the active layer of the tenth transistor T10
  • the active layers 110 all extend along the first direction.
  • the active layer 81 of the eighth transistor T8 extends in the second direction. Wherein, the first direction and the second direction intersect.
  • the active layers of all transistors include a channel region and source and drain connections on both sides of the channel region
  • the source electrode of the transistor is electrically connected to the source connection portion
  • the drain electrode of the transistor is electrically connected to the drain connection portion.
  • the drain connection portion of the active layer of the fourth transistor is multiplexed as a drain electrode
  • the source connection portion of the active layer of the fifth transistor is multiplexed as a source electrode
  • the drain connection portion of the active layer of the fourth transistor is multiplexed. It is electrically connected to the source connection portion of the active layer of the fifth transistor.
  • the channel region may not be doped with impurities and have semiconductor properties.
  • the source connection and the drain connection may be on both sides of the channel region and are doped with impurities and thus have conductivity. Impurities may vary depending on the type of transistor (eg, N-type or P-type).
  • the first metal layer includes: gate electrodes of a plurality of transistors, a first electrode plate C11 of the first capacitor C1, a first electrode plate C21 of the second capacitor C2 and The first plate C31 of the third capacitor C3.
  • the gate electrodes of the plurality of transistors include: the gate electrode 12 of the first transistor T1, the gate electrode 22 of the second transistor T2, the gate electrode 32 of the third transistor T3, the gate electrode 42 of the fourth transistor T4, and the gate electrode of the fifth transistor T5.
  • the gate electrode of the first transistor T1 when the first clock signal terminal in the shift register is electrically connected to the first clock signal line, and the second clock signal terminal is electrically connected to the second clock signal line, the gate electrode of the first transistor T1
  • the orthographic projection of 12 on the base substrate at least partially overlaps the orthographic projection of the first clock signal line on the base substrate.
  • the orthographic projection of the gate electrode 42 of the fourth transistor T4 on the base substrate at least partially overlaps with the orthographic projection of the second clock signal line on the base substrate, and the orthographic projection of the gate electrode 72 of the seventh transistor T7 on the base substrate It at least partially overlaps with the orthographic projection of the second clock signal line on the base substrate, or, when the first clock signal terminal in the shift register is electrically connected to the second clock signal line, the second clock signal terminal is connected to the first clock signal terminal.
  • the orthographic projection of the gate electrode 12 of the first transistor T1 on the base substrate at least partially overlaps the orthographic projection of the second clock signal line on the base substrate.
  • FIG. 2 illustrates an example in which the first clock signal terminal of the shift register is electrically connected to the first clock signal line, and the second clock signal terminal is electrically connected to the second clock signal line.
  • each shift register the gate electrode 22 of the second transistor T2, the gate electrode 120 of the tenth transistor T10, the gate electrode 82 of the eighth transistor T8, and the gate electrode 82 of the second capacitor C2 A polar plate C21 is integrally formed.
  • the gate electrode 52 of the fifth transistor T5 , the gate electrode 62 of the sixth transistor T6 and the first electrode plate C11 of the first capacitor C1 are integrally formed.
  • each shift register the gate electrode 92 of the ninth transistor T9 and the first electrode plate C31 of the third capacitor C3 are integrally formed.
  • the shape of the first electrode plate C11 of the first capacitor may be a square.
  • the shape of the first plate C21 of the second capacitor may be a superposition of two squares, and the first square and the second square are arranged along the first direction, The width of the second square is greater than the width of the first square, the length in the second direction is less than the length in the first direction, and the left edge of the second square is located at the left edge of the first direction near the gate electrode of the second transistor side.
  • the shape of the first electrode plate C31 of the third capacitor may be a square with a missing corner at the lower right corner.
  • the second metal layer includes: a second electrode plate C12 of the first capacitor C1 , a second electrode plate C22 of the second capacitor C2 , and a second electrode plate C22 of the third capacitor C3 Plate C32 and output signal line EL.
  • the gate electrode 22 of the second transistor has a "return" shape.
  • the gate electrode 92 of the ninth transistor has a comb-like structure.
  • the gate electrode 92 of the ninth transistor includes a plurality of first branch segments 92A disposed across the active layer 91 of the ninth transistor and a first connection segment 92B connecting the plurality of first branch segments 92A.
  • the gate electrode 120 of the tenth transistor has a comb-like structure.
  • the gate electrode 120 of the tenth transistor includes a plurality of second branch segments 120A disposed across the active layer 110 of the tenth transistor and a second connection segment 120B connecting the plurality of first branch segments 120A.
  • the output signal line EL in each shift register may include a first connection part OUT1 , a second connection part OUT2 , a third connection part OUT3 and a fourth connection part OUT4 which are integrally formed.
  • the orthographic projection of the first connection portion OUT1 on the base substrate at least partially overlaps with the orthographic projection of the source electrode of the ninth transistor on the base substrate, and overlaps with the orthographic projection of the drain electrode of the tenth transistor on the base substrate At least partially overlapping, the first connection portion OUT1 extends in the first direction.
  • the second connection part OUT2, the third connection part OUT3 and the fourth connection part OUT4 extend along the second direction, the second connection part OUT2 and the third connection part OUT3 are located on the side of the first connection part OUT1 away from the first power supply line VGH, The fourth connection part OUT4 is located on the side of the first connection part OUT1 close to the first power supply line VGH.
  • first connection part OUT1 , the second connection part OUT2 and the third connection part OUT3 may have a linear structure.
  • the fourth connection portion OUT4 may have a zigzag structure.
  • the second connection portion OUT2 is electrically connected to the 2i-1 row of sub-pixels.
  • the third connection portion OUT3 is electrically connected to the sub-pixels in the 2i-th row.
  • the fourth connection portion OUT4 is electrically connected to the signal input terminal of the next-stage shift register.
  • the orthographic projection of the connection electrode on the base substrate and the orthographic projection of the fourth connection portion on the base substrate at least partially overlap, and the fourth connection portion is connected to the next-stage shift register through the connection electrode.
  • the signal input terminal is electrically connected.
  • the shape of the second electrode plate C12 of the first capacitor may be a square, and the side of the second electrode plate C12 of the first capacitor close to the output signal line EL is stepped shape.
  • the shape of the second electrode plate C22 of the second capacitor may lack the L-shape in the lower right corner, and the second electrode plate C22 of the second capacitor is far away from the output signal line EL. There are bumps on the edges.
  • the shape of the second electrode plate C32 of the third capacitor may be a square with the lower right corner missing, and the second electrode plate C32 of the third capacitor is close to the edge of the second capacitor stepped.
  • the third metal layer includes: source electrodes of a plurality of transistors, drain electrodes of a plurality of transistors, a signal input terminal EIN, a first clock signal terminal CK1, a second clock The signal terminal CK2 , the first power supply line VGH, the second power supply line VGL, the first clock signal line ECK, the second clock signal line ECB, the initial signal line ESTV and the connection electrode 40 .
  • the source electrodes of the plurality of transistors include: the source electrode 13 of the first transistor T1, the source electrode 23 of the second transistor T2, the source electrode 33 of the third transistor T3, the source electrode 43 of the fourth transistor T4, and the source of the sixth transistor T6.
  • the drain electrodes of the plurality of transistors include: the drain electrode 14 of the first transistor T1, the drain electrode 24 of the second transistor T2, the drain electrode 34 of the third transistor T3, the drain electrode 54 of the fifth transistor T5, and the drain electrode of the sixth transistor T6.
  • the drain electrode 14 of the first transistor T1 and the source electrode 43 of the fourth transistor T4 may be integrally formed.
  • the drain electrode 34 of the second transistor T2 and the drain electrode 34 of the third transistor T3 may be integrally formed.
  • the source electrode 33 of the third transistor T3, the source electrode 130 of the tenth transistor T10 and the second power supply line VGL may be integrally formed.
  • the drain electrode 64 of the sixth transistor T6 and the source electrode 73 of the seventh transistor T7 may be integrally formed.
  • the drain electrode 74 of the seventh transistor T7 and the drain electrode 84 of the eighth transistor T8 may be integrally formed.
  • the source electrode 83 of the eighth transistor T8, the drain electrode 94 of the ninth transistor T9, the drain electrode 54 of the fifth transistor T5 and the first power supply line VGH are integrally formed.
  • the semiconductor layer may be an amorphous silicon layer, a polysilicon layer, or may be a metal oxide layer.
  • the metal oxide layer can be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten and indium and zinc, an oxide containing titanium and indium, an oxide containing titanium and indium and tin oxides, oxides containing indium and zinc, oxides containing silicon and indium and tin, or oxides containing indium or gallium and zinc.
  • the metal oxide layer may be a single layer, or it may be a double layer, or it may be multiple layers.
  • the first insulating layer, the second insulating layer and the third insulating layer may adopt any one of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON). or more, it may be a single layer, multiple layers or composite layers.
  • the first insulating layer is called a first gate insulating layer
  • the second insulating layer is called a second gate insulating layer
  • the third insulating layer is called an interlayer insulating layer.
  • the first metal layer, the second metal layer, and the third metal layer may use metal materials, such as silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo).
  • metal materials such as silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo).
  • Any one or more, or alloy materials of the above metals such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), can be a single-layer structure, or a multi-layer composite structure, such as Mo/Cu/Mo and the like.
  • the resistance of the third metal layer may be less than the resistance of the first metal layer.
  • the resistance of the third metal layer may be less than the resistance of the second metal layer.
  • the fabrication material of the first metal layer and the second metal layer may include: molybdenum.
  • the third metal layer may be a three-layer stack structure formed of titanium, aluminum, and titanium.
  • the active layer 61 of the sixth transistor T6 extends along the first direction, and the source of the sixth transistor T6 The electrode 63 and the drain electrode 64 are arranged along the first direction.
  • the active layer 61 of the sixth transistor T6 extends along the first direction, and the source electrode 63 and the drain electrode 64 of the sixth transistor T6 are arranged along the first direction so that the sixth transistor T6 is placed in a column direction, which can reduce the width of the driving circuit and achieve Displays the narrow border of the product.
  • the distance L1 between the first power line VGH and the edge of the first capacitor C1 close to the second power line VGL may be smaller than the first power line VGH and the sixth transistor T6
  • the distance L2 between the source electrodes The distance between the first power line VGH and the edge of the first capacitor C1 close to the second power line VGL is smaller than the distance between the first power line VGH and the source electrode of the sixth transistor T6, which can reduce the width of the driving circuit and realize the display product narrow borders.
  • the display substrate may further include: first to tenth via holes penetrating the first insulating layer, the second insulating layer and the third insulating layer.
  • the first via exposes the active layer of the first transistor
  • the second via exposes the active layer of the second transistor
  • the third via exposes the active layer of the third transistor
  • the fourth via exposes the active layer of the fourth transistor
  • the fifth via exposes the active layer of the fifth transistor
  • the sixth via exposes the active layer of the sixth transistor
  • the seventh via exposes the active layer of the sixth transistor
  • the active layer of the seventh transistor, the eighth via hole exposes the active layer of the eighth transistor
  • the ninth via hole exposes the active layer of the ninth transistor
  • the tenth via hole exposes the active layer of the tenth transistor.
  • the source electrode and drain electrode of the first transistor are electrically connected to the active layer of the first transistor through the first via hole
  • the source electrode and drain electrode of the second transistor are electrically connected to the active layer of the second transistor through the second via hole.
  • Connection, the source electrode and drain electrode of the third transistor are electrically connected to the active layer of the third transistor through the third via hole
  • the source electrode and drain electrode of the fourth transistor are electrically connected to the active layer of the fourth transistor through the fourth via hole.
  • Connection, the source electrode and drain electrode of the fifth transistor are electrically connected to the active layer of the fifth transistor through the fifth via hole
  • the source electrode and drain electrode of the sixth transistor are electrically connected to the active layer of the sixth transistor through the sixth via hole.
  • the source electrode and drain electrode of the seventh transistor are electrically connected to the active layer of the seventh transistor through the seventh via hole
  • the source electrode and drain electrode of the eighth transistor are electrically connected to the active layer of the eighth transistor through the eighth via hole.
  • the source electrode and drain electrode of the ninth transistor are electrically connected to the active layer of the ninth transistor through the ninth via hole
  • the source electrode and drain electrode of the tenth transistor are electrically connected to the active layer of the tenth transistor through the tenth via hole. connect.
  • the display substrate may further include: eleventh to sixteenth via holes penetrating the second insulating layer and the third insulating layer.
  • the eleventh via hole exposes the gate electrode of the first transistor
  • the twelfth via hole exposes the gate electrode of the second transistor
  • the thirteenth via hole exposes the gate electrode of the fourth transistor
  • the fourteenth via hole exposes the gate electrode of the fifth transistor
  • the fifteenth via hole exposes the gate electrode of the seventh transistor
  • the sixteenth via hole exposes the first plate of the third capacitor.
  • the source electrode of the second transistor is electrically connected to the gate electrode of the first transistor through the eleventh via hole
  • the drain electrode of the first transistor is electrically connected to the gate electrode of the second transistor through the twelfth via hole
  • the sixth transistor is electrically connected to the gate electrode of the second transistor through the twelfth via hole.
  • the source electrode of the transistor is electrically connected to the gate electrode of the fourth transistor through the thirteenth via hole
  • the drain electrode of the third transistor is electrically connected to the gate electrode of the fifth transistor through the fourteenth via hole
  • the drain electrode of the seventh transistor is electrically connected to the gate electrode of the fifth transistor through the tenth via hole.
  • the six via holes are electrically connected to the first plate of the third capacitor.
  • the eleventh via hole includes two, one eleventh via hole exposes one end of the gate electrode of the first transistor away from the display area, and the other eleventh via hole exposes the first transistor The gate electrode is close to one end of the display area.
  • the thirteenth via hole includes two, one thirteenth via hole exposes one end of the gate electrode of the fourth transistor away from the display area, and the other eleventh via hole exposes the fourth transistor The gate electrode is close to one end of the display area.
  • the fifteenth via hole exposes one end of the gate electrode of the seventh transistor away from the display area.
  • the display substrate may further include: seventeenth to twenty-first via holes disposed on the third insulating layer.
  • the seventeenth via hole exposes the second electrode plate of the first capacitor
  • the eighteenth via hole exposes the second electrode plate of the second capacitor
  • the nineteenth via hole exposes the third electrode plate of the second capacitor.
  • the twentieth via hole exposes the first connection portion of the signal output end
  • the twenty-first via hole exposes the fourth connection portion of the signal output end.
  • the drain electrode of the sixth transistor is electrically connected to the second plate of the first capacitor through the seventeenth via hole
  • the source electrode of the sixth transistor is electrically connected to the second plate of the second capacitor through the eighteenth through hole
  • the drain electrode of the ninth transistor is electrically connected to the second plate of the third capacitor through the nineteenth via hole
  • the source electrode of the ninth transistor and the drain electrode of the tenth transistor are electrically connected to the signal output terminal through the twentieth via hole
  • the connection electrode is electrically connected to the signal output terminal through the twenty-first via hole.
  • the number of the seventeenth via holes may be multiple.
  • the plurality of seventeenth via holes are arranged along the first direction.
  • the number of the seventeenth via holes may be two.
  • the number of the eighteenth via holes may be multiple.
  • the plurality of eighteenth via holes are arranged along the first direction.
  • the number of the seventeenth via holes may be two.
  • the number of the nineteenth via holes may be multiple, and the multiple nineteenth via holes are arranged along the second direction.
  • the number of the nineteenth via holes may be four. The arrangement of the plurality of nineteenth via holes along the second direction can reduce the width of the driving circuit and realize a narrow frame.
  • the number of the twentieth via holes may be plural.
  • the number of the nineteenth via holes may be twelve.
  • the plurality of twentieth via holes are arranged along the first direction.
  • the structure of the display substrate will be described below through an example of a manufacturing process of the display substrate.
  • the "patterning process" referred to in this disclosure includes deposition of film layers, photoresist coating, mask exposure, development, etching and photoresist stripping treatments.
  • Deposition can use any one or more of sputtering, evaporation and chemical vapor deposition
  • coating can use any one or more of spray coating and spin coating
  • etching can use any one or more of dry etching and wet etching. one or more.
  • “Film” refers to a thin film made of a material on a substrate by a deposition or coating process.
  • the “film” may also be referred to as a "layer”. If the "film” needs a patterning process during the entire production process, it is called a "film” before the patterning process, and a “layer” after the patterning process.
  • the “layer” after the patterning process contains at least one "pattern”.
  • “A and B are arranged in the same layer” means that A and B are simultaneously formed through the same patterning process.
  • FIG. 12 to FIG. 16 are schematic diagrams of a manufacturing process of a display substrate provided by an exemplary embodiment. As shown in FIGS. 12 to 16 , a manufacturing process of a display substrate provided by an exemplary embodiment may include:
  • Forming a semiconductor layer pattern on the base substrate includes: depositing a semiconductor thin film on the base substrate, and patterning the semiconductor thin film through a patterning process to form a semiconductor layer pattern.
  • the semiconductor layer includes: the active layer 11 of the first transistor T1, the active layer 21 of the second transistor T2, the active layer 31 of the third transistor T3, the active layer 41 of the fourth transistor T4, The active layer 51 of the fifth transistor T5, the active layer 61 of the sixth transistor T6, the active layer 71 of the seventh transistor T7, the active layer 81 of the eighth transistor T8, the active layer 91 of the ninth transistor T9 and The active layer 110 of the tenth transistor T10 is shown in FIG. 12 .
  • FIG. 12 is a schematic diagram of a semiconductor layer pattern formed on the display substrate of the present disclosure.
  • the active layer 61 of the sixth transistor T6 and the active layer 71 of the seventh transistor T7 extend along the first direction.
  • the active layer 81 of the eighth transistor T8 extends in the second direction.
  • the active layer 91 of the ninth transistor T9 and the active layer 110 of the tenth transistor T10 extend along the first direction and are integrally formed elongated structures.
  • the first metal layer includes: depositing a first insulating film and a first metal film in sequence on the substrate on which the pattern is formed, and patterning the first insulating film and the first metal film through a patterning process to form a first insulating film and a first metal film.
  • the first metal layer includes: the first electrode plate C11 of the first capacitor C1, the first electrode plate C21 of the second capacitor C2, and the third capacitor C3 The first plate C31, the gate electrode 12 of the first transistor T1, the gate electrode 22 of the second transistor T2, the gate electrode 32 of the third transistor T3, the gate electrode 42 of the fourth transistor T4, the gate electrode of the fifth transistor T5 52.
  • FIG. 13 is a schematic diagram of a display substrate of the present disclosure after a first metal layer pattern is formed.
  • Each gate electrode is respectively arranged across the active layer of the corresponding transistor, that is to say, the extending direction of each gate electrode is perpendicular to the extending direction of the active layer of the corresponding transistor.
  • the gate electrode 22 of the second transistor T2, the gate electrode 120 of the tenth transistor T10, the gate electrode 82 of the eighth transistor T8, and the first plate C21 of the second capacitor C2 are integrally formed into a structure .
  • the gate electrode 52 of the fifth transistor T5, the gate electrode 62 of the sixth transistor T6 and the first electrode plate C11 of the first capacitor C1 are integrally formed.
  • the gate electrode 92 of the ninth transistor T9 and the first electrode plate C31 of the third capacitor C3 are integrally formed.
  • this process further includes a conductorization process.
  • Conduction treatment is performed by using the gate electrode 12 of the first transistor T1, the gate electrode 22 of the second transistor T2, the gate electrode 32 of the third transistor T3, the gate electrode 42 of the fourth transistor T4, The gate electrode 52 of the fifth transistor T5, the gate electrode 62 of the sixth transistor T6, the gate electrode 72 of the seventh transistor T7, the gate electrode 82 of the eighth transistor T8, the gate electrode 92 of the ninth transistor T9, and the gate electrode of the tenth transistor T10
  • the semiconductor layer in the region shielded by the gate electrode 120 (that is, the region where the semiconductor layer overlaps with each gate electrode) is used as the channel region of the transistor, and the semiconductor layer in the region not shielded by the first metal layer is processed into a conductive layer to form a conductive source Drain connection.
  • FIG. 14 is a schematic diagram of the display substrate after forming the second metal layer pattern according to the disclosure.
  • FIG. 15 is a schematic diagram of the display substrate after the third insulating layer pattern is formed.
  • the first via V1 exposes the active layer 11 of the first transistor
  • the second via V2 exposes the active layer 21 of the second transistor
  • the third via V3 exposes the third
  • the fourth via V4 exposes the active layer 41 of the fourth transistor
  • the fifth via V5 exposes the active layer 51 of the fifth transistor
  • the sixth via V6 exposes the active layer 51 of the sixth transistor.
  • the active layer 61, the seventh via hole exposes the active layer 71 of the seventh transistor
  • the eighth via hole V8 exposes the active layer 81 of the eighth transistor
  • the ninth via hole exposes the active layer 91 of the ninth transistor
  • the tenth via hole V10 exposes the active layer 110 of the tenth transistor.
  • the eleventh via V11 exposes the gate electrode 12 of the first transistor
  • the twelfth via V12 exposes the gate electrode 22 of the second transistor
  • the thirteenth via V13 exposes the gate electrode 42 of the fourth transistor
  • the tenth via V13 exposes the gate electrode 42 of the fourth transistor.
  • the four vias V14 expose the gate electrode 52 of the fifth transistor
  • the fifteenth via V15 exposes the gate electrode 72 of the seventh transistor
  • the sixteenth via V16 exposes the first plate C31 of the third capacitor.
  • the seventeenth via V17 exposes the second plate C12 of the first capacitor
  • the eighteenth via V18 exposes the second plate C22 of the second capacitor
  • the nineteenth via V19 exposes the second plate C22 of the third capacitor
  • the twentieth via hole V20 exposes the first connection portion of the output signal line EL
  • the twenty-first via hole V21 exposes the fourth connection portion of the output signal line EL.
  • Forming the third metal layer pattern includes: depositing a third metal thin film on the substrate on which the aforementioned pattern is formed, and patterning the third metal thin film through a patterning process to form a third metal layer pattern.
  • the third metal layer includes: the first power supply line VGH, the second power supply line VGL, the first clock signal line ECK, the second clock signal line ECB, the initial signal line ESTV, the connection electrode 40, the source electrode 13 of the first transistor T1, The source electrode 23 of the second transistor T2, the source electrode 33 of the third transistor T3, the source electrode 43 of the fourth transistor T4, the source electrode 63 of the sixth transistor T6, the source electrode 73 of the seventh transistor T7, the source electrode of the eighth transistor T8 The source electrode 83, the source electrode 93 of the ninth transistor T9, the source electrode 130 of the tenth transistor T10, the drain electrode 14 of the first transistor T1, the drain electrode 24 of the second transistor T2, the drain electrode 34 of the third transistor T3, the The drain electrode 54 of the fifth transistor T5, the drain electrode
  • the drain electrode 14 of the first transistor T1 and the source electrode 43 of the fourth transistor T4 are integrally formed.
  • the drain electrode 34 of the second transistor T2 and the drain electrode 34 of the third transistor T3 are integrally formed.
  • the source electrode 33 of the third transistor T3, the source electrode 130 of the tenth transistor T10 and the second power supply line VGL are integrally formed.
  • the drain electrode 64 of the sixth transistor T6 and the source electrode 73 of the seventh transistor T7 are integrally formed.
  • the drain electrode 74 of the seventh transistor T7 and the drain electrode 84 of the eighth transistor T8 are integrally formed.
  • the source electrode 83 of the eighth transistor T8, the drain electrode 94 of the ninth transistor T9, the drain electrode 54 of the fifth transistor T5 and the first power supply line VGH are integrally formed.
  • the source electrode 13 and the drain electrode 14 of the first transistor are electrically connected to the active layer 11 of the first transistor through the first via V1.
  • the source electrode 23 and the drain electrode 24 of the second transistor are electrically connected to the active layer 21 of the second transistor through the second via hole V2.
  • the source electrode 33 and the drain electrode 34 of the third transistor are electrically connected to the active layer 31 of the third transistor through the third via hole V3.
  • the source electrode 43 and the drain electrode 44 of the fourth transistor are electrically connected to the active layer 41 of the fourth transistor through the fourth via hole V4.
  • the source electrode 53 and the drain electrode 54 of the fifth transistor are electrically connected to the active layer of the fifth transistor through the fifth via hole V5.
  • the source electrode 63 and the drain electrode 64 of the sixth transistor are electrically connected to the active layer 61 of the sixth transistor through the sixth via hole V6.
  • the source electrode 73 and the drain electrode 74 of the seventh transistor are electrically connected to the active layer 71 of the seventh transistor through the seventh via hole V7.
  • the source electrode 83 and the drain electrode 84 of the eighth transistor are electrically connected to the active layer 81 of the eighth transistor through the eighth via hole V8.
  • the source electrode 93 and the drain electrode 94 of the ninth transistor are electrically connected to the active layer of the ninth transistor through the ninth via V9, and the source electrode 130 and the drain electrode 140 of the tenth transistor are connected to the tenth transistor through the tenth via V10.
  • the active layer 110 is electrically connected.
  • the first clock signal line ECK is electrically connected to the gate electrode 12 of the first transistor through the eleventh via V11.
  • the source electrode 23 of the second transistor is electrically connected to the gate electrode 12 of the first transistor through the eleventh via V11.
  • the drain electrode 14 of the first transistor is electrically connected to the gate electrode 22 of the second transistor through the twelfth via V12.
  • the second clock signal line ECB is electrically connected to the gate electrode 42 of the fourth transistor through the thirteenth via V13.
  • the source electrode 63 of the sixth transistor is electrically connected to the gate electrode 42 of the fourth transistor through the thirteenth via V13.
  • the drain electrode 34 of the third transistor is electrically connected to the gate electrode 52 of the fifth transistor through the fourteenth via V14.
  • the second clock signal line ECB is electrically connected to the gate electrode 72 of the seventh transistor through the fifteenth via V15.
  • the drain electrode 74 of the seventh transistor is electrically connected to the first plate C31 of the third capacitor through the sixteenth via V16.
  • the drain electrode 64 of the sixth transistor is electrically connected to the second electrode plate C12 of the first capacitor through the seventeenth via hole V17.
  • the source electrode 63 of the sixth transistor is electrically connected to the second electrode plate C22 of the second capacitor through the eighteenth via hole V18.
  • the drain electrode 94 of the ninth transistor is electrically connected to the second electrode plate C32 of the third capacitor through the nineteenth via hole V19.
  • the source electrode 93 of the ninth transistor and the drain electrode 140 of the tenth transistor are electrically connected to the first connection part of the signal output terminal through the twentieth via hole V20.
  • the connection electrode 40 is electrically connected to the fourth connection part of the signal output terminal through the twenty-first via hole V21.
  • FIG. 16 illustrates an example in which the first clock signal terminal of the shift register is electrically connected to the first clock signal line, and the second clock signal terminal of the shift register is electrically connected to the second clock signal line.
  • each shift register drives several rows of sub-pixels, as long as a device with a large area like this changes, and after the change generates additional space, a simple translation of a small device is possible , stretching are all within the protection scope of the present disclosure.
  • Embodiments of the present disclosure also provide a display device, and the display device may include: a display substrate.
  • the display substrate is the display substrate provided in any one of the foregoing embodiments, and the implementation principle and effect are similar, and details are not described herein again.
  • the display device may be a liquid crystal display device (Liquid Crystal Display, LCD for short) or an organic light emitting diode (Organic Light Emitting Diode, OLED for short) display device.
  • the display device can be: liquid crystal panel, electronic paper, OLED panel, active-matrix organic light emitting diode (active-matrix organic light emitting diode, AMOLED for short) panel, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame , navigator and any other product or component with display function.
  • Embodiments of the present disclosure also provide a method for fabricating a display substrate, which is configured to fabricate a display substrate.
  • the manufacturing method of the display substrate provided by the embodiment of the present disclosure includes:
  • Step S1 providing a base substrate.
  • the base substrate may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be, but not limited to, one or more of glass and metal tabs; the flexible substrate may be, but not limited to, a poly ethylene terephthalate, ethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, One or more of polyethylene and textile fibers.
  • Step S2 forming a driving circuit and a first power line in the non-display area on the base substrate.
  • the driving circuit includes: a first capacitor, a second capacitor and a third capacitor; the first capacitor and the third capacitor are arranged along a first direction, and the second capacitor and the third capacitor are respectively located in the first capacitor On both sides of the capacitor, the second capacitor is located on the side of the first capacitor close to the display area, and one plate of the third capacitor is electrically connected to the first power line.
  • the first power line extends along the first direction, and the orthographic projection of the first capacitor on the base substrate at least partially overlaps the orthographic projection of the first power line on the base substrate.
  • the display substrate is the display substrate provided in any one of the foregoing embodiments, and the implementation principle and effect are similar, and details are not described herein again.
  • the driving circuit includes: a plurality of shift registers, each shift register includes: a plurality of transistors and first to third capacitors, and step S2 may include:
  • Step S21 forming a semiconductor layer on the base substrate.
  • the semiconductor layer includes: active layers of a plurality of transistors.
  • the semiconductor layer may be an amorphous silicon layer, a polysilicon layer, or may be a metal oxide layer.
  • the metal oxide layer can be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten and indium and zinc, an oxide containing titanium and indium, an oxide containing titanium and indium and tin oxides, oxides containing indium and zinc, oxides containing silicon and indium and tin, or oxides containing indium or gallium and zinc.
  • the metal oxide layer may be a single layer, or it may be a double layer, or it may be multiple layers.
  • a first insulating layer and a first metal layer are sequentially formed on the semiconductor layer.
  • the first metal layer includes: gate electrodes of a plurality of transistors, a first electrode plate of the first capacitor, a first electrode plate of the second capacitor, and a first electrode plate of the third capacitor.
  • the first metal layer may be a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or the above Metal alloy materials, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), can be a single-layer structure, or a multi-layer composite structure, such as Mo/Cu/Mo and the like.
  • the fabrication material of the first metal layer may include: molybdenum.
  • Step S23 forming a second insulating layer and a second metal layer on the first metal layer in sequence.
  • the second metal layer includes: the second electrode plate of the first capacitor, the second electrode plate of the second capacitor, the second electrode plate of the third capacitor and the signal output terminal.
  • the second metal layer may be a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or the above Metal alloy materials, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), can be a single-layer structure, or a multi-layer composite structure, such as Mo/Cu/Mo and the like.
  • the fabrication material of the second metal layer may include: molybdenum.
  • Step S24 forming a third insulating layer and a third metal layer on the second metal layer in sequence.
  • the third metal layer includes: source electrodes of a plurality of transistors, drain electrodes of a plurality of transistors, a first power supply line, a second power supply line, a first clock signal line, a second clock signal line, an initial signal line and a connection electrode .
  • the third metal layer may adopt a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or the above Metal alloy materials, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), can be a single-layer structure, or a multi-layer composite structure, such as Mo/Cu/Mo and the like.
  • the third metal layer may be a three-layer stack structure formed of titanium, aluminum and titanium.
  • the first insulating layer, the second insulating layer and the third insulating layer may adopt any one of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON). or more, it may be a single layer, multiple layers or composite layers.
  • the first insulating layer is called a first gate insulating layer
  • the second insulating layer is called a second gate insulating layer
  • the third insulating layer is called an interlayer insulating layer.

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Abstract

一种显示基板及其制作方法、显示装置，其中，显示基板包括：衬底基板以及设置在衬底基板上驱动电路和第一电源线，驱动电路至少包括：第一电容、第二电容和第三电容；第一电容和第三电容沿第一方向排布，第二电容和第三电容分别位于第一电容的两侧，第二电容位于第一电容靠近显示区的一侧，第三电容的一个极板与第一电源线电连接；第一电源线沿第一方向延伸，第一电容在衬底基板上的正投影与第一电源线在衬底基板上的正投影至少部分重叠。

Description

一种显示基板及其制作方法、显示装置
本申请要求于2021年4月29日提交中国专利局、申请号为202110476854.7、发明名称为“一种显示基板及其制作方法、显示装置”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本公开实施例涉及但不限于显示技术领域，特别涉及一种显示基板及其制作方法、显示装置。
背景技术
有机发光二极管显示装置(Organic Light Emitting Diode，OLED)具有超薄、大视角、主动发光、高亮度、发光颜色连续可调、成本低、响应速度快、低功耗、工作温度范围宽及可柔性显示等优点，已逐渐成为极具发展前景的下一代显示技术。驱动电路是OLED中一种重要的辅助电路。
随着显示技术的不断发展，大“屏占比(即实际显示区的面积在显示侧总面积中的占比)”已成为显示装置追求的外观特性之一。尤其是对与佩戴式显示装置(如智能手表)，基于便携和视角效果的方面的考虑，极致窄边框甚至全屏显示成为发展的重要趋势。
发明概述
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
第一方面，本公开提供了一种显示基板，包括：显示区和非显示区，包括：衬底基板以及设置在所述衬底基板上，且位于非显示区的驱动电路和第一电源线，所述驱动电路至少包括：第一电容、第二电容和第三电容；所述第一电容和所述第三电容沿第一方向排布，所述第二电容和所述第三电容分 别位于所述第一电容的两侧，所述第二电容位于所述第一电容靠近显示区的一侧，所述第三电容的一个极板与所述第一电源线电连接；
所述第一电源线沿第一方向延伸，所述第一电容在衬底基板上的正投影与所述第一电源线在衬底基板上的正投影至少部分重叠。
在一些可能的实现方式中，所述第三电容在衬底基板上的正投影与所述第一电源线在衬底基板上的正投影至少部分重叠。
在一些可能的实现方式中，所述显示基板还包括：设置在所述衬底基板上，且位于非显示区的第二电源线、初始信号线、第一时钟信号线和第二时钟信号线；
所述第二电源线位于驱动电路靠近显示区的一侧，且沿第一方向延伸，所述初始信号线位于第一电源线远离显示区的一侧，且沿第一方向延伸，所述第一时钟信号线位于所述第一电源线和所述初始信号线之间，且沿第一方向延伸，所述第二时钟信号线位于所述第一时钟信号线和所述初始信号线之间，且沿第一方向延伸；
所述第二电源线的宽度小于或者等于所述第一电源线的宽度，和/或，所述初始信号线的宽度小于所述第一电源线的宽度，和/或，所述第一时钟信号线的宽度小于所述第一电源线的宽度，且大于初始信号线的宽度，和/或，所述第二时钟信号线的宽度小于所述第一电源线的宽度，且大于初始信号线的宽度。
在一些可能的实现方式中，所述驱动电路包括：多个沿第一方向排布的移位寄存器，每个移位寄存器包括：第一晶体管至第十晶体管、第一电容至第三电容、信号输入端、信号输出端、第一时钟信号端、第二时钟信号端、第一电源端和第二电源端；
所述第一晶体管的栅电极与第一时钟信号端电连接，所述第一晶体管的源电极与信号输入端电连接，所述第一晶体管的漏电极与第一节点电连接；
所述第二晶体管的栅电极与第一节点电连接，所述第二晶体管的源电极与第一时钟信号端电连接，所述第二晶体管的第二极与第二节点电连接；
所述第三晶体管的栅电极与第一时钟信号端电连接，所述第三晶体管的 源电极与第二电源端电连接，所述第三晶体管的第二极与第二节点电连接；
所述第四晶体管的栅电极与第二时钟信号端电连接，所述第四晶体管的源电极与第一节点电连接，所述第四晶体管的漏电极与所述第五晶体管的源电极电连接；
所述第五晶体管的栅电极与第二节点电连接，所述第五晶体管的漏电极与第一电源端电连接；
所述第六晶体管的栅电极与第二节点电连接，所述第六晶体管的源电极与第二时钟信号端电连接，所述第六晶体管的漏电极与第三节点电连接；
所述第七晶体管的栅电极与第二时钟信号端电连接，所述第七晶体管的源电极与第三节点电连接，所述第七晶体管的漏电极与第四节点电连接；
所述第八晶体管的栅电极与第一节点电连接，所述第八晶体管的源电极与第一电源端电连接，所述第八晶体管的漏电极与第四节点电连接；
所述第九晶体管的栅电极与第四节点电连接，所述第九晶体管的源电极与信号输出端电连接，所述第九晶体管的漏电极与第一电源端电连接；
所述第十晶体管的栅电极与第一节点电连接，所述第十晶体管的源电极与第二电源端电连接，所述第十晶体管的漏电极与信号输出端电连接；
所述第一电容的第一极板与第二节点电连接，所述第一电容的第二极板与第三节点电连接；
所述第二电容的第一极板与第一节点电连接，所述第二电容的第二极板与第二时钟信号端电连接；
所述第三电容的第一极板与第四节点电连接，所述第三电容的第二极板与第一电源端电连接。
在一些可能的实现方式中，所述第一电容的第一极板位于所述第一电容的第二极板靠近衬底基板的一侧，且所述第一电容的第一极板在衬底基板上的正投影覆盖所述第一电容的第二极板在衬底基板上的正投影；
所述第二电容的第一极板位于所述第二电容的第二极板靠近衬底基板的一侧，且所述第二电容的第一极板在衬底基板上的正投影覆盖所述第二电容的第二极板在衬底基板上的正投影；
所述第三电容的第一极板位于所述第三电容的第二极板靠近衬底基板的一侧，且所述第三电容的第一极板在衬底基板上的正投影覆盖所述第三电容的第二极板在衬底基板上的正投影；
其中，所述第一电容的第一极板与所述第一电源线的重叠部分的面积与所述第一电容的第一极板的面积正相关，所述第三电容的第一极板与所述第一电源线的重叠部分的面积与所述第三电容的第一极板的面积正相关；
所述第一电容的第一极板与所述第一电源线的重叠部分的面积小于所述第三电容的第一极板与所述第一电源线的重叠部分的面积。
在一些可能的实现方式中，所述驱动电路中的多个移位寄存器级联，第一级移位寄存器的信号输入端与初始信号线电连接，第i-1级移位寄存器的信号输出端与第i级移位寄存器的信号输入端电连接，所有移位寄存器的第一电源端与第一电源线电连接，所述移位寄存器的第二电源端与第二电源线电连接，奇数级移位寄存器的第一时钟信号端与第一时钟信号线电连接，奇数级移位寄存器的第二时钟信号端与第二时钟信号线电连接，偶数级移位寄存器的第一时钟信号端与第二时钟信号线电连接，偶数级移位寄存器的第二时钟信号端与第一时钟信号线电连接，其中，i为大于或等于2的正整数。
在一些可能的实现方式中，所述显示基板还包括：设置在所述衬底基板上，且位于显示区的阵列排布的子像素；
第i级移位寄存器的信号输出端与第2i-1行子像素和第2i行子像素电连接。
在一些可能的实现方式中，每个移位寄存器包括：异层设置的连接电极和输出信号线；
所述输出信号线与本级移位寄存器的信号输出端电连接，所述连接电极在衬底基板上的正投影与所述输出信号线在衬底基板上的正投影至少部分重叠；
所述连接电极分别与本级移位寄存器的信号输出端和下一级移位寄存器的信号输入端电连接。
在一些可能的实现方式中，所述显示基板包括：依次叠设在所述衬底基 板上的半导体层、第一绝缘层、第一金属层、第二绝缘层、第二金属层、第三绝缘层和第三金属层；
所述半导体层包括：多个晶体管的有源层，所述第一金属层包括：多个晶体管的栅电极、第一电容的第一极板、第二电容的第一极板和第三电容的第一极板，所述第二金属层包括：第一电容的第二极板、第二电容的第二极板、第三电容的第二极板和输出信号线，所述第三金属层包括：多个晶体管的源电极、多个晶体管的漏电极、第一电源线、第二电源线、第一时钟信号线、第二时钟信号线、初始信号线和连接电极；
所述第三金属层的电阻小于所述第一金属层的电阻，且小于所述第二金属层的电阻。
在一些可能的实现方式中，在每个移位寄存器中，所有晶体管的有源层包括：沟道区和位于沟道区两侧的源极连接部和漏极连接部，晶体管的源电极与源极连接部电连接，晶体管的漏电极与漏极连接部电连接；
第四晶体管的有源层的漏极连接部复用为漏电极，第五晶体管的有源层的源极连接部复用为源电极，第四晶体管的有源层的漏极连接部与第五晶体管的有源层的源极连接部电连接。
在一些可能的实现方式中，在每个移位寄存器中，第二晶体管的栅电极、第十晶体管的栅电极、第八晶体管的栅电极和第二电容的第一极板为一体成型结构，第五晶体管的栅电极、第六晶体管的栅电极和第一电容的第一极板为一体成型结构，第九晶体管的栅电极和第三电容的第一极板为一体成型结构；
第一晶体管的漏电极和第四晶体管的源电极为一体成型结构，第二晶体管的漏电极和第三晶体管的漏电极为一体成型结构，第三晶体管的源电极、第十晶体管的源电极和第二电源线为一体成型结构，第六晶体管的漏电极和第七晶体管的源电极为一体成型结构，第七晶体管的漏电极和第八晶体管的漏电极为一体成型结构，第八晶体管的源电极、第九晶体管的漏电极，第五晶体管的漏电极和第一电源线为一体成型结构。
在一些可能的实现方式中，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管和所述第五晶体管位于所述第一电容远离所述第 三电容的一侧，且位于所述第二电容靠近第一电源线的一侧；所述第六晶体管位于所述第一电容靠近第二电源线的一侧，且位于第二电容靠近第三电容的一侧，所述第七晶体管和第八晶体管位于所述第一电容和所述第三电容之间，所述第九晶体管和所述第十晶体管位于所述第二电容靠近第二电源线的一侧。
在一些可能的实现方式中，在每个移位寄存器中，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管、所述第七晶体管、所述第九晶体管和所述第十晶体管的有源层沿第一方向延伸，所述第八晶体管的有源层沿第二方向延伸，所述第六晶体管的源电极和漏电极沿第一方向排布；
所述第一方向和所述第二方向相交。
在一些可能的实现方式中，所述第一电源线与第一电容靠近第二电源线的边缘之间的距离小于所述第一电源线与第六晶体管的源电极之间的距离。
在一些可能的实现方式中，每个移位寄存器中的输出信号线包括：一体成型的第一连接部、第二连接部、第三连接部和第四连接部；
所述第一连接部在衬底基板上的正投影与第九晶体管的源电极在衬底基板上的正投影至少部分重叠，且与第十晶体管的漏电极在衬底基板上的正投影至少部分重叠，所述第一连接部沿第一方向延伸；
所述第二连接部、所述第三连接部、所述第四连接部沿第二方向延伸，所述第二连接部和所述第三连接部位于所述第一连接部远离第一电源线的一侧，所述第四连接部位于所述第一连接部靠近第一电源线的一侧；
所述第二连接部与第2i-1行子像素电连接，所述第三连接部与第2i行子像素电连接；所述第四连接部与下一级移位寄存器的信号输入端电连接；
所述连接电极在衬底基板上的正投影与所述第四连接部在衬底基板上的正投影至少部分重叠，所述第四连接部通过连接电极与下一级移位寄存器的信号输入端电连接。
在一些可能的实现方式中，对于每个移位寄存器，所述显示基板还包括：贯穿所述第一绝缘层、所述第二绝缘层和所述第三绝缘层的第一过孔至第十 过孔；
所述第一过孔暴露出第一晶体管的有源层，所述第二过孔暴露出第二晶体管的有源层，所述第三过孔暴露出第三晶体管的有源层，所述第四过孔暴露出第四晶体管的有源层，所述第五过孔暴露出第五晶体管的有源层，所述第六过孔暴露出第六晶体管的有源层，所述第七过孔暴露出第七晶体管的有源层，所述第八过孔暴露出第八晶体管的有源层，所述第九过孔暴露出第九晶体管的有源层，所述第十过孔暴露出第十晶体管的有源层；
第一晶体管的源电极和漏电极通过第一过孔与第一晶体管的有源层电连接，第二晶体管的源电极和漏电极通过第二过孔与第二晶体管的有源层电连接，第三晶体管的源电极和漏电极通过第三过孔与第三晶体管的有源层电连接，第四晶体管的源电极和漏电极通过第四过孔与第四晶体管的有源层电连接，第五晶体管的源电极和漏电极通过第五过孔与第五晶体管的有源层电连接，第六晶体管的源电极和漏电极通过第六过孔与第六晶体管的有源层电连接，第七晶体管的源电极和漏电极通过第七过孔与第七晶体管的有源层电连接，第八晶体管的源电极和漏电极通过第八过孔与第八晶体管的有源层电连接，第九晶体管的源电极和漏电极通过第九过孔与第九晶体管的有源层电连接，第十晶体管的源电极和漏电极通过第十过孔与第十晶体管的有源层电连接。
在一些可能的实现方式中，所述显示基板还包括：贯穿第二绝缘层和第三绝缘层的第十一过孔至第十六过孔；
所述第十一过孔暴露出第一晶体管的栅电极，所述第十二过孔暴露出第二晶体管的栅电极，所述第十三过孔暴露出第四晶体管的栅电极，所述第十四过孔暴露出第五晶体管的栅电极，所述第十六过孔暴露出第三电容的第一极板；
第二晶体管的源电极通过第十一过孔与第一晶体管的栅电极的电连接，第一晶体管的漏电极通过第十二过孔与第二晶体管的栅电极电连接，第六晶体管的源电极通过第十三过孔与第四晶体管的栅电极电连接，第三晶体管的漏电极通过第十四过孔与第五晶体管的栅电极电连接，第七晶体管的漏电极通过第十六过孔与第三电容的第一极板电连接。
在一些可能的实现方式中，所述显示基板还包括：设置在第三绝缘层上的第十七过孔至第二十一过孔；
所述第十七过孔暴露出第一电容的第二极板，所述第十八过孔暴露出第二电容的第二极板，所述第十九过孔暴露出第三电容的第二极板，所述第二十过孔暴露出信号输出端的第一连接部，所述第二十一过孔暴露出信号输出端的第四连接部；
第六晶体管的漏电极通过第十七过孔与第一电容的第二极板电连接，第六晶体管的源电极通过第十八过孔与第二电容的第二极板电连接，第九晶体管的漏电极通过第十九过孔与第三电容的第二极板电连接，第九晶体管的源电极和第十晶体管的漏电极通过第二十过孔与信号输出端电连接，连接电极通过第二十一过孔与信号输出端电连接；
所述第十七过孔的数量为多个，多个第十七过孔沿第一方向排布；
所述第十八过孔的数量为多个，多个第十八过孔沿第一方向排布；
所述第十九过孔的数量为多个，多个第十九过孔沿第二方向排布。
所述第二十过孔的数量为多个，多个第二十过孔沿第一方向排布。
第二方面，本公开还提供了一种显示装置，包括上述显示基板。
第三方面，本公开还提供了一种显示基板的制作方法，设置为制作上述显示基板，所述方法包括：
提供一衬底基板；
在衬底基板上形成位于非显示区的驱动电路和第一电源线；所述驱动电路包括：第一电容、第二电容和第三电容；所述第一电容和所述第三电容沿第一方向排布，所述第二电容和所述第三电容分别位于所述第一电容的两侧，所述第二电容位于所述第一电容靠近显示区的一侧，所述第三电容的一个极板与所述第一电源线电连接；
所述第一电源线沿第一方向延伸，所述第一电容在衬底基板上的正投影与所述第一电源线在衬底基板上的正投影至少部分重叠。
在一些可能的实现方式中，所述驱动电路包括：多个移位寄存器，每个移位寄存器包括：多个晶体管以及第一电容至第三电容，所述在衬底基板上 形成位于非显示区的驱动电路和第一电源线包括：
在衬底基板上形成半导体层，所述半导体层包括：多个晶体管的有源层；
在半导体层上依次形成第一绝缘层和第一金属层，所述第一金属层包括：多个晶体管的栅电极、第一电容的第一极板、第二电容的第一极板和第三电容的第一极板；
在第一金属层上依次形成第二绝缘层和第二金属层，所述第二金属层包括：第一电容的第二极板、第二电容的第二极板、第三电容的第二极板和输出信号线；
在第二金属层上依次形成第三绝缘层和第三金属层，所述第三金属层包括：多个晶体管的源电极、多个晶体管的漏电极、第一电源线、第二电源线、第一时钟信号线、第二时钟信号线、初始信号线和连接电极。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图概述
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1为本公开实施例提供的显示基板的结构示意图；
图2为本公开实施例提供的驱动电路的俯视图；
图3为一种显示基板的剖面结构示意图；
图4为一种示例性实施例提供的驱动电路的结构示意图；
图5为一种示例性实施例提供的移位寄存器的等效电路图；
图6为一种示例性实施例提供的移位寄存器的工作时序图；
图7为一种示例性实施例提供的驱动电路的时序图；
图8为一种示例性实施例提供的半导体层的结构示意图；
图9为一种示例性实施例提供的第一金属层的结构示意图；
图10为一种示例性实施例提供的第二金属层的结构示意图；
图11为一种示例性实施例提供的第三金属层的结构示意图；
图12为本公开显示基板形成半导体层图案后的示意图；
图13为本公开显示基板形成第一金属层图案后的示意图；
图14为本公开显示基板形成第二金属层图案后的示意图；
图15为本公开显示基板形成第三绝缘层图案后的示意图；
图16为本公开一个示例性实施例中显示基板的示意图。
详述
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了各构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中各部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连 接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
本领域技术人员可以理解，本公开所有实施例中采用的晶体管可以为薄膜晶体管或场效应管或其他特性相同的器件。薄膜晶体管可以是氧化物半导体薄膜晶体管晶体管、低温多晶硅薄膜晶体管、非晶硅薄膜晶体管或微晶硅薄膜晶体管。薄膜晶体管具体可以选择底栅结构的薄膜晶体管或者顶栅结构的薄膜晶体管，只要能够实现开关功能即可。由于这里采用的晶体管的源极、漏极是对称的，所以其源极、漏极可以互换。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
图1为本公开实施例提供的显示基板的结构示意图，图2为本公开实施 例提供的驱动电路的俯视图。如图1和图2所示，本公开实施例提供的显示基板可以包括：显示区以及位于显示区周边的非显示区。显示基板可以包括：衬底基板以及设置在衬底基板上，且位于非显示区的驱动电路10和第一电源线VGH，驱动电路至少可以包括：第一电容C1、第二电容C2和第三电容C3。第一电容C1和第三电容C3沿第一方向排布，第二电容C2和第三电容C3分别位于第一电容C1的两侧，第二电容C2位于第一电容C1靠近显示区的一侧，第三电容C3的一个极板与第一电源线VGH电连接。
第一电源线VGH沿第一方向延伸。第一电容C1在衬底基板上的正投影与第一电源线VGH在衬底基板上的正投影至少部分重叠。
在一种示例性实施例中，衬底基板可以为刚性基底或柔性基底，其中，刚性基底可以为但不限于玻璃、金属箔片中的一种或多种；柔性基底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。
在一种示例性实施例中，第一电源线VGH可以位于第二电容C2远离显示区的一侧。
在一种示例性实施例中，第一电源线VGH可以持续提供高电平的直流信号。
在一种示例性实施例中，第一电源线VGH的宽度可以约为6微米至12微米。
在一种示例性实施例中，第一电容C1、第二电容C2和第三电容C3的数量为多个，根据显示基板的实际需求确定，本公开对此不作任何限定。
在一种示例性实施例中，显示区可以设置有规则排布的多个子像素PA、沿着第二方向延伸的多条第一信号线(例如，包括扫描线G、控制信号线和发光控制线E)、沿着第一方向延伸的多条第二信号线(例如，包括数据线DL)。
在一种示例性实施例中，至少一条第一信号线可以沿第二方向延伸，且多条第一信号线可以沿第一方向依次排布。至少一条第二信号线可以沿第一 方向延伸，且多条第二信号线可以第二方向依次排布。
在一种示例性实施例中，多个子像素中的至少一个子像素PA可以包括：发光元件和用于驱动发光元件发光的像素驱动电路。像素驱动电路可以采用3T1C、5T1C或7T1C的设计。
在一种示例性实施例中，第一方向与第二方向相交指的是第一方向与第二方向之间的夹角约为70度至90度。第一方向和第二方向可以位于同一平面内。例如，第一方向可以为行方向，平行于扫描线的延伸方向；第二方向可以为列方向，平行于数据线的延伸方向。
在一些示例性实施例中，如图1所示，沿第一方向设置有m行扫描线G1至Gm，沿第一方向设置有m行发光信号线E1至Em，沿第二方向且设置有n列数据线DL1至DLn。扫描线与数据线相互绝缘，发光信号线和数据线相互绝缘。其中，m和n均为大于0的整数。子像素PA可以分布在m行扫描线和n列数据线的交叉位置。多个子像素PA按照矩阵状规则排布。
一种示例性实施例中，子像素可以为红色(R)子像素、绿色(G)子像素、蓝色(B)子像素、白色子像素中的任一种，本公开在此不做限定。当显示面板中包括红色(R)子像素，绿色(G)子像素和蓝色(B)子像素时，三个子像素可以采用水平并列、竖直并列或品字方式排列。当显示面板中包括红色(R)子像素，绿色(G)子像素、蓝色(B)子像素和白色子像素时，四个子像素可以采用水平并列、竖直并列或阵列方式排列，本公开在此不做限定。
图3为一种显示基板的剖面结构示意图，示意了显示基板三个子像素的结构。在垂直于显示基板的平面上，显示基板可以包括设置在基底101上的驱动电路层102、设置在驱动电路层102远离衬底基板101一侧的发光器件103以及设置在发光器件103远离基底101一侧的封装层104。在一些可能的实现方式中，显示基板可以包括其它膜层，如隔垫柱等，本公开在此不做限定。
在示例性实施方式中，基底101可以是柔性基底，或者可以是刚性基底。每个子像素的驱动电路层102可以包括构成像素驱动电路的多个晶体管和存 储电容，图3中的每个子像素仅示出一个晶体管101和一个存储电容101A作为示例。发光器件103可以包括阳极301、像素定义层302、有机发光层303和阴极304，阳极301通过过孔与驱动晶体管210的漏电极连接，有机发光层303与阳极301连接，阴极304与有机发光层303连接，有机发光层303在阳极301和阴极304驱动下出射相应颜色的光线。封装层104可以包括叠设的第一封装层401、第二封装层402和第三封装层403，第一封装层401和第三封装层403可以采用无机材料，第二封装层402可以采用有机材料，第二封装层402设置在第一封装层401和第三封装层403之间，可以保证外界水汽无法进入发光器件103。
在示例性实施方式中，有机发光层303可以包括叠设的空穴注入层(Hole Injection Layer，简称HIL)、空穴传输层(Hole Transport Layer，简称HTL)、电子阻挡层(Electron Block Layer，简称EBL)、发光层(Emitting Layer，简称EML)、空穴阻挡层(Hole Block Layer，简称HBL)、电子传输层(Electron Transport Layer，简称ETL)和电子注入层(Electron Injection Layer，简称EIL)。在示例性实施方式中，所有子像素的空穴注入层可以是连接在一起的共通层，所有子像素的电子注入层可以是连接在一起的共通层，所有子像素的空穴传输层可以是连接在一起的共通层，所有子像素的电子传输层可以是连接在一起的共通层，所有子像素的空穴阻挡层可以是连接在一起的共通层，相邻子像素的发光层可以有少量的交叠，或者可以是隔离的，相邻子像素的电子阻挡层可以有少量的交叠，或者可以是隔离的。
在一种示例性实施例中，发光结构可以是有机电致发光二极管(OLED)，包括叠设的第一极(阳极)、有机发光层和第二极(阴极)。
在一种示例性实施例中，驱动电路可以为扫描驱动电路和/或发光驱动电路，本公开对此不作任何限定。
在一些示例性实施例中，如图1所示，非显示区还可以设置有时序控制器20和数据驱动电路(图中未示出)。其中，驱动电路20可以设置在显示区的左侧或者右侧，时序控制器和数据驱动电路可以设置在显示区的上侧或者下侧。其中，数据驱动电路可以通过多条数据线DL向多列子像素提供数据信号。扫描驱动电路可以通过多条扫描线G向多行子像素提供扫描信号。 扫描驱动电路除了扫描信号之外，还可以按行生成与扫描信号同步的至少一种控制信号，并提供给显示区的多行子像素。发光驱动电路可以通过多条发光控制线E向多行子像素提供发光控制信号。
在一种示例性实施例中，时序控制器可以将适合于数据驱动电路的规格的灰度值和控制信号提供到数据驱动电路，可以将适合于扫描驱动电路的规格的时钟信号、扫描起始信号等提供到扫描驱动电路，可以将适合于发光驱动电路的规格的时钟信号、发射停止信号等提供到发光驱动电路。
在一种示例性实施例中，数据驱动电路可以利用从时序控制器接收的灰度值和控制信号来产生将提供到数据线的数据电压。
在一种示例性实施例中，扫描驱动电路可以通过从时序控制器接收时钟信号、扫描起始信号等来产生将提供到扫描线的扫描信号。例如，扫描驱动电路可以将扫描信号顺序地提供到扫描信号。例如，扫描驱动电路可以由多个级联的移位寄存器的构成，并且可以以在时钟信号的控制下让各个移位寄存器依次顺序地产生扫描信号。
在一种示例性实施例中，发光驱动电路可以通过从时序控制器接收时钟信号、发射停止信号等来产生将提供到发光信号线的发光信号。例如，发光驱动电路可以将发光信号顺序地提供到发光信号线。例如，发光驱动电路可以由多个级联的移位寄存器的构成，并且可以以在时钟信号的控制下各个移位寄存器依次顺序地产生发光信号。
在一种示例性实施例中，本公开提供的显示基板相比于第一电容C1和第三电容C3没有与第一电源线VGH重叠的显示基板来说，第一电容C1沿第一方向的长度变长，沿第二方向的长度变窄，第三电容C3沿第一方向的长度变长，沿第二方向的长度变窄。
本公开实施例提供的显示基板包括：衬底基板以及设置在衬底基板上，且位于非显示区的驱动电路和第一电源线，驱动电路至少包括：第一电容、第二电容和第三电容；第一电容和第三电容沿第一方向排布，第二电容和第三电容分别位于第一电容的两侧，第二电容位于第一电容靠近显示区的一侧，第三电容的一个极板与第一电源线电连接；第一电源线位于第二电容远离显 示区的一侧，且沿第一方向延伸，第一电容在衬底基板上的正投影与第一电源线在衬底基板上的正投影至少部分重叠，第三电容在衬底基板上的正投影与第一电源线在衬底基板上的正投影至少部分重叠。本公开实施例通过第一电容在衬底基板上的正投影与第一电源线在衬底基板上的正投影至少部分重叠，减少了驱动电路所占用的面积，减少显示基板中非显示区的宽度，实现显示产品的窄边框。
如图2所示，在一种示例性实施例中，第三电容C3在衬底基板上的正投影与第一电源线VGH在衬底基板上的正投影至少部分重叠。第三电容在衬底基板上的正投影与第一电源线在衬底基板上的正投影至少部分重叠，减少了驱动电路所占用的面积，减少显示基板中非显示区的宽度，实现显示产品的窄边框。
如图2所示，在一种示例性实施例中，显示基板还可以包括：设置在衬底基板上，且位于非显示区的第二电源线VGL、初始信号线ESTV、第一时钟信号线ECK和第二时钟信号线ECB。
在一种示例性实施例中，第二电源线VGL位于驱动电路10靠近显示区的一侧，且沿第一方向延伸。初始信号线ESTV位于第一电源线VGH远离显示区的一侧，且沿第一方向延伸。第一时钟信号线ECK位于第一电源线VGH和初始信号线ESTV之间，且沿第一方向延伸。第二时钟信号线ECB位于第一时钟信号线ECK和初始信号线ESTV之间，且沿第一方向延伸。
在一种示例性实施例中，第二电源线VGL可以持续提供低电平的直流信号。初始信号线ESTV可以提供脉冲信号。第一时钟信号线ECK可以提供周期性的脉冲信号，第二时钟信号线ECB可以提供周期性的脉冲信号。第一时钟信号线ECK和第二时钟信号线ECB不同时为有效电平信号。
在一种示例性实施例中，第二电源线VGL的宽度可以小于或者等于第一电源线VGH的宽度，和/或，初始信号线ESTV的宽度可以小于第一电源线VGH的宽度，和/或，第一时钟信号线ECK的宽度可以小于第一电源线VGH的宽度，且可以大于初始信号线ESTV的宽度，和/或，第二时钟信号线ECB的宽度可以小于第一电源线VGH的宽度，且可以大于初始信号线ESTV的宽度。
本实施例中，第二电源线VGL的宽度小于或者等于第一电源线VGH的宽度可以减少显示基板的非显示区的宽度，实现窄边框。
在一种示例性实施例中，第二电源线VGL的宽度可以约为6微米至12微米。
本实施例中，初始信号线ESTV的宽度小于第一电源线VGH的宽度可以减少显示基板的非显示区的宽度，实现窄边框。
在一种示例性实施例中，初始信号线ESTV的宽度可以约为5微米至10微米。
本实施例中，第一时钟信号线ECK的宽度小于第一电源线VGH的宽度可以减少显示基板的非显示区的宽度，实现窄边框。
在一种示例性实施例中，第一时钟信号线ECK的宽度可以约为6微米至20微米。
本实施例中，第二时钟信号线ECB的宽度小于第一电源线VGH的宽度可以减少显示基板的非显示区的宽度，实现窄边框。
在一种示例性实施例中，第二时钟信号线ECB的宽度可以约为6微米至20微米。
图4为一种示例性实施例提供的驱动电路的结构示意图，图5为一种示例性实施例提供的移位寄存器的等效电路图。图4是以驱动电路为发光驱动电路为例进行说明的。如图4和图5所示，驱动电路包括：多个沿第一方向排布的移位寄存器EOA(1)至EOA(k)，k＝m/2。每个移位寄存器EOA包括：第一晶体管T1至第十晶体管T10、第一电容C1至第三电容C3、信号输入端EIN、信号输出端EOUT、第一时钟信号端CK1、第二时钟信号端CK2、第一电源端VL1和第二电源端VL2。
第一晶体管T1的栅电极与第一时钟信号端CK1电连接，第一晶体管T1的源电极与信号输入端EIN电连接，第一晶体管T1的漏电极与第一节点N1电连接。第二晶体管T2的栅电极与第一节点N1电连接，第二晶体管T2的源电极与第一时钟信号端CK1电连接，第二晶体管T2的第二极与第二节点N2电连接。第三晶体管T3的栅电极与第一时钟信号端CK1电连接，第三晶 体管T3的源电极与第二电源端VL2电连接，第三晶体管T3的第二极与第二节点N2电连接。第四晶体管T4的栅电极与第二时钟信号端CK2电连接，第四晶体管T4的源电极与第一节点N1电连接，第四晶体管T4的漏电极与第五晶体管的源电极电连接。第五晶体管T5的栅电极与第二节点N2电连接，第五晶体管T5的漏电极与第一电源端VL1电连接。第六晶体管T6的栅电极与第二节点N2电连接，第六晶体管T6的源电极与第二时钟信号端CK2电连接，第六晶体管T6的漏电极与第三节点N3电连接。第七晶体管T7的栅电极与第二时钟信号端CK2电连接，第七晶体管T7的源电极与第三节点N3电连接，第七晶体管T7的漏电极与第四节点N4电连接。第八晶体管T8的栅电极与第一节点N1电连接，第八晶体管T8的源电极与第一电源端VL1电连接，第八晶体管T8的漏电极与第四节点N4电连接。第九晶体管T9的栅电极与第四节点N4电连接，第九晶体管T9的源电极与信号输出端EOUT电连接，第九晶体管T9的漏电极与第一电源端VL1电连接。第十晶体管T10的栅电极与第一节点N1电连接，第十晶体管T10的源电极与第二电源端VL2电连接，第十晶体管T10的漏电极与信号输出端EOUT电连接。第一电容C1的第一极板C11与第二节点N2电连接，第一电容C1的第二极板C12与第三节点N3电连接。第二电容C2的第一极板C21与第一节点N1电连接，第二电容C2的第二极板C22与第二时钟信号端CK2电连接。第三电容C3的第一极板C31与第四节点N4电连接，第三电容C3的第二极板C32与第一电源端VL1电连接。
在一种示例性实施例中，第一时钟信号端CK1和第二时钟信号端CK2分别在高低电平间不断切换。
在一种示例性实施例中，第一电源端VL1持续输出高电平信号，第二电源端VL2持续输出低电平信号。
在一种示例性实施例中，第一电容C1设置为保持第二节点N2的电位。第二电容C2设置为保持第一节点N1的电位。第三电容C3设置为保持第四节点N4的电位。
在一种示例性实施例中，第一晶体管T1到第十晶体管T10可以采用低温多晶硅薄膜晶体管，或者可以采用氧化物薄膜晶体管，或者可以采用低温 多晶硅薄膜晶体管和氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅(Low Temperature Poly-Silicon，简称LTPS)，氧化物薄膜晶体管的有源层采用氧化物(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点。在示例性实施方式中，可以将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示基板上，形成低温多晶氧化物(Low Temperature Polycrystalline Oxide，简称LTPO)显示基板，可以利用两者的优势，可以实现高分辨率(Pixel Per Inch，简称PPI)，低频驱动，可以降低功耗，可以提高显示品质。
在一种示例性实施例中，第一晶体管T1到第十晶体管T10可以是P型晶体管，或者可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。在一种示例性实施例中，第一晶体管T1到第十晶体管T10可以包括P型晶体管和N型晶体管。
当低电平加载在P型晶体管的栅电极时，P型晶体管导通，当高电平加载在P型晶体管的栅电极时，P型晶体管截止。相应的，时钟信号是在两个不同电平间周期性切换的信号，且这两个电平通常也是分别用于使晶体管导通和截止的，故通常也将二者中较高的称为高电平，而较低的称为低电平。
在一个示例性实施例中，第一晶体管T1可以为P型晶体管，当第一时钟信号端CK1的信号为低电平时，第一晶体管T1处于导通状态，当第一时钟信号端CK1的信号为高电平时，第一晶体管T1处于截止状态。第二晶体管T2可以为P型晶体管，当第一节点N1的信号为低电平时，第二晶体管T2处于导通状态，当第一节点N1的信号为高电平时，第二晶体管T2处于截止状态。第三晶体管T3可以为P型晶体管，当第一时钟信号端CK1的信号为低电平时，第三晶体管T3处于导通状态，当第一时钟信号端CK1的信号为高电平时，第三晶体管T3处于截止状态。第四晶体管T4可以为P型晶体管，当第二时钟信号端CK2的信号为低电平时，第四晶体管T4处于导通状态，当第二时钟信号端CK2的信号为高电平时，第四晶体管T4处于截止状态。第五晶体管T5可以为P型晶体管，当第二节点N2的信号为低电平时，第五晶体管T5处于导通状态，当第二节点N2的信号为高电平时，第五晶体 管T5处于截止状态。第六晶体管T6可以为P型晶体管，当第二节点N2的信号为低电平时，第六晶体管T6处于导通状态，当第二节点N2的信号为高电平时，第六晶体管T6处于截止状态。第七晶体管T7可以为P型晶体管，当第二时钟信号端CK2的信号为低电平时，第七晶体管T7处于导通状态，当第二时钟信号端CK2的信号为高电平时，第七晶体管T7处于截止状态。第八晶体管T8可以为P型晶体管，当第一节点N1的信号为低电平时，第八晶体管T8处于导通状态，当第一节点N1的信号为高电平时，第八晶体管T8处于截止状态。第九晶体管T9可以为P型晶体管，当第四节点N4的信号为低电平时，第九晶体管T9处于导通状态，当第四节点N4的信号为高电平时，第九晶体管T9处于截止状态。第十晶体管T10可以为P型晶体管，当第一节点N1的信号为低电平时，第十晶体管T10处于导通状态，当第一节点N1的信号为高电平时，第十晶体管T10处于截止状态。
在一种示例性实施例中，第一电容C1的第一极板C11位于第一电容C1的第二极板C12靠近衬底基板的一侧，且第一电容C1的第一极板C11在衬底基板上的正投影覆盖第一电容C1的第二极板C12在衬底基板上的正投影。
在一种示例性实施例中，第一电容C1的面积可以约为200平方微米至300平方微米。
在一种示例性实施例中，第二电容C2的第一极板C21位于第二电容C2的第二极板C22靠近衬底基板的一侧，且第二电容C2的第一极板C21在衬底基板上的正投影覆盖第二电容C2的第二极板C22在衬底基板上的正投影。
在一种示例性实施例中，第二电容C2的面积可以约为300平方微米至500平方微米。
在一种示例性实施例中，第三电容C3的第一极板C31位于第三电容C3的第二极板C32靠近衬底基板的一侧，且第三电容C3的第一极板C31在衬底基板上的正投影覆盖第三电容C3的第二极板C32在衬底基板上的正投影。
在一种示例性实施例中，第三电容C3的面积可以约为300平方微米至500平方微米。
在一种示例性实施例中，如图2所示，第一电容C1的第一极板在衬底基板上的正投影与第一电源线VGH在衬底基板上的正投影的重叠部分的面 积与第一电容的第一极板的面积正相关，即第一电容的面积越大，第一电容C1在衬底基板上的正投影与第一电源线VGH在衬底基板上的正投影的重叠区域的面积越大。
在一种示例性实施例中，如图2所示，第三电容C3的第一极板在衬底基板上的正投影与第一电源线VGH在衬底基板上的正投影的重叠部分的面积与第一电容的第一极板的面积正相关，即第一电容的面积越大，第三电容C3在衬底基板上的正投影与第一电源线VGH在衬底基板上的正投影的重叠区域的面积越大。
在一种示例性实施例中，第三电容C3的第一极板与第一电源线VGH的重叠部分的宽度可以与第一电源线VGH的宽度可以相等。
在一种示例性实施例中，第一电容的第一极板与第一电源线的重叠部分的面积可以小于第三电容的第一极板与第一电源线的重叠部分的面积。
下面通过移位寄存器的工作过程说明一种示例性实施例提供的移位寄存器。
以一种示例性实施例提供的移位寄存器中的晶体管T1至T10均为P型晶体管为例，图6为一种示例性实施例提供的移位寄存器的工作时序图。如图5和图6所示，一种示例性实施例涉及的移位寄存器包括：10个开关晶体管(T1至T10)，3个电容单元(C1至C3)，3个信号输入端(CK1、CK2和EIN)、1个信号输出端(EOUT)、2个电源端(V1和V2)。
一种示例性实施例提供的移位寄存器的工作过程可以包括：第一阶段P1至第八阶段P8。
第一阶段P1，信号输入端EIN的信号为高电平信号，第一时钟信号端CK1的信号为低电平信号，第一晶体管T1和第三晶体管T3导通，信号输入端EIN的信号被写入至第一节点N1，此时，第一节点N1为高电平，第二电源端VL2的信号被写入至第二节点N2，此时，第二节点N2为低电平。由于第一节点N1为高电平，第二晶体管T2、第八晶体管T8和第十晶体管T10截止。第二时钟信号端CK2的信号为高电平信号，第四晶体管T4和第七晶体管T7截止。由于第二节点N2为低电平，第五晶体管T5和第六晶体管T6 导通，第二时钟信号端CK2的信号被写入至第三节点N3。由于电容两端电压不会突变，所以第四节点N4节点维持上一帧高电平，第九晶体管T9截止，信号输出端EOUT的输出信号维持上一帧低电平。
第二阶段P2，信号输入端EIN的信号和第一时钟信号端CK1的信号为高电平信号，第一晶体管T1和第三晶体管T3截止，第一节点N1保持高电平，第二晶体管T2、第八晶体管T8和第十晶体管T10截止，第二节点N2保持低电平，第五晶体管T5和第六晶体管T6导通，由于第二时钟信号端CK2的信号为低电平信号，第四晶体管T4和第七晶体管T7导通，第二时钟信号端CK2的信号被写入第三节点N3，第三节点N3由高电平变为低电平，第三节点N3的信号写入第四节点N4，第四节点N4为低电平，第九晶体管T9导通，信号输出端EOUT输出第一电源端VL1的高电平信号。
第三阶段P3，信号输入端EIN的信号为高电平信号，第一时钟信号端CK1的信号为低电平信号，第一晶体管T1和第三晶体管T3导通，第一节点N1为高电平，第二晶体管T2、第八晶体管T8和第十晶体管T10截止，第二节点N2保持低电平，第五晶体管T5和第六晶体管T6导通，第二时钟信号端CK2的信号写入第三节点N3，由于第二时钟信号端CK2的信号为高电平信号，第三节点N3由上一阶段的低电平转变为高电平，第四晶体管T4和第七晶体管T7截止，第四节点N4保持低电平，第九晶体管T9导通，信号输出端EOUT输出第一电源端VL1的高电平信号。
第四阶段P4，信号输入端EIN的信号为低电平信号，第一时钟信号端CK1的信号为高电平信号，第一晶体管T1和第三晶体管T3截止，第一节点N1保持高电平，第二晶体管T2、第八晶体管T8和第十晶体管T10截止，第二节点N2保持低电平，第五晶体管T5和第六晶体管T6导通，第二时钟信号端CK2的信号写入第三节点N3，由于第二时钟信号端CK2的信号为低电平信号，第三节点N3由上一阶段的高电平转变为低电平，第四晶体管T4和第七晶体管T7导通，第三节点N3的信号写入第四节点N4，第四节点N4保持低电平，第九晶体管T9导通，信号输出端EOUT输出第一电源端VL1的高电平信号。
第五阶段P5，信号输入端EIN的信号和第一时钟信号端CK1的信号为 低电平信号，第一晶体管T1和第三晶体管T3导通，第一节点N1由高电平转变为低电平，第二晶体管T2、第八晶体管T8和第十晶体管T10导通，第二节点N2保持低电平，第五晶体管T5和第六晶体管T6导通，第二时钟信号端CK2的信号写入第三节点N3，由于第二时钟信号端CK2的信号为高电平信号，第三节点N3由上一阶段的低电平转变为高电平，第四晶体管T4和第七晶体管T7截止，由于第八晶体管T8导通，第一电源端VL1的高电平信号写入第四节点N4中，第四节点N4变为高电平，第九晶体管T9截止，由于第十晶体管T10导通，第二电源端VL2的低电平信号写入信号输出端EOUT，信号输出端EOUT输出低电平信号。
第六阶段P6，信号输入端EIN的信号为低电平信号，第一时钟信号端CK1的信号为高电平信号，第一晶体管T1和第三晶体管T3截止，第一节点N1保持低电平，第二晶体管T2、第八晶体管T8和第十晶体管T10导通，第一时钟信号端CK1的信号写入第二节点N2，第二节点N2由低电平转变为高电平，第五晶体管T5和第六晶体管T6截止，第三节点N3保持高电平，由于第二时钟信号端CK2的信号为低电平信号，第四晶体管T4和第七晶体管T7导通，第三节点N3的信号写入第四节点N4，第四节点N4保持高电平，第九晶体管T9截止，由于第十晶体管T10导通，第二电源端VL2的低电平信号写入信号输出端EOUT，信号输出端EOUT输出低电平信号。
第七阶段P7，信号输入端EIN的信号为低电平信号，第一时钟信号端CK1的信号为低电平信号，第一晶体管T1和第三晶体管T3导通，第一节点N1保持低电平，第二晶体管T2、第八晶体管T8和第十晶体管T10导通，第一时钟信号端CK1的信号写入第二节点N2，第二节点N2为低电平，第五晶体管T5和第六晶体管T6导通，第二时钟信号端CK2的信号写入第三节点N3，由于第二时钟信号端CK2的信号为高电平信号，第四晶体管T4和第七晶体管T7截止，第四节点N4保持高电平，第九晶体管T9截止，由于第十晶体管T10导通，第二电源端VL2的低电平信号写入信号输出端EOUT，信号输出端EOUT输出低电平信号。
第八阶段P8，信号输入端EIN的信号为低电平信号，第一时钟信号端CK1的信号为高电平信号，第一晶体管T1和第三晶体管T3截止，第一节点 N1保持低电平，第二晶体管T2、第八晶体管T8和第十晶体管T10导通，第一时钟信号端CK1的信号写入第二节点N2，第二节点N2由低电平转变为高电平，第五晶体管T5和第六晶体管T6截止，第三节点N3保持高电平，由于第二时钟信号端CK2的信号为低电平信号，第四晶体管T4和第七晶体管T7导通，第三节点N3的信号写入第四节点N4，第四节点N4保持高电平，第九晶体管T9截止，由于第十晶体管T10导通，第二电源端VL2的低电平信号写入信号输出端EOUT，信号输出端EOUT输出低电平信号。
在第一阶段P7之后，第七阶段P7和第八阶段P8循环往复，第八晶体管T8持续导通，第九晶体管T9截止，第一晶体管T1周期性地给第二电容C2充电，第一节点N1保持低电平，第十晶体管T10持续导通，信号输出端EOUT输出低电平信号，直到下一帧信号输入端EIN的脉冲进入。
在一种示例性实施例中，图7为一种示例性实施例提供的驱动电路的时序图。图7中，EOUTi为第i级移位寄存器EOA(i)的信号输出端，EINi第i级移位寄存器EOA(i)的信号输入端。如图4和图7所示，第一级移位寄存器EOA(1)的信号输入端与初始信号线ESTV电连接，第i-1级移位寄存器的信号输出端与第i级移位寄存器的信号输入端电连接，所有移位寄存器的第一电源端VL1与第一电源线VGH电连接，所有移位寄存器的第二电源端VL2与第二电源线VGL电连接，奇数级移位寄存器的第一时钟信号端CK1与第一时钟信号线ECK电连接，奇数级移位寄存器的第二时钟信号端CK2与第二时钟信号线ECB电连接，偶数级移位寄存器的第一时钟信号端CK1与第二时钟信号线ECB电连接，偶数级移位寄存器的第二时钟信号端CK2与第一时钟信号线ECK电连接，其中，i为大于或等于2的正整数。
在一种示例性实施例中，第i级移位寄存器的信号输出端与第2i-1行子像素和第2i行子像素电连接。其中，第i级移位寄存器的信号输出端通过第2i-1行发光信号线与第2i-1行子像素电连接，通过第2i行发光信号线与第2i行子像素电连接。
在一种示例性实施例中，如图2所示，每个移位寄存器包括：连接电极40。连接电极10在衬底基板上的正投影与信号输出端EOUT在衬底基板上的正投影至少部分重叠。其中，连接电极分别与本级移位寄存器的信号输出 端和下一级移位寄存器的信号输入端电连接。
在一种示例性实施例中，如图2所示，第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4和第五晶体管T5位于第一电容C1远离第三电容C3的一侧，且位于第二电容C2靠近第一电源线VGH的一侧。
在一种示例性实施例中，如图2所示，第六晶体管T6位于第一电容C1靠近第二电源线VGL的一侧，且位于第二电容C2靠近第三电容C3的一侧。第六晶体管T6位于第一电容C1靠近第二电源线VGL的一侧，且位于第二电容C2靠近第三电容C3的一侧可以缩小第六晶体在第一方向上占据的空间，可实现显示产品的窄边框。
在一种示例性实施例中，如图2所示，第七晶体管T7和第八晶体管T8位于第一电容C1和第三电容C3之间。
在一种示例性实施例中，如图2所示，第九晶体管T9和第十晶体管T10位于第二电容C2靠近第二电源线VGL的一侧。
图8为一种示例性实施例提供的半导体层的结构示意图，图9为一种示例性实施例提供的第一金属层的结构示意图，图10为一种示例性实施例提供的第二金属层的结构示意图，图11为一种示例性实施例提供的第三金属层的结构示意图。如图8至图11所示，一种示例性实施例提供的显示基板包括：依次叠设在所述衬底基板上的半导体层、第一绝缘层、第一金属层、第二绝缘层、第二金属层、第三绝缘层和第三金属层。
在一种示例性实施例中，如图8所示，半导体层包括：多个晶体管的有源层。其中，多个晶体管的有源层包括：第一晶体管T1的有源层11、第二晶体管T2的有源层21、第三晶体管T3的有源层31、第四晶体管T4的有源层41、第五晶体管T5的有源层51、第六晶体管T6的有源层61、第七晶体管T7的有源层71、第八晶体管T8的有源层81、第九晶体管T9的有源层91和第十晶体管T10的有源层110。
在一种示例性实施例中，如图8所示，第一晶体管T1的有源层11、第二晶体管T2的有源层21、第三晶体管T3的有源层31、第四晶体管T4的有源层41、第五晶体管T5的有源层51、第六晶体管T6的有源层61、第七晶体管T7的有源层71、第九晶体管T9的有源层91和第十晶体管T10的有源 层110均沿第一方向延伸。第八晶体管T8的有源层81沿第二方向延伸。其中，第一方向和第二方向相交。
在一种示例性实施例中，如图8所示，在每个移位寄存器中，所有晶体管的有源层包括：沟道区和位于沟道区两侧的源极连接部和漏极连接部，晶体管的源电极与源极连接部电连接，晶体管的漏电极与漏极连接部电连接。其中，第四晶体管的有源层的漏极连接部复用为漏电极，第五晶体管的有源层的源极连接部复用为源电极，第四晶体管的有源层的漏极连接部与第五晶体管的有源层的源极连接部电连接。
在一些示例性实施例中，沟道区可以不掺杂杂质，并具有半导体特性。源极连接部和漏极连接部可以在沟道区的两侧，并且掺杂有杂质，并因此具有导电性。杂质可以根据晶体管的类型(例如，N型或P型)而变化。
在一种示例性实施例中，如图9所示，第一金属层包括：多个晶体管的栅电极、第一电容C1的第一极板C11、第二电容C2的第一极板C21和第三电容C3的第一极板C31。多个晶体管的栅电极包括：第一晶体管T1的栅电极12、第二晶体管T2的栅电极22、第三晶体管T3的栅电极32、第四晶体管T4的栅电极42、第五晶体管T5的栅电极52、第六晶体管T6的栅电极62、第七晶体管T7的栅电极72、第八晶体管T8的栅电极82、第九晶体管T9的栅电极92和第十晶体管T10的栅电极120。
一种示例性实施例中，当移位寄存器中的第一时钟信号端与第一时钟信号线电连接，第二时钟信号端与第二时钟信号线电连接时，第一晶体管T1的栅电极12在衬底基板上的正投影与第一时钟信号线在衬底基板上的正投影至少部分重叠。第四晶体管T4的栅电极42在衬底基板上的正投影与第二时钟信号线在衬底基板上的正投影至少部分重叠，第七晶体管T7的栅电极72在衬底基板上的正投影与第二时钟信号线在衬底基板上的正投影至少部分重叠，或者，当移位寄存器中的第一时钟信号端与第二时钟信号线电连接，第二时钟信号端与第一时钟信号线电连接时，第一晶体管T1的栅电极12在衬底基板上的正投影与第二时钟信号线在衬底基板上的正投影至少部分重叠。第四晶体管T4的栅电极42在衬底基板上的正投影与第一时钟信号线在衬底基板上的正投影至少部分重叠，第七晶体管T7的栅电极72在衬底基板上的 正投影与第一时钟信号线在衬底基板上的正投影至少部分重叠。图2是以移位寄存器中的第一时钟信号端与第一时钟信号线电连接，第二时钟信号端与第二时钟信号线电连接为例进行说明的。
在一种示例性实施例中，在每个移位寄存器中，第二晶体管T2的栅电极22、第十晶体管T10的栅电极120、第八晶体管T8的栅电极82和第二电容C2的第一极板C21为一体成型结构。
在一种示例性实施例中，在每个移位寄存器中，第五晶体管T5的栅电极52、第六晶体管T6的栅电极62和第一电容C1的第一极板C11为一体成型结构。
在一种示例性实施例中，在每个移位寄存器中，第九晶体管T9的栅电极92和第三电容C3的第一极板C31为一体成型结构。
在一种示例性实施例中，如图9所示，第一电容的第一极板C11的形状可以为方形。
在一种示例性实施例中，如图9所示，第二电容的第一极板C21的形状可以为两个方形的叠加，第一个方形和第二个方形沿第一方向排布，第二个方形的宽度大于第一个方形的宽度，第二个方向的长度小于第一个方向的长度，第二个方形的左边缘位于第一个方向的左边缘靠近第二晶体管的栅电极的一侧。
在一种示例性实施例中，如图9所示，第三电容的第一极板C31的形状可以为右下角缺个角的方形。
在一种示例性实施例中，如图10所示，第二金属层包括：第一电容C1的第二极板C12、第二电容C2的第二极板C22、第三电容C3的第二极板C32和输出信号线EL。
在一种示例性实施例中，如图9所示，第二晶体管的栅电极22呈“回”形结构。
在一种示例性实施例中，第九晶体管的栅电极92呈梳状结构。第九晶体管的栅电极92包括：多个跨设在第九晶体管的有源层91上的第一分支段92A以及连接多个第一分支段92A的第一连接段92B。
在一种示例性实施例中，第十晶体管的栅电极120呈梳状结构。第十晶体管的栅电极120包括：多个跨设在第十晶体管的有源层110上的第二分支段120A以及连接多个第一分支段120A的第二连接段120B。
如图10所示，每个移位寄存器中的输出信号线EL可以包括：一体成型的第一连接部OUT1、第二连接部OUT2、第三连接部OUT3和第四连接部OUT4。其中，第一连接部OUT1在衬底基板上的正投影与第九晶体管的源电极在衬底基板上的正投影至少部分重叠，且与第十晶体管的漏电极在衬底基板上的正投影至少部分重叠，第一连接部OUT1沿第一方向延伸。第二连接部OUT2、第三连接部OUT3、第四连接部OUT4沿第二方向延伸，第二连接部OUT2和第三连接部OUT3位于第一连接部OUT1远离第一电源线VGH的一侧，第四连接部OUT4位于第一连接部OUT1靠近第一电源线VGH的一侧。
在一种示例性实施例中，第一连接部OUT1、第二连接部OUT2和第三连接部OUT3可以为直线型结构。第四连接部OUT4可以为折线形结构。
在一种示例性实施例中，第二连接部OUT2与第2i-1行子像素电连接。第三连接部OUT3与第2i行子像素电连接。第四连接部OUT4与下一级移位寄存器的信号输入端电连接。
在一种示例性实施例中，连接电极在衬底基板上的正投影与第四连接部在衬底基板上的正投影至少部分重叠，第四连接部通过连接电极与下一级移位寄存器的信号输入端电连接。
在一种示例性实施例中，如图10所示，第一电容的第二极板C12的形状可以为方形，且第一电容的第二极板C12靠近输出信号线EL的一侧为阶梯状。
在一种示例性实施例中，如图10所示，第二电容的第二极板C22的形状可以缺右下角的L型，且第二电容的第二极板C22远离输出信号线EL的边缘上设置有凸起。
在一种示例性实施例中，如图10所示，第三电容的第二极板C32的形状可以为缺右下角的方形，且第三电容的第二极板C32靠近第二电容的边缘呈阶梯状。
在一种示例性实施例中，如图11所示，第三金属层包括：多个晶体管的源电极、多个晶体管的漏电极、信号输入端EIN、第一时钟信号端CK1、第二时钟信号端CK2、第一电源线VGH、第二电源线VGL、第一时钟信号线ECK、第二时钟信号线ECB、初始信号线ESTV和连接电极40。多个晶体管的源电极包括：第一晶体管T1的源电极13、第二晶体管T2的源电极23、第三晶体管T3的源电极33、第四晶体管T4的源电极43、第六晶体管T6的源电极63、第七晶体管T7的源电极73、第八晶体管T8的源电极83、第九晶体管T9的源电极93和第十晶体管T10的源电极130。多个晶体管的漏电极包括：第一晶体管T1的漏电极14、第二晶体管T2的漏电极24、第三晶体管T3的漏电极34、第五晶体管T5的漏电极54、第六晶体管T6的漏电极64、第七晶体管T7的漏电极74、第八晶体管T8的漏电极84、第九晶体管T9的漏电极94和第十晶体管T10的漏电极140。
在一种示例性实施例中，第一晶体管T1的漏电极14和第四晶体管T4的源电极43可以为一体成型结构。
在一种示例性实施例中，第二晶体管T2的漏电极34和第三晶体管T3的漏电极34可以为一体成型结构。
在一种示例性实施例中，第三晶体管T3的源电极33、第十晶体管T10的源电极130和第二电源线VGL可以为一体成型结构。
在一种示例性实施例中，第六晶体管T6的漏电极64和第七晶体管T7的源电极73可以为一体成型结构。
在一种示例性实施例中，第七晶体管T7的漏电极74和第八晶体管T8的漏电极84可以为一体成型结构。
在一种示例性实施例中，第八晶体管T8的源电极83、第九晶体管T9的漏电极94，第五晶体管T5的漏电极54和第一电源线VGH为一体成型结构。
在一种示例性实施例中，半导体层可以为非晶硅层、多晶硅层，或者可以为金属氧化物层。其中，金属氧化物层可以采用包含铟和锡的氧化物、包含钨和铟的氧化物、包含钨和铟和锌的氧化物、包含钛和铟的氧化物、包含 钛和铟和锡的氧化物、包含铟和锌的氧化物、包含硅和铟和锡的氧化物或者包含铟或镓和锌的氧化物。金属氧化物层可以单层，或者可以是双层，或者可以是多层。
在一种示例性实施例中，第一绝缘层、第二绝缘层和第三绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或更多种，可以是单层、多层或复合层。第一绝缘层称为第一栅绝缘层、第二绝缘层成为第二栅绝缘层、第三绝缘层称为层间绝缘层。
在一种示例性实施例中，第一金属层、第二金属层和第三金属层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或更多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。
在一种示例性实施例中，第三金属层的电阻可以小于第一金属层的电阻。
在一种示例性实施例中，第三金属层的电阻可以小于第二金属层的电阻。
在一种示例性实施例中，第一金属层和第二金属层的制作材料可以包括：钼。
在一种示例性实施例中，第三金属层可以为钛、铝和钛形成的三层堆叠结构。
在一种示例性实施例中，如图2、图8和图11所示，在每个移位寄存器中，第六晶体管T6的有源层61沿第一方向延伸，第六晶体管T6的源电极63和漏电极64沿第一方向排布。第六晶体管T6的有源层61沿第一方向延伸，第六晶体管T6的源电极63和漏电极64沿第一方向排布使得第六晶体管T6列向放置，可以减少驱动电路的宽度，实现显示产品的窄边框。
在一种示例性实施例中，如图2所示，第一电源线VGH与第一电容C1靠近第二电源线VGL的边缘之间的距离L1可以小于第一电源线VGH与第六晶体管T6的源电极之间的距离L2。第一电源线VGH与第一电容C1靠近第二电源线VGL的边缘之间的距离小于第一电源线VGH与第六晶体管T6的源电极之间的距离可以减少驱动电路的宽度，实现显示产品的窄边框。
在一种示例性实施例中，对于每个移位寄存器，显示基板还可以包括： 贯穿第一绝缘层、第二绝缘层和第三绝缘层的第一过孔至第十过孔。
在一种示例性实施例中，第一过孔暴露出第一晶体管的有源层，第二过孔暴露出第二晶体管的有源层，第三过孔暴露出第三晶体管的有源层，第四过孔暴露出第四晶体管的有源层，第五过孔暴露出第五晶体管的有源层，第六过孔暴露出第六晶体管的有源层，第七过孔暴露出第七晶体管的有源层，第八过孔暴露出第八晶体管的有源层，第九过孔暴露出第九晶体管的有源层，第十过孔暴露出第十晶体管的有源层。其中，第一晶体管的源电极和漏电极通过第一过孔与第一晶体管的有源层电连接，第二晶体管的源电极和漏电极通过第二过孔与第二晶体管的有源层电连接，第三晶体管的源电极和漏电极通过第三过孔与第三晶体管的有源层电连接，第四晶体管的源电极和漏电极通过第四过孔与第四晶体管的有源层电连接，第五晶体管的源电极和漏电极通过第五过孔与第五晶体管的有源层电连接，第六晶体管的源电极和漏电极通过第六过孔与第六晶体管的有源层电连接，第七晶体管的源电极和漏电极通过第七过孔与第七晶体管的有源层电连接，第八晶体管的源电极和漏电极通过第八过孔与第八晶体管的有源层电连接，第九晶体管的源电极和漏电极通过第九过孔与第九晶体管的有源层电连接，第十晶体管的源电极和漏电极通过第十过孔与第十晶体管的有源层电连接。
在一种示例性实施例中，对于每个移位寄存器，显示基板还可以包括：贯穿第二绝缘层和第三绝缘层的第十一过孔至第十六过孔。
在一种示例性实施例中，第十一过孔暴露出第一晶体管的栅电极，第十二过孔暴露出第二晶体管的栅电极，第十三过孔暴露出第四晶体管的栅电极，第十四过孔暴露出第五晶体管的栅电极，第十五过孔暴露出第七晶体管的栅电极，第十六过孔暴露出第三电容的第一极板。其中，第二晶体管的源电极通过第十一过孔与第一晶体管的栅电极的电连接，第一晶体管的漏电极通过第十二过孔与第二晶体管的栅电极电连接，第六晶体管的源电极通过第十三过孔与第四晶体管的栅电极电连接，第三晶体管的漏电极通过第十四过孔与第五晶体管的栅电极电连接，第七晶体管的漏电极通过第十六过孔与第三电容的第一极板电连接。
在一种示例性实施例中，第十一过孔包括两个，一个第十一过孔暴露出 第一晶体管的栅电极远离显示区的一端，另一个第十一过孔暴露出第一晶体管的栅电极靠近显示区的一端。
在一种示例性实施例中，第十三过孔包括两个，一个第十三过孔暴露出第四晶体管的栅电极远离显示区的一端，另一个第十一过孔暴露出第四晶体管的栅电极靠近显示区的一端。
在一种示例性实施例中，第十五过孔暴露出第七晶体管的栅电极远离显示区的一端。
在一种示例性实施例中，对于每个移位寄存器，显示基板还可以包括：设置在第三绝缘层上的第十七过孔至第二十一过孔。
在一种示例性实施例中，第十七过孔暴露出第一电容的第二极板，第十八过孔暴露出第二电容的第二极板，第十九过孔暴露出第三电容的第二极板，第二十过孔暴露出信号输出端的第一连接部，第二十一过孔暴露出信号输出端的第四连接部。其中，第六晶体管的漏电极通过第十七过孔与第一电容的第二极板电连接，第六晶体管的源电极通过第十八过孔与第二电容的第二极板电连接，第九晶体管的漏电极通过第十九过孔与第三电容的第二极板电连接，第九晶体管的源电极和第十晶体管的漏电极通过第二十过孔与信号输出端电连接，连接电极通过第二十一过孔与信号输出端电连接。
在一种示例性实施例中，第十七过孔的数量可以为多个。多个第十七过孔沿第一方向排布。示例性地，第十七过孔的数量可以为两个。
在一种示例性实施例中，第十八过孔的数量可以为多个。多个第十八过孔沿第一方向排布。示例性地，第十七过孔的数量可以为两个。
在一种示例性实施例中，第十九过孔的数量可以为多个，多个第十九过孔沿第二方向排布。示例性地，第十九过孔的数量可以为四个。多个第十九过孔沿第二方向排布可以减少驱动电路的宽度，实现窄边框。
在一种示例性实施例中，第二十过孔的数量可以为多个。示例性地，第十九过孔的数量可以为十二个。多个第二十过孔沿第一方向排布。
下面通过显示基板的制备过程的示例说明显示基板的结构。本公开所说的“构图工艺”包括沉积膜层、涂覆光刻胶、掩模曝光、显影、刻蚀和剥离光 刻胶处理。沉积可以采用溅射、蒸镀和化学气相沉积中的任意一种或多种，涂覆可以采用喷涂和旋涂中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种。“薄膜”是指将某一种材料在基底上利用沉积或涂覆工艺制作出的一层薄膜。若在整个制作过程中该“薄膜”无需构图工艺，则该“薄膜”还可以称为“层”。若在整个制作过程中该“薄膜”需构图工艺，则在构图工艺前称为“薄膜”，构图工艺后称为“层”。经过构图工艺后的“层”中包含至少一个“图案”。本公开中所说的“A和B同层设置”是指，A和B通过同一次构图工艺同时形成。
图12至图16为一个示例性实施例提供的显示基板的制备过程示意图。如图12至16所示，一种示例性实施例提供的显示基板的制作过程可以包括：
(1)在衬底基板上形成半导体层图案，包括：在衬底基板上沉积半导体薄膜，通过构图工艺对半导体薄膜进行构图，形成半导体层图案。如图12所示，半导体层包括：第一晶体管T1的有源层11、第二晶体管T2的有源层21、第三晶体管T3的有源层31、第四晶体管T4的有源层41、第五晶体管T5的有源层51、第六晶体管T6的有源层61、第七晶体管T7的有源层71、第八晶体管T8的有源层81、第九晶体管T9的有源层91和第十晶体管T10的有源层110，如图12所示，图12为本公开显示基板形成半导体层图案后的示意图。
其中，第一晶体管T1的有源层11、第二晶体管T2的有源层21、第三晶体管T3的有源层31、第四晶体管T4的有源层41、第五晶体管T5的有源层51、第六晶体管T6的有源层61、第七晶体管T7的有源层71沿第一方向延伸。第八晶体管T8的有源层81沿第二方向延伸。第九晶体管T9的有源层91和第十晶体管T10的有源层110沿第一方向延伸，且为一体成型的长条状结构。
(2)形成第一金属层图案，包括：在形成前述图案的基底上，依次沉积第一绝缘薄膜和第一金属薄膜，通过构图工艺对第一绝缘薄膜和第一金属薄膜进行构图，形成第一绝缘层图案以及位于第一绝缘层上的第一金属层图案，第一金属层包括：第一电容C1的第一极板C11、第二电容C2的第一极板C21、第三电容C3的第一极板C31、第一晶体管T1的栅电极12、第二晶体 管T2的栅电极22、第三晶体管T3的栅电极32、第四晶体管T4的栅电极42、第五晶体管T5的栅电极52、第六晶体管T6的栅电极62、第七晶体管T7的栅电极72、第八晶体管T8的栅电极82、第九晶体管T9的栅电极92和第十晶体管T10的栅电极120，如图13所示，图13为本公开显示基板形成第一金属层图案后的示意图。
各个栅电极分别跨设在对应晶体管的有源层上，也就是说，各个栅电极的延伸方向与对应晶体管的有源层的延伸方向相互垂直。
在一种示例性实施例中，第二晶体管T2的栅电极22、第十晶体管T10的栅电极120、第八晶体管T8的栅电极82和第二电容C2的第一极板C21为一体成型结构。第五晶体管T5的栅电极52、第六晶体管T6的栅电极62和第一电容C1的第一极板C11为一体成型结构。第九晶体管T9的栅电极92和第三电容C3的第一极板C31为一体成型结构。
在一种示例性实施例中，本次工艺还包括导体化处理。导体化处理是在形成第一金属层图案后，利用第一晶体管T1的栅电极12、第二晶体管T2的栅电极22、第三晶体管T3的栅电极32、第四晶体管T4的栅电极42、第五晶体管T5的栅电极52、第六晶体管T6的栅电极62、第七晶体管T7的栅电极72、第八晶体管T8的栅电极82、第九晶体管T9的栅电极92和第十晶体管T10的栅电极120遮挡区域的半导体层(即半导体层与各个栅电极重叠的区域)作为晶体管的沟道区，未被第一金属层遮挡区域的半导体层被处理成导体化层，形成导体化的源漏连接部。
(3)形成第二金属层图案，包括：在形成前述图案的基底上，依次沉积第二绝缘薄膜和第二金属薄膜，通过构图工艺对第二绝缘薄膜和第二金属薄膜进行构图，形成第二绝缘层图案以及位于第二绝缘层上的第二金属层图案。第二金属层包括：第一电容C1的第二极板C12、第二电容C2的第二极板C22、第三电容C3的第二极板C32和输出信号线EL，如图14所示，图14为本公开显示基板形成第二金属层图案后的示意图。
(4)形成第三绝缘层图案，包括：在形成有前述图案的基底上，沉积第三绝缘薄膜，通过构图工艺对第三绝缘薄膜进行构图，形成覆盖前述结构的第三绝缘层图案，第三绝缘层开设有多个过孔图案，多个过孔图案包括：贯 穿第一绝缘层、第二绝缘层和第三绝缘层的第一过孔V1至第十过孔V10、贯穿第二绝缘层和第三绝缘层的第十一过孔V11至第十六过孔V16以及设置在第三绝缘层上的第十七过孔V17至第二十一过孔V21，如图15所示，图15为本公开显示基板形成第三绝缘层图案后的示意图。
在一种示例性实施例中，第一过孔V1暴露出第一晶体管的有源层11，第二过孔V2暴露出第二晶体管的有源层21，第三过孔V3暴露出第三晶体管的有源层31，第四过孔V4暴露出第四晶体管的有源层41，第五过孔V5暴露出第五晶体管的有源层51，第六过孔V6暴露出第六晶体管的有源层61，第七过孔暴露出第七晶体管的有源层71，第八过孔V8暴露出第八晶体管的有源层81，第九过孔暴露出第九晶体管的有源层91，第十过孔V10暴露出第十晶体管的有源层110。第十一过孔V11暴露出第一晶体管的栅电极12，第十二过孔V12暴露出第二晶体管的栅电极22，第十三过孔V13暴露出第四晶体管的栅电极42，第十四过孔V14暴露出第五晶体管的栅电极52，第十五过孔V15暴露出第七晶体管的栅电极72，第十六过孔V16暴露出第三电容的第一极板C31。第十七过孔V17暴露出第一电容的第二极板C12，第十八过孔V18暴露出第二电容的第二极板C22，第十九过孔V19暴露出第三电容的第二极板C32，第二十过孔V20暴露出输出信号线EL的第一连接部，第二十一过孔V21暴露出输出信号线EL的第四连接部。
(4)形成第三金属层图案，包括：在形成前述图案的基底上，沉积第三金属薄膜，通过构图工艺对第三金属薄膜进行构图，形成第三金属层图案。第三金属层包括：第一电源线VGH、第二电源线VGL、第一时钟信号线ECK、第二时钟信号线ECB、初始信号线ESTV、连接电极40，第一晶体管T1的源电极13、第二晶体管T2的源电极23、第三晶体管T3的源电极33、第四晶体管T4的源电极43、第六晶体管T6的源电极63、第七晶体管T7的源电极73、第八晶体管T8的源电极83、第九晶体管T9的源电极93、第十晶体管T10的源电极130、第一晶体管T1的漏电极14、第二晶体管T2的漏电极24、第三晶体管T3的漏电极34、第五晶体管T5的漏电极54、第六晶体管T6的漏电极64、第七晶体管T7的漏电极74、第八晶体管T8的漏电极84、第九晶体管T9的漏电极94和第十晶体管T10的漏电极140，如图16，图16 为本公开一个示例性实施例中显示基板的示意图。
在一种示例性实施例中，第一晶体管T1的漏电极14和第四晶体管T4的源电极43为一体成型结构。第二晶体管T2的漏电极34和第三晶体管T3的漏电极34为一体成型结构。第三晶体管T3的源电极33、第十晶体管T10的源电极130和第二电源线VGL为一体成型结构。第六晶体管T6的漏电极64和第七晶体管T7的源电极73为一体成型结构。第七晶体管T7的漏电极74和第八晶体管T8的漏电极84为一体成型结构。第八晶体管T8的源电极83、第九晶体管T9的漏电极94，第五晶体管T5的漏电极54和第一电源线VGH为一体成型结构。
在一种示例性实施例中，第一晶体管的源电极13和漏电极14通过第一过孔V1与第一晶体管的有源层11电连接。第二晶体管的源电极23和漏电极24通过第二过孔V2与第二晶体管的有源层21电连接。第三晶体管的源电极33和漏电极34通过第三过孔V3与第三晶体管的有源层31电连接。第四晶体管的源电极43和漏电极44通过第四过孔V4与第四晶体管的有源层41电连接。第五晶体管的源电极53和漏电极54通过第五过孔V5与第五晶体管的有源层电连接。第六晶体管的源电极63和漏电极64通过第六过孔V6与第六晶体管的有源层61电连接。第七晶体管的源电极73和漏电极74通过第七过孔V7与第七晶体管的有源层71电连接。第八晶体管的源电极83和漏电极84通过第八过孔V8与第八晶体管的有源层81电连接。第九晶体管的源电极93和漏电极94通过第九过孔V9与第九晶体管的有源层电连接，第十晶体管的源电极130和漏电极140通过第十过孔V10与第十晶体管的有源层110电连接。第一时钟信号线ECK通过第十一过孔V11与第一晶体管的栅电极12的电连接。第二晶体管的源电极23通过第十一过孔V11与第一晶体管的栅电极12的电连接。第一晶体管的漏电极14通过第十二过孔V12与第二晶体管的栅电极22电连接。第二时钟信号线ECB通过第十三过孔V13与第四晶体管的栅电极42电连接。第六晶体管的源电极63通过第十三过孔V13与第四晶体管的栅电极42电连接。第三晶体管的漏电极34通过第十四过孔V14与第五晶体管的栅电极52电连接。第二时钟信号线ECB通过第十五过孔V15与第七晶体管的栅电极72电连接。第七晶体管的漏电极74通过 第十六过孔V16与第三电容的第一极板C31电连接。第六晶体管的漏电极64通过第十七过孔V17与第一电容的第二极板C12电连接。第六晶体管的源电极63通过第十八过孔V18与第二电容的第二极板C22电连接。第九晶体管的漏电极94通过第十九过孔V19与第三电容的第二极板C32电连接。第九晶体管的源电极93和第十晶体管的漏电极140通过第二十过孔V20与信号输出端的第一连接部电连接。连接电极40通过第二十一过孔V21与信号输出端的第四连接部电连接。图16是以移位寄存器的第一时钟信号端与第一时钟信号线电连接，移位寄存器的第二时钟信号端与第二时钟信号线电连接为例进行说明的。
对于不同显示产品，驱动电路中多个移位寄存器的级联关系可能有所不同。无论多个移位寄存器的级联关系如何，每个移位寄存器驱动几行子像素，只要是类似这种大面积的器件发生改变，以及这种改变产生额外空间以后，小器件可能的简单平移、拉伸都在本公开的保护范围内。
本公开实施例还提供了一种显示装置，该显示装置可以包括：显示基板。
显示基板为前述任一个实施例提供的显示基板，实现原理和实现效果类似，在此不再赘述。
在一种示例性实施例中，显示装置可以为液晶显示装置(Liquid Crystal Display，简称LCD)或有机发光二极管(Organic Light Emitting Diode，简称OLED)显示装置。该显示装置可以为：液晶面板、电子纸、OLED面板、有源矩阵有机发光二极管(active-matrix organic light emitting diode，简称AMOLED)面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开实施例还提供了一种显示基板的制作方法，设置为制作显示基板。本公开实施例提供的显示基板的制作方法包括：
步骤S1、提供一衬底基板。
在一种示例性实施例中，衬底基板可以为刚性基底或柔性基底，其中，刚性基底可以为但不限于玻璃、金属萡片中的一种或多种；柔性基底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织 纤维中的一种或多种。
步骤S2、在衬底基板上形成位于非显示区的驱动电路和第一电源线。
在一种示例性实施例中，驱动电路包括：第一电容、第二电容和第三电容；第一电容和第三电容沿第一方向排布，第二电容和第三电容分别位于第一电容的两侧，第二电容位于第一电容靠近显示区的一侧，第三电容的一个极板与第一电源线电连接。第一电源线沿第一方向延伸，第一电容在衬底基板上的正投影与第一电源线在衬底基板上的正投影至少部分重叠。
显示基板为前述任一个实施例提供的显示基板，实现原理和实现效果类似，在此不再赘述。
在一种示例性实施例中，驱动电路包括：多个移位寄存器，每个移位寄存器包括：多个晶体管以及第一电容至第三电容，步骤S2可以包括：
步骤S21、在衬底基板上形成半导体层。其中，半导体层包括：多个晶体管的有源层。
在一种示例性实施例中，半导体层可以为非晶硅层、多晶硅层，或者可以为金属氧化物层。其中，金属氧化物层可以采用包含铟和锡的氧化物、包含钨和铟的氧化物、包含钨和铟和锌的氧化物、包含钛和铟的氧化物、包含钛和铟和锡的氧化物、包含铟和锌的氧化物、包含硅和铟和锡的氧化物或者包含铟或镓和锌的氧化物。金属氧化物层可以单层，或者可以是双层，或者可以是多层。
步骤S22、在半导体层上依次形成第一绝缘层和第一金属层。其中，第一金属层包括：多个晶体管的栅电极、第一电容的第一极板、第二电容的第一极板和第三电容的第一极板。
在一种示例性实施例中，第一金属层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或更多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。示例性的，第一金属层的制作材料可以包括：钼。
步骤S23、在第一金属层上依次形成第二绝缘层和第二金属层。其中， 第二金属层包括：第一电容的第二极板、第二电容的第二极板、第三电容的第二极板和信号输出端。
在一种示例性实施例中，第二金属层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或更多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。示例性的，第二金属层的制作材料可以包括：钼。
步骤S24、在第二金属层上依次形成第三绝缘层和第三金属层。其中，第三金属层包括：多个晶体管的源电极、多个晶体管的漏电极、第一电源线、第二电源线、第一时钟信号线、第二时钟信号线、初始信号线和连接电极。
在一种示例性实施例中，第三金属层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或更多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。示例性地，第三金属层可以为钛、铝和钛形成的三层堆叠结构。
在一种示例性实施例中，第一绝缘层、第二绝缘层和第三绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或更多种，可以是单层、多层或复合层。第一绝缘层称为第一栅绝缘层、第二绝缘层成为第二栅绝缘层、第三绝缘层称为层间绝缘层。
本公开中的附图只涉及本公开实施例涉及到的结构，其他结构可参考通常设计。
为了清晰起见，在用于描述本公开的实施例的附图中，层或微结构的厚度和尺寸被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细 节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (21)

  1. 一种显示基板，包括：显示区和非显示区，包括：衬底基板以及设置在所述衬底基板上，且位于非显示区的驱动电路和第一电源线，所述驱动电路至少包括：第一电容、第二电容和第三电容；所述第一电容和所述第三电容沿第一方向排布，所述第二电容和所述第三电容分别位于所述第一电容的两侧，所述第二电容位于所述第一电容靠近显示区的一侧，所述第三电容的一个极板与所述第一电源线电连接；
    所述第一电源线沿第一方向延伸，所述第一电容在衬底基板上的正投影与所述第一电源线在衬底基板上的正投影至少部分重叠。
  2. 根据权利要求1所述的显示基板，其中，所述第三电容在衬底基板上的正投影与所述第一电源线在衬底基板上的正投影至少部分重叠。
  3. 根据权利要求1或2所述的显示基板，还包括：设置在所述衬底基板上，且位于非显示区的第二电源线、初始信号线、第一时钟信号线和第二时钟信号线；
    所述第二电源线位于驱动电路靠近显示区的一侧，且沿第一方向延伸，所述初始信号线位于第一电源线远离显示区的一侧，且沿第一方向延伸，所述第一时钟信号线位于所述第一电源线和所述初始信号线之间，且沿第一方向延伸，所述第二时钟信号线位于所述第一时钟信号线和所述初始信号线之间，且沿第一方向延伸；
    所述第二电源线的宽度小于或者等于所述第一电源线的宽度，和/或，所述初始信号线的宽度小于所述第一电源线的宽度，和/或，所述第一时钟信号线的宽度小于所述第一电源线的宽度，且大于初始信号线的宽度，和/或，所述第二时钟信号线的宽度小于所述第一电源线的宽度，且大于初始信号线的宽度。
  4. 根据权利要求3所述的显示基板，其中，所述驱动电路包括：多个沿第一方向排布的移位寄存器，每个移位寄存器包括：第一晶体管至第十晶体管、第一电容至第三电容、信号输入端、信号输出端、第一时钟信号端、第二时钟信号端、第一电源端和第二电源端；
    所述第一晶体管的栅电极与第一时钟信号端电连接，所述第一晶体管的源电极与信号输入端电连接，所述第一晶体管的漏电极与第一节点电连接；
    所述第二晶体管的栅电极与第一节点电连接，所述第二晶体管的源电极与第一时钟信号端电连接，所述第二晶体管的第二极与第二节点电连接；
    所述第三晶体管的栅电极与第一时钟信号端电连接，所述第三晶体管的源电极与第二电源端电连接，所述第三晶体管的第二极与第二节点电连接；
    所述第四晶体管的栅电极与第二时钟信号端电连接，所述第四晶体管的源电极与第一节点电连接，所述第四晶体管的漏电极与所述第五晶体管的源电极电连接；
    所述第五晶体管的栅电极与第二节点电连接，所述第五晶体管的漏电极与第一电源端电连接；
    所述第六晶体管的栅电极与第二节点电连接，所述第六晶体管的源电极与第二时钟信号端电连接，所述第六晶体管的漏电极与第三节点电连接；
    所述第七晶体管的栅电极与第二时钟信号端电连接，所述第七晶体管的源电极与第三节点电连接，所述第七晶体管的漏电极与第四节点电连接；
    所述第八晶体管的栅电极与第一节点电连接，所述第八晶体管的源电极与第一电源端电连接，所述第八晶体管的漏电极与第四节点电连接；
    所述第九晶体管的栅电极与第四节点电连接，所述第九晶体管的源电极与信号输出端电连接，所述第九晶体管的漏电极与第一电源端电连接；
    所述第十晶体管的栅电极与第一节点电连接，所述第十晶体管的源电极与第二电源端电连接，所述第十晶体管的漏电极与信号输出端电连接；
    所述第一电容的第一极板与第二节点电连接，所述第一电容的第二极板与第三节点电连接；
    所述第二电容的第一极板与第一节点电连接，所述第二电容的第二极板与第二时钟信号端电连接；
    所述第三电容的第一极板与第四节点电连接，所述第三电容的第二极板与第一电源端电连接。
  5. 根据权利要求4所述的显示基板，其中，所述第一电容的第一极板位于所述第一电容的第二极板靠近衬底基板的一侧，且所述第一电容的第一极板在衬底基板上的正投影覆盖所述第一电容的第二极板在衬底基板上的正投影；
    所述第二电容的第一极板位于所述第二电容的第二极板靠近衬底基板的一侧，且所述第二电容的第一极板在衬底基板上的正投影覆盖所述第二电容的第二极板在衬底基板上的正投影；
    所述第三电容的第一极板位于所述第三电容的第二极板靠近衬底基板的一侧，且所述第三电容的第一极板在衬底基板上的正投影覆盖所述第三电容的第二极板在衬底基板上的正投影；
    其中，所述第一电容的第一极板在衬底基板上的正投影与所述第一电源线在衬底基板上的正投影的重叠部分的面积与所述第一电容的第一极板的面积正相关，所述第三电容的第一极板在衬底基板上的正投影与所述第一电源线在衬底基板上的正投影的重叠部分的面积与所述第三电容的第一极板的面积正相关；
    所述第一电容的第一极板与所述第一电源线的重叠部分的面积小于所述第三电容的第一极板与所述第一电源线的重叠部分的面积。
  6. 根据权利要求4或5所述的显示基板，其中，所述驱动电路中的多个移位寄存器级联，第一级移位寄存器的信号输入端与初始信号线电连接，第i-1级移位寄存器的信号输出端与第i级移位寄存器的信号输入端电连接，所有移位寄存器的第一电源端与第一电源线电连接，所述移位寄存器的第二电源端与第二电源线电连接，奇数级移位寄存器的第一时钟信号端与第一时钟信号线电连接，奇数级移位寄存器的第二时钟信号端与第二时钟信号线电连接，偶数级移位寄存器的第一时钟信号端与第二时钟信号线电连接，偶数级移位寄存器的第二时钟信号端与第一时钟信号线电连接，其中，i为大于或等于2的正整数。
  7. 根据权利要求6所述的显示基板，还包括：设置在所述衬底基板上，且位于显示区的阵列排布的子像素；
    第i级移位寄存器的信号输出端与第2i-1行子像素和第2i行子像素电连 接。
  8. 根据权利要求4至7任一所述的显示基板，其中，每个移位寄存器包括：异层设置的连接电极和输出信号线；
    所述输出信号线与本级移位寄存器的信号输出端电连接，所述连接电极在衬底基板上的正投影与所述输出信号线在衬底基板上的正投影至少部分重叠；
    所述连接电极分别与本级移位寄存器的信号输出端和下一级移位寄存器的信号输入端电连接。
  9. 根据权利要求8所述的显示基板，其中，所述显示基板包括：依次叠设在所述衬底基板上的半导体层、第一绝缘层、第一金属层、第二绝缘层、第二金属层、第三绝缘层和第三金属层；
    所述半导体层包括：多个晶体管的有源层，所述第一金属层包括：多个晶体管的栅电极、第一电容的第一极板、第二电容的第一极板和第三电容的第一极板，所述第二金属层包括：第一电容的第二极板、第二电容的第二极板、第三电容的第二极板和输出信号线，所述第三金属层包括：多个晶体管的源电极、多个晶体管的漏电极、第一电源线、第二电源线、第一时钟信号线、第二时钟信号线、初始信号线和连接电极；
    所述第三金属层的电阻小于所述第一金属层的电阻，且小于所述第二金属层的电阻。
  10. 根据权利要求9所述的显示基板，其中，在每个移位寄存器中，所有晶体管的有源层包括：沟道区和位于沟道区两侧的源极连接部和漏极连接部，晶体管的源电极与源极连接部电连接，晶体管的漏电极与漏极连接部电连接；
    第四晶体管的有源层的漏极连接部复用为漏电极，第五晶体管的有源层的源极连接部复用为源电极，第四晶体管的有源层的漏极连接部与第五晶体管的有源层的源极连接部电连接。
  11. 根据权利要求9或10所述的显示基板，其中，在每个移位寄存器中，第二晶体管的栅电极、第十晶体管的栅电极、第八晶体管的栅电极和第二电 容的第一极板为一体成型结构，第五晶体管的栅电极、第六晶体管的栅电极和第一电容的第一极板为一体成型结构，第九晶体管的栅电极和第三电容的第一极板为一体成型结构；
    第一晶体管的漏电极和第四晶体管的源电极为一体成型结构，第二晶体管的漏电极和第三晶体管的漏电极为一体成型结构，第三晶体管的源电极、第十晶体管的源电极和第二电源线为一体成型结构，第六晶体管的漏电极和第七晶体管的源电极为一体成型结构，第七晶体管的漏电极和第八晶体管的漏电极为一体成型结构，第八晶体管的源电极、第九晶体管的漏电极，第五晶体管的漏电极和第一电源线为一体成型结构。
  12. 根据权利要求9或10所述的显示基板，其中，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管和所述第五晶体管位于所述第一电容远离所述第三电容的一侧，且位于所述第二电容靠近第一电源线的一侧；所述第六晶体管位于所述第一电容靠近第二电源线的一侧，且位于第二电容靠近第三电容的一侧，所述第七晶体管和第八晶体管位于所述第一电容和所述第三电容之间，所述第九晶体管和所述第十晶体管位于所述第二电容靠近第二电源线的一侧。
  13. 根据权利要求9或10所述的显示基板，其中，在每个移位寄存器中，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管、所述第七晶体管、所述第九晶体管和所述第十晶体管的有源层沿第一方向延伸，所述第八晶体管的有源层沿第二方向延伸，所述第六晶体管的源电极和漏电极沿第一方向排布；
    所述第一方向和所述第二方向相交。
  14. 根据权利要求8所述的显示基板，其中，所述第一电源线与第一电容靠近第二电源线的边缘之间的距离小于所述第一电源线与第六晶体管的源电极之间的距离。
  15. 根据权利要求8所述的显示基板，其中，每个移位寄存器中的输出信号线包括：一体成型的第一连接部、第二连接部、第三连接部和第四连接部；
    所述第一连接部在衬底基板上的正投影与第九晶体管的源电极在衬底基 板上的正投影至少部分重叠，且与第十晶体管的漏电极在衬底基板上的正投影至少部分重叠，所述第一连接部沿第一方向延伸；
    所述第二连接部、所述第三连接部、所述第四连接部沿第二方向延伸，所述第二连接部和所述第三连接部位于所述第一连接部远离第一电源线的一侧，所述第四连接部位于所述第一连接部靠近第一电源线的一侧；
    所述第二连接部与第2i-1行子像素电连接，所述第三连接部与第2i行子像素电连接；所述第四连接部与下一级移位寄存器的信号输入端电连接；
    所述连接电极在衬底基板上的正投影与所述第四连接部在衬底基板上的正投影至少部分重叠，所述第四连接部通过连接电极与下一级移位寄存器的信号输入端电连接。
  16. 根据权利要求9或10所述的显示基板，其中，对于每个移位寄存器，所述显示基板还包括：贯穿所述第一绝缘层、所述第二绝缘层和所述第三绝缘层的第一过孔至第十过孔；
    所述第一过孔暴露出第一晶体管的有源层，所述第二过孔暴露出第二晶体管的有源层，所述第三过孔暴露出第三晶体管的有源层，所述第四过孔暴露出第四晶体管的有源层，所述第五过孔暴露出第五晶体管的有源层，所述第六过孔暴露出第六晶体管的有源层，所述第七过孔暴露出第七晶体管的有源层，所述第八过孔暴露出第八晶体管的有源层，所述第九过孔暴露出第九晶体管的有源层，所述第十过孔暴露出第十晶体管的有源层；
    第一晶体管的源电极和漏电极通过第一过孔与第一晶体管的有源层电连接，第二晶体管的源电极和漏电极通过第二过孔与第二晶体管的有源层电连接，第三晶体管的源电极和漏电极通过第三过孔与第三晶体管的有源层电连接，第四晶体管的源电极和漏电极通过第四过孔与第四晶体管的有源层电连接，第五晶体管的源电极和漏电极通过第五过孔与第五晶体管的有源层电连接，第六晶体管的源电极和漏电极通过第六过孔与第六晶体管的有源层电连接，第七晶体管的源电极和漏电极通过第七过孔与第七晶体管的有源层电连接，第八晶体管的源电极和漏电极通过第八过孔与第八晶体管的有源层电连接，第九晶体管的源电极和漏电极通过第九过孔与第九晶体管的有源层电连接，第十晶体管的源电极和漏电极通过第十过孔与第十晶体管的有源层电连 接。
  17. 根据权利要求9或10所述的显示基板，其中，所述显示基板还包括：贯穿第二绝缘层和第三绝缘层的第十一过孔至第十六过孔；
    所述第十一过孔暴露出第一晶体管的栅电极，所述第十二过孔暴露出第二晶体管的栅电极，所述第十三过孔暴露出第四晶体管的栅电极，所述第十四过孔暴露出第五晶体管的栅电极，所述第十五过孔暴露出第七晶体管的栅电极，所述第十六过孔暴露出第三电容的第一极板；
    第二晶体管的源电极和一个时钟信号线通过第十一过孔与第一晶体管的栅电极的电连接，第一晶体管的漏电极通过第十二过孔与第二晶体管的栅电极电连接，第六晶体管的源电极和另一个时钟信号线通过第十三过孔与第四晶体管的栅电极电连接，第三晶体管的漏电极通过第十四过孔与第五晶体管的栅电极电连接，第七晶体管的漏电极和另一个时钟信号线通过第十六过孔与第三电容的第一极板电连接。
  18. 根据权利要求9或10所述的显示基板，其中，所述显示基板还包括：设置在第三绝缘层上的第十七过孔至第二十一过孔；
    所述第十七过孔暴露出第一电容的第二极板，所述第十八过孔暴露出第二电容的第二极板，所述第十九过孔暴露出第三电容的第二极板，所述第二十过孔暴露出输出信号线的第一连接部，所述第二十一过孔暴露出输出信号线的第四连接部；
    第六晶体管的漏电极通过第十七过孔与第一电容的第二极板电连接，第六晶体管的源电极通过第十八过孔与第二电容的第二极板电连接，第九晶体管的漏电极通过第十九过孔与第三电容的第二极板电连接，第九晶体管的源电极和第十晶体管的漏电极通过第二十过孔与输出信号线电连接，连接电极通过第二十一过孔与输出信号线电连接；
    所述第十七过孔的数量为多个，多个第十七过孔沿第一方向排布；
    所述第十八过孔的数量为多个，多个第十八过孔沿第一方向排布；
    所述第十九过孔的数量为多个，多个第十九过孔沿第二方向排布；
    所述第二十过孔的数量为多个，多个第二十过孔沿第一方向排布。
  19. 一种显示装置，包括如权利要求1至18任一项所述的显示基板。
  20. 一种显示基板的制作方法，设置为制作如权利要求1至18任一项所述的显示基板，所述方法包括：
    提供一衬底基板；
    在衬底基板上形成位于非显示区的驱动电路和第一电源线；所述驱动电路包括：第一电容、第二电容和第三电容；所述第一电容和所述第三电容沿第一方向排布，所述第二电容和所述第三电容分别位于所述第一电容的两侧，所述第二电容位于所述第一电容靠近显示区的一侧，所述第三电容的一个极板与所述第一电源线电连接；
    所述第一电源线沿第一方向延伸，所述第一电容在衬底基板上的正投影与所述第一电源线在衬底基板上的正投影至少部分重叠。
  21. 根据权利要求20所述的方法，其中，所述驱动电路包括：多个移位寄存器，每个移位寄存器包括：多个晶体管以及第一电容至第三电容，所述在衬底基板上形成位于非显示区的驱动电路和第一电源线包括：
    在衬底基板上形成半导体层，所述半导体层包括：多个晶体管的有源层；
    在半导体层上依次形成第一绝缘层和第一金属层，所述第一金属层包括：多个晶体管的栅电极、第一电容的第一极板、第二电容的第一极板和第三电容的第一极板；
    在第一金属层上依次形成第二绝缘层和第二金属层，所述第二金属层包括：第一电容的第二极板、第二电容的第二极板、第三电容的第二极板和输出信号线；
    在第二金属层上依次形成第三绝缘层和第三金属层，所述第三金属层包括：多个晶体管的源电极、多个晶体管的漏电极、第一电源线、第二电源线、第一时钟信号线、第二时钟信号线、初始信号线和连接电极。
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