WO2023206462A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

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Publication number
WO2023206462A1
WO2023206462A1 PCT/CN2022/090541 CN2022090541W WO2023206462A1 WO 2023206462 A1 WO2023206462 A1 WO 2023206462A1 CN 2022090541 W CN2022090541 W CN 2022090541W WO 2023206462 A1 WO2023206462 A1 WO 2023206462A1
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WIPO (PCT)
Prior art keywords
signal line
transistor
scanning signal
pixel
layer
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PCT/CN2022/090541
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English (en)
French (fr)
Inventor
龙祎璇
承天一
李孟
尚庭华
刘彪
陈家兴
牛佐吉
徐鹏
屈忆
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/090541 priority Critical patent/WO2023206462A1/zh
Priority to CN202280001029.4A priority patent/CN117356189A/zh
Publication of WO2023206462A1 publication Critical patent/WO2023206462A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels

Definitions

  • This article relates to but is not limited to the field of display technology, and specifically relates to a display substrate, a preparation method thereof, and a display device.
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diodes
  • TFT thin film transistors
  • the present disclosure provides a display substrate, including a display area and a binding area located on one side of the display area.
  • the display area includes M pixel rows arranged in sequence, where M is a positive integer greater than 1; at least One pixel row includes a scanning signal line and a plurality of sub-pixels arranged sequentially along the extending direction of the scanning signal line. At least one sub-pixel includes a pixel driving circuit connected to the scanning signal line, and the pixel driving circuit at least includes a storage capacitor.
  • the plurality of transistors at least including a first transistor as a first initialization transistor, the scanning signal line including at least a second scanning signal line, the second scanning signal line being configured to control the first
  • the transistor is turned on or off; in at least one pixel row, the second scanning signal line is set on a side of the storage capacitor close to the boundary of the display area, and the boundary of the display area is the display area close to the binding area. edge on one side.
  • the first electrode of the first transistor is connected to a first initial signal line, and the first initial signal line is provided on a side of the storage capacitor close to the boundary of the display area.
  • an edge of the first initial signal line close to the side of the binding area in the M-th pixel row forms a pixel driving circuit boundary.
  • the pixel driving circuit boundary is located on a side of the display area boundary away from the binding area.
  • the distance between the pixel driving circuit boundary and the display area boundary is 6 ⁇ m to 10 ⁇ m.
  • the plurality of transistors further includes a seventh transistor serving as a second initialization transistor
  • the scan signal line further includes a first scan signal line
  • the first scan signal line is configured to control the The seventh transistor is turned on or off, and the first scanning signal line is provided on a side of the storage capacitor away from the boundary of the display area.
  • the first electrode of the seventh transistor is connected to a second initial signal line, and the second initial signal line is provided on a side of the storage capacitor away from the boundary of the display area.
  • the orthographic projection of the second initial signal line in the i-th pixel row on the display substrate is at least partially the same as the orthographic projection of the second scanning signal line in the i-1th pixel row on the display substrate.
  • Overlap, i 2, 3,...,M.
  • the plurality of transistors further includes a second transistor serving as a compensation transistor and a fourth transistor serving as a data writing transistor
  • the scanning signal line further includes controlling the fourth transistor to be turned on or off.
  • the third scanning signal line and the fourth scanning signal line that control the compensation transistor to be turned on or off, the third scanning signal line and the fourth scanning signal line are arranged on the storage capacitor close to the boundary of the display area. one side.
  • the third scanning signal line is disposed on a side of the fourth scanning signal line close to the boundary of the display area.
  • the plurality of transistors further includes a fifth transistor and a sixth transistor
  • the display substrate further includes a light emitting control line configured to control the fifth and sixth transistors.
  • the light-emitting control line is provided on the side of the storage capacitor away from the boundary of the display area.
  • the plurality of transistors further includes a second transistor as a compensation transistor, a third transistor as a driving transistor, a fourth transistor as a data writing transistor, a fifth transistor and a sixth transistor as a light emitting transistor.
  • transistor, and a seventh transistor as a second initialization transistor; the first transistor, the second transistor and the fourth transistor are provided on one side of the third transistor close to the boundary of the display area, and the fifth transistor, The sixth transistor and the seventh transistor are disposed on a side of the third transistor away from the boundary of the display area.
  • the first and second transistors are oxide transistors
  • the third to seventh transistors are low-temperature polysilicon transistors.
  • the display substrate in a plane perpendicular to the display substrate, includes a driving circuit layer provided on a substrate and a light-emitting structure layer provided on a side of the driving circuit layer away from the substrate;
  • the driving circuit layer includes a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer and a third conductive layer arranged along a direction away from the substrate;
  • the first semiconductor layer at least includes a plurality of The active layer of a polysilicon transistor
  • the first conductive layer at least includes a first scanning signal line, a third scanning signal line, gate electrodes of a plurality of polysilicon transistors and a first plate of a storage capacitor
  • the second conductive layer at least Comprising a second scanning signal line, a fourth scanning signal line, a first initial signal line, gate electrodes of a plurality of oxide transistors and a second plate of a storage capacitor
  • the second semiconductor layer at least includes a plurality of oxide transistors.
  • the present disclosure also provides a display device, including the aforementioned display substrate.
  • the present disclosure also provides a method for preparing a display substrate.
  • the display substrate includes a display area and a binding area located on one side of the display area.
  • the display area includes M pixel rows, where M is greater than A positive integer of 1; at least one pixel row includes a scanning signal line and a plurality of sub-pixels arranged sequentially along the extending direction of the scanning signal line, at least one sub-pixel includes a pixel driving circuit connected to the scanning signal line, the pixel
  • the driving circuit at least includes a storage capacitor and a plurality of transistors, the plurality of transistors at least include a first transistor as a first initialization transistor, the scanning signal line includes at least a second scanning signal line, the second scanning signal line is configured In order to control the first transistor to be turned on or off; the preparation method includes:
  • a pixel driving circuit and a second scanning signal line are formed in at least one pixel row, and the second scanning signal line is disposed on a side of the storage capacitor close to a display area boundary.
  • the display area boundary is where the display area is close to the display area. Describes the boundary on one side of the binding area.
  • Figure 1 is a schematic structural diagram of a display device
  • Figure 2 is a schematic structural diagram of a display substrate
  • Figure 3 is a schematic plan view of a display area in a display substrate
  • Figure 4 is a schematic cross-sectional structural diagram of a display area in a display substrate
  • Figure 5 is an equivalent circuit schematic diagram of a pixel driving circuit
  • Figure 6 is a working timing diagram of a pixel driving circuit
  • Figure 7 is a schematic plan view of a display substrate according to an exemplary embodiment of the present disclosure.
  • Figure 8 is a schematic diagram after the first semiconductor layer pattern is formed according to an embodiment of the present disclosure.
  • 9a and 9b are schematic diagrams after the first conductive layer pattern is formed according to an embodiment of the present disclosure.
  • Figures 10a and 10b are schematic diagrams after forming a second conductive layer pattern according to an embodiment of the present disclosure
  • FIG. 11a and 11b are schematic diagrams after the second semiconductor layer pattern is formed according to an embodiment of the present disclosure.
  • Figure 12 is a schematic diagram after forming a fifth insulating layer pattern according to an embodiment of the present disclosure.
  • Figures 13a and 13b are schematic diagrams after forming a third conductive layer pattern according to an embodiment of the present disclosure
  • Figure 14 is a schematic diagram after forming a first flat layer pattern according to an embodiment of the present disclosure.
  • 15a and 15b are schematic diagrams after the fourth conductive layer pattern is formed according to an embodiment of the present disclosure.
  • Figure 16 is a schematic diagram after forming a second flat layer pattern according to an embodiment of the present disclosure.
  • 17a to 17d are schematic diagrams after forming an anode conductive layer pattern according to an embodiment of the present disclosure.
  • Figures 18a and 18b are schematic diagrams after forming a pixel definition layer pattern according to an embodiment of the present disclosure
  • Figure 19 is a schematic plan view of a conventional display substrate.
  • 61 data signal line
  • 62 first power line
  • 63 anode connecting electrode
  • 102 Drive circuit layer
  • 103 Light-emitting structure layer
  • 104 Packaging structure layer
  • the scale of the drawings in this disclosure can be used as a reference in actual processes, but is not limited thereto.
  • the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs.
  • the number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures.
  • the figures described in the present disclosure are only structural schematic diagrams, and one mode of the present disclosure is not limited to the figures. The shape or numerical value shown in the figure.
  • connection should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements.
  • connection should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements.
  • a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode.
  • the transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, channel region, and source electrode .
  • the channel region refers to the region through which current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and the “drain electrode” may be interchanged with each other. Therefore, in this specification, “source electrode” and “drain electrode” can be interchanged with each other, and “source terminal” and “drain terminal” can be interchanged with each other.
  • electrical connection includes a case where constituent elements are connected together through an element having some electrical effect.
  • component having some electrical function There is no particular limitation on the “component having some electrical function” as long as it can transmit and receive electrical signals between the connected components.
  • elements having some electrical function include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.
  • parallel refers to a state in which the angle formed by two straight lines is -10° or more and 10° or less. Therefore, it also includes a state in which the angle is -5° or more and 5° or less.
  • vertical refers to a state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore includes an angle of 85° or more and 95° or less.
  • film and “layer” may be interchanged.
  • conductive layer may sometimes be replaced by “conductive film.”
  • insulating film may sometimes be replaced by “insulating layer”.
  • triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not strictly speaking. They can be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances. There can be leading angles, arc edges, deformations, etc.
  • Figure 1 is a schematic structural diagram of a display device.
  • the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array.
  • the timing controller is connected to the data driver, the scan driver, and the light-emitting driver respectively.
  • the data driver is connected to a plurality of data signal lines. (D1 to Dn) are connected, the scanning driver is connected to a plurality of scanning signal lines (S1 to Sm), and the light emitting driver is connected to a plurality of light emitting signal lines (E1 to Eo).
  • the pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, at least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit, and the circuit unit may include at least one scanning signal line, at least one data signal line, At least one light-emitting signal line and pixel driving circuit.
  • the timing controller may provide a gray value and a control signal suitable for the specifications of the data driver to the data driver, and may provide a clock signal, a scan start signal, and the like suitable for the specifications of the scan driver to the scan driver.
  • the driver can provide a clock signal, an emission stop signal, and the like suitable for the specifications of the light-emitting driver to the light-emitting driver.
  • the data driver may generate data voltages to be provided to the data signal lines D1, D2, D3, . . . and Dn using the grayscale values and control signals received from the timing controller. For example, the data driver may sample a grayscale value using a clock signal, and apply a data voltage corresponding to the grayscale value to the data signal lines D1 to Dn in units of pixel rows, where n may be a natural number.
  • the scan driver may generate scan signals to be supplied to the scan signal lines S1, S2, S3, . . .
  • the scan driver may sequentially supply scan signals having on-level pulses to the scan signal lines S1 to Sm.
  • the scan driver may be configured in the form of a shift register, and may generate the scan signal in a manner that sequentially transmits a scan start signal provided in the form of an on-level pulse to a next-stage circuit under the control of a clock signal, m can be a natural number.
  • the light-emitting driver may generate emission signals to be provided to the light-emitting signal lines E1, E2, E3, . . . and Eo by receiving a clock signal, an emission stop signal, or the like from the timing controller.
  • the light-emitting driver may sequentially provide emission signals with off-level pulses to the light-emitting signal lines E1 to Eo.
  • the light-emitting driver may be configured in the form of a shift register, and may generate the emission signal in a manner that sequentially transmits an emission stop signal provided in the form of a cut-off level pulse to a next-stage circuit under the control of a clock signal, o Can be a natural number.
  • FIG. 2 is a schematic structural diagram of a display substrate.
  • the display substrate may include a display area 100 , a binding area 200 located on one side of the display area 100 , and a frame area 300 located on other sides of the display area 100 .
  • the display area 100 may be a flat area including a plurality of sub-pixels Pxij constituting a pixel array, the plurality of sub-pixels Pxij are configured to display dynamic pictures or still images, and the display area 100 may be called an active area (AA).
  • the display substrate may be a flexible substrate, and thus the display substrate may be deformable, such as curled, bent, folded, or rolled.
  • the display substrate may further include a display area boundary BD, and the display area boundary BD may be an edge of the display area 100 close to the binding area 200 .
  • the bonding area 200 may include a fan-out area, a bending area, a driver chip area and a bonding pin area that are sequentially arranged in a direction away from the display area.
  • the fan-out area is connected to the display area, including multiple A data fan-out line, which is configured to connect the data signal line (Data Line) of the display area in a fan-out wiring method.
  • the bending area is connected to the fan-out area and may include a composite insulating layer provided with grooves configured to bend the binding area to the back of the display area.
  • the driver chip area may include an integrated circuit (Integrated Circuit, IC for short) configured to be connected to multiple data fan-out lines.
  • the bonding pin area may include a bonding pad (Bonding Pad), which is configured to be bonded to an external flexible circuit board (Flexible Printed Circuit, referred to as FPC).
  • the frame area 300 may include a circuit area, a power line area, a crack dam area, and a cutting area that are sequentially arranged in a direction away from the display area.
  • the circuit area is connected to the display area and may include at least a gate driving circuit connected to the first scanning signal line, the second scanning signal line, the third scanning signal line and the light emitting control line of the pixel driving circuit in the display area.
  • the power line area is connected to the circuit area and may at least include a power lead extending in a direction parallel to the edge of the display area and connected to a cathode in the display area.
  • the crack dam area is connected to the power line area and may include at least a plurality of cracks provided on the composite insulation layer.
  • the cutting area is connected to the crack dam area and may at least include cutting grooves provided on the composite insulating layer. The cutting grooves are configured such that after all film layers of the display substrate are prepared, the cutting equipment cuts along the cutting grooves respectively.
  • the fan-out area in the binding area 200 and the power line area in the frame area 300 may be provided with first isolation dams and second isolation dams, and the first isolation dams and the second isolation dams may be provided along It extends in a direction parallel to the edge of the display area to form a ring structure surrounding the display area.
  • the edge of the display area is the edge on one side of the display area binding area or the border area.
  • Figure 3 is a schematic plan view of a display area in a display substrate.
  • the display substrate may include a plurality of pixel units P arranged in a matrix.
  • At least one pixel unit P may include a first sub-pixel P1 that emits light of a first color, and a second sub-pixel that emits light of a second color.
  • the pixel P2 and the third and fourth sub-pixels P3 and P4 that emit light of the third color.
  • Each sub-pixel may include a circuit unit and a light-emitting device.
  • the circuit unit may include at least a pixel driving circuit.
  • the pixel driving circuit is connected to the scanning signal line, the data signal line and the light-emitting signal line respectively.
  • the pixel driving circuit is configured to operate between the scanning signal line and the light-emitting signal line. Under the control of the light-emitting signal line, it receives the data voltage transmitted by the data signal line and outputs the corresponding current to the light-emitting device.
  • the light-emitting device in each sub-pixel is respectively connected to the pixel driving circuit of the sub-pixel, and the light-emitting device is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.
  • the first sub-pixel P1 may be a red sub-pixel (R) emitting red light
  • the second sub-pixel P2 may be a blue sub-pixel (B) emitting blue light
  • the fourth sub-pixel P4 may be a green sub-pixel (G) emitting green light.
  • the shape of the sub-pixels may be rectangular, rhombus, pentagon or hexagon, and the four sub-pixels may be arranged in a diamond shape to form an RGBG pixel arrangement.
  • the four sub-pixels may be arranged horizontally, vertically, or in a square manner, which is not limited in this disclosure.
  • the pixel unit may include three sub-pixels, and the three sub-pixels may be arranged horizontally, vertically, or vertically, which is not limited in this disclosure.
  • FIG. 4 is a schematic cross-sectional structural diagram of a display area in a display substrate, illustrating the structure of four sub-pixels in the display area.
  • the display substrate may include a driving circuit layer 102 disposed on a substrate 101 , a light-emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the substrate 101 , and a light-emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the substrate 101 .
  • the structural layer 103 is away from the packaging structural layer 104 on one side of the substrate 101.
  • the display substrate may include other film layers, such as touch structure layers, etc., which are not limited in this disclosure.
  • substrate 101 may be a flexible substrate, or may be a rigid substrate.
  • the driving circuit layer 102 of each sub-pixel may include a pixel driving circuit composed of a plurality of transistors and storage capacitors.
  • the light-emitting structure layer 103 of each sub-pixel may include a light-emitting device composed of multiple film layers.
  • the multiple film layers may include at least an anode, a pixel definition layer, an organic light-emitting layer and a cathode.
  • the anode is connected to the pixel driving circuit, and the organic light-emitting layer is connected to the pixel driving circuit.
  • the anode is connected, and the cathode is connected to the organic light-emitting layer.
  • the organic light-emitting layer emits light of corresponding colors driven by the anode and cathode.
  • the packaging structure layer 104 may include a stacked first packaging layer, a second packaging layer, and a third packaging layer.
  • the first packaging layer and the third packaging layer may be made of inorganic materials
  • the second packaging layer may be made of organic materials.
  • the layer is arranged between the first encapsulation layer and the third encapsulation layer to form an inorganic material/organic material/inorganic material stack structure, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.
  • the organic light-emitting layer may include an emitting layer (EML) and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), Hole blocking layer (HBL), electron transport layer (ETL) and electron injection layer (EIL).
  • EML emitting layer
  • HIL hole injection layer
  • HTL hole transport layer
  • EBL electron blocking layer
  • HBL Hole blocking layer
  • ETL electron transport layer
  • EIL electron injection layer
  • one or more of the hole injection layer, hole transport layer, electron blocking layer, hole blocking layer, electron transport layer and electron injection layer of all sub-pixels may be connected together Common layer, the light-emitting layers of adjacent sub-pixels may have a small amount of overlap, or may be isolated from each other.
  • Figure 5 is an equivalent circuit schematic diagram of a pixel driving circuit.
  • the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure.
  • the pixel driving circuit may include 7 transistors (first transistor T1 to seventh transistor T7) and 1 storage capacitor C.
  • the pixel driving circuit is respectively connected to 10 signal lines (data signal line D, first scanning Signal line S1, second scanning signal line S2, third scanning signal line S3, fourth scanning signal line S4, light emitting signal line E, first initial signal line INIT1, second initial signal line INIT1, first power supply line VDD and The second power line VSS) is connected.
  • the pixel driving circuit may include a first node N1, a second node N2, and a third node N3.
  • the first node N1 is respectively connected to the first pole of the third transistor T3, the second pole of the fourth transistor T4 and the second pole of the fifth transistor T5, and the second node N2 is respectively connected to the second pole of the first transistor T1.
  • the control electrode of the third transistor T3 is connected to the second end of the storage capacitor C, and the third node N3 is respectively connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3 and the first electrode of the sixth transistor T6. connect.
  • the first end of the storage capacitor C is connected to the first power line VDD, and the second end of the storage capacitor C is connected to the second node N2, that is, the second end of the storage capacitor C is connected to the third transistor T3. Control pole connection.
  • control electrode of the first transistor T1 is connected to the second scanning signal line S2, the first electrode of the first transistor T1 is connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is connected to the first initial signal line INIT1.
  • Two nodes N2 are connected.
  • the first transistor T1 transmits the first initializing voltage to the second end of the storage capacitor C to initialize the storage capacitor C.
  • control electrode of the second transistor T2 is connected to the fourth scanning signal line S4, the first electrode of the second transistor T2 is connected to the second electrode of the first transistor T1, and the second electrode of the second transistor T2 Connected to the third node N3.
  • the second transistor T2 connects the control electrode of the third transistor T3 and the second electrode of the third transistor T3.
  • the control electrode of the third transistor T3 is connected to the second node N2, that is, the control electrode of the third transistor T3 is connected to the second end of the storage capacitor C, and the first electrode of the third transistor T3 is connected to the first node N2.
  • the node N1 is connected, and the second pole of the third transistor T3 is connected to the third node N3.
  • the third transistor T3 may be called a driving transistor, and the third transistor T3 determines the size of the driving current flowing between the first power supply line VDD and the light-emitting device according to the potential difference between its control electrode and the first electrode.
  • control electrode of the fourth transistor T4 is connected to the third scanning signal line S3, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node. N1 connection.
  • the fourth transistor T4 causes the data voltage of the data signal line D to be input to the first node N1.
  • control electrode of the fifth transistor T5 is connected to the light-emitting signal line E
  • first electrode of the fifth transistor T5 is connected to the first power supply line VDD
  • second electrode of the fifth transistor T5 is connected to the first node N1 connect.
  • the control electrode of the sixth transistor T6 is connected to the light-emitting signal line E
  • first electrode of the sixth transistor T6 is connected to the third node N3
  • the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting device.
  • the fifth transistor T5 and the sixth transistor T6 cause the light-emitting device to emit light by forming a driving current path between the first power supply line VDD and the light-emitting device.
  • the control electrode of the seventh transistor T7 is connected to the first scanning signal line S1
  • the first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2
  • the second electrode of the seventh transistor T7 is connected to the light emitting line.
  • the seventh transistor T7 transmits the second initial voltage to the first pole of the light-emitting device to initialize or release the amount of charge accumulated in the first pole of the light-emitting device. The amount of charge accumulated in the first pole of a light-emitting device.
  • the light-emitting device may be an OLED including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or may be a QLED including a stacked first electrode (anode) , quantum dot light-emitting layer and second electrode (cathode).
  • the second pole of the light-emitting device is connected to the second power line VSS, the signal of the second power line VSS is a low-level signal, and the signal of the first power line VDD continuously provides a high-level signal.
  • the first to seventh transistors T1 to T7 may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel drive circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the product yield. In some possible implementations, the first to seventh transistors T1 to T7 may include P-type transistors and N-type transistors.
  • the first to seventh transistors T1 to T7 may employ low-temperature polysilicon transistors, or may employ oxide transistors, or may employ low-temperature polysilicon transistors and metal oxide transistors.
  • the active layer of a low temperature polysilicon transistor is made of low temperature polysilicon (LTPS), and the active layer of a metal oxide transistor is made of metal oxide semiconductor (Oxide).
  • LTPS low temperature polysilicon
  • Oxide metal oxide semiconductor
  • Low-temperature polysilicon transistors have the advantages of high mobility and fast charging, while oxide transistors have the advantages of low leakage current.
  • Low-temperature polysilicon transistors and metal oxide transistors are integrated on a display substrate to form low-temperature polycrystalline oxide (Low Temperature Polycrystalline Oxide). , referred to as LTPO) display substrate, can take advantage of the advantages of both, can achieve low-frequency driving, can reduce power consumption, and can improve display quality.
  • LTPO Low Temperature Polycrystalline Oxide
  • FIG. 6 is a working timing diagram of a pixel driving circuit.
  • the following describes an exemplary embodiment of the present disclosure through the working process of the pixel driving circuit illustrated in Figure 5.
  • the pixel driving circuit in Figure 5 includes 7 transistors (first transistor T1 to seventh transistor T7) and 1 storage capacitor C.
  • the first transistor T1 and the second transistor T2 are N-type oxide transistors, and the third to seventh transistors T3 to T7 are P-type low-temperature polysilicon transistors.
  • the working process of the pixel driving circuit may include:
  • the first phase A1 is called the reset phase.
  • the signal of the second scanning signal line S2 is a conduction signal (high level).
  • the signal on signal line E is a disconnect signal.
  • the conduction signal of the second scanning signal line S2 turns on the first transistor T1, and the signal of the first initial signal line INIT1 is provided to the second node N2 through the first transistor T1 to initialize (reset) the storage capacitor C and clear the storage The original charge in the capacitor.
  • the disconnect signals of the first scanning signal line S1, the third scanning signal line S3, the fourth scanning signal line S4 and the light emitting signal line E cause the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and The seventh transistor T7 is turned off, and the OLED does not emit light at this stage.
  • the second stage A2 is called the data writing stage or the threshold compensation stage.
  • the signals of the first scanning signal line S1, the third scanning signal line S3 and the fourth scanning signal line S4 are conduction signals.
  • the second scanning signal line S2 and The signal of the light-emitting signal line E is a disconnect signal, and the data signal line D outputs a data voltage.
  • the third transistor T3 is turned on.
  • the turn-on signals of the first scanning signal line S1, the third scanning signal line S3, and the fourth scanning signal line S4 turn on the second transistor T2, the fourth transistor T4, and the seventh transistor T7.
  • the second transistor T2 and the fourth transistor T4 are turned on so that the data voltage output by the data signal line D is provided to the second transistor through the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. Node N2, and the difference between the data voltage output by the data signal line D and the threshold voltage of the third transistor T3 is charged into the storage capacitor C.
  • the voltage at the second end (second node N2) of the storage capacitor C is Vd-
  • the seventh transistor T7 is turned on to provide the signal of the second initial signal line INIT2 to the first pole of the OLED, initialize (reset) the first pole of the OLED, clear its internal pre-stored voltage, complete the initialization, and ensure that the OLED does not emit light.
  • the off signal of the second scanning signal line S2 turns off the first transistor T1
  • the off signal on the light emitting signal line E turns off the fifth transistor T5 and the sixth transistor T6.
  • the third stage A3 is called the light-emitting stage.
  • the signal of the light-emitting signal line E is a conduction signal, and the signals of the first scanning signal line S1, the second scanning signal line S2, the third scanning signal line S3 and the fourth scanning signal line S4 for disconnection signal.
  • the turn-on signal of the light-emitting signal line E turns on the fifth transistor T5 and the sixth transistor T6.
  • the power supply voltage output by the first power line VDD passes through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6 to the OLED.
  • the first pole provides the driving voltage to drive the OLED to emit light.
  • the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the second node N2 is Vdata-
  • I is the driving current flowing through the third transistor T3, that is, the driving current that drives the OLED
  • K is a constant
  • Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3
  • Vth is the third transistor T3.
  • Vd is the data voltage output by the data signal line D
  • Vdd is the power supply voltage output by the first power supply line VDD.
  • the display substrate may include a display area and a binding area located on one side of the display area.
  • the display area includes M pixel rows arranged in sequence, where M is a positive integer greater than 1; at least one pixel
  • the rows include scanning signal lines and a plurality of sub-pixels arranged sequentially along the extending direction of the scanning signal lines.
  • At least one sub-pixel includes a pixel driving circuit connected to the scanning signal lines.
  • the pixel driving circuit at least includes a storage capacitor and a plurality of transistors, the plurality of transistors at least include a first transistor as a first initialization transistor, the scan signal line includes at least a second scan signal line, the second scan signal line is configured to control the conduction of the first transistor.
  • the second scanning signal line is set on the side of the storage capacitor close to the boundary of the display area, and the boundary of the display area is the side of the display area close to the binding area the edge of.
  • the first electrode of the first transistor is connected to a first initial signal line, and the first initial signal line is provided on a side of the storage capacitor close to the boundary of the display area.
  • an edge of the first initial signal line close to the side of the binding area in the M-th pixel row forms a pixel driving circuit boundary.
  • the pixel driving circuit boundary is located on a side of the display area boundary away from the binding area.
  • the distance between the pixel driving circuit boundary and the display area boundary is 6 ⁇ m to 10 ⁇ m.
  • FIG. 7 is a schematic plan view of a display substrate according to an exemplary embodiment of the present disclosure, illustrating the pixel driving circuit structure of the M-1th pixel row and the Mth pixel row close to the binding area in the display area.
  • the display substrate may include a display area 100 and a binding area 200 located on one side of the display area 100 in the second direction Y, and the display area 100 may include M pixel rows sequentially arranged along the second direction Y, At least one pixel row may include a plurality of sub-pixels arranged sequentially along the first direction X, and M is a positive integer greater than 1.
  • the M-th row is the pixel row closest to the display area boundary BD
  • the M-1th row is the pixel row located on the side of the M-th row away from the display area boundary BD
  • the display area boundary BD is the pixel row closest to the display area 100.
  • each anode has an edge close to one side of the binding area, and the edge closest to the binding area among the multiple anodes is called the anode boundary, and the display area boundary BD It may be a straight line passing through the anode boundary and extending along the first direction X.
  • the display area boundary may be located within the display area, or may be located within the binding area, and the display area boundary may be a related structural reference line with structural features.
  • the display area boundary could be the location of the isolation dam boundary within the binding area.
  • the display area boundary may be the location within the binding area where the cathode ends.
  • the display area boundary may be the position of the straight edge area of the fan-out trace within the binding area.
  • the boundary of the display area may be the location where the data signal line is transferred and accessed (transferred via hole) in the binding area, which is not limited in this disclosure.
  • At least one pixel row may include a scanning signal line extending along the first direction X, and at least one sub-pixel in one pixel row may include a pixel driving circuit, and the pixel driving circuit may be connected to the scanning signal line.
  • the pixel driving circuit may include at least a plurality of transistors and a storage capacitor.
  • the plurality of transistors in the pixel driving circuit may include at least a first transistor T1 as a first initialization transistor, and the scanning signal line may include at least a second scanning signal line 32 configured to control the first transistor T1. On or off.
  • the storage capacitor 40 may be located in the middle area of the sub-pixel in the second direction Y, and may include a stacked first plate and a second plate.
  • the second scanning signal line 32 may be disposed on a side of the storage capacitor 40 close to the display area boundary BD.
  • the first transistor T1 may include a gate electrode, a first electrode and a second electrode, the gate electrode of the first transistor T1 may be connected to the second scan signal line 32 , and the first electrode of the first transistor T1 may Connected to the first initial signal line 31 , the first initial signal line 31 may be disposed on a side of the storage capacitor 40 close to the display area boundary BD.
  • the edge of the first initial signal line 31 in the M-th pixel row close to the binding area 200 forms a pixel driving circuit boundary PD, and the pixel driving circuit boundary PD may be located at the display area boundary BD away from the binding area 200 side.
  • the distance L between the pixel driving circuit boundary PD and the display area boundary BD may be approximately 6 ⁇ m to 10 ⁇ m.
  • the plurality of transistors in the pixel driving circuit may further include a seventh transistor T7 as a second initialization transistor, and the scanning signal line may further include a first scanning signal line 21 configured to In order to control the on or off of the seventh transistor T7, the first scanning signal line 21 is provided on the side of the storage capacitor 40 away from the display area boundary BD.
  • the seventh transistor T7 may include a gate electrode, a first electrode and a second electrode.
  • the gate electrode of the seventh transistor T7 may be connected to the first scanning signal line 21 .
  • the first electrode of the seventh transistor T7 may be connected to the first scanning signal line 21 . It may be connected to the second initial signal line 57 , and the second initial signal line 57 may be disposed on a side of the storage capacitor 40 away from the display area boundary BD.
  • the plurality of transistors in the pixel driving circuit may further include a second transistor T2 as a compensation transistor and a fourth transistor T4 as a data writing transistor
  • the scan signal line may further include a third scan signal line 23 and a fourth scanning signal line 33
  • the third scanning signal line 23 is configured to control the turning on or off of the fourth transistor T4
  • the fourth scanning signal line 33 is configured to control the turning on or off of the second transistor T2
  • the third scanning signal line 23 and the fourth scanning signal line 33 are provided on the side of the storage capacitor 40 close to the display area boundary BD.
  • the third scanning signal line 23 may be disposed on a side of the fourth scanning signal line 33 close to the display area boundary BD.
  • the first scanning signal line 21 in the i-th pixel row and the third scanning signal line 23 in the i-1th pixel row may have an integrated structure.
  • the plurality of transistors in the pixel driving circuit further include fifth transistors T5 and sixth transistors T6 as light emitting transistors, and the display substrate may further include a light emitting control line 22 configured to control the first light emitting transistor.
  • the fifth transistor T5 and the sixth transistor T6 are turned on or off, and the light emission control line 22 is provided on the side of the storage capacitor 40 away from the display area boundary BD.
  • the plurality of transistors in the pixel driving circuit may include a first transistor T1 as a first initialization transistor, a second transistor T2 as a compensation transistor, a third transistor T3 as a driving transistor, and a third transistor T3 as a data writing transistor.
  • the fourth transistor T4 may be disposed on a side of the third transistor T3 close to the display area boundary BD, and the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be disposed on a side of the third transistor T3 away from the display area.
  • the first and second transistors T1 and T2 may be oxide transistors, and the third to seventh transistors T3 to T7 may be low-temperature polysilicon transistors.
  • the display substrate in a plane perpendicular to the display substrate, may include a driving circuit layer disposed on a substrate and a light-emitting structure layer disposed on a side of the driving circuit layer away from the substrate.
  • the driving circuit layer may include a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer and a third conductive layer arranged in a direction away from the substrate.
  • the first semiconductor layer may include at least an active layer of a plurality of polysilicon transistors, and the first conductive layer may include at least a first scanning signal line 21 , a third scanning signal line 23 , gate electrodes of the plurality of polysilicon transistors, and a third of the storage capacitor 40 .
  • the second conductive layer may include at least a second scanning signal line 32, a fourth scanning signal line 33, a first initial signal line 31, gate electrodes of a plurality of oxide transistors and a second plate of the storage capacitor 40,
  • the second semiconductor layer may include at least active layers of a plurality of oxide transistors, and the third conductive layer may include at least the second initial signal line 57 .
  • a extending along direction B means that A may include a main part and a secondary part connected to the main part.
  • the main part is a line, line segment or bar-shaped body, the main part extends along direction B, and the main part
  • the length extending in direction B is greater than the length of the secondary portion extending in other directions.
  • “A extends along direction B” means "the main body part of A extends along direction B".
  • the second direction Y may be a direction from the display area to the binding area, and the opposite direction of the second direction Y may be a direction from the binding area to the display area.
  • the following is an exemplary description through the preparation process of the display substrate.
  • the "patterning process" mentioned in this disclosure includes processes such as coating of photoresist, mask exposure, development, etching, and stripping of photoresist for metal materials, inorganic materials, or transparent conductive materials.
  • organic materials it includes Processes such as coating of organic materials, mask exposure and development.
  • Deposition can use any one or more of sputtering, evaporation, and chemical vapor deposition.
  • Coating can use any one or more of spraying, spin coating, and inkjet printing.
  • Etching can use dry etching and wet etching. Any one or more of them are not limited by this disclosure.
  • Thin film refers to a thin film produced by depositing, coating or other processes of a certain material on a substrate. If the "thin film” does not require a patterning process during the entire production process, the “thin film” can also be called a “layer.” If the "thin film” requires a patterning process during the entire production process, it will be called a “thin film” before the patterning process and a “layer” after the patterning process. The “layer” after the patterning process contains at least one "pattern”. “A and B are arranged on the same layer” mentioned in this disclosure means that A and B are formed simultaneously through the same patterning process, and the “thickness” of the film layer is the size of the film layer in the direction perpendicular to the display substrate.
  • the orthographic projection of B is within the range of the orthographic projection of A
  • the orthographic projection of A includes the orthographic projection of B means that the boundary of the orthographic projection of B falls within the orthographic projection of A. within the bounds of A, or the bounds of the orthographic projection of A overlap with the bounds of the orthographic projection of B.
  • the preparation process of the display substrate may include the following operations.
  • the substrate may be a flexible substrate, or may be a rigid substrate.
  • the rigid substrate may include, but is not limited to, one or more of glass and quartz
  • the flexible substrate may be, but is not limited to, polyethylene terephthalate, ethylene terephthalate, polyether ether ketone, One or more of polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.
  • the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked on a glass carrier.
  • the first and second flexible material layers can be made of polyimide (PI), polyethylene terephthalate (PET) or surface-treated polymer soft film.
  • the first and second inorganic materials The material of the layer can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., used to improve the water and oxygen resistance of the substrate.
  • the first and second inorganic material layers are also called barrier layers.
  • the materials of the semiconductor layer Amorphous silicon (a-si) can be used.
  • the preparation process may include: first coating a layer of polyimide on a glass substrate, and then curing to form a film.
  • first flexible (PI1) layer Form a first flexible (PI1) layer; then deposit a barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible layer; then deposit a layer of amorphous silicon on the first barrier layer Thin film to form an amorphous silicon (a-si) layer covering the first barrier layer; then apply a layer of polyimide on the amorphous silicon layer, and solidify the film to form a second flexible (PI2) layer; then Deposit a barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, completing the preparation of the substrate.
  • forming the first semiconductor layer pattern may include: sequentially depositing a first insulating film and a first semiconductor film on the substrate, patterning the first semiconductor film through a patterning process, and forming a first semiconductor film covering the substrate.
  • the insulating layer, and the first semiconductor layer pattern disposed on the first insulating layer, are shown in FIG. 8 .
  • the first semiconductor layer pattern of each sub-pixel may include at least the third active layer 13 of the third transistor T3 to the seventh active layer 17 of the seventh transistor T7 , and the third active layer 13
  • the seventh active layer 17 is an integral structure connected to each other.
  • the sixth active layer 16 may be located on one side of the third active layer 13 in this sub-pixel, and the fourth active layer 14 and the fifth active layer 15 may be located on The other side of the third active layer 13 in this sub-pixel.
  • the fourth active layer 14 in the i-th row of sub-pixels may be located on one side of the third active layer 13 in the current sub-pixel in the second direction Y (ie, the side close to the display area boundary BD).
  • the third active layer 13 may be in an inverted " ⁇ " shape, and the fourth to seventh active layers 14 to 17 may be in an "I" shape.
  • the active layer of each transistor may include a first region, a second region, and a channel region between the first region and the second region.
  • the first region 13-1 of the third active layer 13 may simultaneously serve as the second region 14-2 of the fourth active layer 14 and the second region 15-2 of the fifth active layer 15.
  • the second region 13-2 of the third active layer 13 can simultaneously serve as the first region 16-1 of the sixth active layer 16, and the second region 16-2 of the sixth active layer 16 can simultaneously serve as the seventh active layer 16.
  • the second area 17-2 of the source layer 17, the first area 14-1 of the fourth active layer 14, the first area 15-1 of the fifth active layer 15, and the first area 17 of the seventh active layer 17 -1 can be set individually.
  • the first regions 15 - 1 of the fifth active layer 15 in two adjacent sub-pixels may be connected to each other.
  • the first area 15-1 of the fifth active layer 15 in the N-2th column and the first area 15-1 of the fifth active layer 15 in the N-1th column are connected to each other, and the fifth active layer 15 in the N-th column is connected to each other.
  • the first area 15-1 of the active layer 15 and the first area 15-1 of the fifth active layer 15 in the N+1th column are connected to each other, and the first area 15-1 of the fifth active layer 15 in the N+2th column is connected to each other.
  • 15-1 and the first area 15-1 of the fifth active layer 15 of the N+3th column are connected to each other.
  • the first region of the fifth active layer in each sub-pixel is configured to be connected to the subsequently formed first power supply line, by connecting the first region of the fifth active layer of the adjacent sub-pixel.
  • the regions form an interconnected integrated structure, which can ensure that the first pole of the fifth transistor T5 of adjacent sub-pixels has the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.
  • the first semiconductor layer may be made of polysilicon (p-Si), that is, the first to sixth transistors are LTPS thin film transistors.
  • patterning the first semiconductor film through a patterning process may include: first forming an amorphous silicon (a-si) film on the first insulating film, and performing dehydrogenation treatment on the amorphous silicon film , the dehydrogenated amorphous silicon film is crystallized to form a polycrystalline silicon film. Subsequently, the polysilicon film is patterned to form a first semiconductor layer pattern.
  • forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on the substrate on which the foregoing pattern is formed, patterning the first conductive film through a patterning process, and forming The second insulating layer covering the first semiconductor layer pattern and the first conductive layer pattern disposed on the second insulating layer are shown in Figures 9a and 9b.
  • Figure 9b is a schematic plan view of the first conductive layer in Figure 9a.
  • the first conductive layer may be referred to as a first gate metal (GATE1) layer.
  • the first conductive layer pattern of each sub-pixel at least includes: a first scanning signal line 21, a light emitting control line 22, a third scanning signal line 23, and a first plate 24 of a storage capacitor.
  • the shape of the first plate 24 may be a rectangle, and the corners of the rectangle may be chamfered.
  • the orthographic projections of the layers on the substrate at least partially overlap.
  • the first plate 24 may simultaneously serve as a plate of the storage capacitor and a gate electrode of the third transistor T3.
  • the shape of the first scanning signal line 21 may be a polyline shape with the main part extending along the first direction
  • the area where the first scanning signal line 21 overlaps with the seventh active layer of this sub-pixel serves as the area of the seventh transistor T7. gate electrode.
  • the first scanning signal line 21 in the i-th row of sub-pixels may be provided in the i-1-th row of sub-pixels.
  • the shape of the light-emitting control line 22 may be a line shape with the main body extending along the first direction X, and the light-emitting control line 22 in the i-th row of sub-pixels may be located in the second direction Y of the first plate 24
  • the light emission control line 22 overlaps with the fifth active layer of this sub-pixel.
  • the region serves as the gate electrode of the fifth transistor T5, and the region where the light emission control line 22 overlaps with the sixth active layer of this sub-pixel serves as the gate electrode of the sixth transistor T6.
  • the shape of the third scanning signal line 23 may be a polyline shape with the main part extending along the first direction On one side of the plate 24 in the second direction Y (that is, the side close to the display area boundary BD), the area where the third scanning signal line 23 overlaps with the fourth active layer of this sub-pixel serves as the gate electrode of the fourth transistor T4.
  • the third scanning signal line 23 in the i-1th row of sub-pixels may serve as the first scanning signal line 21 in the i-th row of sub-pixels, that is, the third scanning signal line in the i-1th row.
  • 23 is an integral structure with the first scanning signal line 21 in the i-th row.
  • the first scanning signal line 21 , the lighting control line 22 and the third scanning signal line 23 may be designed with unequal widths.
  • the first scanning signal line 21 , the lighting control line 22 and the third scanning signal line 23 The width is the size in the second direction Y, which not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between signal lines, which is not limited in this disclosure.
  • the first scanning signal line 21 and the third scanning signal line 23 may include an area overlapping the first semiconductor layer and an area not overlapping the first semiconductor layer.
  • the width of the first scanning signal line 21 and the third scanning signal line 23 may be smaller than the width of the first scanning signal line 21 and the third scanning signal line 23 in a region that does not overlap with the first semiconductor layer.
  • the width LS1 of the first and third scanning signal lines 21 and 23 in the overlapping area with the first semiconductor layer may be approximately 3.6 ⁇ m to 4.0 ⁇ m.
  • the width LS1 may be approximately 3.8 ⁇ m.
  • the light emission control line 22 may include an area overlapping the first semiconductor layer and an area not overlapping the first semiconductor layer, and the width of the first scanning signal line 21 in the area overlapping the first semiconductor layer may be It is greater than the width of the first scanning signal line 21 in the area that does not overlap with the first semiconductor layer.
  • the width LEM of the first scanning signal line 21 in a region that does not overlap the first semiconductor layer may be approximately 1.8 ⁇ m to 2.2 ⁇ m.
  • the width LEM may be approximately 2.0 ⁇ m.
  • the first conductive layer can be used as a shield to perform a conductive process on the first semiconductor layer, and the first semiconductor layer in the area blocked by the first conductive layer forms a third transistor.
  • the channel area of T3 to the seventh transistor T7 and the first semiconductor layer in the area not blocked by the first conductive layer are conductive, that is, the first and second areas of the third transistor T3 to the seventh active layer are all conductive. change.
  • forming the second conductive layer pattern may include: sequentially depositing a third insulating film and a second conductive film on the substrate on which the foregoing pattern is formed, and patterning the second conductive film using a patterning process to form The third insulating layer covering the first conductive layer, and the second conductive layer pattern disposed on the third insulating layer, are shown in Figures 10a and 10b.
  • Figure 10b is a schematic plan view of the second conductive layer in Figure 10a.
  • the second conductive layer may be referred to as a second gate metal (GATE2) layer.
  • GATE2 second gate metal
  • the second conductive layer pattern of each sub-pixel at least includes: a first initial signal line 31, a second scanning signal line 32, a fourth scanning signal line 33, and a second plate 34 of a storage capacitor.
  • the outline of the second electrode plate 34 may be rectangular, and the corners of the rectangular shape may be chamfered.
  • the orthographic projection of the second electrode plate 34 on the base is consistent with the orthographic projection of the first electrode plate 24 on the base.
  • the orthographic projections at least partially overlap, and the second plate 34 can serve as another plate of the storage capacitor.
  • the first plate 24 and the second plate 34 constitute the storage capacitor of the pixel driving circuit.
  • the second electrode plate 34 is provided with an opening 35 .
  • the shape of the opening 35 may be rectangular and may be located in the middle of the second electrode plate 34 , so that the second electrode plate 34 forms an annular structure.
  • the opening 35 exposes the third insulating layer covering the first electrode plate 24 , and the orthographic projection of the first electrode plate 24 on the substrate includes the orthographic projection of the opening 35 on the substrate.
  • the opening 35 is configured to accommodate a subsequently formed first via hole.
  • the first via hole is located within the opening 35 and exposes the first plate 24 so that the subsequently formed second transistor T1 can The pole is connected to the first pole plate 24 .
  • the second plates 34 in two adjacent sub-pixels in one pixel row may be connected to each other.
  • the second pole plate 34 in the N-2th column and the second pole plate 34 in the N-1th column may be connected to each other through the first connecting strip 34 .
  • the second pole plate 34 in the Nth column and the second pole plate 34 in the N+1th column are connected to each other through the second connecting strip 35.
  • the second pole plate 34 in the N+2nd column and the second pole plate 34 in the N+3th column are connected to each other through the second connecting strip 35 .
  • the second plate 34 in each sub-pixel is connected to the subsequently formed first power line, by forming the second plates 34 of adjacent sub-pixels into an integrated structure connected to each other, the integrated structure
  • the second electrode plate can be reused as a power signal line, which can ensure that multiple second electrode plates in a pixel row have the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display of the display substrate. Effect.
  • the shape of the first initial signal line 31 may be a straight line with the main part extending along the first direction One side of the electrode plate 34 in the second direction Y (that is, the side close to the display area boundary BD).
  • the width LIN1 of the first initial signal line 31 may be approximately 1.8 ⁇ m to 2.2 ⁇ m.
  • the width of the first initial signal line 31 may be approximately 2.0 ⁇ m.
  • the first initial signal line 31 of the M-th pixel row may form a pixel driving circuit boundary, and the distance L between the first initial signal line 31 and the display area boundary BD may be approximately 6 ⁇ m to 10 ⁇ m.
  • the distance L may be approximately 7.99 ⁇ m.
  • the shape of the second scanning signal line 32 may be a polyline shape with the main part extending along the first direction On one side of the electrode plate 34 in the second direction Y (that is, the side close to the display area boundary BD), the second scanning signal line 32 may be located between the first initial signal line 31 and the second electrode plate 34 .
  • the second scanning signal line 32 may be located between the first initial signal line 31 and the third scanning signal line 23 .
  • the shape of the fourth scanning signal line 33 may be a line shape with the main part extending along the first direction On one side of the electrode plate 34 in the second direction Y (that is, the side close to the display area boundary BD), the fourth scanning signal line 33 may be located between the second scanning signal line 32 and the second electrode plate 34 .
  • the fourth scanning signal line 33 may be located between the third scanning signal line 23 and the second plate 34 .
  • the second scanning signal line 32 and the fourth scanning signal line 33 may be designed with unequal widths, and the widths of the second scanning signal line 32 and the fourth scanning signal line 33 are the size in the second direction Y, This not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between signal lines, which is not limited in this disclosure.
  • the second scanning signal line 32 may include an area that overlaps with a subsequently formed second semiconductor layer and an area that does not overlap with the second semiconductor layer.
  • the second scanning signal line 32 of the area that overlaps with the second semiconductor layer The width of the line 32 may be greater than the width of the second scanning signal line 32 in a region that does not overlap with the second semiconductor layer.
  • the width LS2 of the second scanning signal line 32 in a region that does not overlap the second semiconductor layer may be approximately 2.2 ⁇ m to 2.6 ⁇ m.
  • the width LS2 may be approximately 2.4 ⁇ m.
  • the fourth scanning signal line 33 may include an area overlapping with a subsequently formed second semiconductor layer and an area not overlapping with the second semiconductor layer.
  • the fourth scanning signal line 33 may include an area overlapping with the second semiconductor layer.
  • the width of the line 33 may be greater than the width of the fourth scanning signal line 33 in a region that does not overlap with the second semiconductor layer.
  • the width LS3 of the fourth scanning signal line 33 in the region not overlapping the second semiconductor layer may be approximately 1.8 ⁇ m to 2.2 ⁇ m.
  • the width LS3 may be approximately 2.0 ⁇ m.
  • forming the second semiconductor layer pattern may include: sequentially depositing a fourth insulating film and a second semiconductor film on the substrate on which the foregoing pattern is formed, patterning the second semiconductor film through a patterning process, and forming The fourth insulating layer covering the base, and the second semiconductor layer pattern disposed on the fourth insulating layer, are shown in Figures 11a and 11b.
  • Figure 11b is a schematic plan view of the second semiconductor layer in Figure 11a.
  • the second semiconductor layer pattern of each sub-pixel includes at least: a first active layer 11 of the first transistor T1 and a second active layer 12 of the second transistor T2.
  • the shape of the first active layer 11 may be an "I" shape, and the orthographic projection of the first active layer 11 on the substrate at least partially intersects the orthographic projection of the second scanning signal line 32 on the substrate. Overlapping, the area where the second scanning signal line 32 overlaps with the first active layer 11 of this sub-pixel serves as the gate electrode of the first transistor T1.
  • the first area 11 - 1 of the first active layer 11 may be located on one side of the second scanning signal line 32 in the second direction Y (ie, the side close to the display area boundary BD).
  • the second region 11 - 2 of the source layer 11 may be located on a side opposite to the second direction Y of the second scanning signal line 32 (ie, a side away from the display area boundary BD).
  • the shape of the second active layer 12 may be in an "I" shape, and the orthographic projection of the second active layer 12 on the substrate at least partially intersects the orthographic projection of the fourth scanning signal line 33 on the substrate. Overlapping, the area where the fourth scanning signal line 33 overlaps with the second active layer 12 of this sub-pixel serves as the gate electrode of the second transistor T2.
  • the first region 12-1 of the second active layer 12 may be located on one side of the fourth scanning signal line 33 in the second direction Y (ie, the side close to the display area boundary BD), and the second The second region 12 - 2 of the source layer 12 may be located on a side opposite to the second direction Y of the fourth scanning signal line 33 (ie, a side away from the display area boundary BD).
  • the second region 11 - 2 of the first active layer 11 may serve as the first region 12 - 1 of the second active layer 12 , that is, the second region 11 - 2 of the first active layer 11
  • the first region 12 - 1 of the second active layer 12 is an integral structure connected to each other, and may be located between the second scanning signal line 32 and the fourth scanning signal line 33 .
  • the orthographic projection of the second area 11-2 of the first active layer 11 and the first area 12-1 of the second active layer 12 of the integrated structure on the substrate in the i-th row sub-pixel is equal to
  • the orthographic projection of the third scanning signal line 23 on the substrate in the i-th row of sub-pixels at least partially overlaps, and the second area 11-2 and the second integrated structure of the first active layer 11 in the i-1-th row of sub-pixels
  • the orthographic projection of the first region 12-1 of the active layer 12 on the substrate is the same as the third scanning signal line 23 in the i-1th row sub-pixel (ie, the first scanning signal line 21 in the i-th row sub-pixel) on the substrate. Orthographic projections on at least partially overlap.
  • the second semiconductor layer may adopt an oxide, that is, the first transistor T1 and the second transistor T2 are oxide transistors.
  • the second semiconductor film may be indium gallium zinc oxide (IGZO), and the electron mobility of indium gallium zinc oxide (IGZO) is higher than that of amorphous silicon.
  • forming the fifth insulating layer pattern may include: depositing a fifth insulating film on the substrate on which the foregoing pattern is formed, patterning the fifth insulating film using a patterning process, and forming a pattern covering the second semiconductor layer.
  • the fifth insulating layer has a plurality of via holes, as shown in Figure 12.
  • the plurality of via holes of each sub-pixel at least include: a first via hole V1, a second via hole V2, a third via hole V3, a fourth via hole V4, a fifth via hole V5, a sixth via hole V5, and a third via hole V3.
  • the orthographic projection of the first via hole V1 on the substrate is within the range of the orthographic projection of the opening 35 on the substrate, and the fifth insulating layer, the fourth insulating layer and the third insulating layer in the first via hole V1
  • the three insulating layers are etched away, exposing the surface of the first electrode plate 24 .
  • the first via hole V1 is configured so that the second electrode of the subsequently formed first transistor T1 is connected to the first plate 24 through the via hole.
  • the second via hole V2 is located within the range of the orthographic projection of the second plate 34 on the substrate, and the fifth insulating layer and the fourth insulating layer in the second via hole V2 are etched away, The surface of the second electrode plate 34 is exposed.
  • the second via hole V2 is configured so that the first electrode of the subsequently formed fifth transistor T5 is connected to the second electrode plate 34 through the via hole.
  • the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the first region of the fifth active layer on the substrate, and the fifth insulating layer in the third via hole V3 , the fourth insulating layer, the third insulating layer and the second insulating layer are etched away to expose the surface of the first region of the fifth active layer, and the third via V3 is configured to enable the subsequently formed fifth transistor T5
  • the first pole is connected to the first region of the fifth active layer through the via hole.
  • the orthographic projection of the fourth via hole V4 on the substrate is located within the range of the orthographic projection of the second region of the sixth active layer on the substrate, and the fifth insulating layer in the fourth via hole V4 , the fourth insulating layer, the third insulating layer and the second insulating layer are etched away, exposing the surface of the second area of the sixth active layer (also the second area of the seventh active layer), and the fourth via hole V4 is configured to connect the second electrode of the subsequently formed sixth transistor T6 (the second electrode of the seventh transistor T7) to the second region of the sixth active layer through the via hole.
  • the orthographic projection of the fifth via hole V5 on the substrate is located within the range of the orthographic projection of the first region of the fourth active layer on the substrate, and the fifth insulating layer in the fifth via hole V5 , the fourth insulating layer, the third insulating layer and the second insulating layer are etched away to expose the surface of the first region of the fourth active layer, and the fifth via V5 is configured to enable the subsequently formed fourth transistor T4
  • the first pole is connected to the first region of the fourth active layer through the via hole.
  • the orthographic projection of the sixth via hole V6 on the substrate is located within the range of the orthographic projection of the second region of the third active layer on the substrate, and the fifth insulating layer in the sixth via hole V6 , the fourth insulating layer, the third insulating layer and the second insulating layer are etched away, exposing the surface of the second area of the third active layer (also the first area of the sixth active layer), and the sixth via hole V6 is configured to connect the second electrode of the subsequently formed third transistor T3 (the first electrode of the sixth transistor T6) to the second region of the third active layer through the via hole.
  • the orthographic projection of the seventh via hole V7 on the substrate is within the range of the orthographic projection of the first region of the seventh active layer on the substrate, and the fifth insulating layer in the seventh via hole V7 , the fourth insulating layer, the third insulating layer and the second insulating layer are etched away, exposing the surface of the first region of the seventh active layer, and the seventh via V7 is configured to enable the subsequently formed seventh transistor T7
  • the first pole is connected to the first region of the seventh active layer through the via hole.
  • the orthographic projection of the eighth via hole V8 on the substrate is within the range of the orthographic projection of the first region of the first active layer on the substrate, and the fifth insulating layer in the eighth via hole V8 , the fourth insulating layer, the third insulating layer and the second insulating layer are etched away to expose the surface of the first region of the first active layer, and the eighth via V8 is configured to enable the subsequently formed first transistor T1
  • the first pole is connected to the first region of the first active layer through the via hole.
  • the orthographic projection of the ninth via hole V9 on the substrate is located within the range of the orthographic projection of the second region of the second active layer on the substrate, and the fifth insulating layer in the ninth via hole V9 is etched away to expose the surface of the second region of the second active layer, and the ninth via V9 is configured to allow the second electrode of the subsequently formed second transistor T2 to pass through the via hole and the second active layer. Second zone connection.
  • the orthographic projection of the tenth via hole V10 on the substrate is within the range of the orthographic projection of the second region of the first active layer on the substrate, and the fifth insulating layer in the tenth via hole V10 , the fourth insulating layer, the third insulating layer and the second insulating layer are etched away, exposing the surface of the second area of the first active layer (also the first area of the second active layer), and the tenth via hole V10 is configured so that the second electrode of the subsequently formed first transistor T1 (also the first electrode of the second transistor T2) is connected to the second region of the first active layer through the via hole.
  • the orthographic projection of the eleventh via hole V11 on the substrate is within the range of the orthographic projection of the first initial signal line 31 on the substrate, and the fifth insulating layer in the eleventh via hole V11 and The fourth insulating layer is etched away, exposing the surface of the first initial signal line 31, and the eleventh via hole V11 is configured to allow the first pole of the subsequently formed first transistor T1 to pass through the via hole and the first initial signal Line 31 is connected.
  • forming the third conductive layer may include: depositing a third conductive film on the substrate on which the foregoing pattern is formed, patterning the third conductive film using a patterning process, and forming a layer disposed on the fifth insulating layer.
  • the third conductive layer is as shown in Figures 13a and 13b.
  • Figure 13b is a schematic plan view of the third conductive layer in Figure 13a.
  • the third conductive layer may be referred to as a third gate metal (GATE3) layer.
  • the third conductive layer of each sub-pixel at least includes: a first connection electrode 51, a second connection electrode 52, a third connection electrode 53, a fourth connection electrode 54, a fifth connection electrode 55, a sixth The electrode 56 and the second initial signal line 57 are connected.
  • the shape of the first connection electrode 51 may be a polygonal shape with the main body extending along the second direction Y.
  • the first end of the first connection electrode 51 passes through the first via hole V1 and the first plate 24 connection, after the second end of the first connection electrode 51 extends along the second direction Y, it is connected to the second area of the first active layer (also the first area of the second active layer) through the tenth via hole V10,
  • the first electrode plate 24, the second electrode of the first transistor T1 and the first electrode of the second transistor T2 are made to have the same potential.
  • the first connection electrode 51 may simultaneously serve as the second electrode of the first transistor T1 and the first electrode (second node N2) of the second transistor T2.
  • the shape of the second connection electrode 52 may be a strip shape extending along the first direction The first area is connected, and the second end of the second connection electrode 52 is connected to the first initial signal line 31 through the eleventh via hole V11, so that the first initial voltage transmitted by the first initial signal line 31 is written into the first terminal of the first transistor T1.
  • the second connection electrode 52 may serve as the first electrode of the first transistor T1.
  • the second connection electrode 52 of the N-1th column and the second connection electrode 52 of the Nth column may be an integral structure connected to each other, and the second connection electrode 52 of the N+1th column may be an integral structure connected to each other.
  • the connection electrode 52 and the second connection electrode 52 of the N+2th column may be an integral structure connected to each other.
  • the shape of the third connection electrode 53 may be a rectangular shape, and the third connection electrode 53 is connected to the first region of the fourth active layer through the fifth via hole V5.
  • the third connection electrode 53 may serve as the first electrode of the fourth transistor T4 and be configured to be connected to a subsequently formed data signal line.
  • the shape of the fourth connection electrode 54 may be a "Y" shape.
  • the first end of the fourth connection electrode 54 is connected to the second plate 34 through the second via hole V2.
  • the second end is connected to the first region of the fifth active layer through the third via V3, thereby realizing that the first electrode of the fifth transistor T5 in the sub-pixel and the second electrode plate 34 of the storage capacitor have the same potential.
  • the fourth connection electrode 54 may serve as the first electrode of the fifth transistor T5.
  • the orthographic projection of the fourth connection electrode 54 on the substrate at least partially overlaps the orthographic projection of the second region of the seventh active layer on the substrate.
  • the fourth connection electrode 54 of the N-2th column and the fourth connection electrode 54 of the N-1th column may be an integral structure connected to each other, and the fourth connection electrode 54 of the N-th column may be an integral structure connected to each other.
  • the connection electrode 54 and the fourth connection electrode 54 in the N+1th column may be an integral structure connected to each other, and the fourth connection electrode 54 in the N+2nd column and the fourth connection electrode 54 in the N+3th column may be connected to each other. integrated structure.
  • the fourth connection electrode 54 in each sub-pixel is connected to the first power supply line formed subsequently, by forming the fourth connection electrodes 54 of adjacent sub-pixels into an integral structure connected to each other, it is possible to ensure that the phase is connected to each other.
  • the fourth connection electrode 54 of adjacent sub-pixels has the same potential, so that the first electrode of the fifth transistor T5 in the adjacent sub-pixel has the same potential, and the second plate 34 of the storage capacitor in the adjacent sub-pixel has the same potential. potential, which is conducive to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.
  • the shape of the fifth connection electrode 55 may be a rectangular shape, and the first end of the fifth connection electrode 55 communicates with the second region of the third active layer (also the sixth active layer) through the sixth via hole V6.
  • the second end of the fifth connection electrode 55 is connected to the second area of the second active layer through the ninth via hole V9.
  • the fifth connection electrode 55 may simultaneously serve as the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode (third node N3) of the sixth transistor T6.
  • the shape of the sixth connection electrode 56 may be a rectangular shape, and the sixth connection electrode 56 communicates with the second area of the sixth active layer (also the second area of the seventh active layer) through the fourth via hole V4. area) connection.
  • the sixth connection electrode 56 may serve as the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 at the same time, and the sixth connection electrode 56 is configured to be connected to a subsequently formed anode connection electrode.
  • the second initial signal line 57 may be in the shape of a polygonal line with the main body portion extending along the first direction X.
  • the second initial signal line 57 may be disposed on a side of the storage capacitor away from the display area boundary BD.
  • the initial signal line 57 is connected to the first areas of the plurality of seventh active layers through the plurality of seventh vias V7 in a pixel row, and writes the second initial voltage into the plurality of seventh transistors T7 in the pixel row.
  • the second initial signal line 57 since the second initial signal line 57 is connected to the first areas of all seventh active layers in one pixel row, it can be ensured that the first poles of all seventh transistors T7 in one pixel row have the same The potential is conducive to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.
  • the width LIN2 of the second initial signal line 57 may be approximately 1.9 ⁇ m to 2.3 ⁇ m.
  • the width of the second initial signal line 57 may be approximately 2.1 ⁇ m.
  • the second initial signal line 57 of the i-th pixel row may be located in the area where the i-1-th pixel row is located.
  • forming the first flat layer pattern may include: coating a first flat film on the substrate on which the foregoing pattern is formed, patterning the first flat film using a patterning process, and forming a covering third conductive layer.
  • the first flat layer of the pattern is provided with multiple via holes, as shown in Figure 14.
  • the plurality of via holes in each sub-pixel includes at least: a twenty-first via hole V21, a twenty-second via hole V22, and a twenty-third via hole V23.
  • the orthographic projection of the twenty-first via hole V21 on the substrate is within the range of the orthographic projection of the third connection electrode 53 on the substrate, and the first flat layer in the twenty-first via hole V21 is etched away to expose the surface of the third connection electrode 53 , and the twenty-first via hole V21 is configured so that the subsequently formed data signal line is connected to the third connection electrode 53 through the via hole.
  • the orthographic projection of the twenty-second via hole V22 on the substrate is within the range of the orthographic projection of the first sub-electrode 54-1 of the fourth connection electrode 54 on the substrate.
  • the twenty-second via hole V22 is The first flat layer in the hole V22 is etched away, exposing the surface of the first sub-electrode 54-1, and the twenty-second via hole V22 is configured to connect the subsequently formed first power line to the fourth via hole. Electrode 54 is connected.
  • the orthographic projection of the twenty-third via hole V23 on the substrate is within the range of the orthographic projection of the sixth connection electrode 56 on the substrate, and the first flat layer in the twenty-third via hole V23 is etched away to expose the surface of the sixth connection electrode 56 , and the twenty-third via hole V232 is configured to connect the subsequently formed anode connection electrode to the sixth connection electrode 56 .
  • forming the fourth conductive layer may include: depositing a fourth conductive film on the substrate on which the foregoing pattern is formed, patterning the fourth conductive film using a patterning process, and forming a layer disposed on the first flat layer.
  • the fourth conductive layer is as shown in Figures 15a and 15b.
  • Figure 15b is a schematic plan view of the fourth conductive layer in Figure 15a.
  • the fourth conductive layer may be referred to as a first source-drain metal (SD1) layer.
  • the fourth conductive layer of each sub-pixel includes at least: a data signal line 61 , a first power supply line 62 and an anode connection electrode 63 .
  • the shape of the data signal line 61 may be a straight line shape with the main body extending along the second direction Y, and the data signal line 61 is connected to the third connection electrode 53 through the twenty-first via hole V21. Since the third connection electrode 53 is connected to the first area of the fourth active layer through the via hole, the connection between the data signal line 61 and the first electrode of the fourth transistor T4 is realized, and the data signal is written into the fourth transistor T4 The first pole.
  • the shape of the first power line 62 may be a polygonal shape with a main body portion extending along the second direction Y, and the first power line 62 is connected to the fourth connection electrode 54 through the twenty-second via hole V22. Since the fourth connection electrode 54 is connected to the second plate 34 and the first area of the fifth active layer through via holes respectively, the first power supply line 62 is connected to the second plate 34 and the fifth transistor T5. The power signal is written into the first pole of the fifth transistor T5.
  • the first power lines 62 in two adjacent sub-pixels in one pixel row may be an integral structure connected to each other.
  • the first power line 62 in the N-1th column and the first power line 62 in the Nth column are connected to each other, and the first power line 62 in the N+1th column and the first power line 62 in the N+2th column are connected to each other. connect.
  • by forming the first power lines 62 of adjacent sub-pixels into an integrated structure connected to each other it can be ensured that the first power lines 62 of adjacent sub-pixels have the same potential, which is beneficial to improving the uniformity of the panel. , to avoid poor display of the display substrate and ensure the display effect of the display substrate.
  • the first power supply line 62 may be a polygonal line of unequal width, which not only facilitates the layout of the pixel structure, but also reduces parasitic capacitance between the first power supply line and the data signal line.
  • the orthographic projection of the first power line 62 on the substrate may at least partially overlap with the orthographic projection of the first connection electrode 51 on the substrate, and the orthographic projection of the first power line 62 on the substrate may overlap with the orthographic projection of the first power line 62 on the substrate.
  • the orthographic projections of the two connection electrodes 52 on the substrate at least partially overlap, so that the first power line 62 can serve as a shielding electrode, which can effectively shield the impact of data voltage jumps on key nodes in the pixel driving circuit and avoid the impact of data voltage jumps.
  • the potential of key nodes of the pixel drive circuit improves the display effect.
  • the shape of the anode connection electrode 63 may be a rectangular shape, the anode connection electrode 63 is connected to the sixth connection electrode 56 through the twenty-third via hole V23, and the anode connection electrode 63 is configured to connect with the subsequently formed anode. connect.
  • forming the second flat layer pattern may include: coating a second flat film on the substrate on which the foregoing pattern is formed, patterning the second flat film using a patterning process, and forming a covering fourth conductive layer.
  • the second flat layer of the pattern is provided with multiple via holes, as shown in Figure 16.
  • the via hole of each sub-pixel includes at least the thirty-first via hole V31.
  • the orthographic projection of the thirty-first via hole V31 on the substrate is within the range of the orthographic projection of the anode connection electrode 63 on the substrate, and the second flat layer in the thirty-first via hole V31 is Removed, the surface of the anode connection electrode 63 is exposed, and the thirty-first via hole V31 is configured to allow a subsequently formed anode to be connected to the anode connection electrode 63 through the via hole.
  • the driver circuit layer is prepared on the substrate.
  • the driving circuit layer may include a plurality of sub-pixels, and each sub-pixel may include a pixel driving circuit, and a first scanning signal line, a second scanning signal line, and a third scanning signal line connected to the pixel driving circuit. line, a light-emitting control line, a data signal line, a first power line, a first initial signal line and a second initial signal line.
  • the driving circuit layer may include a first insulating layer, a first semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, and a first insulating layer. layer, a fourth insulating layer, a second semiconductor layer, a fifth insulating layer, a third conductive layer, a first planar layer, a fourth conductive layer and a second planar layer.
  • the first semiconductor layer at least includes active layers of the third to seventh transistors
  • the first conductive layer includes at least the gate electrodes of the third to seventh transistors and the first plate of the storage capacitor
  • the second conductive layer includes at least a third The gate electrodes of one transistor to the second transistor and the second plate of the storage capacitor
  • the second semiconductor layer at least includes the active layer of the first transistor to the second transistor
  • the third conductive layer at least includes the first electrodes of a plurality of transistors and
  • the second pole and the fourth conductive layer at least include data signal lines and first power lines.
  • the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer may adopt metal materials, such as silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo). ), or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), which can be a single-layer structure or a multi-layer composite structure, such as Mo/Cu/Mo wait.
  • metal materials such as silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo).
  • alloy materials of the above metals such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), which can be a single-layer structure or a multi-layer composite structure, such as Mo/Cu/Mo wait.
  • the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer and the fifth insulating layer may be made of any one of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON).
  • silicon oxide SiOx
  • SiNx silicon nitride
  • SiON silicon oxynitride
  • the first insulating layer may be called a buffer layer and is used to improve the water and oxygen resistance of the substrate.
  • the second insulating layer, the third insulating layer, the fourth insulating layer and the fifth insulating layer may be called gate insulation (GI).
  • layer, the fifth insulating layer may be called an interlayer insulating (ILD) layer.
  • the first flat layer and the second flat layer may be made of organic materials, such as resin.
  • the pixel driving circuits in two adjacent sub-pixels in a pixel row may be substantially mirror symmetrical with respect to the first center line, which is located between the two adjacent sub-pixels and along the first center line.
  • a straight line extending in direction Y may be provided.
  • the pixel driving circuit of the N-1th column and the pixel driving circuit of the Nth column may be mirror symmetrical with respect to the first center line.
  • the pixel driving circuit of the Nth column and the pixel driving circuit of the N+1th column may be mirror symmetrical with respect to the first center line.
  • the pixel driving circuits in two adjacent sub-pixels may be substantially mirror-symmetrical with respect to the first center line and may include any one or more of the following: the first of the two adjacent sub-pixels in a pixel row.
  • a semiconductor layer may be mirror symmetrical with respect to the first center line
  • the first conductive layer in two adjacent sub-pixels in a pixel row may be mirror symmetrical with respect to the first center line
  • the first conductive layer in two adjacent sub-pixels in a pixel row may be mirror symmetrical with respect to the first center line.
  • the two conductive layers may be mirror symmetrical with respect to the first center line.
  • the second semiconductor layer in two adjacent sub-pixels in a pixel row may be mirror symmetrical with respect to the first center line.
  • the second semiconductor layer in two adjacent sub-pixels in a pixel row may be mirror symmetrical with respect to the first center line.
  • the three conductive layers may be mirror symmetrical with respect to the first center line, and the fourth conductive layer in two adjacent sub-pixels in a pixel row may be mirror symmetrical with respect to the first center line.
  • a light-emitting structure layer is prepared on the driving circuit layer.
  • the preparation process of the light-emitting structure layer may include the following operations.
  • Form an anode conductive layer pattern may include: depositing an anode conductive film on the substrate on which the foregoing pattern is formed, patterning the anode conductive film using a patterning process, and forming an anode disposed on the second flat layer.
  • the conductive layer, the anode conductive layer at least includes a plurality of anode patterns, as shown in Figures 17a to 17d.
  • Figure 17a is a schematic diagram of an anode conductive layer pattern formed according to an embodiment of the present disclosure.
  • Figure 17b is the anode conductive layer in Figure 17a.
  • Figure 17c is a schematic plan view of another anode conductive layer pattern formed according to an embodiment of the present disclosure.
  • Figure 17d is a schematic plan view of the anode conductive layer in Figure 17c.
  • the anode conductive layer adopts a single-layer structure, such as indium tin oxide ITO or indium zinc oxide IZO, or may adopt a multi-layer composite structure, such as ITO/Ag/ITO, etc.
  • the plurality of anode patterns may include a first anode 90A of the red light emitting device, a second anode 90B of the blue light emitting device, a third anode 90C of the first green light emitting device, and a third anode 90C of the second green light emitting device.
  • the first anode 90A can be located at the red sub-pixel that emits red light
  • the second anode 90B can be located at the blue sub-pixel that emits blue light
  • the third anode 90C can be located at the first green sub-pixel that emits green light.
  • the fourth anode 90D may be located at the second green sub-pixel that emits green light.
  • the first anode 90A and the second anode 90B may be disposed in sequence along the second direction Y
  • the third anode 90C and the fourth anode 90D may be disposed in sequence along the second direction Y
  • the third anode 90C and the fourth anode 90D may be disposed in sequence along the second direction Y
  • the fourth anode 90D may be disposed on one side of the first anode 90A and the second anode 90B in the first direction X.
  • first anode 90A and the second anode 90B may be disposed in sequence along the first direction X
  • the third anode 90C and the fourth anode 90D may be disposed in sequence along the first direction X
  • third anode 90C and the fourth anode 90D may be Disposed on one side of the first anode 90A and the second anode 90B in the second direction Y.
  • the first anode 90A, the second anode 90B, the third anode 90C and the fourth anode 90D can be connected to the anode connection electrode 63 of the sub-pixel through the thirty-first via hole V31 respectively.
  • One pixel unit The anode shapes and areas of the four sub-pixels can be the same or different.
  • each anode has an edge close to one side of the binding area, and the edge closest to the binding area among the multiple anodes is called the anode boundary 90-1.
  • the display area boundary BD of the disclosed exemplary embodiment is a straight line passing through the anode boundary 90-1 and extending along the first direction X.
  • At least one of the first anode 90A, the second anode 90B, the third anode 90C, and the fourth anode 90D may include an anode body portion and an anode connection portion connected to each other, the anode connection portion passing through the thirtieth A via hole V31 is connected to the anode connection electrode 63 .
  • the first anode 90A may include a first anode body part and a first anode connection part connected to each other, the shape of the first anode body part may be a rectangle, and the corners of the rectangle may be provided with arc shapes. chamfer, the shape of the first anode connection part may be a strip shape extending along the second direction Y, and the first anode connection part is connected to the anode connection electrode 63 through the thirty-first via hole V31.
  • the second anode 90B may include a second anode body part and a second anode connection part connected to each other.
  • the shape of the second anode body part may be a rectangle, and the corners of the rectangle may be provided with arc shapes. chamfer, the shape of the second anode connection part may be a strip shape extending along the second direction Y, and the second anode connection part is connected to the anode connection electrode 63 through the thirty-first via hole V31.
  • the third anode 90C may include a third anode body part and a third anode connection part connected to each other, the shape of the third anode body part may be a rectangle, and the corners of the rectangle may be provided with arc shapes. chamfer, the third anode connection part may be in a strip shape extending along the first direction X, and the third anode connection part is connected to the anode connection electrode 63 through the thirty-first via hole V31.
  • the fourth anode 90D may include a fourth anode body part and a fourth anode connection part connected to each other, the shape of the fourth anode body part may be a rectangle, and the corners of the rectangle may be provided with arc shapes. chamfer, the fourth anode connection part may be in a strip shape extending along the first direction X, and the fourth anode connection part is connected to the anode connection electrode 63 through the thirty-first via hole V31.
  • the subsequent preparation process may include: first forming a pixel definition layer pattern, then using an evaporation or inkjet printing process to form an organic light-emitting layer, then forming a cathode on the organic light-emitting layer, and then forming an encapsulation structure layer.
  • the structural layer may include a stacked first encapsulation layer, a second encapsulation layer and a third encapsulation layer.
  • the first encapsulation layer and the third encapsulation layer may use inorganic materials.
  • the second encapsulation layer may use organic materials.
  • the second encapsulation layer is provided Between the first encapsulation layer and the third encapsulation layer, it can be ensured that external water vapor cannot enter the light-emitting structure layer.
  • forming the pixel definition layer pattern may include: coating a pixel definition film on the substrate on which the foregoing pattern is formed, patterning the pixel definition film using a patterning process, and forming a pixel definition layer covering the anode conductive layer pattern. layer, a plurality of pixel openings 400 are provided on the pixel definition layer, and the pixel definition film in the pixel openings 400 is removed to expose the surface of the anode 90, as shown in Figures 18a and 18b.
  • Figure 18a is formed according to an embodiment of the present disclosure.
  • FIG. 17b is a schematic diagram of another pixel definition layer pattern formed according to an embodiment of the present disclosure.
  • each pixel opening has an edge close to one side of the binding area, and the edge closest to the binding area among the multiple pixel openings is called Pixel opening boundary
  • the display area boundary BD of the exemplary embodiment of the present disclosure may be a straight line passing through the pixel opening boundary and extending along the first direction X.
  • FIG. 19 is a schematic plan view of an existing display substrate, which is a pixel driving circuit structure of the M-1th pixel row and the Mth pixel row in the display area close to the binding area.
  • the layout of the pixel driving circuit in this existing display substrate is as follows: the first transistor T1, the second transistor T2 and the fourth transistor T4 are located on the side of the third transistor T3 of this sub-pixel away from the display area boundary BD, and the fifth transistor T5, The sixth transistor T6 and the seventh transistor T7 are located on the side of the third transistor T3 of this sub-pixel close to the display area boundary BD.
  • the seventh transistor T7 in the sub-pixel of the i-th pixel row is used in the design.
  • the pixel driving circuit of the M-th pixel row (last row) sub-pixel needs to additionally set up the first scanning signal line 21 of the next row to drive the seventh transistor T7 and the second initialization line of the next row that provides the second initial signal.
  • the signal line 57, the additional first scanning signal line 21 and the second initial signal line 57 can only be arranged outside the display area, that is, the additional first scanning signal line 21 and the second initial signal line 57 and other signal lines are located Displays the side of the area boundary BD close to the binding area. Since the pixel driving circuit boundary PD formed by the additionally provided first scanning signal line 21 and the second initial signal line 57 exceeds the display area boundary BD, the binding area can only be set accordingly based on the pixel driving circuit boundary PD. This increases the width of the bottom border. In an exemplary embodiment, the excess distance B between the display area boundary BD and the pixel driving circuit boundary PD is about 20 ⁇ m to 30 ⁇ m. The larger the excess distance B, the larger the lower border.
  • the solution of moving the entire pixel driving circuit upward can be used to adjust the position of the pixel driving circuit boundary so that the display area boundary BD overlaps with the pixel driving circuit boundary PD, in order to realize the connection between the anode and the pixel driving circuit Connection, this processing solution requires changing the position of the anode connection electrode, so that the distance between the anode openings is reduced, which will not only increase signal crosstalk, but also cause short circuit defects.
  • the solution of moving the pixel driving circuit upward as a whole will move the pixel opening of the pixel definition layer upward as a whole, which will reduce the distance between the metal mask (FMM) and the boundary of the display area, resulting in evaporation under existing process conditions.
  • the display area is darkened due to shadows, which poses a greater risk of poor display.
  • the display substrate provided by the exemplary embodiments of the present disclosure can effectively reduce the width of the lower frame by changing the layout of the pixel driving circuit.
  • the first scanning signal line 21, the second scanning signal line 32, the fourth scanning signal line 33, the first initial signal line 31 and the second initial signal line 57 of the sub-pixel in the i-th pixel row are located at the location of the sub-pixel.
  • the storage capacitor 40 is on the side close to the display area boundary BD
  • the light emission control line 22 is located on the side of the storage capacitor 40 of this sub-pixel away from the display area boundary BD
  • the first transistor T1, the second transistor T2 and the fourth transistor T4 are located on the side of this sub-pixel.
  • the third transistor T3 is close to the side of the display area boundary BD, and the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are located on the side of the third transistor T3 of this sub-pixel away from the display area boundary BD, so that the i-th pixel row ( The seventh transistor T7 of the sub-pixel in the current row) is driven by the first scanning signal line 21 of the sub-pixel in the i-1th pixel row (the previous row).
  • the pixel driving circuit of the sub-pixel in the M-th pixel row (the last row) is not only There is no need to set additional signal lines for the next row, and the pixel driving circuit boundary PD can be located within the display area, that is, the pixel driving circuit boundary PD is located on the side of the display area boundary BD away from the binding area.
  • the binding area can not only be set correspondingly based on the display area boundary BD, but also can be set correspondingly based on the pixel driving circuit boundary PD, effectively reducing the width of the lower frame. .
  • the distance L between the display area boundary BD and the pixel driving circuit boundary PD may be approximately 6 ⁇ m to 10 ⁇ m.
  • the distance L may be approximately 7.99 ⁇ m.
  • the display substrate according to the exemplary embodiment of the present disclosure can reduce the width of the lower frame by about 30 ⁇ m to 40 ⁇ m, which is beneficial to realizing a narrow frame. .
  • the pixel driving circuit layout provided by the exemplary embodiments of the present disclosure not only ensures the safe distance between the anode openings and the safe distance between the metal mask and the display area boundary, but also avoids short circuit defects and defects during the evaporation process. It shows the risk of bad display, and can effectively save layout space and help achieve high resolution.
  • the preparation process of the present disclosure can be well compatible with the existing preparation process. The process is simple to realize, easy to implement, has high production efficiency, low production cost and high yield rate.
  • the display substrate of the present disclosure can be applied to other display devices with pixel driving circuits, such as quantum dot displays, etc., and the present disclosure is not limited here.
  • the display substrate includes a display area and a binding area located on one side of the display area.
  • the display area includes M pixel rows, where M is a positive integer greater than 1; at least one pixel row includes A scanning signal line and a plurality of sub-pixels arranged sequentially along the extending direction of the scanning signal line.
  • At least one sub-pixel includes a pixel driving circuit connected to the scanning signal line.
  • the pixel driving circuit at least includes a storage capacitor and a plurality of transistors.
  • the plurality of transistors at least include a first transistor as a first initialization transistor
  • the scan signal line at least includes a second scan signal line
  • the second scan signal line is configured to control the first transistor to turn on or Disconnect;
  • the preparation method includes:
  • a pixel driving circuit and a second scanning signal line are formed in at least one pixel row, and the second scanning signal line is disposed on a side of the storage capacitor close to a display area boundary.
  • the display area boundary is where the display area is close to the display area. Describes the boundary on one side of the binding area.
  • the present disclosure also provides a display device, which includes the aforementioned display substrate.
  • the display device may be: a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function.
  • the embodiments of the present invention are not limited thereto.

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Abstract

一种显示基板及其制备方法、显示装置。显示基板包括显示区域（100）和绑定区域（200），显示区域（100）包括依次设置的M个像素行，至少一个像素行包括扫描信号线和沿着扫描信号线延伸方向依次设置的多个子像素，至少一个子像素包括与扫描信号线连接的像素驱动电路，像素驱动电路至少包括存储电容（40）和作为第一初始化晶体管的第一晶体管（T1），扫描信号线至少包括控制第一晶体管（T1）导通或断开的第二扫描信号线（32）；至少一个像素行中，第二扫描信号线（32）设置在存储电容（40）靠近显示区域边界（BD）的一侧，显示区域边界（BD）是显示区域（100）靠近绑定区域（200）一侧的边缘。

Description

显示基板及其制备方法、显示装置 技术领域
本文涉及但不限于显示技术领域，具体涉及一种显示基板及其制备方法、显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)和量子点发光二极管(Quantum-dot Light Emitting Diodes，简称QLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。随着显示技术的不断发展，以OLED或QLED为发光器件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的柔性显示装置(Flexible Display)已成为目前显示领域的主流产品。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
一方面，本公开提供了一种显示基板，包括显示区域和位于所述显示区域一侧的绑定区域，所述显示区域包括依次设置的M个像素行，M为大于1的正整数；至少一个像素行包括扫描信号线和沿着所述扫描信号线延伸方向依次设置的多个子像素，至少一个子像素包括与所述扫描信号线连接的像素驱动电路，所述像素驱动电路至少包括存储电容和多个晶体管，所述多个晶体管至少包括作为第一初始化晶体管的第一晶体管，所述扫描信号线至少包括第二扫描信号线，所述第二扫描信号线被配置为控制所述第一晶体管导通或断开；至少一个像素行中，所述第二扫描信号线设置在所述存储电容靠近显示区域边界的一侧，所述显示区域边界是所述显示区域靠近所述绑定区域一侧的边缘。
在示例性实施方式中，所述第一晶体管的第一极与第一初始信号线连 接，所述第一初始信号线设置在所述存储电容靠近所述显示区域边界的一侧。
在示例性实施方式中，第M像素行中所述第一初始信号线靠近所述绑定区域一侧的边缘形成像素驱动电路边界。
在示例性实施方式中，所述像素驱动电路边界位于所述显示区域边界远离所述绑定区域的一侧。
在示例性实施方式中，所述像素驱动电路边界与所述显示区域边界之间的距离为6μm至10μm。
在示例性实施方式中，所述多个晶体管还包括作为第二初始化晶体管的第七晶体管，所述扫描信号线还包括第一扫描信号线，所述第一扫描信号线被配置为控制所述第七晶体管导通或断开，所述第一扫描信号线设置在所述存储电容远离所述显示区域边界的一侧。
在示例性实施方式中，所述第七晶体管的第一极与第二初始信号线连接，所述第二初始信号线设置在所述存储电容远离所述显示区域边界的一侧。
在示例性实施方式中，第i像素行中所述第二初始信号线在显示基板上的正投影与第i-1像素行中所述第二扫描信号线在显示基板上的正投影至少部分交叠，i＝2，3，……，M。
在示例性实施方式中，所述多个晶体管还包括作为补偿晶体管的第二晶体管和作为数据写入晶体管的第四晶体管，所述扫描信号线还包括控制所述第四晶体管导通或断开的第三扫描信号线和控制所述补偿晶体管导通或断开的第四扫描信号线，所述第三扫描信号线和第四扫描信号线设置在所述存储电容靠近所述显示区域边界的一侧。
在示例性实施方式中，所述第三扫描信号线设置在所述第四扫描信号线靠近所述显示区域边界的的一侧。
在示例性实施方式中，第i像素行中所述第一扫描信号线与第i-1像素行中所述第三扫描信号线为一体结构，i＝2，3，……，M。
在示例性实施方式中，所述多个晶体管还包括第五晶体管和第六晶体管，所述显示基板还包括发光控制线，所述发光控制线被配置为控制所述第 五晶体管和第六晶体管导通或断开，所述发光控制线设置在所述存储电容远离所述显示区域边界的一侧。
在示例性实施方式中，所述多个晶体管还包括作为补偿晶体管的第二晶体管、作为驱动晶体管的第三晶体管、作为数据写入晶体管的第四晶体管、作为发光晶体管的第五晶体管和第六晶体管、以及作为第二初始化晶体管的第七晶体管；所述第一晶体管、第二晶体管和第四晶体管设置在所述第三晶体管靠近所述显示区域边界的一侧，所述第五晶体管、第六晶体管和第七晶体管设置在所述第三晶体管远离所述显示区域边界的一侧。
在示例性实施方式中，所述第一晶体管和第二晶体管为氧化物晶体管，所述第三晶体管至第七晶体管为低温多晶硅晶体管。
在示例性实施方式中，在垂直于所述显示基板的平面内，所述显示基板包括设置在基底上的驱动电路层和设置在所述驱动电路层远离所述基底一侧的发光结构层；所述驱动电路层包括沿着远离所述基底方向设置的第一半导体层、第一导电层、第二导电层、第二半导体层和第三导电层；所述第一半导体层至少包括多个多晶硅晶体管的有源层，所述第一导电层至少包括第一扫描信号线、第三扫描信号线、多个多晶硅晶体管的栅电极和存储电容的第一极板，所述第二导电层至少包括第二扫描信号线、第四扫描信号线、第一初始信号线、多个氧化物晶体管的栅电极和存储电容的第二极板，所述第二半导体层至少包括多个氧化物晶体管的有源层，所述第三导电层至少包括第二初始信号线。
另一方面，本公开还提供了一种显示装置，包括前述的显示基板。
又一方面，本公开还提供了一种显示基板的制备方法，所述显示基板包括显示区域和位于所述显示区域一侧的绑定区域，所述显示区域包括M个像素行，M为大于1的正整数；至少一个像素行包括扫描信号线和沿着所述扫描信号线延伸方向依次设置的多个子像素，至少一个子像素包括与所述扫描信号线连接的像素驱动电路，所述像素驱动电路至少包括存储电容和多个晶体管，所述多个晶体管至少包括作为第一初始化晶体管的第一晶体管，所述扫描信号线至少包括第二扫描信号线，所述第二扫描信号线被配置为控制所述第一晶体管导通或断开；所述制备方法包括：
在至少一个像素行中形成像素驱动电路和第二扫描信号线，所述第二扫描信号线设置在所述存储电容靠近显示区域边界的一侧，所述显示区域边界是所述显示区域靠近所述绑定区域一侧的边界。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1为一种显示装置的结构示意图；
图2为一种显示基板的结构示意图；
图3为一种显示基板中显示区域的平面结构示意图；
图4为一种显示基板中显示区域的剖面结构示意图；
图5为一种像素驱动电路的等效电路示意图；
图6为一种像素驱动电路的工作时序图；
图7为本公开示例性实施例一种显示基板的平面结构示意图；
图8为本公开实施例形成第一半导体层图案后的示意图；
图9a和图9b为本公开实施例形成第一导电层图案后的示意图；
图10a和图10b为本公开实施例形成第二导电层图案后的示意图；
图11a和图11b为本公开实施例形成第二半导体层图案后的示意图；
图12为本公开实施例形成第五绝缘层图案后的示意图；
图13a和图13b为本公开实施例形成第三导电层图案后的示意图；
图14为本公开实施例形成第一平坦层图案后的示意图；
图15a和图15b为本公开实施例形成第四导电层图案后的示意图；
图16为本公开实施例形成第二平坦层图案后的示意图；
图17a至图17d为本公开实施例形成阳极导电层图案后的示意图；
图18a和图18b为本公开实施例形成像素定义层图案后的示意图；
图19为一种现有显示基板的平面结构示意图。
附图标记说明:
11—第一有源层；       12—第二有源层；       13—第三有源层；
14—第四有源层；       15—第五有源层；       16—第六有源层；
17—第七有源层；       21—第一扫描信号线；   22—发光控制线；
23—第三扫描信号线；   24—第一极板；         31—第一初始信号线；
32—第二扫描信号线；   33—第四扫描信号线；   34—第二极板；
35—开口；             40—存储电容；         51—第一连接电极；
52—第二连接电极；     53—第三连接电极；     54—第四连接电极；
55—第五连接电极；     56—第六连接电极；     57—第二初始信号线；
61—数据信号线；       62—第一电源线；       63—阳极连接电极；
90—阳极；             100—显示区域；        101—基底；
102—驱动电路层；      103—发光结构层；      104—封装结构层；
200—绑定区域；        300—边框区域；        400—像素开口。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
本公开中的附图比例可以作为实际工艺中的参考，但不限于此。例如：沟道的宽长比、各个膜层的厚度和间距、各个信号线的宽度和间距，可以根据实际需要进行调整。显示基板中像素的个数和每个像素中子像素的个数也 不是限定为图中所示的数量，本公开中所描述的附图仅是结构示意图，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换，“源端”和“漏端”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的 电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本说明书中三角形、矩形、梯形、五边形或六边形等并非严格意义上的，可以是近似三角形、矩形、梯形、五边形或六边形等，可以存在公差导致的一些小变形，可以存在导角、弧边以及变形等。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
图1为一种显示装置的结构示意图。如图1所示，显示装置可以包括时序控制器、数据驱动器、扫描驱动器、发光驱动器和像素阵列，时序控制器分别与数据驱动器、扫描驱动器和发光驱动器连接，数据驱动器分别与多个数据信号线(D1到Dn)连接，扫描驱动器分别与多个扫描信号线(S1到Sm)连接，发光驱动器分别与多个发光信号线(E1到Eo)连接。像素阵列可以包括多个子像素Pxij，i和j可以是自然数，至少一个子像素Pxij可以包括电路单元和与电路单元连接的发光器件，电路单元可以包括至少一个扫描信号线、至少一个数据信号线、至少一个发光信号线和像素驱动电路。在示例性实施方式中，时序控制器可以将适合于数据驱动器的规格的灰度值和控制信号提供到数据驱动器，可以将适合于扫描驱动器的规格的时钟信号、扫描起始信号等提供到扫描驱动器，可以将适合于发光驱动器的规格的时钟信号、发射停止信号等提供到发光驱动器。数据驱动器可以利用从时序控制器接收的灰度值和控制信号来产生将提供到数据信号线D1、D2、D3、……和Dn的数据电压。例如，数据驱动器可以利用时钟信号对灰度值进行采样，并且以像素行为单位将与灰度值对应的数据电压施加到数据信号线D1至Dn， n可以是自然数。扫描驱动器可以通过从时序控制器接收时钟信号、扫描起始信号等来产生将提供到扫描信号线S1、S2、S3、……和Sm的扫描信号。例如，扫描驱动器可以将具有导通电平脉冲的扫描信号顺序地提供到扫描信号线S1至Sm。例如，扫描驱动器可以被构造为移位寄存器的形式，并且可以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产生扫描信号，m可以是自然数。发光驱动器可以通过从时序控制器接收时钟信号、发射停止信号等来产生将提供到发光信号线E1、E2、E3、……和Eo的发射信号。例如，发光驱动器可以将具有截止电平脉冲的发射信号顺序地提供到发光信号线E1至Eo。例如，发光驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以截止电平脉冲形式提供的发射停止信号传输到下一级电路的方式产生发射信号，o可以是自然数。
图2为一种显示基板的结构示意图。如图2所示，显示基板可以包括显示区域100、位于显示区域100一侧的绑定区域200以及位于显示区域100其它侧的边框区域300。在示例性实施方式中，显示区域100可以是平坦的区域，包括组成像素阵列的多个子像素Pxij，多个子像素Pxij配置为显示动态图片或静止图像，显示区域100可以称为有效区域(AA)。在示例性实施方式中，显示基板可以采用柔性基板，因而显示基板可以是可变形的，例如卷曲、弯曲、折叠或卷起。在示例性实施方式中，显示基板还可以包括显示区域边界BD，显示区域边界BD可以是显示区域100靠近绑定区域200一侧的边缘。
在示例性实施方式中，绑定区域200可以包括沿着远离显示区域方向依次设置的扇出区、弯折区、驱动芯片区和绑定引脚区，扇出区连接到显示区域，包括多条数据扇出线，数据扇出线被配置为以扇出(Fanout)走线方式连接显示区域的数据信号线(Data Line)。弯折区连接到扇出区，可以包括设置有凹槽的复合绝缘层，被配置为使绑定区域弯折到显示区域的背面。驱动芯片区可以包括集成电路(Integrated Circuit，简称IC)，被配置为与多条数据扇出线连接。绑定引脚区可以包括绑定焊盘(Bonding Pad)，被配置为与外部的柔性线路板(Flexible Printed Circuit，简称FPC)绑定连接。
在示例性实施方式中，边框区域300可以包括沿着远离显示区域的方向依次设置的电路区、电源线区、裂缝坝区和切割区。电路区连接到显示区域，可以至少包括栅极驱动电路，栅极驱动电路与显示区域中像素驱动电路的第一扫描信号线、第二扫描信号线、第三扫描信号线和发光控制线连接。电源线区连接到电路区，可以至少包括电源引线，电源引线沿着平行于显示区域边缘的方向延伸，与显示区域中的阴极连接。裂缝坝区连接到电源线区，可以至少包括在复合绝缘层上设置的多个裂缝。切割区连接到裂缝坝区，可以至少包括在复合绝缘层上设置的切割槽，切割槽配置为在显示基板的所有膜层制备完成后，切割设备分别沿着切割槽进行切割。
在示例性实施方式中，绑定区域200中的扇出区和边框区域300中的电源线区可以设置有第一隔离坝和第二隔离坝，第一隔离坝和第二隔离坝可以沿着平行于显示区域边缘的方向延伸，形成环绕显示区域的环形结构，显示区域边缘是显示区域绑定区域或者边框区域一侧的边缘。
图3为一种显示基板中显示区域的平面结构示意图。如图3所示，显示基板可以包括以矩阵方式排布的多个像素单元P，至少一个像素单元P可以包括出射第一颜色光线的第一子像素P1、出射第二颜色光线的第二子像素P2和出射第三颜色光线的第三子像素P3和第四子像素P4。每个子像素可以均包括电路单元和发光器件，电路单元可以至少包括像素驱动电路，像素驱动电路分别与扫描信号线、数据信号线和发光信号线连接，像素驱动电路被配置为在扫描信号线和发光信号线的控制下，接收数据信号线传输的数据电压，向发光器件输出相应的电流。每个子像素中的发光器件分别与所在子像素的像素驱动电路连接，发光器件被配置为响应所在子像素的像素驱动电路输出的电流发出相应亮度的光。
在示例性实施方式中，第一子像素P1可以是出射红色光线的红色子像素(R)，第二子像素P2可以是出射蓝色光线的蓝色子像素(B)，第三子像素P3和第四子像素P4可以是出射绿色光线的绿色子像素(G)。在示例性实施方式中，子像素的形状可以是矩形状、菱形、五边形或六边形，四个子像素可以采用钻石形(Diamond)方式排列，形成RGBG像素排布。在其它示例性实施方式中，四个子像素可以采用水平并列、竖直并列或正方形等 方式排列，本公开在此不做限定。
在示例性实施方式中，像素单元可以包括三个子像素，三个子像素可以采用水平并列、竖直并列或品字等方式排列，本公开在此不做限定。
图4为一种显示基板中显示区域的剖面结构示意图，示意了显示区域中四个子像素的结构。如图4所示，在垂直于显示基板的平面上，显示基板可以包括设置在基底101上的驱动电路层102、设置在驱动电路层102远离基底101一侧的发光结构层103以及设置在发光结构层103远离基底101一侧的封装结构层104。在一些可能的实现方式中，显示基板可以包括其它膜层，如触控结构层等，本公开在此不做限定。
在示例性实施方式中，基底101可以是柔性基底，或者可以是刚性基底。每个子像素的驱动电路层102可以包括由多个晶体管和存储电容构成的像素驱动电路。每个子像素的发光结构层103可以包括由多个膜层构成的发光器件，多个膜层可以至少包括阳极、像素定义层、有机发光层和阴极，阳极与像素驱动电路连接，有机发光层与阳极连接，阴极与有机发光层连接，有机发光层在阳极和阴极驱动下出射相应颜色的光线。封装结构层104可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可以采用无机材料，第二封装层可以采用有机材料，第二封装层设置在第一封装层和第三封装层之间，形成无机材料/有机材料/无机材料叠层结构，可以保证外界水汽无法进入发光结构层103。
在示例性实施方式中，有机发光层可以包括发光层(EML)以及如下任意一层或多层：空穴注入层(HIL)、空穴传输层(HTL)、电子阻挡层(EBL)、、空穴阻挡层(HBL)、电子传输层(ETL)和电子注入层(EIL)。在示例性实施方式中，所有子像素的空穴注入层、空穴传输层、电子阻挡层、空穴阻挡层、电子传输层和电子注入层中的一层或多层可以是连接在一起的共通层，相邻子像素的发光层可以有少量的交叠，或者可以是相互隔离的。
图5为一种像素驱动电路的等效电路示意图。在示例性实施方式中，像素驱动电路可以是3T1C、4T1C、5T1C、5T2C、6T1C、7T1C或8T1C结构。如图5所示，像素驱动电路可以包括7个晶体管(第一晶体管T1至第七晶体管T7)和1个存储电容C，像素驱动电路分别与10条信号线(数据信号 线D、第一扫描信号线S1、第二扫描信号线S2、第三扫描信号线S3、第四扫描信号线S4、发光信号线E、第一初始信号线INIT1、第二初始信号线INIT1、第一电源线VDD和第二电源线VSS)连接。
在示例性实施方式中，像素驱动电路可以包括第一节点N1、第二节点N2和第三节点N3。其中，第一节点N1分别与第三晶体管T3的第一极、第四晶体管T4的第二极和第五晶体管T5的第二极连接，第二节点N2分别与第一晶体管T1的第二极、第三晶体管T3的控制极和存储电容C的第二端连接，第三节点N3分别与第二晶体管T2的第二极、第三晶体管T3的第二极和第六晶体管T6的第一极连接。
在示例性实施方式中，存储电容C的第一端与第一电源线VDD连接，存储电容C的第二端与第二节点N2连接，即存储电容C的第二端与第三晶体管T3的控制极连接。
在示例性实施方式中，第一晶体管T1的控制极与第二扫描信号线S2连接，第一晶体管T1的第一极与第一初始信号线INIT1连接，第一晶体管T1的第二极与第二节点N2连接。当导通的扫描信号施加到第二扫描信号线S2时，第一晶体管T1将第一初始化电压传输到存储电容C的第二端，实现存储电容C的初始化。
在示例性实施方式中，第二晶体管T2的控制极与第四扫描信号线S4连接，第二晶体管T2的第一极与第一晶体管T1的第二极连接，第二晶体管T2的第二极与第三节点N3连接。当导通的扫描信号施加到第四扫描信号线S4时，第二晶体管T2使第三晶体管T3的控制极与第三晶体管T3的第二极连接。
在示例性实施方式中，第三晶体管T3的控制极与第二节点N2连接，即第三晶体管T3的控制极与存储电容C的第二端连接，第三晶体管T3的第一极与第一节点N1连接，第三晶体管T3的第二极与第三节点N3连接。第三晶体管T3可以称为驱动晶体管，第三晶体管T3根据其控制极与第一极之间的电位差来确定在第一电源线VDD与发光器件之间流动的驱动电流的大小。
在示例性实施方式中，第四晶体管T4的控制极与第三扫描信号线S3连 接，第四晶体管T4的第一极与数据信号线D连接，第四晶体管T4的第二极与第一节点N1连接。当导通的扫描信号施加到第三扫描信号线S3时，第四晶体管T4使数据信号线D的数据电压输入到第一节点N1。
在示例性实施方式中，第五晶体管T5的控制极与发光信号线E连接，第五晶体管T5的第一极与第一电源线VDD连接，第五晶体管T5的第二极与第一节点N1连接。第六晶体管T6的控制极与发光信号线E连接，第六晶体管T6的第一极与第三节点N3连接，第六晶体管T6的第二极与发光器件的第一极连接。当导通的发光信号施加到发光信号线E时，第五晶体管T5和第六晶体管T6通过在第一电源线VDD与发光器件之间形成驱动电流路径而使发光器件发光。
在示例性实施方式中，第七晶体管T7的控制极与第一扫描信号线S1连接，第七晶体管T7的第一极与第二初始信号线INIT2连接，第七晶体管T7的第二极与发光器件的第一极连接。当导通的扫描信号施加到第一扫描信号线S1时，第七晶体管T7将第二初始电压传输到发光器件的第一极，以使发光器件的第一极中累积的电荷量初始化或释放发光器件的第一极中累积的电荷量。
在示例性实施方式中，发光器件可以是OLED，包括叠设的第一极(阳极)、有机发光层和第二极(阴极)，或者可以是QLED，包括叠设的第一极(阳极)、量子点发光层和第二极(阴极)。
在示例性实施方式中，发光器件的第二极与第二电源线VSS连接，第二电源线VSS的信号为低电平信号，第一电源线VDD的信号为持续提供高电平信号。
在示例性实施方式中，第一晶体管T1至第七晶体管T7可以是P型晶体管，或者可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。在一些可能的实现方式中，第一晶体管T1至第七晶体管T7可以包括P型晶体管和N型晶体管。
在示例性实施方式中，第一晶体管T1至第七晶体管T7可以采用低温多 晶硅晶体管，或者可以采用氧化物晶体管，或者可以采用低温多晶硅晶体管和金属氧化物晶体管。低温多晶硅晶体管的有源层采用低温多晶硅(Low Temperature Poly-Silicon，简称LTPS)，金属氧化物晶体管的有源层采用金属氧化物半导体(Oxide)。低温多晶硅晶体管具有迁移率高、充电快等优点，氧化物晶体管具有漏电流低等优点，将低温多晶硅晶体管和金属氧化物晶体管集成在一个显示基板上，形成低温多晶氧化物(Low Temperature Polycrystalline Oxide，简称LTPO)显示基板，可以利用两者的优势，可以实现低频驱动，可以降低功耗，可以提高显示品质。
图6为一种像素驱动电路的工作时序图。下面通过图5示例的像素驱动电路的工作过程说明本公开示例性实施例，图5中的像素驱动电路包括7个晶体管(第一晶体管T1到第七晶体管T7)和1个存储电容C，第一晶体管T1和第二晶体管T2为N型的氧化物晶体管，第三晶体管T3至第七晶体管T7为P型的低温多晶硅晶体管。在示例性实施方式中，像素驱动电路的工作过程可以包括：
第一阶段A1，称为复位阶段，第二扫描信号线S2的信号为导通信号(高电平)，第一扫描信号线S1、第三扫描信号线S3、第四扫描信号线S4和发光信号线E的信号为断开信号。第二扫描信号线S2的导通信号使第一晶体管T1导通，第一初始信号线INIT1的信号通过第一晶体管T1提供至第二节点N2，对存储电容C进行初始化(复位)，清除存储电容中原有电荷。第一扫描信号线S1、第三扫描信号线S3、第四扫描信号线S4和发光信号线E的断开信号使第二晶体管T2、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7断开，此阶段OLED不发光。
第二阶段A2、称为数据写入阶段或者阈值补偿阶段，第一扫描信号线S1、第三扫描信号线S3和第四扫描信号线S4的信号为导通信号，第二扫描信号线S2和发光信号线E的信号为断开信号，数据信号线D输出数据电压。此阶段由于存储电容C的第二端为低电平，因此第三晶体管T3导通。第一扫描信号线S1、第三扫描信号线S3和第四扫描信号线S4的导通信号使第二晶体管T2、第四晶体管T4和第七晶体管T7导通。第二晶体管T2和第四晶体管T4导通使得数据信号线D输出的数据电压经过第一节点N1、导通的第 三晶体管T3、第三节点N3、导通的第二晶体管T2提供至第二节点N2，并将数据信号线D输出的数据电压与第三晶体管T3的阈值电压之差充入存储电容C，存储电容C的第二端(第二节点N2)的电压为Vd-|Vth|，Vd为数据信号线D输出的数据电压，Vth为第三晶体管T3的阈值电压。第七晶体管T7导通使第二初始信号线INIT2的信号提供至OLED的第一极，对OLED的第一极进行初始化(复位)，清空其内部的预存电压，完成初始化，确保OLED不发光。第二扫描信号线S2的断开信号使第一晶体管T1断开，发光信号线E的断开信号使第五晶体管T5和第六晶体管T6断开。
第三阶段A3、称为发光阶段，发光信号线E的信号为导通信号，第一扫描信号线S1、第二扫描信号线S2、第三扫描信号线S3和第四扫描信号线S4的信号为断开信号。发光信号线E的导通信号使第五晶体管T5和第六晶体管T6导通，第一电源线VDD输出的电源电压通过导通的第五晶体管T5、第三晶体管T3和第六晶体管T6向OLED的第一极提供驱动电压，驱动OLED发光。
在像素驱动电路驱动过程中，流过第三晶体管T3(驱动晶体管)的驱动电流由其栅电极和第一极之间的电压差决定。由于第二节点N2的电压为Vdata-|Vth|，因而第三晶体管T3的驱动电流为：
I＝K*(Vgs-Vth) 2＝K*[(Vdd-Vd+|Vth|)-Vth] 2＝K*[(Vdd-Vd] 2
其中，I为流过第三晶体管T3的驱动电流，也就是驱动OLED的驱动电流，K为常数，Vgs为第三晶体管T3的栅电极和第一极之间的电压差，Vth为第三晶体管T3的阈值电压，Vd为数据信号线D输出的数据电压，Vdd为第一电源线VDD输出的电源电压。
随着OLED显示技术的发展，消费者对显示产品显示效果的要求越来越高，极窄边框成为显示产品发展的新趋势，因此边框的窄化甚至无边框设计在OLED显示产品设计中越来越受到重视。目前，显示装置的左边框、右边框和上边框可以控制在1.0mm以内，但下边框(绑定区域一侧的边框)的窄化设计难度较大，一直维持在2.0mm左右。为了减小下边框的宽度，一些显示基板主要采用减小扇出区或者弯折区长度的方案，但在现有工艺能力条件下，下边框仍比左边框和右边框大很多。
本公开示例性实施例提供了一种显示基板。在示例性实施方式中，显示基板可以包括显示区域和位于所述显示区域一侧的绑定区域，所述显示区域包括依次设置的M个像素行，M为大于1的正整数；至少一个像素行包括扫描信号线和沿着所述扫描信号线延伸方向依次设置的多个子像素，至少一个子像素包括与所述扫描信号线连接的像素驱动电路，所述像素驱动电路至少包括存储电容和多个晶体管，所述多个晶体管至少包括作为第一初始化晶体管的第一晶体管，所述扫描信号线至少包括第二扫描信号线，所述第二扫描信号线被配置为控制所述第一晶体管导通或断开；至少一个像素行中，所述第二扫描信号线设置在所述存储电容靠近显示区域边界的一侧，所述显示区域边界是所述显示区域靠近所述绑定区域一侧的边缘。
在示例性实施方式中，所述第一晶体管的第一极与第一初始信号线连接，所述第一初始信号线设置在所述存储电容靠近所述显示区域边界的一侧。
在示例性实施方式中，第M像素行中所述第一初始信号线靠近所述绑定区域一侧的边缘形成像素驱动电路边界。
在示例性实施方式中，所述像素驱动电路边界位于所述显示区域边界远离所述绑定区域的一侧。
在示例性实施方式中，所述像素驱动电路边界与所述显示区域边界之间的距离为6μm至10μm。
图7为本公开示例性实施例一种显示基板的平面结构示意图，为显示区域中靠近绑定区域的第M-1像素行和第M像素行的像素驱动电路结构。在示例性实施方式中，显示基板可以包括显示区域100和位于显示区域100第二方向Y一侧的绑定区域200，显示区域100可以包括沿着第二方向Y依次设置的M个像素行，至少一个像素行可以包括沿着第一方向X依次设置的多个子像素，M为大于1的正整数。如图7所示，第M行是最靠近显示区域边界BD的像素行，第M-1行是位于第M行远离显示区域边界BD一侧的像素行，显示区域边界BD是显示区域100靠近绑定区域200一侧的边缘。
在示例性实施方式中，对于显示区域设置的多个阳极，每个阳极都具有靠近绑定区域一侧的边缘，多个阳极中最靠近绑定区域的边缘称为阳极边界，显示区域边界BD可以是经过该阳极边界且沿着第一方向X延伸的直线。
在示例性实施方式中，显示区域边界可以位于显示区域内，或者，可以位于绑定区域内，显示区域边界可以是相关具有结构特征的结构参考线。例如，显示区域边界可以是绑定区域内隔离坝边界的位置。又如，显示区域边界可以是绑定区域内阴极结束的位置。再如，显示区域边界可以是绑定区域内扇出走线直边区域的位置。再如，显示区域边界可以是绑定区域内数据信号线转接接入(转接过孔)的位置，本公开在此不做限定。
在示例性实施方式中，至少一个像素行可以包括沿着第一方向X延伸的扫描信号线，一个像素行中至少一个子像素可以包括像素驱动电路，像素驱动电路与扫描信号线连接。
在示例性实施方式中，像素驱动电路可以至少包括多个晶体管和存储电容。像素驱动电路中的多个晶体管可以至少包括作为第一初始化晶体管的第一晶体管T1，扫描信号线可以至少包括第二扫描信号线32，第二扫描信号线32被配置为控制第一晶体管T1的导通或断开。
在示例性实施方式中，存储电容40可以位于子像素第二方向Y的中部区域，可以包括叠设的第一极板和第二极板。
在示例性实施方式中，至少一个像素行中，第二扫描信号线32可以设置在存储电容40靠近显示区域边界BD的一侧。
在示例性实施方式中，第一晶体管T1可以包括栅电极、第一极和第二极，第一晶体管T1的栅电极可以与第二扫描信号线32连接，第一晶体管T1的第一极可以与第一初始信号线31连接，第一初始信号线31可以设置在存储电容40靠近显示区域边界BD的一侧。
在示例性实施方式中，第M像素行中第一初始信号线31靠近绑定区域200一侧的边缘形成像素驱动电路边界PD，像素驱动电路边界PD可以位于显示区域边界BD远离绑定区域200的一侧。
在示例性实施方式中，像素驱动电路边界PD与显示区域边界BD之间的距离L可以约为6μm至10μm。
在示例性实施方式中，像素驱动电路中的多个晶体管还可以包括作为第二初始化晶体管的第七晶体管T7，扫描信号线还可以包括第一扫描信号线 21，第一扫描信号线21被配置为控制第七晶体管T7的导通或断开，第一扫描信号线21设置在存储电容40远离显示区域边界BD的一侧。
在示例性实施方式中，第七晶体管T7可以包括栅电极、第一极和第二极，第七晶体管T7的栅电极可以与第一扫描信号线21连接，第七晶体管T7的的第一极可以与第二初始信号线57连接，第二初始信号线57可以设置在存储电容40远离显示区域边界BD的一侧。
在示例性实施方式中，第i像素行中第二初始信号线57在显示基板上的正投影与第i-1像素行中第二扫描信号线32在显示基板上的正投影至少部分交叠，i＝2，3，……，M。
在示例性实施方式中，像素驱动电路中的多个晶体管还可以包括作为补偿晶体管的第二晶体管T2和作为数据写入晶体管的第四晶体管T4，扫描信号线还可以包括第三扫描信号线23和第四扫描信号线33，第三扫描信号线23被配置为控制第四晶体管T4的导通或断开，第四扫描信号线33被配置为控制第二晶体管T2的导通或断开，第三扫描信号线23和第四扫描信号线33设置在存储电容40靠近显示区域边界BD的一侧。
在示例性实施方式中，第三扫描信号线23可以设置在第四扫描信号线33靠近显示区域边界BD的的一侧。
在示例性实施方式中，第i像素行中所述第一扫描信号线21与第i-1像素行中第三扫描信号线23可以为一体结构。
在示例性实施方式中，像素驱动电路中的多个晶体管还包括作为发光晶体管的第五晶体管T5和第六晶体管T6，显示基板还可以包括发光控制线22，发光控制线22被配置为控制第五晶体管T5和第六晶体管T6的导通或断开，发光控制线22设置在存储电容40远离显示区域边界BD的一侧。
在示例性实施方式中，像素驱动电路中的多个晶体管可以包括作为第一初始化晶体管的第一晶体管T1、作为补偿晶体管的第二晶体管T2、作为驱动晶体管的第三晶体管T3、作为数据写入晶体管的第四晶体管T4、作为发光晶体管的第五晶体管T5和第六晶体管T6、以及作为第二初始化晶体管的第七晶体管T7。第一晶体管T1、第二晶体管T2
在示例性实施方式中，第四晶体管T4可以设置在第三晶体管T3靠近显示区域边界BD的一侧，第五晶体管T5、第六晶体管T6和第七晶体管T7可以设置在第三晶体管T3远离显示区域边界BD的一侧。
在示例性实施方式中，第一晶体管T1和第二晶体管T2可以为氧化物晶体管，第三晶体管T3至第七晶体管T7可以为低温多晶硅晶体管。
在示例性实施方式中，在垂直于所述显示基板的平面内，显示基板可以包括设置在基底上的驱动电路层和设置在驱动电路层远离基底一侧的发光结构层。驱动电路层可以包括沿着远离基底方向设置的第一半导体层、第一导电层、第二导电层、第二半导体层和第三导电层。第一半导体层可以至少包括多个多晶硅晶体管的有源层，第一导电层可以至少包括第一扫描信号线21、第三扫描信号线23、多个多晶硅晶体管的栅电极和存储电容40的第一极板，第二导电层可以至少包括第二扫描信号线32、第四扫描信号线33、第一初始信号线31、多个氧化物晶体管的栅电极和存储电容40的第二极板，第二半导体层可以至少包括多个氧化物晶体管的有源层，第三导电层可以至少包括第二初始信号线57。
本公开中，A沿着B方向延伸是指，A可以包括主要部分和与主要部分连接的次要部分，主要部分是线、线段或条形状体，主要部分沿着B方向伸展，且主要部分沿着B方向伸展的长度大于次要部分沿着其它方向伸展的长度。以下描述中所说的“A沿着B方向延伸”均是指“A的主体部分沿着B方向延伸”。在示例性实施方式中，第二方向Y可以是从显示区域指向绑定区域的方向，第二方向Y的反方向可以是从绑定区域指向显示区域的方向。
下面通过显示基板的制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在 整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。本公开示例性实施方式中，“B的正投影位于A的正投影的范围之内”或者“A的正投影包含B的正投影”是指，B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
在示例性实施方式中，以靠近显示区域边界BD的第M-1像素行和第M个像素行中的8个子像素为例，显示基板的制备过程可以包括如下操作。
(1)在玻璃载板上制备基底。在示例性实施方式中，基底可以是柔性基底，或者可以是刚性基底。刚性基底可以包括但不限于玻璃、石英中的一种或多种，柔性衬底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。在示例性实施方式中，柔性基底可以包括在玻璃载板上叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层。第一、第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一、第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基底的抗水氧能力，第一、第二无机材料层也称为阻挡(Barrier)层，半导体层的材料可以采用非晶硅(a-si)。在示例性实施方式中，以叠层结构PI1/Barrier1/a-si/PI2/Barrier2为例，其制备过程可以包括：先在玻璃载板上涂布一层聚酰亚胺，固化成膜后形成第一柔性(PI1)层；随后在第一柔性层上沉积一层阻挡薄膜，形成覆盖第一柔性层的第一阻挡(Barrier1)层；然后在第一阻挡层上沉积一层非晶硅薄膜，形成覆盖第一阻挡层的非晶硅(a-si)层；然后在非晶硅层上再涂布一层聚酰亚胺，固化成膜后形成第二柔性(PI2)层；然后在第二柔性层上沉积一层阻挡薄膜，形成覆盖第二柔性层的第二阻挡(Barrier2)层，完成基底的制备。
(2)形成第一半导体层图案。在示例性实施方式中，形成第一半导体层图案可以包括：在基底上依次沉积第一绝缘薄膜和第一半导体薄膜，通过图 案化工艺对第一半导体薄膜进行图案化，形成覆盖基底的第一绝缘层，以及设置在第一绝缘层上的第一半导体层图案，如图8所示。
在示例性实施方式中，每个子像素的第一半导体层图案可以至少包括第三晶体管T3的第三有源层13至第七晶体管T7的第七有源层17，且第三有源层13至第七有源层17为相互连接的一体结构。
在示例性实施方式中，在第一方向X上，第六有源层16可以位于本子像素中第三有源层13的一侧，第四有源层14和第五有源层15可以位于本子像素中第三有源层13的另一侧。在第二方向Y上，第i行子像素中第四有源层14可以位于本子像素中第三有源层13第二方向Y的一侧(即靠近显示区域边界BD的一侧)，第i行子像素中的第五有源层15、第六有源层16和第七有源层17可以位于本子像素中第三有源层13第二方向Y的反方向的一侧(即远离显示区域边界BD的一侧)，i＝2，3，……，M。
在示例性实施方式中，第三有源层13的形状可以呈倒“Ω”形，第四有源层14至第七有源层17的形状可以呈“I”字形。
在示例性实施方式中，每个晶体管的有源层可以包括第一区、第二区以及位于第一区和第二区之间的沟道区。在示例性实施方式中，第三有源层13的第一区13-1可以同时作为第四有源层14的第二区14-2和第五有源层15的第二区15-2，第三有源层13的第二区13-2可以同时作为第六有源层16的第一区16-1，第六有源层16的第二区16-2可以同时作为第七有源层17的第二区17-2，第四有源层14的第一区14-1、第五有源层15的第一区15-1和第七有源层17的第一区17-1可以单独设置。
在示例性实施方式中，第i行子像素中的第七有源层17的第一区17-1可以设置在第i-1行子像素中，i＝2，3，……，M。
在示例性实施方式中，一个像素行中，相邻两个子像素中的第五有源层15的第一区15-1可以相互连接。例如，第N-2列的第五有源层15的第一区15-1和第N-1列的第五有源层15的第一区15-1相互连接，第N列的第五有源层15的第一区15-1和第N+1列的第五有源层15的第一区15-1相互连接，第N+2列的第五有源层15的第一区15-1和第N+3列的第五有源层15的第一区15-1相互连接。在示例性实施方式中，由于每个子像素中的第五有源层 的第一区被配置为与后续形成的第一电源线连接，通过将相邻子像素的第五有源层的第一区形成相互连接的一体结构，可以保证相邻子像素的第五晶体管T5的第一极具有相同的电位，有利于提高面板的均一性，避免显示基板的显示不良，保证显示基板的显示效果。
在示例性实施方式中，第一半导体层可以采用多晶硅(p-Si)，即第一晶体管至第六晶体管为LTPS薄膜晶体管。在示例性实施方式中，通过图案化工艺对第一半导体薄膜进行图案化，可以包括：先在第一绝缘薄膜上形成非晶硅(a-si)薄膜，对非晶硅薄膜进行脱氢处理，对脱氢处理后的非晶硅薄膜进行结晶处理，形成多晶硅薄膜。随后，对多晶硅薄膜进行图案化，形成第一半导体层图案。
(3)形成第一导电层图案。在示例性实施方式中，形成第一导电层图案可以包括：在形成前述图案的基底上，依次沉积第二绝缘薄膜和第一导电薄膜，通过图案化工艺对第一导电薄膜进行图案化，形成覆盖第一半导体层图案的第二绝缘层，以及设置在第二绝缘层上的第一导电层图案，如图9a和图9b所示，图9b为图9a中第一导电层的平面示意图。在示例性实施方式中，第一导电层可以称为第一栅金属(GATE1)层。
在示例性实施方式中，每个子像素的第一导电层图案至少包括：第一扫描信号线21、发光控制线22、第三扫描信号线23和存储电容的第一极板24。
在示例性实施方式中，第一极板24的形状可以为矩形状，矩形状的角部可以设置倒角，第一极板24在基底上的正投影与第三晶体管T3的第三有源层在基底上的正投影至少部分交叠。在示例性实施方式中，第一极板24可以同时作为存储电容的一个极板和第三晶体管T3的栅电极。
在示例性实施方式中，第一扫描信号线21的形状可以为主体部分沿着第一方向X延伸的折线状，第i行子像素中的第一扫描信号线21可以位于本子像素的第一极板24第二方向Y的反方向的一侧(即远离显示区域边界BD的一侧)，第一扫描信号线21与本子像素的第七有源层相重叠的区域作为第七晶体管T7的栅电极。
在示例性实施方式中，第i行子像素中的第一扫描信号线21可以设置在第i-1行子像素中。
在示例性实施方式中，发光控制线22的形状可以为主体部分沿着第一方向X延伸的线形状，第i行子像素中的发光控制线22可以位于第一极板24第二方向Y的反方向的一侧(即远离显示区域边界BD的一侧)，且位于第一极板24与第一扫描信号线21之间，发光控制线22与本子像素的第五有源层相重叠的区域作为第五晶体管T5的栅电极，发光控制线22与本子像素的第六有源层相重叠的区域作为第六晶体管T6的栅电极。
在示例性实施方式中，第三扫描信号线23的形状可以为主体部分沿着第一方向X延伸的折线状，第i行子像素中的第三扫描信号线23可以位于本子像素的第一极板24第二方向Y的一侧(即靠近显示区域边界BD的一侧)，第三扫描信号线23与本子像素的第四有源层相重叠的区域作为第四晶体管T4的栅电极。
在示例性实施方式中，第i-1行子像素中的第三扫描信号线23可以作为第i行子像素中的第一扫描信号线21，即第i-1行的第三扫描信号线23与第i行中的第一扫描信号线21为一体结构。
在示例性实施方式中，第一扫描信号线21、发光控制线22和第三扫描信号线23可以为非等宽度设计，第一扫描信号线21、发光控制线22和第三扫描信号线23的宽度为第二方向Y的尺寸，不仅可以便于像素结构的布局，而且可以降低信号线之间的寄生电容，本公开在此不做限定。
在示例性实施方式中，第一扫描信号线21和第三扫描信号线23可以包括与第一半导体层相重叠区域和与第一半导体层不相重叠区域，与第一半导体层相重叠区域的第一扫描信号线21和第三扫描信号线23的宽度可以小于与第一半导体层不相重叠区域的第一扫描信号线21和第三扫描信号线23的宽度。在示例性实施方式中，与第一半导体层相重叠区域的第一扫描信号线21和第三扫描信号线23的宽度LS1可以约为3.6μm至4.0μm。例如，宽度LS1可以约为3.8μm左右。
在示例性实施方式中，发光控制线22可以包括与第一半导体层相重叠区域和与第一半导体层不相重叠区域，与第一半导体层相重叠区域的第一扫描信号线21的宽度可以大于与第一半导体层不相重叠区域的第一扫描信号线21的宽度。在示例性实施方式中，与第一半导体层不相重叠区域的第一扫描 信号线21的宽度LEM可以约为1.8μm至2.2μm。例如，宽度LEM可以约为2.0μm左右。
在示例性实施方式中，形成第一导电层图案后，可以利用第一导电层作为遮挡，对第一半导体层进行导体化处理，被第一导电层遮挡区域的第一半导体层形成第三晶体管T3至第七晶体管T7的沟道区域，未被第一导电层遮挡区域的第一半导体层被导体化，即第三晶体管T3至第七有源层的第一区和第二区均被导体化。
(4)形成第二导电层图案。在示例性实施方式中，形成第二导电层图案可以包括：在形成前述图案的基底上，依次沉积第三绝缘薄膜和第二导电薄膜，采用图案化工艺对第二导电薄膜进行图案化，形成覆盖第一导电层的第三绝缘层，以及设置在第三绝缘层上的第二导电层图案，如图10a和图10b所示，图10b为图10a中第二导电层的平面示意图。在示例性实施方式中，第二导电层可以称为第二栅金属(GATE2)层。
在示例性实施方式中，每个子像素的第二导电层图案至少包括：第一初始信号线31、第二扫描信号线32、第四扫描信号线33和存储电容的第二极板34。
在示例性实施方式中，第二极板34的轮廓可以为矩形状，矩形状的角部可以设置倒角，第二极板34在基底上的正投影与第一极板24在基底上的正投影至少部分交叠，第二极板34可以作为存储电容的另一个极板，第一极板24和第二极板34构成像素驱动电路的存储电容。第二极板34上设置有开口35，开口35的形状可以为矩形状，可以位于第二极板34的中部，使第二极板34形成环形结构。开口35暴露出覆盖第一极板24的第三绝缘层，且第一极板24在基底上的正投影包含开口35在基底上的正投影。在示例性实施方式中，开口35被配置为容置后续形成的第一过孔，第一过孔位于开口35内并暴露出第一极板24，使后续形成的第一晶体管T1的第二极与第一极板24连接。
在示例性实施方式中，一个像素行中相邻两个子像素中的第二极板34可以相互连接。例如，第N-2列的第二极板34和第N-1列的第二极板34可以通过第一连接条34相互连接。又如，第N列的第二极板34和第N+1列 的第二极板34通过第二连接条35相互连接。再如，第N+2列的第二极板34和第N+3列的第二极板34通过第二连接条35相互连接。在示例性实施方式中，由于每个子像素中的第二极板34与后续形成的第一电源线连接，通过将相邻子像素的第二极板34形成相互连接的一体结构，一体结构的第二极板可以复用为电源信号线，可以保证一像素行中的多个第二极板具有相同的电位，有利于提高面板的均一性，避免显示基板的显示不良，保证显示基板的显示效果。
在示例性实施方式中，第一初始信号线31的形状可以为主体部分沿着第一方向X延伸的直线状，第i行子像素中的第一初始信号线31可以位于本子像素的第二极板34第二方向Y的一侧(即靠近显示区域边界BD的一侧)。
在示例性实施方式中，第一初始信号线31的宽度LIN1可以约为1.8μm至2.2μm。例如，第一初始信号线31的宽度可以约为2.0μm左右。
在示例性实施方式中，第M像素行的第一初始信号线31可以形成像素驱动电路边界，第一初始信号线31与显示区域边界BD之间的距离L可以约为6μm至10μm。例如，距离L可以约为7.99μm左右。
在示例性实施方式中，第二扫描信号线32的形状可以为主体部分沿着第一方向X延伸的折线状，第i行子像素中的第二扫描信号线32可以位于本子像素的第二极板34第二方向Y的一侧(即靠近显示区域边界BD的一侧)，第二扫描信号线32可以位于第一初始信号线31和第二极板34之间。
在示例性实施方式中，第二扫描信号线32可以位于第一初始信号线31和第三扫描信号线23之间。
在示例性实施方式中，第四扫描信号线33的形状可以为主体部分沿着第一方向X延伸的线形状，第i行子像素中的第四扫描信号线33可以位于本子像素的第二极板34第二方向Y的一侧(即靠近显示区域边界BD的一侧)，第四扫描信号线33可以位于第二扫描信号线32和第二极板34之间。
在示例性实施方式中，第四扫描信号线33可以位于第三扫描信号线23和第二极板34之间。
在示例性实施方式中，第二扫描信号线32和第四扫描信号线33可以为 非等宽度设计，第二扫描信号线32和第四扫描信号线33的宽度为第二方向Y的尺寸，不仅可以便于像素结构的布局，而且可以降低信号线之间的寄生电容，本公开在此不做限定。
在示例性实施方式中，第二扫描信号线32可以包括与后续形成的第二半导体层相重叠区域和与第二半导体层不相重叠区域，与第二半导体层相重叠区域的第二扫描信号线32的宽度可以大于与第二半导体层不相重叠区域的第二扫描信号线32的宽度。在示例性实施方式中，与第二半导体层不相重叠区域的第二扫描信号线32的宽度LS2可以约为2.2μm至2.6μm。例如，宽度LS2可以约为2.4μm左右。
在示例性实施方式中，第四扫描信号线33可以包括与后续形成的第二半导体层相重叠区域和与第二半导体层不相重叠区域，与第二半导体层相重叠区域的第四扫描信号线33的宽度可以大于与第二半导体层不相重叠区域的第四扫描信号线33的宽度。在示例性实施方式中，与第二半导体层不相重叠区域的第四扫描信号线33的宽度LS3可以约为1.8μm至2.2μm。例如，宽度LS3可以约为2.0μm左右。
(5)形成第二半导体层图案。在示例性实施方式中，形成第二半导体层图案可以包括：在形成前述图案的基底上，依次沉积第四绝缘薄膜和第二半导体薄膜，通过图案化工艺对第二半导体薄膜进行图案化，形成覆盖基底的第四绝缘层，以及设置在第四绝缘层上的第二半导体层图案，如图11a和图11b所示，图11b为图11a中第二半导体层的平面示意图。
在示例性实施方式中，每个子像素的第二半导体层图案至少包括：第一晶体管T1的第一有源层11和第二晶体管T2的第二有源层12。
在示例性实施方式中，第一有源层11的形状可以呈“I”字形，第一有源层11在基底上的正投影与第二扫描信号线32在基底上的正投影至少部分交叠，第二扫描信号线32与本子像素的第一有源层11相重叠的区域作为第一晶体管T1的栅电极。
在示例性实施方式中，第一有源层11的第一区11-1可以位于第二扫描信号线32第二方向Y的一侧(即靠近显示区域边界BD的一侧)，第一有源层11的第二区11-2可以位于第二扫描信号线32第二方向Y的反方向的 一侧(即远离显示区域边界BD的一侧)。
在示例性实施方式中，第二有源层12的形状可以呈“I”字形，第二有源层12在基底上的正投影与第四扫描信号线33在基底上的正投影至少部分交叠，第四扫描信号线33与本子像素的第二有源层12相重叠的区域作为第二晶体管T2的栅电极。
在示例性实施方式中，第二有源层12的第一区12-1可以位于第四扫描信号线33第二方向Y的一侧(即靠近显示区域边界BD的一侧)，第二有源层12的第二区12-2可以位于第四扫描信号线33第二方向Y的反方向的一侧(即远离显示区域边界BD的一侧)。
在示例性实施方式中，第一有源层11的第二区11-2可以作为第二有源层12的第一区12-1，即第一有源层11的第二区11-2和第二有源层12的第一区12-1为相互连接的一体结构，可以位于第二扫描信号线32和第四扫描信号线33之间。
在示例性实施方式中，第i行子像素中一体结构的第一有源层11的第二区11-2和第二有源层12的第一区12-1在基底上的正投影与第i行子像素中第三扫描信号线23在基底上的正投影至少部分交叠，第i-1行子像素中一体结构的第一有源层11的第二区11-2和第二有源层12的第一区12-1在基底上的正投影与第i-1行子像素中第三扫描信号线23(即第i行子像素中的第一扫描信号线21)在基底上的正投影至少部分交叠。
在示例性实施方式中，第二半导体层可以采用氧化物，即第一晶体管T1和第二晶体管T2为氧化物晶体管。在示例性实施方式中，第二半导体薄膜可以采用氧化铟镓锌(IGZO)，氧化铟镓锌(IGZO)的电子迁移率高于非晶硅。
(6)形成第五绝缘层图案。在示例性实施方式中，形成第五绝缘层图案可以包括：在形成前述图案的基底上，沉积第五绝缘薄膜，采用图案化工艺对第五绝缘薄膜进行图案化，形成覆盖第二半导体层的第五绝缘层，第五绝缘层上设置有多个过孔，如图12所示。
在示例性实施方式中，每个子像素的多个过孔至少包括：第一过孔V1、 第二过孔V2、第三过孔V3、第四过孔V4、第五过孔V5、第六过孔V6、第七过孔V7、第八过孔V8、第九过孔V9、第十过孔V10和第十一过孔V11。
在示例性实施方式中，第一过孔V1在基底上的正投影位于开口35在基底上的正投影的范围之内，第一过孔V1内的第五绝缘层、第四绝缘层和第三绝缘层被刻蚀掉，暴露出第一极板24的表面。第一过孔V1配置为使后续形成的第一晶体管T1的第二极通过该过孔与第一极板24连接。
在示例性实施方式中，第二过孔V2位于第二极板34在基底上的正投影的范围之内，第二过孔V2内的第五绝缘层和第四绝缘层被刻蚀掉，暴露出第二极板34的表面。第二过孔V2被配置为使后续形成的第五晶体管T5的第一极通过该过孔与第二极板34连接。
在示例性实施方式中，第三过孔V3在基底上的正投影位于第五有源层的第一区在基底上的正投影的范围之内，第三过孔V3内的第五绝缘层、第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第五有源层的第一区的表面，第三过孔V3被配置为使后续形成的第五晶体管T5的第一极通过该过孔与第五有源层的第一区连接。
在示例性实施方式中，第四过孔V4在基底上的正投影位于第六有源层的第二区在基底上的正投影的范围之内，第四过孔V4内的第五绝缘层、第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第六有源层的第二区(也是第七有源层的第二区)的表面，第四过孔V4被配置为使后续形成的第六晶体管T6的第二极(第七晶体管T7的第二极)通过该过孔与第六有源层的第二区连接。
在示例性实施方式中，第五过孔V5在基底上的正投影位于第四有源层的第一区在基底上的正投影的范围之内，第五过孔V5内的第五绝缘层、第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第四有源层的第一区的表面，第五过孔V5被配置为使后续形成的第四晶体管T4的第一极通过该过孔与第四有源层的第一区连接。
在示例性实施方式中，第六过孔V6在基底上的正投影位于第三有源层的第二区在基底上的正投影的范围之内，第六过孔V6内的第五绝缘层、第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第三有源层的第二区 (也是第六有源层的第一区)的表面，第六过孔V6被配置为使后续形成的第三晶体管T3的第二极(第六晶体管T6的第一极)通过该过孔与第三有源层的第二区连接。
在示例性实施方式中，第七过孔V7在基底上的正投影位于第七有源层的第一区在基底上的正投影的范围之内，第七过孔V7内的第五绝缘层、第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第七有源层的第一区的表面，第七过孔V7被配置为使后续形成的第七晶体管T7的第一极通过该过孔与第七有源层的第一区连接。
在示例性实施方式中，第八过孔V8在基底上的正投影位于第一有源层的第一区在基底上的正投影的范围之内，第八过孔V8内的第五绝缘层、第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第一有源层的第一区的表面，第八过孔V8被配置为使后续形成的第一晶体管T1的第一极通过该过孔与第一有源层的第一区连接。
在示例性实施方式中，第九过孔V9在基底上的正投影位于第二有源层的第二区在基底上的正投影的范围之内，第九过孔V9内的第五绝缘层被刻蚀掉，暴露出第二有源层的第二区的表面，第九过孔V9被配置为使后续形成的第二晶体管T2的第二极通过该过孔与第二有源层的第二区连接。
在示例性实施方式中，第十过孔V10在基底上的正投影位于第一有源层的第二区在基底上的正投影的范围之内，第十过孔V10内的第五绝缘层、第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第一有源层的第二区(也是第二有源层的第一区)的表面，第十过孔V10被配置为使后续形成的第一晶体管T1的第二极(也是第二晶体管T2的第一极)通过该过孔与第一有源层的第二区连接。
在示例性实施方式中，第十一过孔V11在基底上的正投影位于第一初始信号线31在基底上的正投影的范围之内，第十一过孔V11内的第五绝缘层和第四绝缘层被刻蚀掉，暴露出第一初始信号线31的表面，第十一过孔V11被配置为使后续形成的第一晶体管T1的第一极通过该过孔与第一初始信号线31连接。
(7)形成第三导电层图案。在示例性实施方式中，形成第三导电层可以 包括：在形成前述图案的基底上，沉积第三导电薄膜，采用图案化工艺对第三导电薄膜进行图案化，形成设置在第五绝缘层上的第三导电层，如图13a和图13b所示，图13b为图13a中第三导电层的平面示意图。在示例性实施方式中，第三导电层可以称为第三栅金属(GATE3)层。
在示例性实施方式中，每个子像素的第三导电层至少包括：第一连接电极51、第二连接电极52、第三连接电极53、第四连接电极54、第五连接电极55、第六连接电极56和第二初始信号线57。
在示例性实施方式中，第一连接电极51的形状可以为主体部分沿着第二方向Y延伸的折线形，第一连接电极51的第一端通过第一过孔V1与第一极板24连接，第一连接电极51的第二端沿着第二方向Y延伸后，通过第十过孔V10与第一有源层的第二区(也是第二有源层的第一区)连接，使第一极板24、第一晶体管T1的第二极和第二晶体管T2的第一极具有相同的电位。在示例性实施方式中，第一连接电极51可以同时作为第一晶体管T1的第二极和第二晶体管T2的第一极(第二节点N2)。
在示例性实施方式中，第二连接电极52的形状可以为沿着第一方向X延伸的条形状，第二连接电极52的第一端通过第八过孔V8与第一有源层的第一区连接，第二连接电极52的第二端通过第十一过孔V11与第一初始信号线31连接，使第一初始信号线31传输的第一初始电压写入第一晶体管T1的第一极。在示例性实施方式中，第二连接电极52可以作为第一晶体管T1的第一极。
在示例性实施方式中，每个像素行中，第N-1列的第二连接电极52和第N列的第二连接电极52可以为相互连接的一体结构，第N+1列的第二连接电极52和第N+2列的第二连接电极52可以为相互连接的一体结构。
在示例性实施方式中，第三连接电极53的形状可以为矩形状，第三连接电极53通过第五过孔V5与第四有源层的第一区连接。在示例性实施方式中，第三连接电极53可以作为第四晶体管T4的第一极，被配置为与后续形成的数据信号线连接。
在示例性实施方式中，第四连接电极54的形状可以为“Y”形状，第四连接电极54的第一端通过第二过孔V2与第二极板34连接，第四连接电极54 的第二端通过第三过孔V3与第五有源层的第一区连接，因而实现了子像素中第五晶体管T5的第一极和存储电容的第二极板34具有相同的电位。在示例性实施方式中，第四连接电极54可以作为第五晶体管T5的第一极。
在示例性实施方式中，第四连接电极54在基底上的正投影与第七有源层的第二区在基底上的正投影至少部分交叠。
在示例性实施方式中，每个像素行中，第N-2列的第四连接电极54和第N-1列的第四连接电极54可以为相互连接的一体结构，第N列的第四连接电极54和第N+1列的第四连接电极54可以为相互连接的一体结构，第N+2列的第四连接电极54和第N+3列的第四连接电极54可以为相互连接的一体结构。在示例性实施方式中，由于每个子像素中的第四连接电极54与后续形成的第一电源线连接，通过将相邻子像素的第四连接电极54形成相互连接的一体结构，可以保证相邻子像素的第四连接电极54具有相同的电位，因而使得相邻子像素中第五晶体管T5的第一极具有相同的电位，相邻子像素中存储电容的第二极板34具有相同的电位，有利于提高面板的均一性，避免显示基板的显示不良，保证显示基板的显示效果。
在示例性实施方式中，第五连接电极55的形状可以为矩形状，第五连接电极55的第一端通过第六过孔V6与第三有源层的第二区(也是第六有源层的第一区)连接，第五连接电极55的第二端通过第九过孔V9与第二有源层的第二区连接。第五连接电极55可以同时作为第二晶体管T2的第二极、第三晶体管T3的第二极和第六晶体管T6的第一极(第三节点N3)。
在示例性实施方式中，第六连接电极56的形状可以为矩形状，第六连接电极56通过第四过孔V4与第六有源层的第二区(也是第七有源层的第二区)连接。在示例性实施方式中，第六连接电极56可以同时作为第六晶体管T6的第二极和第七晶体管T7的第二极，第六连接电极56被配置为与后续形成的阳极连接电极连接。
在示例性实施方式中，第二初始信号线57可以为主体部分沿着第一方向X延伸的折线状，第二初始信号线57可以设置在存储电容远离显示区域边界BD的一侧，第二初始信号线57通过一像素行中的多个第七过孔V7与多个第七有源层的第一区连接，将第二初始电压写入一像素行中多个第七晶体管 T7。在示例性实施方式中，由于第二初始信号线57与一个像素行中所有的第七有源层的第一区连接，可以保证一个像素行中所有的第七晶体管T7的第一极具有相同的电位，有利于提高面板的均一性，避免显示基板的显示不良，保证显示基板的显示效果。在示例性实施方式中，第二初始信号线57的宽度LIN2可以约为1.9μm至2.3μm。例如，第二初始信号线57的宽度可以约为2.1μm左右。
在示例性实施方式中，第i像素行的第二初始信号线57可以位于第i-1像素行所在区域内。
(8)形成第一平坦层图案。在示例性实施方式中，形成第一平坦层图案可以包括：在形成前述图案的基底上，涂覆第一平坦薄膜，采用图案化工艺对第一平坦薄膜进行图案化，形成覆盖第三导电层图案的第一平坦层，第一平坦层上设置有多个过孔，如图14所示。
在示例性实施方式中，每个子像素中的多个过孔至少包括：第二十一过孔V21、第二十二过孔V22和第二十三过孔V23。
在示例性实施方式中，第二十一过孔V21在基底上的正投影位于第三连接电极53在基底上的正投影的范围之内，第二十一过孔V21内的第一平坦层被刻蚀掉，暴露出第三连接电极53的表面，第二十一过孔V21被配置为使后续形成的数据信号线通过该过孔与第三连接电极53连接。
在示例性实施方式中，第二十二过孔V22在基底上的正投影位于第四连接电极54的第一子电极54-1在基底上的正投影的范围之内，第二十二过孔V22内的第一平坦层被刻蚀掉，暴露出第一子电极54-1的表面，第二十二过孔V22被配置为使后续形成的第一电源线该过孔与第四连接电极54连接。
在示例性实施方式中，第二十三过孔V23在基底上的正投影位于第六连接电极56在基底上的正投影的范围之内，第二十三过孔V23内的第一平坦层被刻蚀掉，暴露出第六连接电极56的表面，第二十三过孔V232被配置为使后续形成的阳极连接电极该过孔与第六连接电极56连接。
(9)形成第四导电层图案。在示例性实施方式中，形成第四导电层可以包括：在形成前述图案的基底上，沉积第四导电薄膜，采用图案化工艺对第四导电薄膜进行图案化，形成设置在第一平坦层上的第四导电层，如图15a 和图15b所示，图15b为图15a中第四导电层的平面示意图。在示例性实施方式中，第四导电层可以称为第一源漏金属(SD1)层。
在示例性实施方式中，每个子像素的第四导电层至少包括：数据信号线61、第一电源线62和阳极连接电极63。
在示例性实施方式中，数据信号线61的形状可以为主体部分沿着第二方向Y延伸的直线形，数据信号线61通过第二十一过孔V21与第三连接电极53连接。由于第三连接电极53通过过孔与第四有源层的第一区连接，因而实现了数据信号线61与第四晶体管T4的第一极的连接，将数据信号写入第四晶体管T4的第一极。
在示例性实施方式中，第一电源线62的形状可以为主体部分沿着第二方向Y延伸的折线形，第一电源线62通过第二十二过孔V22与第四连接电极54连接。由于第四连接电极54分别通过过孔与第二极板34和第五有源层的第一区连接，因而实现了第一电源线62与第二极板34和第五晶体管T5的第一极的连接，将电源信号写入第五晶体管T5的第一极。
在示例性实施方式中，一个像素行中相邻两个子像素中的第一电源线62可以为相互连接的一体结构。例如，第N-1列的第一电源线62和第N列的第一电源线62相互连接，第N+1列的第一电源线62和第N+2列的第一电源线62相互连接。在示例性实施方式中，通过将相邻子像素的第一电源线62形成相互连接的一体结构，可以保证相邻子像素的第一电源线62具有相同的电位，有利于提高面板的均一性，避免显示基板的显示不良，保证显示基板的显示效果。
在示例性实施方式中，第一电源线62可以为非等宽度的折线，不仅可以便于像素结构的布局，而且可以降低第一电源线与数据信号线之间的寄生电容。
在示例性实施方式中，第一电源线62在基底上的正投影可以与第一连接电极51在基底上的正投影至少部分交叠，第一电源线62在基底上的正投影可以与第二连接电极52在基底上的正投影至少部分交叠，使得第一电源线62可以作为屏蔽电极，可以有效屏蔽数据电压跳变对像素驱动电路中关键节点的影响，避免了数据电压跳变影响像素驱动电路的关键节点的电位，提高 了显示效果。
在示例性实施方式中，阳极连接电极63的形状可以为矩形状，阳极连接电极63通过第二十三过孔V23与第六连接电极56连接，阳极连接电极63被配置为与后续形成的阳极连接。
(10)形成第二平坦层图案。在示例性实施方式中，形成第二平坦层图案可以包括：在形成前述图案的基底上，涂覆第二平坦薄膜，采用图案化工艺对第二平坦薄膜进行图案化，形成覆盖第四导电层图案的第二平坦层，第二平坦层上设置有多个过孔，如图16所示。
在示例性实施方式中，每个子像素的过孔至少包括第三十一过孔V31。
在示例性实施方式中，第三十一过孔V31在基底上的正投影位于阳极连接电极63在基底上的正投影的范围之内，第三十一过孔V31内的第二平坦层被去掉，暴露出阳极连接电极63的表面，第三十一过孔V31被配置为使后续形成的阳极通过该过孔与阳极连接电极63连接。
至此，在基底上制备完成驱动电路层。在平行于显示基板的平面内，驱动电路层可以包括多个子像素，每个子像素可以包括像素驱动电路，以及与像素驱动电路连接的第一扫描信号线、第二扫描信号线、第三扫描信号线、发光控制线、数据信号线、第一电源线、第一初始信号线和第二初始信号线。在垂直于显示基板的平面内，所述驱动电路层可以包括在基底上依次设置的第一绝缘层、第一半导体层、第二绝缘层、第一导电层、第三绝缘层、第二导电层、第四绝缘层、第二半导体层、第五绝缘层、第三导电层、第一平坦层、第四导电层和第二平坦层。第一半导体层至少包括第三晶体管至第七晶体管的有源层，第一导电层至少包括第三晶体管至第七晶体管的栅电极和存储电容的第一极板，第二导电层至少包括第一晶体管至第二晶体管的栅电极和存储电容的第二极板，第二半导体层至少包括第一晶体管至第二晶体管的有源层，第三导电层至少包括多个晶体管的第一极和第二极，第四导电层至少包括数据信号线和第一电源线。
在示例性实施方式中，第一导电层、第二导电层、第三导电层和第四导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合 金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层和第五绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。第一绝缘层可以称为缓冲(Buffer)层，用于提高基底的抗水氧能力，第二绝缘层、第三绝缘层、第四绝缘层和第五绝缘层可以称为栅绝缘(GI)层，第五绝缘层可以称为层间绝缘(ILD)层。第一平坦层和第二平坦层可以采用有机材料，如树脂等。
在示例性实施方式中，一个像素行中相邻两个子像素中的像素驱动电路可以相对于第一中心线基本上镜像对称，第一中心线是位于相邻两个子像素之间且沿着第二方向Y延伸的直线。例如，第N-1列的像素驱动电路和第N列的像素驱动电路可以相对于第一中心线镜像对称。又如，第N列的像素驱动电路和第N+1列的像素驱动电路可以相对于第一中心线镜像对称。
在示例性实施方式中，相邻两个子像素中的像素驱动电路可以相对于第一中心线基本上镜像对称可以包括如下任意一种或多种：一个像素行中相邻两个子像素中的第一半导体层可以相对于第一中心线镜像对称，一个像素行中相邻两个子像素中的第一导电层可以相对于第一中心线镜像对称，一个像素行中相邻两个子像素中的第二导电层可以相对于第一中心线镜像对称，一个像素行中相邻两个子像素中的第二半导体层可以相对于第一中心线镜像对称，一个像素行中相邻两个子像素中的第三导电层可以相对于第一中心线镜像对称，一个像素行中相邻两个子像素中的第四导电层可以相对于第一中心线镜像对称。
在示例性实施方式中，制备完成驱动电路层后，在驱动电路层上制备发光结构层，发光结构层的制备过程可以包括如下操作。
(11)形成阳极导电层图案。在示例性实施方式中，形成阳极导电层图案可以包括：在形成前述图案的基底上，沉积阳极导电薄膜，采用图案化工艺对阳极导电薄膜进行图案化，形成设置在第二平坦层上的阳极导电层，阳极导电层至少包括多个阳极图案，如图17a至图17d所示，图17a为本公开实施例形成的一种阳极导电层图案后的示意图，图17b为图17a中阳极导电层的平面示意图，图17c为本公开实施例形成的另一种阳极导电层图案后的 示意图，图17d为图17c中阳极导电层的平面示意图。
在示例性实施方式中，阳极导电层采用单层结构，如氧化铟锡ITO或氧化铟锌IZO，或者可以采用多层复合结构，如ITO/Ag/ITO等。
在示例性实施方式中，多个阳极图案可以包括红色发光器件的第一阳极90A、蓝色发光器件的第二阳极90B、第一绿色发光器件的第三阳极90C和第二绿色发光器件的第四阳极90D，第一阳极90A可以位于出射红色光线的红色子像素，第二阳极90B可以位于出射蓝色光线的蓝色子像素，第三阳极90C可以位于出射绿色光线的第一绿色子像素，第四阳极90D可以位于出射绿色光线的第二绿色子像素。
在示例性实施方式中，第一阳极90A和第二阳极90B可以沿着第二方向Y依次设置，第三阳极90C和第四阳极90D可以沿着第二方向Y依次设置，第三阳极90C和第四阳极90D可以设置在第一阳极90A和第二阳极90B第一方向X的一侧。或者，第一阳极90A和第二阳极90B可以沿着第一方向X依次设置，第三阳极90C和第四阳极90D可以沿着第一方向X依次设置，第三阳极90C和第四阳极90D可以设置在第一阳极90A和第二阳极90B第二方向Y的一侧。
在示例性实施方式中，第一阳极90A、第二阳极90B、第三阳极90C和第四阳极90D可以分别通过第三十一过孔V31与所在子像素的阳极连接电极63连接，一个像素单元中四个子像素的阳极形状和面积可以相同，或者可以不同。
在示例性实施方式中，对于显示区域设置的多个阳极，每个阳极都具有靠近绑定区域一侧的边缘，多个阳极中最靠近绑定区域的边缘称为阳极边界90-1，本公开示例性实施例的显示区域边界BD是经过该阳极边界90-1且沿着第一方向X延伸的直线。
在示例性实施方式中，第一阳极90A、第二阳极90B、第三阳极90C和第四阳极90D中的至少一个可以包括相互连接的阳极主体部和阳极连接部，阳极连接部通过第三十一过孔V31与阳极连接电极63连接。
在示例性实施方式中，第一阳极90A可以包括相互连接的第一阳极主体部和第一阳极连接部，第一阳极主体部的形状可以为矩形状，矩形状的角部 可以设置圆弧状的倒角，第一阳极连接部的形状可以为沿着第二方向Y延伸的条形状，第一阳极连接部通过第三十一过孔V31与阳极连接电极63连接。
在示例性实施方式中，第二阳极90B可以包括相互连接的第二阳极主体部和第二阳极连接部，第二阳极主体部的形状可以为矩形状，矩形状的角部可以设置圆弧状的倒角，第二阳极连接部的形状可以为沿着第二方向Y延伸的条形状，第二阳极连接部通过第三十一过孔V31与阳极连接电极63连接。
在示例性实施方式中，第三阳极90C可以包括相互连接的第三阳极主体部和第三阳极连接部，第三阳极主体部的形状可以为矩形状，矩形状的角部可以设置圆弧状的倒角，第三阳极连接部可以为沿着第一方向X延伸的条形状，第三阳极连接部通过第三十一过孔V31与阳极连接电极63连接。
在示例性实施方式中，第四阳极90D可以包括相互连接的第四阳极主体部和第四阳极连接部，第四阳极主体部的形状可以为矩形状，矩形状的角部可以设置圆弧状的倒角，第四阳极连接部可以为沿着第一方向X延伸的条形状，第四阳极连接部通过第三十一过孔V31与阳极连接电极63连接。
在示例性实施方式中，后续制备流程可以包括：先形成像素定义层图案，然后采用蒸镀或喷墨打印工艺形成有机发光层，然后在有机发光层上形成阴极，然后形成封装结构层，封装结构层可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可以采用无机材料，第二封装层可以采用有机材料，第二封装层设置在第一封装层和第三封装层之间，可以保证外界水汽无法进入发光结构层。
(12)形成像素定义层图案。在示例性实施方式中，形成像素定义层图案可以包括：在形成前述图案的基底上，涂覆像素定义薄膜，采用图案化工艺对像素定义薄膜进行图案化，形成覆盖阳极导电层图案的像素定义层，像素定义层上设置有多个像素开口400，像素开口400内的像素定义薄膜被去掉，暴露出阳极90的表面，如图18a和图18b所示，图18a为本公开实施例形成的一种像素定义层图案后的示意图，图17b为本公开实施例形成的另一种像素定义层图案后的示意图。
在一种可能的示例性实施方式中，对于显示区域设置的多个像素开口，每个像素开口都具有靠近绑定区域一侧的边缘，多个像素开口中最靠近绑定 区域的边缘称为像素开口边界，本公开示例性实施例的显示区域边界BD可以是经过该像素开口边界且沿着第一方向X延伸的直线。
图19为一种现有显示基板的平面结构示意图，为显示区域中靠近绑定区域第M-1像素行和第M个像素行的像素驱动电路结构。如图19所示。该现有显示基板中像素驱动电路的布局为：第一晶体管T1、第二晶体管T2和第四晶体管T4位于本子像素的第三晶体管T3远离显示区域边界BD的一侧，第五晶体管T5、第六晶体管T6和第七晶体管T7位于本子像素的第三晶体管T3靠近显示区域边界BD的一侧。根据该布局的特点，为了实现第i像素行中子像素的第六晶体管T6的第二极和第七晶体管T7的第二极共用，设计上采用第i像素行子像素中的第七晶体管T7由第i+1像素行(下一行)子像素中的第一扫描信号线21驱动，i＝1，2，……，M。由于这种驱动特点，因而第M像素行(最后一行)子像素的像素驱动电路需要额外设置驱动第七晶体管T7的下一行第一扫描信号线21和提供第二初始信号的下一行第二初始信号线57，额外设置的第一扫描信号线21和第二初始信号线57只能设置在显示区域之外，即额外设置的第一扫描信号线21和第二初始信号线57等信号线位于显示区域边界BD靠近绑定区域的一侧。由于额外设置的第一扫描信号线21和第二初始信号线57所形成的像素驱动电路边界PD超出了显示区域边界BD，因而绑定区域只能以像素驱动电路边界PD为基准进行相应设置，因而增加了下边框的宽度。在示例性实施方式中，显示区域边界BD与像素驱动电路边界PD之间的超出距离B约为20μm至30μm左右，超出距离B越大，下边框就越大。
在示例性实施方式中，虽然可以采用将像素驱动电路整体上移的方案来调整像素驱动电路边界的位置，使显示区域边界BD与像素驱动电路边界PD重叠，但为了实现阳极与像素驱动电路的连接，这种处理方案需要改变阳极连接电极的位置，使得阳极开口之间的距离减小，不仅会增加信号串扰，而且会导致短路缺陷。此外，像素驱动电路整体上移的方案会使像素定义层的像素开口整体上移，使得金属掩膜板(FMM)与显示区域边界之间的距离减小，在现有工艺条件下，导致蒸镀过程中由阴影(Shadow)造成显示区域偏暗，存在较大的显示不良风险。
从本公开显示基板的结构以及制备过程可以看出，本公开示例性实施例所提供的显示基板，通过改变像素驱动电路的布局，可以有效减小下边框的宽度。本公开通过将第i像素行中子像素的第一扫描信号线21、第二扫描信号线32、第四扫描信号线33、第一初始信号线31和第二初始信号线57位于本子像素的存储电容40靠近显示区域边界BD的一侧，发光控制线22位于本子像素的存储电容40远离显示区域边界BD的一侧，第一晶体管T1、第二晶体管T2和第四晶体管T4位于本子像素的第三晶体管T3靠近显示区域边界BD的一侧，第五晶体管T5、第六晶体管T6和第七晶体管T7位于本子像素的第三晶体管T3远离显示区域边界BD的一侧，使得第i像素行(本行)中子像素的第七晶体管T7由第i-1像素行(上一行)中子像素的第一扫描信号线21驱动，因而第M像素行(最后一行)子像素的像素驱动电路不仅不需要额外设置下一行的信号线，而且像素驱动电路边界PD可以位于显示区域内，即像素驱动电路边界PD位于显示区域边界BD远离绑定区域的一侧。本公开示例性实施例这种驱动电路布局，绑定区域不但可以按照显示区域边界BD为基准进行相应设置，而且可以按照像素驱动电路边界PD为基准进行相应设置，有效减小了下边框的宽度。在示例性实施方式中，显示区域边界BD与像素驱动电路边界PD之间的距离L可以约为6μm至10μm。例如，距离L可以约为7.99μm左右。相比于现有结构中像素驱动电路边界PD超出显示区域边界BD约为20μm至30μm左右，本公开示例性实施例显示基板可以使下边框宽度减小约30μm至40μm左右，有利于实现窄边框。此外，本公开示例性实施例所提供的像素驱动电路布局，不仅保证了阳极开口之间的安全距离以及金属掩膜板与显示区域边界之间的安全距离，避免短路缺陷和蒸镀过程中的显示不良风险，而且可以有效节省布局空间，有利于实现高分辨率。本公开的制备工艺可以很好地与现有制备工艺兼容，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。
本公开前述所示结构及其制备过程仅仅是一种示例性说明，在示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺，本公开在此不做限定。
在示例性实施方式中，本公开显示基板可以应用于具有像素驱动电路的 其它显示装置中，如如量子点显示等，本公开在此不做限定。
本公开还提供一种显示基板的制备方法，以制作上述实施例提供的显示基板。在示例性实施方式中，所述显示基板包括显示区域和位于所述显示区域一侧的绑定区域，所述显示区域包括M个像素行，M为大于1的正整数；至少一个像素行包括扫描信号线和沿着所述扫描信号线延伸方向依次设置的多个子像素，至少一个子像素包括与所述扫描信号线连接的像素驱动电路，所述像素驱动电路至少包括存储电容和多个晶体管，所述多个晶体管至少包括作为第一初始化晶体管的第一晶体管，所述扫描信号线至少包括第二扫描信号线，所述第二扫描信号线被配置为控制所述第一晶体管导通或断开；所述制备方法包括：
在至少一个像素行中形成像素驱动电路和第二扫描信号线，所述第二扫描信号线设置在所述存储电容靠近显示区域边界的一侧，所述显示区域边界是所述显示区域靠近所述绑定区域一侧的边界。
本公开还提供一种显示装置，显示装置包括前述的显示基板。显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，本发明实施例并不以此为限。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本发明。任何所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (17)

  1. 一种显示基板，包括显示区域和位于所述显示区域一侧的绑定区域，所述显示区域包括依次设置的M个像素行，M为大于1的正整数；至少一个像素行包括扫描信号线和沿着所述扫描信号线延伸方向依次设置的多个子像素，至少一个子像素包括与所述扫描信号线连接的像素驱动电路，所述像素驱动电路至少包括存储电容和多个晶体管，所述多个晶体管至少包括作为第一初始化晶体管的第一晶体管，所述扫描信号线至少包括第二扫描信号线，所述第二扫描信号线被配置为控制所述第一晶体管导通或断开；至少一个像素行中，所述第二扫描信号线设置在所述存储电容靠近显示区域边界的一侧，所述显示区域边界是所述显示区域靠近所述绑定区域一侧的边缘。
  2. 根据权利要求1所述的显示基板，其中，所述第一晶体管的第一极与第一初始信号线连接，所述第一初始信号线设置在所述存储电容靠近所述显示区域边界的一侧。
  3. 根据权利要求2所述的显示基板，其中，第M像素行中所述第一初始信号线靠近所述绑定区域一侧的边缘形成像素驱动电路边界。
  4. 根据权利要求3所述的显示基板，其中，所述像素驱动电路边界位于所述显示区域边界远离所述绑定区域的一侧。
  5. 根据权利要求4所述的显示基板，其中，所述像素驱动电路边界与所述显示区域边界之间的距离为6μm至10μm。
  6. 根据权利要求1至5任一项所述的显示基板，其中，所述多个晶体管还包括作为第二初始化晶体管的第七晶体管，所述扫描信号线还包括第一扫描信号线，所述第一扫描信号线被配置为控制所述第七晶体管导通或断开，所述第一扫描信号线设置在所述存储电容远离所述显示区域边界的一侧。
  7. 根据权利要求6所述的显示基板，其中，所述第七晶体管的第一极与第二初始信号线连接，所述第二初始信号线设置在所述存储电容远离所述显示区域边界的一侧。
  8. 根据权利要求7所述的显示基板，其中，第i像素行中所述第二初始信号线在显示基板上的正投影与第i-1像素行中所述第二扫描信号线在显示 基板上的正投影至少部分交叠，i＝2，3，……，M。
  9. 根据权利要求6所述的显示基板，其中，所述多个晶体管还包括作为补偿晶体管的第二晶体管和作为数据写入晶体管的第四晶体管，所述扫描信号线还包括控制所述第四晶体管导通或断开的第三扫描信号线和控制所述补偿晶体管导通或断开的第四扫描信号线，所述第三扫描信号线和第四扫描信号线设置在所述存储电容靠近所述显示区域边界的一侧。
  10. 根据权利要求9所述的显示基板，其中，所述第三扫描信号线设置在所述第四扫描信号线靠近所述显示区域边界的的一侧。
  11. 根据权利要求9所述的显示基板，其中，第i像素行中所述第一扫描信号线与第i-1像素行中所述第三扫描信号线为一体结构，i＝2，3，……，M。
  12. 根据权利要求1所述的显示基板，其中，所述多个晶体管还包括第五晶体管和第六晶体管，所述显示基板还包括发光控制线，所述发光控制线被配置为控制所述第五晶体管和第六晶体管导通或断开，所述发光控制线设置在所述存储电容远离所述显示区域边界的一侧。
  13. 根据权利要求1所述的显示基板，其中，所述多个晶体管还包括作为补偿晶体管的第二晶体管、作为驱动晶体管的第三晶体管、作为数据写入晶体管的第四晶体管、作为发光晶体管的第五晶体管和第六晶体管、以及作为第二初始化晶体管的第七晶体管；所述第一晶体管、第二晶体管和第四晶体管设置在所述第三晶体管靠近所述显示区域边界的一侧，所述第五晶体管、第六晶体管和第七晶体管设置在所述第三晶体管远离所述显示区域边界的一侧。
  14. 根据权利要求13所述的显示基板，其中，所述第一晶体管和第二晶体管为氧化物晶体管，所述第三晶体管至第七晶体管为低温多晶硅晶体管。
  15. 根据权利要求1所述的显示基板，其中，在垂直于所述显示基板的平面内，所述显示基板包括设置在基底上的驱动电路层和设置在所述驱动电路层远离所述基底一侧的发光结构层；所述驱动电路层包括沿着远离所述基底方向设置的第一半导体层、第一导电层、第二导电层、第二半导体层和第 三导电层；所述第一半导体层至少包括多个多晶硅晶体管的有源层，所述第一导电层至少包括第一扫描信号线、第三扫描信号线、多个多晶硅晶体管的栅电极和存储电容的第一极板，所述第二导电层至少包括第二扫描信号线、第四扫描信号线、第一初始信号线、多个氧化物晶体管的栅电极和存储电容的第二极板，所述第二半导体层至少包括多个氧化物晶体管的有源层，所述第三导电层至少包括第二初始信号线。
  16. 一种显示装置，包括如权利要求1至15任一项所述的显示基板。
  17. 一种显示基板的制备方法，所述显示基板包括显示区域和位于所述显示区域一侧的绑定区域，所述显示区域包括M个像素行，M为大于1的正整数；至少一个像素行包括扫描信号线和沿着所述扫描信号线延伸方向依次设置的多个子像素，至少一个子像素包括与所述扫描信号线连接的像素驱动电路，所述像素驱动电路至少包括存储电容和多个晶体管，所述多个晶体管至少包括作为第一初始化晶体管的第一晶体管，所述扫描信号线至少包括第二扫描信号线，所述第二扫描信号线被配置为控制所述第一晶体管导通或断开；所述制备方法包括：
    在至少一个像素行中形成像素驱动电路和第二扫描信号线，所述第二扫描信号线设置在所述存储电容靠近显示区域边界的一侧，所述显示区域边界是所述显示区域靠近所述绑定区域一侧的边界。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107481669A (zh) * 2017-09-08 2017-12-15 武汉天马微电子有限公司 一种显示面板及显示装置
CN108806578A (zh) * 2018-06-08 2018-11-13 上海天马有机发光显示技术有限公司 一种显示面板及显示装置
CN109346009A (zh) * 2018-12-25 2019-02-15 武汉天马微电子有限公司 有机发光显示面板和显示装置
CN111710239A (zh) * 2020-06-17 2020-09-25 昆山国显光电有限公司 显示面板、显示面板的驱动方法和显示装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107481669A (zh) * 2017-09-08 2017-12-15 武汉天马微电子有限公司 一种显示面板及显示装置
CN108806578A (zh) * 2018-06-08 2018-11-13 上海天马有机发光显示技术有限公司 一种显示面板及显示装置
CN109346009A (zh) * 2018-12-25 2019-02-15 武汉天马微电子有限公司 有机发光显示面板和显示装置
CN111710239A (zh) * 2020-06-17 2020-09-25 昆山国显光电有限公司 显示面板、显示面板的驱动方法和显示装置

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