WO2023230912A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

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Publication number
WO2023230912A1
WO2023230912A1 PCT/CN2022/096462 CN2022096462W WO2023230912A1 WO 2023230912 A1 WO2023230912 A1 WO 2023230912A1 CN 2022096462 W CN2022096462 W CN 2022096462W WO 2023230912 A1 WO2023230912 A1 WO 2023230912A1
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line
layer
connection
conductive layer
display substrate
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PCT/CN2022/096462
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English (en)
French (fr)
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丁彦红
卢辉
刘斌
陈义鹏
鲍建东
高涛
刘烺
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280001567.3A priority Critical patent/CN117501850A/zh
Priority to PCT/CN2022/096462 priority patent/WO2023230912A1/zh
Publication of WO2023230912A1 publication Critical patent/WO2023230912A1/zh

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  • This article relates to but is not limited to the field of display technology, and specifically relates to a display substrate, a preparation method thereof, and a display device.
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diodes
  • TFT thin film transistors
  • the present disclosure provides a display substrate, including a shielding conductive layer disposed on a substrate and a functional structural layer disposed on a side of the shielding conductive layer away from the substrate, where the shielding conductive layer at least includes a first connection lines, the functional structure layer at least includes data signal lines and second connection lines; in a plane parallel to the display substrate, the display substrate includes a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, At least one circuit unit includes a pixel drive circuit, the data signal line is connected to a plurality of pixel drive circuits of one unit column, the data signal line is configured to provide a data signal to the pixel drive circuit; the second connection line The data signal line is connected to the first connection line, and the data signal line is connected to the second connection line.
  • the functional structure layer includes a plurality of conductive layers, the second connection line and the data signal line are provided on different conductive layers, and the second connection line passes through a first overlapping via hole. Connected to the first connection line, the data signal line is connected to the second connection line through a second overlapping via hole.
  • the display substrate on a plane parallel to the display substrate, includes a display area and a binding area located on one side of the display area in the second direction, the binding area at least includes lead lines ;
  • the first end of the first connection line is connected to the lead-out line, and the second end of the first connection line extends to the display area and is connected to the second through the first overlapping via hole.
  • the first end of the connection line is connected, and the second end of the second connection line extends along the first direction and is connected to the data signal line through the second overlapping via hole, and the first direction is connected to the data signal line.
  • the second direction crosses.
  • a first connection block is provided at an end of the first connection line close to the second connection line, and an orthographic projection of the first connection block on the substrate is in contact with the second connection line. Orthographic projections of lines on the substrate at least partially overlap, and the second connection line is connected to the first connection block through the first overlapping via hole.
  • the second connection line is provided with a second connection block near an end of the first connection line, and an orthographic projection of the second connection block on the substrate is in contact with the first connection block. Orthographic projections of lines on the substrate at least partially overlap, and the second connection block is connected to the first connection line through the first overlapping via hole.
  • a first connection block is provided at an end of the first connection line close to the second connection line, and an orthographic projection of the first connection block on the substrate is in contact with the second connection line. Orthographic projections of the blocks on the substrate at least partially overlap, and the second connection block is connected to the first connection block through the first overlapping via hole.
  • the second connection line includes at least a first sub-line, a second sub-line, a third sub-line and a fourth sub-line, and a first end of the first sub-line is connected to the first sub-line.
  • the second end of the connecting line is connected.
  • the second end of the first sub-line extends along the direction of the unit column and is connected to the first end of the second sub-line.
  • the second end of the second sub-line is connected. After two ends extend along the direction of the unit row, they are connected to the first end of the third sub-line. After the second end of the third sub-line extends along the direction of the unit column, they are connected to the first end of the third sub-line.
  • the first end of the fourth sub-line is connected, and the second end of the fourth sub-line is connected to the data signal line after extending along the direction of the unit row.
  • the first sub-lines are disposed between adjacent cell columns.
  • the shape of the second sub-line is a fold line extending along the direction of the unit row, and the second sub-line includes at least one protruding segment protruding toward the direction of the binding area.
  • the third sub-line is disposed between adjacent cell columns.
  • the pixel driving circuit at least includes a data writing transistor
  • the functional structure layer further includes a first pole of the data writing transistor, and in at least one circuit unit, the fourth sub-line and the The first electrode of the data writing transistor is connected, and the data signal line is connected to the first electrode of the data writing transistor through the second overlapping via hole.
  • the fourth sub-line and the first pole of the data writing transistor are arranged on the same layer and are an integral structure connected to each other.
  • the functional structure layer further includes a first initial signal line configured to provide a first initial signal to the pixel driving circuit, and the second sub-line is The orthographic projection on the substrate at least partially overlaps the orthographic projection of the first initial signal line on the substrate.
  • the first connection lines are provided between adjacent cell columns.
  • the shielding conductive layer further includes a shielding electrode and a first shielding connection line, the shielding electrode is provided in the circuit unit, and the first shielding connection line is connected to a plurality of shielding connection lines in a unit column. Electrode connections.
  • the shielding conductive layer includes a stacked first titanium layer, an aluminum layer, and a second titanium layer.
  • the first titanium layer has a thickness of 40 nm to 60 nm
  • the aluminum layer has a thickness of 250 nm. to 550nm
  • the second titanium layer has a thickness of 20nm to 40nm.
  • the pixel driving circuit includes a storage capacitor and a plurality of transistors; on a plane perpendicular to the display substrate, the functional structure layer at least includes a layer disposed on the shielding conductive layer away from the substrate.
  • the second conductive layer at least includes the second plate of the storage capacitor, the fourth conductive layer at least includes the second connection line, and the fifth conductive layer at least includes the data signal line.
  • the plurality of transistors includes at least one polysilicon transistor and at least one oxide transistor
  • the functional structure layer further includes a first semiconductor layer and a second semiconductor layer
  • the first semiconductor layer is disposed at between the shielding conductive layer and the first conductive layer, the first semiconductor layer including the active layer of the polysilicon transistor, the second semiconductor layer being disposed between the second conductive layer and the third conductive layer
  • the second semiconductor layer includes an active layer of the oxide transistor.
  • the present disclosure also provides a display device, including the aforementioned display substrate.
  • the present disclosure also provides a method for preparing a display substrate.
  • the display substrate includes a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least A circuit unit includes a pixel driving circuit, and the preparation method includes:
  • the shielding conductive layer at least including a first connection line
  • a functional structural layer is formed on the shielding conductive layer.
  • the functional structural layer at least includes a second connection line and a data signal line.
  • the data signal line is connected to multiple pixel driving circuits of a unit column.
  • the data signal line Configured to provide a data signal to the pixel driving circuit, the second connection line is connected to the first connection line, and the data signal line is connected to the second connection line.
  • Figure 1 is a schematic structural diagram of a display device
  • Figure 2 is a schematic structural diagram of a display substrate
  • Figure 3 is a schematic plan view of a display area in a display substrate
  • Figure 4 is a schematic cross-sectional structural diagram of a display area in a display substrate
  • Figure 5 is an equivalent circuit schematic diagram of a pixel driving circuit
  • Figure 6 is a working timing diagram of a pixel driving circuit
  • Figures 7a and 7b are schematic structural diagrams of two data connection lines according to exemplary embodiments of the present disclosure.
  • Figure 8 is a schematic diagram of the connection between a data connection line and a data signal line according to an embodiment of the present disclosure
  • FIGS. 9a and 9b are schematic diagrams after forming a shielding conductive layer pattern according to an embodiment of the present disclosure.
  • Figure 10 is a schematic diagram after the first semiconductor layer pattern is formed according to an embodiment of the present disclosure.
  • 11a and 11b are schematic diagrams after the first conductive layer pattern is formed according to an embodiment of the present disclosure
  • 12a and 12b are schematic diagrams after the second conductive layer pattern is formed according to an embodiment of the present disclosure
  • FIG. 13a and 13b are schematic diagrams after the second semiconductor layer pattern is formed according to an embodiment of the present disclosure.
  • Figures 14a and 14b are schematic diagrams after forming a third conductive layer pattern according to an embodiment of the present disclosure.
  • Figure 15 is a schematic diagram after forming a sixth insulating layer pattern according to an embodiment of the present disclosure.
  • Figures 16a and 16b are schematic diagrams after the fourth conductive layer pattern is formed according to an embodiment of the present disclosure.
  • Figure 17 is a schematic diagram after forming a first flat layer pattern according to an embodiment of the present disclosure.
  • 18a to 18d are schematic diagrams after the fifth conductive layer pattern is formed according to the embodiment of the present disclosure.
  • Figure 19 is a schematic diagram after forming a second flat layer pattern according to an embodiment of the present disclosure.
  • 20a and 20b are schematic diagrams after the anode conductive layer pattern is formed according to an embodiment of the present disclosure.
  • 102 Drive circuit layer
  • 103 Light-emitting structure layer
  • 104 Packaging structure layer
  • 303 organic light-emitting layer
  • 304 cathode
  • 401 first encapsulation layer
  • 402 The second encapsulation layer
  • 403 The third encapsulation layer.
  • the scale of the drawings in this disclosure can be used as a reference in actual processes, but is not limited thereto.
  • the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs.
  • the number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures.
  • the figures described in the present disclosure are only structural schematic diagrams, and one mode of the present disclosure is not limited to the figures. The shape or numerical value shown in the figure.
  • connection should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements.
  • connection should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements.
  • a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode.
  • the transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, channel region, and source electrode .
  • the channel region refers to the region through which current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and the “drain electrode” may be interchanged with each other. Therefore, in this specification, “source electrode” and “drain electrode” can be interchanged with each other, and “source terminal” and “drain terminal” can be interchanged with each other.
  • electrical connection includes a case where constituent elements are connected together through an element having some electrical effect.
  • component having some electrical function There is no particular limitation on the “component having some electrical function” as long as it can transmit and receive electrical signals between the connected components.
  • elements having some electrical function include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.
  • parallel refers to a state in which the angle formed by two straight lines is -10° or more and 10° or less. Therefore, it also includes a state in which the angle is -5° or more and 5° or less.
  • vertical refers to a state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore includes an angle of 85° or more and 95° or less.
  • film and “layer” may be interchanged.
  • conductive layer may sometimes be replaced by “conductive film.”
  • insulating film may sometimes be replaced by “insulating layer”.
  • the triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not strictly speaking. They can be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances. There can be leading angles, arc edges, deformations, etc.
  • the word “approximately” in this disclosure refers to a value that does not strictly limit the limit and allows for process and measurement errors.
  • Figure 1 is a schematic structural diagram of a display device.
  • the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array.
  • the timing controller is connected to the data driver, the scan driver, and the light-emitting driver respectively.
  • the data driver is connected to a plurality of data signal lines. (D1 to Dn) are connected, the scanning driver is connected to a plurality of scanning signal lines (S1 to Sm), and the light emitting driver is connected to a plurality of light emitting signal lines (E1 to Eo).
  • the pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, and at least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit.
  • the circuit unit may include a pixel driving circuit, and the pixel driving circuit is connected to a scanning signal line, The light-emitting signal line and the data signal line are connected.
  • the timing controller may provide a gray value and a control signal suitable for the specifications of the data driver to the data driver, and may provide a clock signal, a scan start signal, and the like suitable for the specifications of the scan driver to the scan driver.
  • the driver can provide a clock signal, an emission stop signal, and the like suitable for the specifications of the light-emitting driver to the light-emitting driver.
  • the data driver may generate data voltages to be provided to the data signal lines D1, D2, D3, . . . and Dn using the grayscale values and control signals received from the timing controller. For example, the data driver may sample the grayscale value using a clock signal, and apply a data voltage corresponding to the grayscale value to the data signal lines D1 to Dn in unit row units, where n may be a natural number.
  • the scan driver may generate scan signals to be supplied to the scan signal lines S1, S2, S3, . . . and Sm by receiving a clock signal, a scan start signal, and the like from the timing controller.
  • the scan driver may sequentially supply scan signals having on-level pulses to the scan signal lines S1 to Sm.
  • the scan driver may be configured in the form of a shift register, and may generate the scan signal in a manner that sequentially transmits a scan start signal provided in the form of an on-level pulse to a next-stage circuit under the control of a clock signal, m can be a natural number.
  • the light-emitting driver may generate emission signals to be provided to the light-emitting signal lines E1, E2, E3, . . . and Eo by receiving a clock signal, an emission stop signal, or the like from the timing controller.
  • the light-emitting driver may sequentially provide emission signals with off-level pulses to the light-emitting signal lines E1 to Eo.
  • the light-emitting driver may be configured in the form of a shift register, and may generate the emission signal in a manner that sequentially transmits an emission stop signal provided in the form of a cut-off level pulse to a next-stage circuit under the control of a clock signal, o Can be a natural number.
  • FIG. 2 is a schematic structural diagram of a display substrate.
  • the display substrate may include a display area 100 , a binding area 200 located on one side of the display area 100 , and a frame area 300 located on other sides of the display area 100 .
  • the display area 100 may be a flat area including a plurality of sub-pixels Pxij constituting a pixel array, the plurality of sub-pixels Pxij are configured to display dynamic pictures or still images, and the display area 100 may be called an active area (AA).
  • the display substrate may be a flexible substrate, and thus the display substrate may be deformable, such as curled, bent, folded, or rolled.
  • the bonding area 200 may include a fan-out area, a bending area, a driver chip area, and a bonding pin area that are sequentially arranged in a direction away from the display area 100 .
  • the fan-out area is connected to the display area 100 and may include at least a plurality of data fan-out lines.
  • the plurality of data fan-out lines are configured to connect data signal lines of the display area in a fan-out (Fanout) wiring manner.
  • the bending area is connected to the fan-out area and may include a composite insulating layer provided with grooves configured to bend the binding area to the back of the display area.
  • the driver chip area may at least include an integrated circuit (Integrated Circuit, IC for short) configured to be connected to multiple data fan-out lines.
  • the bonding pin area may include at least a plurality of bonding pads (Bonding Pads) configured to be bonded to an external flexible circuit board (Flexible Printed Circuit, referred to as FPC).
  • the frame area 300 may include a circuit area, a power line area, a crack dam area, and a cutting area sequentially arranged in a direction away from the display area 100 .
  • the circuit area is connected to the display area 100 and may include at least a gate driving circuit connected to the first scanning line, the second scanning line and the light emission control line of the pixel driving circuit in the display area 100 .
  • the power line area is connected to the circuit area and may include at least a frame power lead.
  • the frame power lead extends in a direction parallel to the edge of the display area and is connected to the cathode in the display area 100 .
  • the crack dam area is connected to the power line area and may include at least a plurality of cracks provided on the composite insulation layer.
  • the cutting area is connected to the crack dam area and may at least include cutting grooves provided on the composite insulating layer. The cutting grooves are configured such that after all film layers of the display substrate are prepared, the cutting equipment cuts along the cutting grooves respectively.
  • the fan-out area in the binding area 200 and the power line area in the frame area 300 may be provided with first isolation dams and second isolation dams, and the first isolation dams and the second isolation dams may be provided along Extending in a direction parallel to the edge of the display area, forming a ring-shaped structure surrounding the display area 100, the edge of the display area is an edge on one side of the display area binding area or the frame area.
  • Figure 3 is a schematic plan view of a display area in a display substrate.
  • the display substrate may include a plurality of pixel units P arranged in a matrix.
  • At least one pixel unit P may include a first sub-pixel P1 that emits light of a first color, and a second sub-pixel that emits light of a second color.
  • the pixel P2 and the third and fourth sub-pixels P3 and P4 that emit light of the third color.
  • Each circuit unit may include a circuit unit and a light-emitting device.
  • the circuit unit may include at least a pixel driving circuit.
  • the pixel driving circuit is connected to the scanning signal line, the light-emitting signal line and the data signal line respectively.
  • the pixel driving circuit is configured to operate on the scanning signal line. Under the control of the light-emitting signal line, it receives the data voltage transmitted by the data signal line and outputs a corresponding current to the light-emitting device.
  • the light-emitting device in each circuit unit is respectively connected to the pixel driving circuit of the sub-pixel where it is located, and the light-emitting device is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel where it is located.
  • the first sub-pixel P1 may be a red sub-pixel (R) emitting red light
  • the second sub-pixel P2 may be a blue sub-pixel (B) emitting blue light
  • the fourth sub-pixel P4 may be a green sub-pixel (G) emitting green light.
  • the shape of the sub-pixels may be rectangular, rhombus, pentagon or hexagon, and the four sub-pixels may be arranged in a diamond shape to form an RGBG pixel arrangement.
  • the four sub-pixels may be arranged horizontally, vertically, or in a square manner, which is not limited in this disclosure.
  • the pixel unit may include three sub-pixels, and the three sub-pixels may be arranged horizontally, vertically, or vertically, which is not limited in this disclosure.
  • FIG. 4 is a schematic cross-sectional structural diagram of a display area in a display substrate, illustrating the structure of four sub-pixels in the display area.
  • the display substrate may include a driving circuit layer 102 disposed on a substrate 101 , a light-emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the substrate 101 , and a light-emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the substrate 101 .
  • the structural layer 103 is away from the packaging structural layer 104 on one side of the substrate 101.
  • the display substrate may include other film layers, such as touch structure layers, etc., which are not limited in this disclosure.
  • substrate 101 may be a flexible substrate, or may be a rigid substrate.
  • the driving circuit layer 102 may include a plurality of circuit units, and each circuit unit may include at least a pixel driving circuit composed of a plurality of transistors and storage capacitors.
  • the light-emitting structure layer 103 may include multiple light-emitting devices. Each light-emitting device may at least include an anode 301, a pixel definition layer 302, an organic light-emitting layer 303, and a cathode 304.
  • the anode 301 is connected to the pixel driving circuit
  • the organic light-emitting layer 303 is connected to the anode 301.
  • the packaging structure layer 104 may include a stacked first packaging layer 401, a second packaging layer 402, and a third packaging layer 403.
  • the first packaging layer 401 and the third packaging layer 403 may be made of inorganic materials, and the second packaging layer 402 may be made of Organic material, the second encapsulation layer 402 is disposed between the first encapsulation layer 401 and the third encapsulation layer 403 to form an inorganic material/organic material/inorganic material stack structure, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.
  • the organic light-emitting layer may include an emitting layer (EML) and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), Hole blocking layer (HBL), electron transport layer (ETL) and electron injection layer (EIL).
  • EML emitting layer
  • HIL hole injection layer
  • HTL hole transport layer
  • EBL electron blocking layer
  • HBL Hole blocking layer
  • ETL electron transport layer
  • EIL electron injection layer
  • one or more of the hole injection layer, hole transport layer, electron blocking layer, hole blocking layer, electron transport layer and electron injection layer of all sub-pixels may be connected together Common layer, the light-emitting layers of adjacent circuit units may have a small amount of overlap, or may be isolated from each other.
  • Figure 5 is an equivalent circuit schematic diagram of a pixel driving circuit.
  • the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure.
  • the pixel driving circuit may include 8 transistors (first transistor T1 to eighth transistor T8) and 1 storage capacitor C.
  • the pixel driving circuit is respectively connected to 9 signal lines (data signal line D, first scanning The signal line S1, the second scanning signal line S2, the third scanning signal line S3, the light emitting signal line E, the first initial signal line INIT1, the second initial signal line INIT1, the first power supply line VDD and the second power supply line VSS) are connected .
  • the pixel driving circuit may include a first node N1, a second node N2, and a third node N3.
  • the first node N1 is respectively connected to the first pole of the third transistor T3, the second pole of the fourth transistor T4 and the second pole of the fifth transistor T5, and the second node N2 is respectively connected to the second pole of the eighth transistor T8.
  • the control electrode of the third transistor T3 is connected to the second end of the storage capacitor C
  • the third node N3 is respectively connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3 and the first electrode of the sixth transistor T6. connect.
  • the first end of the storage capacitor C is connected to the first power line VDD, and the second end of the storage capacitor C is connected to the second node N2, that is, the second end of the storage capacitor C is connected to the third transistor T3. Control pole connection.
  • the control electrode of the first transistor T1 is connected to the second scanning signal line S2, the first electrode of the first transistor T1 is connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is connected to the first initial signal line INIT1.
  • the first pole of eight transistor T8 is connected.
  • the control electrode of the eighth transistor T8 is connected to the third scanning signal line S3, the first electrode of the eighth transistor T8 is connected to the second electrode of the first transistor T1, and the second electrode of the eighth transistor T8 is connected to the second node N2.
  • control electrode of the second transistor T2 is connected to the first scanning signal line S1
  • first electrode of the second transistor T2 is connected to the second electrode of the first transistor T1 and the first electrode of the eighth transistor T8.
  • the second pole of the second transistor T2 is connected to the third node N3.
  • the control electrode of the third transistor T3 is connected to the second node N2, that is, the control electrode of the third transistor T3 is connected to the second end of the storage capacitor C, and the first electrode of the third transistor T3 is connected to the first node N2.
  • the node N1 is connected, and the second pole of the third transistor T3 is connected to the third node N3.
  • the third transistor T3 may be called a driving transistor, and the third transistor T3 determines the size of the driving current flowing between the first power supply line VDD and the light-emitting device according to the potential difference between its control electrode and the first electrode.
  • control electrode of the fourth transistor T4 is connected to the first scanning signal line S1
  • first electrode of the fourth transistor T4 is connected to the data signal line D
  • second electrode of the fourth transistor T4 is connected to the first node. N1 connection.
  • control electrode of the fifth transistor T5 is connected to the light-emitting signal line E
  • first electrode of the fifth transistor T5 is connected to the first power supply line VDD
  • second electrode of the fifth transistor T5 is connected to the first node N1 connect.
  • the control electrode of the sixth transistor T6 is connected to the light-emitting signal line E
  • first electrode of the sixth transistor T6 is connected to the third node N3
  • the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting device.
  • the fifth transistor T5 and the sixth transistor T6 cause the light-emitting device to emit light by forming a driving current path between the first power supply line VDD and the light-emitting device.
  • the control electrode of the seventh transistor T7 is connected to the second scanning signal line S2, the first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is connected to the light emitting line.
  • the first pole connection of the device When the on-level scan signal is applied to the second scan signal line S2, the seventh transistor T7 transmits the second initial voltage to the first pole of the light-emitting device to initialize the amount of charge accumulated in the first pole of the light-emitting device or The amount of charge accumulated in the first pole of the light-emitting device is released.
  • the light-emitting device may be an OLED including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or may be a QLED including a stacked first electrode (anode) , quantum dot light-emitting layer and second electrode (cathode).
  • the second pole of the light-emitting device is connected to the second power line VSS, the signal of the second power line VSS is a continuously provided low-level signal, and the signal of the first power line VDD is a continuously provided high-level signal. flat signal.
  • the first to eighth transistors T1 to T8 may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel drive circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the product yield. In some possible implementations, the first to eighth transistors T1 to T8 may include P-type transistors and N-type transistors.
  • the first to eighth transistors T1 to T8 may use low-temperature polysilicon transistors, or may use oxide transistors, or may use low-temperature polysilicon transistors and metal oxide transistors.
  • the active layer of a low temperature polysilicon transistor is made of low temperature polysilicon (LTPS), and the active layer of a metal oxide transistor is made of metal oxide semiconductor (Oxide).
  • LTPS low temperature polysilicon
  • Oxide metal oxide semiconductor
  • Low-temperature polysilicon transistors have the advantages of high mobility and fast charging, while oxide transistors have the advantages of low leakage current.
  • Low-temperature polysilicon transistors and metal oxide transistors are integrated on a display substrate to form low-temperature polycrystalline oxide (Low Temperature Polycrystalline Oxide). , referred to as LTPO) display substrate, can take advantage of the advantages of both, can achieve low-frequency driving, can reduce power consumption, and can improve display quality.
  • LTPO Low Temperature Polycrystalline Oxide
  • FIG. 6 is a working timing diagram of a pixel driving circuit.
  • the following describes an exemplary embodiment of the present disclosure through the working process of the pixel driving circuit illustrated in Figure 5.
  • the pixel driving circuit in Figure 5 includes 8 transistors (first transistor T1 to eighth transistor T8) and 1 storage capacitor C.
  • the first to seventh transistors T1 to T7 are all P-type transistors, and the eighth transistor T8 is an N-type transistor.
  • the working process of the pixel driving circuit may include:
  • the first phase A1 is called the reset phase.
  • the signal of the second scanning signal line S2 is a low-level signal, and the signals of the first scanning signal line S1, the third scanning signal line S3 and the light-emitting signal line E are high-level signals.
  • the first transistor T1 is turned on.
  • the eighth transistor T8 is turned on.
  • the signal of the first initial signal line INIT1 The first transistor T1 and the eighth transistor T8 are provided to the second node N2 to initialize (reset) the storage capacitor C and clear the original charge in the storage capacitor.
  • the signal of the second scanning signal line S2 is a low-level signal, turning on the seventh transistor T7.
  • the signal of the second initial signal line INIT2 is provided to the first pole of the OLED to initialize (reset) the first pole of the OLED. Clear its internal pre-stored voltage, complete initialization, and ensure that the OLED does not emit light.
  • the signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals, causing the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 to turn off. At this stage, the OLED Not glowing.
  • the second stage A2 is called the data writing stage or the threshold compensation stage.
  • the signal of the first scanning signal line S1 is a low-level signal
  • the signals of the second scanning signal line S2, the third scanning signal line S3 and the light-emitting signal line E is a high-level signal
  • the data signal line D outputs data voltage.
  • the third transistor T3 is turned on.
  • the signal of the first scanning signal line S1 is a low-level signal
  • the second transistor T2 and the fourth transistor T4 are turned on.
  • the eighth transistor T8 is turned on.
  • the second transistor T2, the fourth transistor T4, and the eighth transistor T8 are turned on so that the data voltage output by the data signal line D passes through the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor.
  • T2 the turned-on eighth transistor T8 is provided to the second node N2, and the difference between the data voltage output by the data signal line D and the threshold voltage of the third transistor T3 is charged into the storage capacitor C.
  • the second terminal of the storage capacitor C ( The voltage of the second node N2) is Vd-
  • the signal of the second scanning signal line S2 is a high-level signal, causing the first transistor T1 and the seventh transistor T7 to be turned off.
  • the signal of the light-emitting signal line E is a high-level signal, causing the fifth transistor T5 and the sixth transistor T6 to be turned off.
  • the third stage A3 is called the light-emitting stage.
  • the signals of the light-emitting signal line E and the third scanning signal line S3 are low-level signals, and the signals of the first scanning signal line S1 and the second scanning signal line S2 are high-level signals.
  • the signal of the light-emitting signal line E is a low-level signal, causing the fifth transistor T5 and the sixth transistor T6 to be turned on.
  • the power supply voltage output by the first power supply line VDD passes through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6.
  • the transistor T6 provides a driving voltage to the first pole of the OLED to drive the OLED to emit light.
  • the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the second node N2 is Vdata-
  • I is the driving current flowing through the third transistor T3, that is, the driving current that drives the OLED
  • K is a constant
  • Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3
  • Vth is the third transistor T3.
  • Vd is the data voltage output by the data signal line D
  • Vdd is the power supply voltage output by the first power supply line VDD.
  • Exemplary embodiments of the present disclosure provide a display substrate that adopts a structure in which data connection lines are located in the display area (Fanout in AA, FIAA for short).
  • the first ends of the plurality of data connection lines are correspondingly connected to the integrated circuits in the binding area.
  • the second end of each data connection line extends from the binding area to the display area, and is correspondingly connected to a plurality of data signal lines in the display area. Since there is no need to set fan-shaped diagonal lines in the binding area, the width of the fan-out area is reduced, effectively reducing the width of the bottom border.
  • the display substrate may include a driving circuit layer disposed on the substrate, a light-emitting structure layer disposed on the side of the driving circuit layer away from the base, and a light-emitting structure layer disposed on the side of the light-emitting structure layer away from the base.
  • Encapsulation structural layer In a plane parallel to the display substrate, the display substrate may at least include a display area, a binding area located on one side of the display area, and a frame area located on other sides of the display area.
  • the driving circuit layer of the display area may include a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, and at least one circuit unit may include a pixel driving circuit configured to provide the connected The light-emitting device outputs a corresponding current.
  • the light-emitting structure layer of the display area may include a plurality of sub-pixels constituting a pixel array. At least one sub-pixel may include a light-emitting device. The light-emitting device is connected to the pixel driving circuit of the corresponding circuit unit. The light-emitting device is configured to respond to the output of the connected pixel driving circuit. The current emits light with corresponding brightness.
  • the sub-pixels mentioned in this disclosure refer to areas divided according to light-emitting devices, and the circuit units mentioned in this disclosure refer to areas divided according to pixel driving circuits.
  • the orthographic projection position of the sub-pixel on the substrate may correspond to the orthographic projection position of the circuit unit on the substrate, or the orthographic projection position of the sub-pixel on the substrate corresponds to the orthographic projection position of the circuit unit on the substrate. The positions may not correspond.
  • an exemplary embodiment of the present disclosure shows that the substrate may include a shielding conductive layer disposed on the substrate and a functional structural layer disposed on a side of the shielding conductive layer away from the substrate, and the shielding conductive layer at least Including a first connection line, the functional structure layer includes at least a second connection line and a data signal line; in a plane parallel to the display substrate, the display substrate includes a plurality of unit rows and a plurality of unit columns.
  • At least one circuit unit includes a pixel drive circuit
  • the data signal line is connected to a plurality of pixel drive circuits of one unit column, the data signal line is configured to provide a data signal to the pixel drive circuit
  • the The second connection line is connected to the first connection line, and the data signal line is connected to the second connection line.
  • the functional structure layer includes a plurality of conductive layers, the second connection line and the data signal line are provided on different conductive layers, and the second connection line passes through a first overlapping via hole. Connected to the first connection line, the data signal line is connected to the second connection line through a second overlapping via hole.
  • the display substrate on a plane parallel to the display substrate, includes a display area and a binding area located on one side of the display area in the second direction, the binding area at least includes lead lines ;
  • the first end of the first connection line is connected to the lead-out line, and the second end of the first connection line extends to the display area and is connected to the second through the first overlapping via hole.
  • the first end of the connection line is connected, and the second end of the second connection line extends along the first direction and is connected to the data signal line through the second overlapping via hole, and the first direction is connected to the data signal line.
  • the second direction crosses.
  • the pixel driving circuit includes a storage capacitor and a plurality of transistors; on a plane perpendicular to the display substrate, the functional structure layer at least includes a layer disposed on the shielding conductive layer away from the substrate.
  • the second conductive layer at least includes the second plate of the storage capacitor, the fourth conductive layer at least includes the second connection line, and the fifth conductive layer at least includes the data signal line.
  • the plurality of transistors includes at least one polysilicon transistor and at least one oxide transistor
  • the functional structure layer further includes a first semiconductor layer and a second semiconductor layer
  • the first semiconductor layer is disposed at between the shielding conductive layer and the first conductive layer, the first semiconductor layer including the active layer of the polysilicon transistor, the second semiconductor layer being disposed between the second conductive layer and the third conductive layer
  • the second semiconductor layer includes an active layer of the oxide transistor.
  • the display substrate may include a display area 100, a binding area 200 located on one side of the display area 100, and a frame area 300 located on other sides of the display area 100.
  • the display area 100 may include at least a plurality of circuit units.
  • a plurality of data signal lines 60 and a plurality of data connection lines 70 the binding area 200 may include at least a lead line area 210
  • the lead line area 210 may include a plurality of lead lines 220 .
  • the plurality of circuit units may form a plurality of unit rows and a plurality of unit columns.
  • Each unit row may include a plurality of circuit units sequentially arranged along the first direction
  • the second direction Y is arranged sequentially.
  • Each unit column may include a plurality of circuit units arranged sequentially along the second direction Y.
  • the plurality of unit columns may be arranged sequentially along the first direction X.
  • the first direction X and the second direction Y cross.
  • the second direction Y may be an extending direction (vertical direction) of the data signal line, and the first direction X may be perpendicular to the second direction Y.
  • the data signal line 60 may be in the shape of a line extending along the second direction Y.
  • a plurality of data signal lines 60 are sequentially arranged at set intervals in the first direction X, and each data signal line 60 Connected to the pixel driving circuits of multiple circuit units in one unit column.
  • the plurality of data connection lines 70 may be located in an area on one side of the display area close to the binding area 200, and the first ends of the plurality of data connection lines 70 are correspondingly connected to the plurality of lead lines 220 of the lead line area 210. , after the second ends of the plurality of data connection lines 70 extend toward the direction of the display area 10, they are connected correspondingly to the plurality of data signal lines 60, so that the plurality of data signal lines 60 in the display area 100 pass through the plurality of data signal lines 60 in the display area 100.
  • the data connection line 70 is connected correspondingly to the plurality of lead lines 220 in the binding area 200 .
  • the number of data connection lines in the display area may be the same as the number of data signal lines, and each data signal line is connected to a lead-out line through a data connection line.
  • the number of data connection lines in the display area may be less than the number of data signal lines.
  • FIG. 8 is a schematic diagram of a connection between a data connection line and a data signal line according to an exemplary embodiment of the present disclosure.
  • the data connection line 70 may include a first connection line 71 and a second connection line 72 , and the shape of the first connection line 71 may be such that the main body portion extends along the second direction Y.
  • Line shape, the shape of the second connection line 72 may be a line shape with the main part extending along the first direction X, and the data signal line 60 may be a line shape extending along the second direction Y.
  • a extending along direction B means that A may include a main part and a secondary part connected to the main part.
  • the main part is a line, line segment or bar-shaped body, the main part extends along direction B, and the main part
  • the length extending in direction B is greater than the length of the secondary portion extending in other directions.
  • “A extends along direction B” means "the main body part of A extends along direction B".
  • the second direction Y may be a direction from the display area to the binding area, and the opposite direction of the second direction Y may be a direction from the binding area to the display area.
  • the display substrate may include a shielding conductive layer disposed on the substrate and a functional structure layer disposed on a side of the shielding conductive layer away from the substrate, the first connection line 71 may be disposed in the shielding conductive layer, and the data signal line 60 and the second connection line 72 may be provided in the functional structure layer.
  • the functional structure layer may include multiple conductive layers, the second connection line 72 and the data signal line 60 may be disposed on different conductive layers, and the second connection line is connected to the first through the first overlapping via K1
  • the connection line 71 is connected, and the data signal line 60 can be connected to the second connection line 72 through the second overlapping via K2.
  • the first connection lines 71 may be provided between adjacent unit columns.
  • the first end of the first connection line 71 is connected to the lead line 220 of the lead line area 210 , and the second end of the first connection line 71 extends toward the display area 100 along the opposite direction of the second direction Y. Then, it is connected to the first end of the second connection line 72 through the first overlapping via hole K1. After the second end of the second connection line 72 extends along the first direction X or the opposite direction of the first direction X, it passes through the first end of the second connection line 72.
  • the two overlapping vias K2 are connected to the data signal line 60 .
  • the end of the first connection line 71 close to the second connection line 72 may be connected with a first connection block, and the shape of the first connection block may be along the second connection line 72 .
  • the orthographic projection of the first connection block on the substrate at least partially overlaps with the orthographic projection of the second connection line 72 on the substrate.
  • the second connection line 72 passes through the first overlapping via hole K1 and is connected to the first connection line 72 . Connection block connection.
  • a second connection block is connected to an end of the second connection line 72 close to the first connection line 71 .
  • the shape of the second connection block may be a strip shape extending along the second direction Y.
  • the second connection block The orthographic projection of the block on the substrate at least partially overlaps the orthographic projection of the first connection line 71 on the substrate, and the second connection block is connected to the first connection line 71 through the first overlapping via hole K1.
  • the orthographic projection of the first connection block on the substrate at least partially overlaps the orthographic projection of the second connection block on the substrate, and the second connection block is connected to the first connection block through the first overlapping via hole K1 connect.
  • the second connection line 72 may include at least a first sub-line, a second sub-line, a third sub-line and a fourth sub-line, and the first end of the first sub-line is connected to the first connection line 71 The second end is connected. After the second end of the first sub-line extends along the opposite direction of the second direction Y, it is connected to the first end of the second sub-line. The second end of the second sub-line extends along the first direction X. Or after extending in the opposite direction of the first direction After the second end of the fourth sub-line extends along the first direction X or the opposite direction of the first direction X, it is connected to the data signal line 60 .
  • the first sub-line may be disposed between adjacent unit columns.
  • the shape of the second sub-line may be a fold line extending along the first direction X or the opposite direction of the first direction X, and may include at least one protruding segment protruding toward the binding area.
  • the third sub-line may be disposed between adjacent cell columns.
  • the functional structure layer may at least include a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer disposed on a side of the shielding conductive layer away from the substrate.
  • the first conductive layer The conductive layer may include at least a first plate of the storage capacitor and gate electrodes of the plurality of transistors
  • the second conductive layer may include at least a second plate of the storage capacitor
  • the fourth conductive layer may include at least a second connection line 72
  • a fifth The conductive layer may include at least the data signal line 60 .
  • the plurality of transistors of the pixel driving circuit may include at least one polysilicon transistor and at least one oxide transistor
  • the functional structure layer may further include a first semiconductor layer and a second semiconductor layer
  • the first semiconductor layer may be disposed on between the shielding conductive layer and the first conductive layer
  • the first semiconductor layer may include an active layer of a polysilicon transistor
  • the second semiconductor layer may be disposed between the second conductive layer and the third conductive layer
  • the second semiconductor layer may include an oxide The active layer of the physical transistor.
  • the functional structure layer may also include multiple insulating layers, and the multiple insulating layers may be respectively provided between: the first conductive layer and the first semiconductor layer, and between the first semiconductor layer and the second conductive layer, between the second conductive layer and the second semiconductor layer, between the second semiconductor layer and the third conductive layer, between the third conductive layer and the fourth conductive layer, and between the fourth conductive layer and the fifth conductive layer.
  • connection method between the data connection line and the data signal line may be as shown in FIG. 7a or as shown in FIG. 7b, which is not limited in this disclosure.
  • the following is an exemplary description through the preparation process of the display substrate.
  • the "patterning process" mentioned in this disclosure includes processes such as coating of photoresist, mask exposure, development, etching, and stripping of photoresist for metal materials, inorganic materials, or transparent conductive materials.
  • organic materials it includes Processes such as coating of organic materials, mask exposure and development.
  • Deposition can use any one or more of sputtering, evaporation, and chemical vapor deposition.
  • Coating can use any one or more of spraying, spin coating, and inkjet printing.
  • Etching can use dry etching and wet etching. Any one or more than 8 types of engravings are not limited by this disclosure.
  • Thin film refers to a thin film produced by depositing, coating or other processes of a certain material on a substrate. If the "thin film” does not require a patterning process during the entire production process, the “thin film” can also be called a “layer.” If the "thin film” requires a patterning process during the entire production process, it will be called a “thin film” before the patterning process and a “layer” after the patterning process. The “layer” after the patterning process contains at least one "pattern”. “A and B are arranged on the same layer” mentioned in this disclosure means that A and B are formed simultaneously through the same patterning process, and the “thickness” of the film layer is the size of the film layer in the direction perpendicular to the display substrate.
  • the orthographic projection of B is within the range of the orthographic projection of A
  • the orthographic projection of A includes the orthographic projection of B means that the boundary of the orthographic projection of B falls within the orthographic projection of A. within the bounds of A, or the bounds of the orthographic projection of A overlap with the bounds of the orthographic projection of B.
  • the preparation process of the display substrate may include the following operations.
  • forming the shielding conductive layer pattern may include: depositing a shielding film on a substrate, patterning the shielding film through a patterning process, and forming a shielding conductive layer pattern on the substrate, as shown in Figures 9a and 9b , Figure 9a illustrates the shielding conductive layer structure with the first connection line region, and Figure 9b illustrates the shielding conductive layer structure without the first connection line region.
  • the shielding conductive layer pattern may include at least the first connection line 71 , the shielding electrode 80 and the first shielding connection line 81 .
  • the shielding electrode 80 may be rectangular in shape and may be disposed in each circuit unit.
  • the shielding electrode 80 is configured to shield the driving transistor of the pixel driving circuit and reduce the impact of light on the electrical characteristics of the driving transistor. Influence.
  • the shielding electrode 80 may also be configured to suppress the accumulation of electrons generated by impact ionization inside the channel and to reduce the accumulation of Joule heat in the channel.
  • the shape of the first shielding connection line 81 may be a straight line extending along the second direction Y, and the first shielding connection line 81 is configured to connect with a plurality of shielding electrodes 80 in one unit column.
  • the shape of the first connecting line 71 may be a strip shape extending along the second direction Y.
  • the first end of the first connecting line 71 is connected to the leading line in the binding area.
  • the first connecting line 71 The second end of 71 extends from the binding area to the display area and is connected to the second connection line formed subsequently.
  • the second end of the first connection line 71 (the end away from the binding area) is provided with a first connection block 71-1, and the shape of the first connection block 71-1 may be along the second
  • the first connection block 71-1 is configured to be connected to the second connection line through the first overlapping via hole formed subsequently.
  • the first connection line 71 may be disposed between adjacent unit columns, that is, the first connection line 71 may be disposed between adjacent circuit units in the first direction X.
  • a first connection line 71 may be disposed between the circuit unit of the N+1th column and the circuit unit of the N+1th column.
  • another first connection line 71 may be provided between the circuit unit of the N+2th column and the circuit unit of the N+3th column.
  • the shielding conductive layer pattern may include at least the first connection line 71 , the shielding electrode 80 , the first shielding connection line 81 and the second shielding connection line 82 .
  • the shielding electrode 80 and the first shielding connection line 81 in the region where the first connection line is not provided may be substantially the same as the region in which the first connection line is provided.
  • the shape of the second shielding connection line 82 may be a straight line extending along the first X direction Y, and the second shielding connection line 82 is configured to communicate with the plurality of shielding electrodes 80 in one unit row. connect.
  • a shielding layer network with a mesh-like connected structure can be formed, which is beneficial to improving the electrical performance of the transistor.
  • the shielding conductive layer may be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or
  • the above-mentioned metal alloy material may have a single-layer structure or a multi-layer composite structure.
  • the shielding conductive layer may adopt a multi-layer composite structure of Ti-Al-Ti
  • the thickness of the first titanium layer (bottom layer) may be approximately 40 nm to 60 nm
  • the thickness of the aluminum layer may be approximately 250 nm to 550 nm
  • the thickness of the second titanium layer (upper layer) may be approximately 20 nm to 40 nm.
  • the thickness of the first titanium layer (bottom layer) may be approximately 50 nm
  • the thickness of the aluminum layer may be approximately 450 nm
  • the thickness of the second titanium layer (upper layer) may be approximately 30 nm.
  • forming the first semiconductor layer pattern may include: sequentially depositing a first insulating film and a first semiconductor film on the substrate, patterning the first semiconductor film through a patterning process, and forming a first semiconductor film covering the substrate.
  • the insulating layer, and the first semiconductor layer pattern disposed on the first insulating layer, are shown in FIG. 10 .
  • the first semiconductor layer pattern may include the first active layer 11 of the first transistor T1 to the seventh active layer 17 of the seventh transistor T7 provided in each circuit unit, and the The first active layer 11 to the seventh active layer 17 are an integral structure connected to each other.
  • the second active layer 12 and the sixth active layer 16 may be located on the same side of the third active layer 13 in this circuit unit, and the fourth active layer 14,
  • the fifth active layer 15 and the seventh active layer 17 may be located on the same side of the third active layer 13 in this circuit unit, and the second active layer 12 and the fourth active layer 14 may be located on the third side of this circuit unit. different sides of the active layer 13 .
  • the first active layer 11 , the second active layer 12 and the fourth active layer 14 in the M-th row circuit unit may be located in the third active layer 13 in this circuit unit away from the M+1-th circuit unit.
  • the fifth active layer 15, the sixth active layer 16 and the seventh active layer 17 in the Mth row circuit unit may be located in the third active layer 13 of this circuit unit close to the M+th 1 side of row circuit unit.
  • the third active layer 13 may be in an “ ⁇ ” shape, and the first active layer 11 , the second active layer 12 , the fourth active layer 14 to the seventh active layer 17 are The shape can be in the shape of an "I".
  • the orthographic projection of the third active layer 13 on the substrate may be located within the range of the orthographic projection of the shielding electrode 80 on the substrate.
  • the active layer of each transistor may include a first region, a second region, and a channel region between the first region and the second region.
  • the second region 11-2 of the first active layer 11 may serve as the first region 12-1 of the second active layer 12, and the first region 13-1 of the third active layer 13 may Simultaneously serving as the second region 14-2 of the fourth active layer 14 and the second region 15-2 of the fifth active layer 15, the second region 13-2 of the third active layer 13 may simultaneously serve as the second active layer 14-2.
  • the second region 12-2 of the layer 12 and the first region 16-1 of the sixth active layer 16, and the second region 16-2 of the sixth active layer 16 can simultaneously serve as the second region of the seventh active layer 17. 17-2, the first region 11-1 of the first active layer 11, the first region 14-1 of the fourth active layer 14, the first region 15-1 of the fifth active layer 15 and the seventh active layer 17-2.
  • the first zone 17-1 of the layer 17 can be provided separately.
  • the first regions 15 - 1 of the fifth active layer 15 in two adjacent circuit units may be connected to each other.
  • the first area 15-1 of the fifth active layer 15 in the N-2th column and the first area 15-1 of the fifth active layer 15 in the N-1th column are connected to each other, and the fifth active layer 15 in the N-th column is connected to each other.
  • the first area 15-1 of the active layer 15 and the first area 15-1 of the fifth active layer 15 of the N+1th column are connected to each other. Since the first area of the fifth active layer in each circuit unit is configured to be connected to the subsequently formed first power line, the first areas of the fifth active layer of adjacent circuit units are formed into an interconnected body.
  • the structure can ensure that the first pole of the fifth transistor T5 of adjacent circuit units has the same potential, which is conducive to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.
  • the first regions 17 - 1 of the seventh active layer 17 in two adjacent circuit units in one unit row may be connected to each other.
  • the first area 17-1 of the seventh active layer 17 in the N-1th column and the first area 17-1 of the seventh active layer 17 in the Nth column are connected to each other, and the seventh active layer 17 in the N+1th column is connected to each other.
  • the first area 17-1 of the active layer 17 and the first area 17-1 of the seventh active layer 17 of the N+2th column are connected to each other. Since the first area of the seventh active layer in each circuit unit is configured to be connected to the subsequently formed second initial signal line, the first areas of the seventh active layer of adjacent circuit units are formed to be connected to each other.
  • the integrated structure can ensure that the first area of the seventh active layer of adjacent circuit units has the same potential, which is conducive to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.
  • the first semiconductor layer may be made of polysilicon (p-Si), that is, the first to seventh transistors are LTPS thin film transistors.
  • patterning the first semiconductor film through a patterning process may include: first forming an amorphous silicon (a-si) film on the first insulating film, and performing dehydrogenation treatment on the amorphous silicon film , the dehydrogenated amorphous silicon film is crystallized to form a polycrystalline silicon film. Subsequently, the polysilicon film is patterned to form a first semiconductor layer pattern.
  • forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on the substrate on which the foregoing pattern is formed, patterning the first conductive film through a patterning process, and forming The second insulating layer covering the first semiconductor layer pattern and the first conductive layer pattern disposed on the second insulating layer are shown in Figures 11a and 11b.
  • Figure 11b is a schematic plan view of the first conductive layer in Figure 11a.
  • the first conductive layer may be referred to as a first gate metal (GATE1) layer.
  • the first conductive layer pattern of each circuit unit at least includes: a first scanning signal line 21, a second scanning signal line 22, a light emitting control line 23, and a first plate 24 of a storage capacitor.
  • the shape of the first plate 24 may be a rectangle, and the corners of the rectangle may be chamfered.
  • the orthographic projections of the layers on the substrate at least partially overlap.
  • the first plate 24 may simultaneously serve as a plate of the storage capacitor and a gate electrode of the third transistor T3.
  • the shape of the first scanning signal line 21 may be a line shape with the main body extending along the first direction X, and the first scanning signal line 21 in the Mth row circuit unit may be located in the On the side of one plate 24 away from the circuit unit of the M+1th row, the area where the first scanning signal line 21 overlaps with the second active layer of this circuit unit serves as the gate electrode of the second transistor T2.
  • the first scanning signal line The area 21 overlapping with the fourth active layer of this circuit unit serves as the gate electrode of the fourth transistor T4.
  • the shape of the second scanning signal line 22 may be a polygonal shape with the main part extending along the first direction X, and the second scanning signal line 22 in the Mth row of circuit units may be located in the th One plate 24 is close to the side of the circuit unit of the M+1th row.
  • the second scanning signal line 22 is connected to a gate block 22-1 extending in a direction away from the first plate 24.
  • the second scanning signal line 22 is connected to the second scanning signal line 22.
  • the area where the seventh active layer of the circuit unit overlaps is used as the gate electrode of the seventh transistor T7, and the area where the gate block 22-1 overlaps with the first active layer of the circuit unit in the next row serves as the gate electrode of the first transistor T1. .
  • the second scanning signal line 22 in the M-th row circuit unit simultaneously drives the seventh transistor T7 in the M-th row circuit unit and the first transistor T1 in the M+1-th row circuit unit.
  • the shape of the light-emitting control line 23 may be a line shape with the main body portion extending along the first direction X, and the light-emitting control line 23 may be located between the first plate 24 and the second scanning signal line 22.
  • the area where the control line 23 overlaps with the fifth active layer of this circuit unit serves as the gate electrode of the fifth transistor T5
  • the area where the light-emitting control line 23 overlaps with the sixth active layer of this circuit unit serves as the gate electrode of the sixth transistor T6. gate electrode.
  • the first conductive layer can be used as a shield to perform a conductive process on the first semiconductor layer, and the first semiconductor layer in the area blocked by the first conductive layer forms the first transistor.
  • the channel region of T1 to the seventh transistor T7 and the first semiconductor layer in the area not blocked by the first conductive layer are conductive, that is, the first and second regions of the first transistor T1 to the seventh active layer are both conductive. change.
  • forming the second conductive layer pattern may include: sequentially depositing a third insulating film and a second conductive film on the substrate on which the foregoing pattern is formed, and patterning the second conductive film using a patterning process to form The third insulating layer covering the first conductive layer, and the second conductive layer pattern disposed on the third insulating layer, are shown in Figures 12a and 12b.
  • Figure 12b is a schematic plan view of the second conductive layer in Figure 12a.
  • the second conductive layer may be referred to as a second gate metal (GATE2) layer.
  • GATE2 second gate metal
  • the second conductive layer pattern of each circuit unit at least includes: a third shielding connection line 31 , a second plate 32 of the storage capacitor, and a plate connection line 33 .
  • the outline of the second electrode plate 32 may be rectangular, and the corners of the rectangular shape may be chamfered.
  • the orthographic projection of the second electrode plate 32 on the base is consistent with the orthographic projection of the first electrode plate 24 on the base.
  • the orthographic projection at least partially overlaps, the second plate 32 can serve as another plate of the storage capacitor, and the first plate 24 and the second plate 32 constitute the storage capacitor of the pixel driving circuit.
  • the plate connection line 33 may be disposed on one side of the second plate 32 in the first direction X or on a side in the opposite direction of the first direction X, so that two adjacent circuit units in one unit row
  • the second plates 32 are connected to each other.
  • the second electrode plate 32 in the N-1th column and the second electrode plate 32 in the Nth column may be connected to each other through the electrode plate connection line 33 .
  • the second electrode plate 32 in the Nth column and the second electrode plate 32 in the N+1th column are connected to each other through the electrode plate connection line 33 .
  • the integrated structure of the second pole plate 32 can Multiplexing as a power signal line can ensure that multiple second plates 32 in a unit row have the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.
  • the second electrode plate 32 is provided with an opening 34 .
  • the opening 34 may be rectangular in shape and may be located in the middle of the second electrode plate 32 , so that the second electrode plate 32 forms an annular structure.
  • the opening 34 exposes the third insulating layer covering the first electrode plate 24 , and the orthographic projection of the first electrode plate 24 on the substrate includes the orthographic projection of the opening 34 on the substrate.
  • the opening 34 is configured to accommodate a subsequently formed first via hole.
  • the first via hole is located within the opening 34 and exposes the first plate 24 so that the subsequently formed second via hole of the first transistor T1
  • the pole is connected to the first pole plate 24 .
  • the shape of the third shielding connection line 31 may be a line shape with the main body portion extending along the first direction
  • the diode plate 32 is on the side away from the circuit unit of the M+1th row.
  • the third shielding connection line 31 in the M-th row circuit unit may be located on the side of the first scanning signal line 21 of this circuit unit away from the second plate 32 .
  • the third shielding connection line 31 may be a straight line of unequal width.
  • the width of the position where the third shielding connection line 31 overlaps with the subsequently formed eighth active layer may be greater than the width of other positions.
  • the third shielding connection line at a wider position may 31 can be used as the lower gate electrode of the eighth transistor and at the same time as a shielding layer of the eighth transistor to shield the channel region of the eighth transistor and ensure the electrical performance of the eighth transistor.
  • forming the second semiconductor layer pattern may include: sequentially depositing a fourth insulating film and a second semiconductor film on the substrate on which the foregoing pattern is formed, patterning the second semiconductor film through a patterning process, and forming The fourth insulating layer covering the base, and the second semiconductor layer pattern disposed on the fourth insulating layer, are shown in Figures 13a and 13b.
  • Figure 13b is a schematic plan view of the second semiconductor layer in Figure 13a.
  • the second semiconductor layer pattern of each circuit unit includes at least: the eighth active layer 18 of the eighth transistor T8.
  • the shape of the eighth active layer 18 may be an "I" shape, and the orthographic projection of the eighth active layer 18 on the substrate at least partially intersects the orthographic projection of the third shielding connection line 31 on the substrate.
  • the first region 18 - 1 of the eighth active layer 18 may be located on a side of the third shielding connection line 31 away from the second plate 32
  • the second region 12 - 1 of the eighth active layer 18 2 may be located on the side of the third shielding connection line 31 close to the second plate 32 .
  • the second semiconductor layer may be made of oxide, that is, the eighth transistor T8 is an oxide transistor.
  • the second semiconductor film may be indium gallium zinc oxide (IGZO), and the electron mobility of indium gallium zinc oxide (IGZO) is higher than that of amorphous silicon.
  • forming the third conductive layer pattern may include: sequentially depositing a fifth insulating film and a third conductive film on the substrate on which the foregoing pattern is formed, and patterning the third conductive film using a patterning process to form The fifth insulating layer covering the second semiconductor layer and the third conductive layer pattern disposed on the fifth insulating layer are shown in Figures 14a and 14b.
  • Figure 14b is a schematic plan view of the third conductive layer in Figure 14a.
  • the third conductive layer may be referred to as a third gate metal (GATE3) layer.
  • the third conductive layer pattern of each circuit unit includes at least: a third scanning signal line 41 and a first initial signal line 42 .
  • the shape of the third scanning signal line 41 may be a line shape with the main body portion extending along the first direction A scanning signal line 21 is on the side away from the circuit unit of the M+1th row, and the area where the third scanning signal line 41 of each circuit unit overlaps with the eighth active layer serves as the upper gate electrode of the eighth transistor T8.
  • the shape of the first initial signal line 42 may be a line shape with the main body portion extending along the first direction
  • the first initial signal line 42 is configured to be connected to the first region of the first active layer through the first pole of the subsequently formed first transistor T1.
  • Form a sixth insulating layer pattern may include: depositing a sixth insulating film on the substrate on which the foregoing pattern is formed, patterning the sixth insulating film using a patterning process, and forming a pattern covering the third conductive layer.
  • the sixth insulating layer is provided with multiple via holes, as shown in Figure 15.
  • the plurality of via holes of each circuit unit at least include: a first via hole V1, a second via hole V2, a third via hole V3, a fourth via hole V4, a fifth via hole V5, and a third via hole V4.
  • the orthographic projection of the first via hole V1 on the substrate is within the range of the orthographic projection of the opening 34 on the substrate, and the sixth insulating layer, the fifth insulating layer, and the third insulating layer in the first via hole V1
  • the fourth insulating layer and the third insulating layer are etched away to expose the surface of the first plate 24.
  • the first via hole V1 is configured to allow the second electrode of the subsequently formed eighth transistor T8 to pass through the via hole and the first electrode. Board 24 connection.
  • the second via hole V2 is located within the range of the orthographic projection of the second plate 32 on the substrate, and the sixth insulating layer, the fifth insulating layer and the fourth insulating layer in the second via hole V2 is etched away to expose the surface of the second electrode plate 32 , and the second via hole V2 is configured so that the first electrode of the subsequently formed fifth transistor T5 is connected to the second electrode plate 32 through the via hole.
  • the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the first region of the fifth active layer on the substrate, and the sixth insulating layer in the third via hole V3 , the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer are etched away to expose the surface of the first region of the fifth active layer, and the third via V3 is configured to enable subsequent formation
  • the first electrode of the fifth transistor T5 is connected to the first region of the fifth active layer through the via hole.
  • the orthographic projection of the fourth via V4 on the substrate is located within the range of the orthographic projection of the second area of the sixth active layer (also the second area of the seventh active layer) on the substrate.
  • the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the fourth via hole V4 are etched away, exposing the surface of the second region of the sixth active layer
  • the fourth via V4 is configured to allow the second electrode of the subsequently formed sixth transistor T6 (also the second electrode of the seventh transistor T7) to pass through the via hole and the second region of the sixth active layer (also the seventh second area of the active layer) connection.
  • the orthographic projection of the fifth via hole V5 on the substrate is located within the range of the orthographic projection of the first region of the fourth active layer on the substrate, and the sixth insulating layer in the fifth via hole V5 , the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer are etched away to expose the surface of the first region of the fourth active layer, and the fifth via V5 is configured to enable subsequent formation
  • the first electrode of the fourth transistor T4 is connected to the first region of the fourth active layer through the via hole.
  • the orthographic projection of the sixth via hole V6 on the substrate is located within the range of the orthographic projection of the first region of the eighth active layer on the substrate, and the sixth insulating layer in the sixth via hole V6 and the fifth insulating layer is etched away, exposing the surface of the first region of the eighth active layer, and the sixth via hole V6 is configured to allow the first pole of the subsequently formed eighth transistor T8 to pass through the via hole and the first electrode of the eighth transistor T8.
  • the first zone of eight active layers is connected.
  • the orthographic projection of the seventh via hole V7 on the substrate is within the range of the orthographic projection of the first region of the seventh active layer on the substrate, and the sixth insulating layer in the seventh via hole V7 , the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer are etched away to expose the surface of the first region of the seventh active layer, and the seventh via V7 is configured to enable subsequent formation
  • the second initial signal line is connected to the first region of the seventh active layer through the via hole.
  • the orthographic projection of the eighth via hole V8 on the substrate is located within the range of the orthographic projection of the first region of the first active layer on the substrate, and the sixth insulating layer in the eighth via hole V8 , the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer are etched away to expose the surface of the first region of the first active layer, and the eighth via hole V8 is configured to enable subsequent formation
  • the first pole of the first transistor T1 is connected to the first region of the first active layer through the via hole.
  • the orthographic projection of the ninth via hole V9 on the substrate is within the range of the orthographic projection of the second region of the eighth active layer on the substrate, and the sixth insulating layer in the ninth via hole V9 and the fifth insulating layer is etched away, exposing the surface of the second region of the eighth active layer, and the ninth via hole V9 is configured to allow the second pole of the subsequently formed eighth transistor T8 to pass through the via hole and the second electrode of the eighth transistor T8.
  • the orthographic projection of the tenth via hole V10 on the substrate is located within the range of the orthographic projection of the second area of the first active layer (also the first area of the second active layer) on the substrate.
  • the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the tenth via hole V10 are etched away, exposing the surface of the second region of the first active layer
  • the tenth via hole V10 is configured to allow the second electrode of the subsequently formed first transistor T1 (also the first electrode of the second transistor T2) to pass through the via hole and the second region of the first active layer (also the second The first area of the active layer) is connected.
  • the orthographic projection of the eleventh via hole V11 on the substrate is within the range of the orthographic projection of the first initial signal line 42 on the substrate, and the sixth insulating layer in the eleventh via hole V11 is It is etched away to expose the surface of the first initial signal line 42 , and the eleventh via hole V11 is configured so that the first pole of the subsequently formed first transistor T1 is connected to the first initial signal line 42 through the via hole.
  • the sixth insulating layer provided with a plurality of via holes may also include a twelfth via hole V12 , and the orthographic projection of the twelfth via hole V12 on the substrate is located at the first connection of the first connection line 71 Within the range of the orthographic projection of the block 71-1 on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, the second insulating layer and the first insulating layer in the twelfth via hole V12 The insulating layer is etched away to expose the surface of the first connection block 71-1.
  • the twelfth via V12 can be used as the first overlapping via of the present disclosure.
  • the twelfth via V12 is configured to enable subsequent formation of The second connection line is connected to the first connection block 71-1 through the via hole.
  • forming the fourth conductive layer may include: depositing a fourth conductive film on the substrate on which the foregoing pattern is formed, patterning the fourth conductive film using a patterning process, and forming a layer disposed on the sixth insulating layer.
  • the fourth conductive layer is as shown in Figures 16a and 16b.
  • Figure 16b is a schematic plan view of the fourth conductive layer in Figure 16a.
  • the fourth conductive layer may be referred to as a first source-drain metal (SD1) layer.
  • SD1 first source-drain metal
  • the fourth conductive layer of each circuit unit at least includes: a first connection electrode 51 , a second connection electrode 52 , a third connection electrode 53 , a fourth connection electrode 54 , a fifth connection electrode 55 , The sixth connection electrode 56 and the second initial signal line 57 are connected.
  • the shape of the first connection electrode 51 may be a strip shape with a main body portion extending along the second direction Y, and the first end of the first connection electrode 51 communicates with the first plate through the first via hole V1 24 is connected, the second end of the first connection electrode 51 is connected to the second region of the eighth active layer through the ninth via hole V9, so that the first plate 24 and the second electrode of the eighth transistor T8 have the same potential.
  • the first connection electrode 51 may serve as the second electrode of the eighth transistor T8.
  • the shape of the second connection electrode 52 may be a rectangular shape.
  • the first end of the second connection electrode 52 is connected to the first initial signal line 42 through the eleventh via hole V11 .
  • the second end is connected to the first region of the first active layer through the eighth via V8, so that the first initial voltage transmitted by the first initial signal line 42 is written into the first pole of the first transistor T1.
  • the second connection electrode 52 may serve as the first electrode of the first transistor T1.
  • the shape of the third connection electrode 53 may be a rectangular shape, and the third connection electrode 53 is connected to the first region of the fourth active layer through the fifth via hole V5.
  • the third connection electrode 53 may serve as the first electrode of the fourth transistor T4, and the third connection electrode 53 is configured to be connected to a subsequently formed data signal line.
  • the shape of the fourth connection electrode 54 may be a polygonal shape, the first end of the fourth connection electrode 54 is connected to the second plate 32 through the second via hole V2, and the second end of the fourth connection electrode 54 is The terminal is connected to the first region of the fifth active layer through the third via hole V3.
  • the fourth connection electrode 54 may serve as the first pole of the fifth transistor T5, realizing that the first pole of the fifth transistor T5 and the second plate 32 of the storage capacitor in the circuit unit have the same potential,
  • the fourth connection electrode 54 is configured to be connected to the first power supply line formed later.
  • the fourth connection electrode 54 of the N-2th column and the fourth connection electrode 54 of the N-1th column may be an integral structure connected to each other, and the fourth connection electrode 54 of the N-th column may be an integral structure connected to each other.
  • the connection electrode 54 and the fourth connection electrode 54 in the N+1th column may be an integral structure connected to each other.
  • the fourth connection electrode 54 in each circuit unit is connected to the subsequently formed first power line, by forming the fourth connection electrodes 54 of adjacent circuit units into an integral structure connected to each other, it can be ensured that The fourth connection electrodes 54 of adjacent circuit units have the same potential, so that the first pole of the fifth transistor T5 in the adjacent circuit units has the same potential, and the second plate 32 of the storage capacitor in the adjacent circuit unit has the same potential.
  • the potential is conducive to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.
  • the shape of the fifth connection electrode 55 may be a rectangular shape.
  • the first end of the fifth connection electrode 55 is connected to the second region of the first active layer through the tenth via hole V10.
  • the fifth connection electrode 55 may be in a rectangular shape.
  • the second end of 55 is connected to the first region of the eighth active layer through the sixth via V6.
  • the fifth connection electrode 55 may simultaneously serve as the second electrode of the first transistor T1, the first electrode of the second transistor T2, and the first electrode of the eighth transistor T8.
  • the shape of the sixth connection electrode 56 may be a rectangular shape, and the sixth connection electrode 56 communicates with the second area of the sixth active layer (also the second area of the seventh active layer) through the fourth via hole V4. area) connection.
  • the sixth connection electrode 56 may serve as the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 at the same time, and the sixth connection electrode 56 is configured to be connected to a subsequently formed anode connection electrode.
  • the shape of the second initial signal line 57 may be a straight line with a main body portion extending along the first direction
  • the first regions of the plurality of seventh active layers are connected, and the second initial voltage is written into the plurality of seventh transistors T7 in a unit row.
  • since the second initial signal line 57 is connected to the first areas of all seventh active layers in one unit row it can be ensured that the first poles of all seventh transistors T7 in one unit row have the same
  • the potential is conducive to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.
  • the fourth conductive layer may further include a second connection line 72 , the first end of the second connection line 72 is connected to the first connection line 71 through the twelfth via V12 , and the second connection line 72 The second end is connected to the third connection electrode 53 in the corresponding circuit unit, thereby realizing the connection between the second connection line 72 located in the fourth conductive layer and the first connection line 71 located in the shielding conductive layer.
  • At least one second connection line 72 may include a second connection block 72-1 and a plurality of sub-lines connected in sequence.
  • the plurality of sub-lines may include at least a first sub-line 72-A, a second sub-line 72 -B, third sub-line 72-C and fourth sub-line 72-D.
  • the shape of the second connection block 72-1 may be a strip shape extending along the second direction Y and connected to the second connection line 72.
  • the projection at least partially overlaps with the orthographic projection of the first connection block 71-1 of the first connection line 71 on the substrate, and the second connection block 72-1 is connected to the first connection block 71-1 through the twelfth via hole V12, Therefore, the connection between the first connection line 71 and the second connection line 72 is achieved.
  • the first end of the first sub-line 72-A is connected to the second connection block 72-1, and the second end of the first sub-line 72-A extends along the opposite direction of the second direction Y. , connected to the first end of the second sub-line 72-B. After the second end of the second sub-line 72-B extends along the first direction X or the opposite direction of the first direction X, it is connected to the first end of the third sub-line 72-C. After the second end of the third sub-line 72-C extends along the second direction Y, it is connected to the first end of the fourth sub-line 72-D. The second end of the fourth sub-line 72 -D extends along the first direction X or the opposite direction of the first direction X, and then is connected to the third connection electrode 53 .
  • the electrodes 53 may be an integral structure connected to each other.
  • the first sub-line 72-A may be disposed between adjacent unit columns, that is, the first sub-line 72-A may be disposed between adjacent circuit units in the first direction X.
  • the second sub-line 72-B may be in the shape of a polygonal line extending along the first direction
  • the orthographic projections of the second sub-line 72-B on the substrate at least partially overlap with the orthographic projection of the first initial signal line 42 on the substrate.
  • the second sub-line 72-B may include at least one protruding segment 72-E protruding toward the binding area, and the shape of the protruding segment 72-E may be trapezoidal.
  • the third sub-line 72-C may be disposed between adjacent unit columns, that is, the third sub-line 72-C may be disposed between adjacent circuit units in the first direction X.
  • forming the first flat layer pattern may include: first depositing a seventh insulating film on the substrate on which the foregoing pattern is formed, and then coating the first flat film, and using a patterning process to layer the first flat film and the first flat layer.
  • the seven insulating films are patterned to form a seventh insulating layer covering the pattern of the fourth conductive layer and a first flat layer disposed on the seventh insulating layer. Multiple via holes are provided on the first flat layer, as shown in Figure 17 .
  • the plurality of via holes in each circuit unit at least include: a twenty-first via hole V21, a twenty-second via hole V22, and a twenty-third via hole V23.
  • the orthographic projection of the twenty-first via hole V21 on the substrate is within the range of the orthographic projection of the third connection electrode 53 on the substrate, and the first flat layer in the twenty-first via hole V21 and the seventh insulating layer is etched away to expose the surface of the third connection electrode 53.
  • the twenty-first via hole V21 is configured to allow the subsequently formed data signal line to be connected to the third connection electrode 53 through the via hole.
  • Twenty-one vias V21 can serve as the second overlapping vias of the present disclosure.
  • the orthographic projection of the twenty-second via hole V22 on the substrate is within the range of the orthographic projection of the fourth connection electrode 54 on the substrate, and the first planar layer in the twenty-second via hole V22
  • the seventh insulating layer is etched away to expose the surface of the fourth connection electrode 54
  • the twenty-second via hole V22 is configured to connect the subsequently formed first power line to the fourth connection electrode 54 .
  • the orthographic projection of the twenty-third via hole V23 on the substrate is within the range of the orthographic projection of the sixth connection electrode 56 on the substrate, and the first flat layer in the twenty-third via hole V23
  • the seventh insulating layer is etched away to expose the surface of the sixth connection electrode 56
  • the twenty-third via hole V232 is configured to connect the subsequently formed anode connection electrode to the sixth connection electrode 56 .
  • forming the fifth conductive layer may include: depositing a fifth conductive film on the substrate on which the foregoing pattern is formed, patterning the fifth conductive film using a patterning process, and forming a layer disposed on the first flat layer.
  • the fifth conductive layer is as shown in Figures 18a to 18d.
  • Figure 18a is a schematic diagram after forming a fifth conductive layer pattern.
  • Figure 18b is a plan view of the fifth conductive layer in Figure 18a.
  • Figure 18c is a schematic diagram after forming another fifth conductive layer pattern.
  • a schematic diagram after the pattern of the fifth conductive layer is planted.
  • FIG. 18d is a schematic plan view of the fifth conductive layer in FIG. 18c.
  • the fifth conductive layer may be referred to as a second source-drain metal (SD2) layer.
  • SD2 second source-drain metal
  • the fifth conductive layer of each circuit unit at least includes: a data signal line 60 , an anode connection electrode 61 and a first power supply line 62 .
  • the shape of the data signal line 60 may be a straight line with the main body extending along the second direction Y, and the data signal line 60 is connected to the third connection electrode 53 through the twenty-first via hole V21. Since the third connection electrode 53 is connected to the first area of the fourth active layer through the via hole, the connection between the data signal line 60 and the first electrode of the fourth transistor T4 is realized. The data signal line 60 can write the data signal. The first pole of the fourth transistor T4. At the same time, since the third connection electrode 53 in some circuit units is connected to the second connection line 72, the second connection line 72 is connected to the first connection line 71 through the via hole, and the first connection line 71 is connected to the lead line in the binding area.
  • the lead wire is connected to the integrated circuit, thus realizing the data signal line 60 is connected to the integrated circuit in the binding area through the first connection line 71, the second connection line 72 and the lead wire, and the integrated circuit can output the data signal to the data signal Line 60.
  • the shape of the anode connection electrode 61 may be a rectangular shape, the anode connection electrode 61 is connected to the sixth connection electrode 56 through the twenty-third via hole V23, and the anode connection electrode 61 is configured to connect with the subsequently formed anode. connect.
  • the shape of the first power line 62 may be a polygonal shape with a main body portion extending along the second direction Y, and the first power line 62 is connected to the fourth connection electrode 54 through the twenty-second via hole V22. Since the fourth connection electrode 54 is connected to the second plate 32 and the first area of the fifth active layer through the via holes respectively, the first power line 62 can write the first power signal into the fifth transistor T5. One pole, and the first pole of the fifth transistor T5 and the second plate of the storage capacitor have the same potential.
  • the adjacent first power lines 62 are connected to the same fourth connection electrode 54, so that the adjacent first power lines 62 are connected to the same fourth connection electrode 54.
  • the adjacent first power lines 62 have the same potential, which is helpful to improve the uniformity of the panel, avoid display defects of the display substrate, and ensure the display effect of the display substrate.
  • the first power supply line 62 may be a polygonal line of unequal width, which not only facilitates the layout of the pixel structure, but also reduces parasitic capacitance between the first power supply line and the data signal line.
  • the orthographic projection of the first power line 62 on the substrate may at least partially overlap with the orthographic projection of the first connection electrode 51 on the substrate, so that the first power line 62 may serve as a shielding electrode, which may effectively shield
  • the impact of the data voltage jump on the key nodes in the pixel drive circuit is avoided, thereby preventing the data voltage jump from affecting the potential of the key nodes in the pixel drive circuit, thereby improving the display effect.
  • the orthographic projection of the first power line 62 on the substrate may at least partially overlap with the orthographic projection of the second connection electrode 52 on the substrate, and the orthographic projection of the first power line 62 on the substrate may overlap with the orthographic projection of the first power line 62 on the substrate.
  • the orthographic projections of the five connection electrodes 55 on the substrate at least partially overlap.
  • the structure of the fifth conductive layer in each circuit unit is basically similar to the structure shown in Figures 18a and 18b. The difference is that the structure of the fifth conductive layer in two adjacent circuit units in a unit row is
  • the first power lines 62 may be connected to each other to form an integrated structure of the first power lines 62 in the two unit columns.
  • the first power line 62 in the N-1th column and the first power line 62 in the Nth column may be an integral structure connected to each other.
  • the first power line 62 in the N+1th column and the first power line 62 in the N+2th column may be an integral structure connected to each other.
  • the present disclosure can not only help improve the uniformity of the panel and avoid poor display of the display substrate, but also effectively block the connection between the first connection line and the third
  • the first overlapping via hole of the two connecting lines avoids astigmatism caused by the overlapping via hole and ensures the display quality and display effect of the display substrate.
  • forming the second flat layer pattern may include: coating a second flat film on the substrate on which the foregoing pattern is formed, patterning the second flat film using a patterning process, and forming a covering fifth conductive layer.
  • the second flat layer of the pattern is provided with multiple via holes, as shown in Figure 19.
  • the via hole in each circuit unit includes at least the thirty-first via hole V31.
  • the orthographic projection of the thirty-first via hole V31 on the substrate is within the range of the orthographic projection of the anode connection electrode 61 on the substrate, and the second flat layer in the thirty-first via hole V31 is Removed, the surface of the anode connection electrode 61 is exposed, and the thirty-first via hole V31 is configured to allow a subsequently formed anode to be connected to the anode connection electrode 61 through the via hole.
  • the driver circuit layer is prepared on the substrate.
  • the driving circuit layer may include a plurality of circuit units, and each circuit unit may include a pixel driving circuit, and a first scanning signal line, a second scanning signal line, and a third scanning signal line connected to the pixel driving circuit. Scanning signal lines, light emission control lines, data signal lines, first power supply lines, first initial signal lines and second initial signal lines.
  • the driving circuit layer may include a shielding conductive layer, a first insulating layer, a first semiconductor layer, a second insulating layer, a first conductive layer, and a third insulating layer sequentially disposed on the substrate.
  • the shielding conductive layer may include at least a first connection line
  • the first semiconductor layer may include at least an active layer of the first to seventh transistors
  • the first conductive layer may include at least a gate electrode and a storage capacitor of the first to seventh transistors.
  • the first plate, the second conductive layer may include at least the second plate of the storage capacitor and the lower gate electrode of the eighth transistor
  • the second semiconductor layer may include at least the active layer of the eighth transistor
  • the third conductive layer may at least Comprising an upper gate electrode of the eighth transistor
  • the fourth conductive layer may at least include a second connection line and first and second poles of a plurality of transistors, and the second connection line is connected to the first connection line through a first overlapping via hole.
  • the fifth conductive layer may include at least a data signal line and a first power line, and the data signal line is connected to the second connection line through the second overlapping via hole.
  • the substrate may be a flexible substrate, or may be a rigid substrate.
  • the rigid substrate may include, but is not limited to, one or more of glass and quartz
  • the flexible substrate may be, but is not limited to, polyethylene terephthalate, ethylene terephthalate, polyether ether ketone, One or more of polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.
  • the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked on a glass carrier.
  • the first and second flexible material layers can be made of polyimide (PI), polyethylene terephthalate (PET) or surface-treated polymer soft film.
  • the first and second inorganic materials The material of the layer can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., used to improve the water and oxygen resistance of the substrate.
  • the first and second inorganic material layers are also called barrier layers.
  • the materials of the semiconductor layer Amorphous silicon (a-si) can be used.
  • the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer and the fifth conductive layer may be made of metal materials, such as silver (Ag), copper (Cu), aluminum (Al ) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), which can be a single-layer structure or a multi-layer composite structure, such as Mo/Cu/Mo etc.
  • metal materials such as silver (Ag), copper (Cu), aluminum (Al ) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), which can be a single-layer structure or a multi-layer composite structure, such as Mo/Cu/Mo etc.
  • the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer, the sixth insulating layer and the seventh insulating layer can be made of silicon oxide (SiOx), silicon nitride (SiNx) and Any one or more types of silicon oxynitride (SiON) can be a single layer, multi-layer or composite layer.
  • the first insulating layer may be called a buffer layer
  • the second insulating layer, the third insulating layer, the fourth insulating layer and the fifth insulating layer may be called gate insulating (GI) layers
  • the sixth insulating layer may be called a layer.
  • the seventh insulating layer can be called a passivation (PVX) layer.
  • the first flat layer and the second flat layer may be made of organic materials, such as resin.
  • the pixel driving circuits in two adjacent circuit units in a unit row may be substantially mirror symmetrical with respect to a first center line located between the two adjacent circuit units and along the A straight line extending in the second direction Y.
  • the pixel driving circuit of the N-1th column and the pixel driving circuit of the Nth column may be mirror symmetrical with respect to the first center line.
  • the pixel driving circuit of the Nth column and the pixel driving circuit of the N+1th column may be mirror symmetrical with respect to the first center line.
  • the pixel driving circuits in two adjacent circuit units may be substantially mirror-symmetrical with respect to the first center line and may include any one or more of the following: in two adjacent circuit units in a unit row
  • the first semiconductor layer may be mirror symmetrical with respect to the first center line
  • the first conductive layer in two adjacent circuit units in one unit row may be mirror symmetrical with respect to the first center line
  • the first conductive layer in two adjacent circuit units in one unit row may be mirror symmetrical with respect to the first center line.
  • the second conductive layer in the unit may be mirror symmetrical with respect to the first centerline.
  • the second semiconductor layers in two adjacent circuit units in a unit row may be mirror symmetrical with respect to the first centerline.
  • Two adjacent circuit units in a unit row may be mirror symmetrical with respect to the first centerline.
  • the third conductive layer in one circuit unit may be mirror symmetrical with respect to the first center line, and the fifth conductive layer in two adjacent circuit units in a unit row may be mirror symmetrical with respect to the first center line.
  • the shielding conductive layers in two adjacent circuit units in one unit row may be mirror symmetrical with respect to the first center line.
  • the fourth conductive layer in two adjacent circuit units in one unit row may be mirror symmetrical with respect to the first center line.
  • a light-emitting structure layer may be prepared on the driving circuit layer.
  • the preparation process of the light-emitting structure layer may include the following operations.
  • forming the anode conductive layer pattern may include: depositing an anode conductive film on the substrate on which the foregoing pattern is formed, patterning the anode conductive film using a patterning process, and forming an anode disposed on the third flat layer.
  • the conductive layer, the anode conductive layer may at least include a plurality of anode patterns, as shown in Figures 20a and 20b.
  • Figure 20b is a schematic plan view of the anode conductive layer in Figure 20a.
  • the anode conductive layer adopts a single-layer structure, such as indium tin oxide ITO or indium zinc oxide IZO, or may adopt a multi-layer composite structure, such as ITO/Ag/ITO, etc.
  • the plurality of anode patterns may include a first anode 301A of the red light emitting device, a second anode 301B of the blue light emitting device, a third anode 301C of the first green light emitting device, and a third anode 301C of the second green light emitting device.
  • the first anode 301A can be located at the red sub-pixel that emits red light
  • the second anode 301B can be located at the blue sub-pixel that emits blue light
  • the third anode 301C can be located at the first green sub-pixel that emits green light.
  • the fourth anode 301D may be located at the second green sub-pixel that emits green light.
  • the first anode 301A and the second anode 301B may be disposed in sequence along the first direction X
  • the third anode 301C and the fourth anode 301D may be disposed in sequence along the first direction X
  • the third anode 301C and The fourth anode 301D may be disposed on one side of the first anode 301A and the second anode 301B in the second direction Y.
  • first anode 301A and the second anode 301B may be disposed in sequence along the second direction Y
  • the third anode 301C and the fourth anode 301D may be disposed in sequence along the second direction Y
  • third anode 301C and the fourth anode 301D may be disposed in sequence along the second direction Y. Disposed on one side of the first direction X of the first anode 301A and the second anode 301B.
  • the first anode 301A, the second anode 301B, the third anode 301C and the fourth anode 301D can be connected to the anode connection electrode 61 of the corresponding circuit unit through the thirty-first via hole V31 respectively, and one pixel unit
  • the anode shapes and areas of the four sub-pixels can be the same or different.
  • At least one of the first anode 301A, the second anode 301B, the third anode 301C and the fourth anode 301D may include an anode body part and an anode connection part connected to each other, and the shape of the anode body part may be Rectangular shape, the corners of the rectangular shape may be provided with arc-shaped chamfers, the shape of the anode connection part may be a strip shape extending along the first direction X or the second direction Y, and the anode connection part passes through the thirty-first via hole V31 is connected to the anode connection electrode 61 .
  • the anode connection electrode 61 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through the via hole, the anode and the second electrode of the sixth transistor T6 and the seventh transistor can be realized. Connection of the second pole of T7.
  • the position and shape of the corresponding anode can be adaptively adjusted according to the position of the overlapping via hole, and the anode can be used to effectively shield the overlapping via hole to avoid astigmatism caused by the overlapping via hole.
  • the position and shape of the anode in the area where the first overlapping via hole is located can be adjusted, and a blocking protrusion is provided on the anode, and the blocking protrusion faces the first overlapping via hole.
  • An overlapping via hole extends where it is located, and the orthographic projection of the shielding protrusion on the substrate includes the orthographic projection of the first overlapping via hole on the substrate, thereby shielding the first overlapping via hole.
  • the subsequent preparation process may include: first forming a pixel definition layer pattern, then using an evaporation or inkjet printing process to form an organic light-emitting layer, then forming a cathode on the organic light-emitting layer, and then forming an encapsulation structure layer.
  • the structural layer may include a stacked first encapsulation layer, a second encapsulation layer and a third encapsulation layer.
  • the first encapsulation layer and the third encapsulation layer may use inorganic materials.
  • the second encapsulation layer may use organic materials.
  • the second encapsulation layer is provided Between the first encapsulation layer and the third encapsulation layer, it can be ensured that external water vapor cannot enter the light-emitting structure layer.
  • a display substrate using a FIAA structure needs to add a third source-drain metal layer (SD3), and set the first connection line and the second connection line in the third source-drain metal layer.
  • SD3 source-drain metal layer
  • the first connection line is provided on the shielding conductive layer
  • the second connection line is provided on the fourth conductive layer
  • the data signal line is provided on the fifth conductive layer
  • the data signal line is connected to the second connection line through a via hole.
  • the second connection line is connected to the first connection line through the via hole, enabling the integrated circuit to provide the data signal to the data signal line through the first connection line and the second connection line, which can effectively reduce the width of the lead-out line area in the binding area , which can effectively reduce the width of the lower border and help achieve a full screen.
  • the first connection line is provided on the shielding conductive layer
  • the second connection line is provided on the fourth conductive layer.
  • the flat layer of organic material is relatively thick, so the first connecting line and the second connecting line will not affect the flatness of the anode, and the height difference of the anode can be avoided, ensuring that
  • the light-emitting performance of the light-emitting devices in each area is basically the same, which not only avoids large viewing angle deviation, but also avoids defects such as screen-off watermarks and improves the quality of the display substrate.
  • Exemplary embodiments of the present disclosure do not require a third source-drain metal layer, which not only simplifies the structure of the display substrate, but also saves two patterning processes (third source-drain metal layer patterning and third flatness patterning). Save production costs to the greatest extent.
  • the preparation process of the present disclosure can be well compatible with the existing preparation process. The process is simple to realize, easy to implement, has high production efficiency, low production cost and high yield rate.
  • the display substrate of the present disclosure can be applied to other display devices with pixel driving circuits, such as quantum dot displays, etc., and the disclosure is not limited here.
  • the present disclosure also provides a method for preparing a display substrate to produce the display substrate provided in the above embodiments.
  • the display substrate in a plane parallel to the display substrate, includes a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one circuit unit including a pixel driving circuit, and the Preparation methods may include:
  • the shielding conductive layer at least including a first connection line
  • a functional structural layer is formed on the shielding conductive layer.
  • the functional structural layer at least includes a second connection line and a data signal line.
  • the data signal line is connected to multiple pixel driving circuits of a unit column.
  • the data signal line Configured to provide a data signal to the pixel driving circuit, the second connection line is connected to the first connection line, and the data signal line is connected to the second connection line.
  • the present disclosure also provides a display device, which includes the aforementioned display substrate.
  • the display device may be: a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function.
  • the embodiments of the present invention are not limited thereto.

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Abstract

一种显示基板及其制备方法、显示装置。显示基板包括遮挡导电层和功能结构层，遮挡导电层至少包括第一连接线(71)，功能结构层至少包括数据信号线(60)和第二连接线(72)；在平行于显示基板的平面内，显示基板包括形成多个单元行和多个单元列的多个电路单元，至少一个电路单元包括像素驱动电路，数据信号线(60)与一个单元列的多个像素驱动电路连接，数据信号线(60)被配置为向像素驱动电路提供数据信号；第二连接线(72)与第一连接线(71)连接，数据信号线(60)与第二连接线(72)连接。

Description

显示基板及其制备方法、显示装置 技术领域
本文涉及但不限于显示技术领域，具体涉及一种显示基板及其制备方法、显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)和量子点发光二极管(Quantum-dot Light Emitting Diodes，简称QLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。随着显示技术的不断发展，以OLED或QLED为发光器件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的柔性显示装置(Flexible Display)已成为目前显示领域的主流产品。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
一方面，本公开提供了一种显示基板，包括设置在基底上的遮挡导电层和设置在所述遮挡导电层远离所述基底一侧的功能结构层，所述遮挡导电层至少包括第一连接线，所述功能结构层至少包括数据信号线和第二连接线；在平行于所述显示基板的平面内，所述显示基板包括形成多个单元行和多个单元列的多个电路单元，至少一个电路单元包括像素驱动电路，所述数据信号线与一个单元列的多个像素驱动电路连接，所述数据信号线被配置为向所述像素驱动电路提供数据信号；所述第二连接线与所述第一连接线连接，所述数据信号线与所述第二连接线连接。
在示例性实施方式中，所述功能结构层包括多个导电层，所述第二连接线和所述数据信号线设置在不同的导电层，所述第二连接线通过第一搭接过孔与所述第一连接线连接，所述数据信号线通过第二搭接过孔与所述第二连 接线连接。
在示例性实施方式中，在平行于所述显示基板的平面上，所述显示基板包括显示区域和位于所述显示区域第二方向一侧的绑定区域，所述绑定区域至少包括引出线；所述第一连接线的第一端与所述引出线连接，所述第一连接线的第二端延伸到所述显示区域后，通过所述第一搭接过孔与所述第二连接线的第一端连接，所述第二连接线的第二端沿着第一方向延伸后，通过所述第二搭接过孔与所述数据信号线连接，所述第一方向与所述第二方向交叉。
在示例性实施方式中，所述第一连接线靠近所述第二连接线的端部设置有第一连接块，所述第一连接块在所述基底上的正投影与所述第二连接线在所述基底上的正投影至少部分交叠，所述第二连接线通过所述第一搭接过孔与所述第一连接块连接。
在示例性实施方式中，所述第二连接线靠近所述第一连接线的端部设置有第二连接块，所述第二连接块在所述基底上的正投影与所述第一连接线在所述基底上的正投影至少部分交叠，所述第二连接块通过所述第一搭接过孔与所述第一连接线连接。
在示例性实施方式中，所述第一连接线靠近所述第二连接线的端部设置有第一连接块，所述第一连接块在所述基底上的正投影与所述第二连接块在所述基底上的正投影至少部分交叠，所述第二连接块通过所述第一搭接过孔与所述第一连接块连接。
在示例性实施方式中，所述第二连接线至少包括第一子线、第二子线、第三子线和第四子线，所述第一子线的第一端与所述第一连接线的第二端连接，所述第一子线的第二端沿着所述单元列的方向延伸后，与所述第二子线的第一端连接，所述第二子线的第二端沿着所述单元行的方向延伸后，与所述第三子线的第一端连接，所述第三子线的第二端沿着所述单元列的方向延伸后，与所述第四子线的第一端连接，所述第四子线的第二端沿着所述单元行的方向延伸后，与所述数据信号线连接。
在示例性实施方式中，所述第一子线设置在相邻的单元列之间。
在示例性实施方式中，所述第二子线的形状为沿着所述单元行方向延伸 的折线，所述第二子线包括至少一个向着所述绑定区域方向凸出的凸出段。
在示例性实施方式中，所述第三子线设置在相邻的单元列之间。
在示例性实施方式中，所述像素驱动电路至少包括数据写入晶体管，所述功能结构层还包括数据写入晶体管的第一极，至少一个电路单元中，所述第四子线与所述数据写入晶体管的第一极连接，所述数据信号线通过所述第二搭接过孔与所述数据写入晶体管的第一极连接。
在示例性实施方式中，所述第四子线和所述数据写入晶体管的第一极同层设置，且为相互连接的一体结构。
在示例性实施方式中，所述功能结构层还包括第一初始信号线，所述第一初始信号线被配置为向所述像素驱动电路提供第一初始信号，所述第二子线在所述基底上的正投影与所述第一初始信号线在所述基底上的正投影至少部分交叠。
在示例性实施方式中，所述第一连接线设置在相邻的单元列之间。
在示例性实施方式中，所述遮挡导电层还包括遮挡电极和第一遮挡连接线，所述遮挡电极设置在所述电路单元，所述第一遮挡连接线与一个单元列中的多个遮挡电极连接。
在示例性实施方式中，所述遮挡导电层包括叠设的第一钛层、铝层和第二钛层，所述第一钛层的厚度为40nm至60nm，所述铝层的厚度为250nm至550nm，所述第二钛层的厚度为20nm至40nm。
在示例性实施方式中，所述像素驱动电路包括存储电容和多个晶体管；在垂直于所述显示基板的平面上，所述功能结构层至少包括设置在所述遮挡导电层远离所述基底一侧的第一导电层、第二导电层、第三导电层、第四导电层和第五导电层，所述第一导电层至少包括存储电容的第一极板和多个晶体管的栅电极，所述第二导电层至少包括存储电容的第二极板，所述第四导电层至少包括所述第二连接线，所述第五导电层至少包括所述数据信号线。
在示例性实施方式中，所述多个晶体管包括至少一个多晶硅晶体管和至少一个氧化物晶体管，所述功能结构层还包括第一半导体层和第二半导体层， 所述第一半导体层设置在所述遮挡导电层和第一导电层之间，所述第一半导体层包括所述多晶硅晶体管的有源层，所述第二半导体层设置在所述第二导电层和第三导电层之间，所述第二半导体层包括所述氧化物晶体管的有源层。
另一方面，本公开还提供了一种显示装置，包括前述的显示基板。
又一方面，本公开还提供了一种显示基板的制备方法，在平行于所述显示基板的平面内，所述显示基板包括形成多个单元行和多个单元列的多个电路单元，至少一个电路单元包括像素驱动电路，所述制备方法包括：
在基底上形成遮挡导电层，所述遮挡导电层至少包括第一连接线；
在所述遮挡导电层上形成功能结构层，所述功能结构层至少包括第二连接线和数据信号线，所述数据信号线与一个单元列的多个像素驱动电路连接，所述数据信号线被配置为向所述像素驱动电路提供数据信号，所述第二连接线与所述第一连接线连接，所述数据信号线通与所述第二连接线连接。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1为一种显示装置的结构示意图；
图2为一种显示基板的结构示意图；
图3为一种显示基板中显示区域的平面结构示意图；
图4为一种显示基板中显示区域的剖面结构示意图；
图5为一种像素驱动电路的等效电路示意图；
图6为一种像素驱动电路的工作时序图；
图7a和图7b为本公开示例性实施例两种数据连接线的结构示意图；
图8为本公开实施例一种数据连接线与数据信号线连接的示意图；
图9a和图9b为本公开实施例形成遮挡导电层图案后的示意图；
图10为本公开实施例形成第一半导体层图案后的示意图；
图11a和图11b为本公开实施例形成第一导电层图案后的示意图；
图12a和图12b为本公开实施例形成第二导电层图案后的示意图；
图13a和图13b为本公开实施例形成第二半导体层图案后的示意图；
图14a和图14b为本公开实施例形成第三导电层图案后的示意图；
图15为本公开实施例形成第六绝缘层图案后的示意图；
图16a和图16b为本公开实施例形成第四导电层图案后的示意图；
图17为本公开实施例形成第一平坦层图案后的示意图；
图18a至图18d为本公开实施例形成第五导电层图案后的示意图；
图19为本公开实施例形成第二平坦层图案后的示意图；
图20a和图20b为本公开实施例形成阳极导电层图案后的示意图。
附图标记说明:
11—第一有源层；       12—第二有源层；       13—第三有源层；
14—第四有源层；       15—第五有源层；       16—第六有源层；
17—第七有源层；       18—第八有源层；       21—第一扫描信号线；
22—第二扫描信号线；   23—发光控制线；       24—第一极板；
31—第三遮挡连接线；   32—第二极板；         33—极板连接线；
34—开口；             41—第三扫描信号线；   42—第一初始信号线；
51—第一连接电极；     52—第二连接电极；     53—第三连接电极；
54—第四连接电极；     55—第五连接电极；     56—第六连接电极；
57—第二初始信号线；   60—数据信号线；       61—阳极连接电极；
62—第一电源线；       70—数据连接线；       71—第一连接线；
72—第二连接线；       80—遮挡电极；         81—第一遮挡连接线；
82—第二遮挡连接线；   100—显示区域；        101—基底；
102—驱动电路层；      103—发光结构层；      104—封装结构层；
200—绑定区域；        210—引线区；          220—引出线；
300—边框区域；         301—阳极；             302—像素定义层；
303—有机发光层；       304—阴极；             401—第一封装层；
402—第二封装层；       403—第三封装层。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
本公开中的附图比例可以作为实际工艺中的参考，但不限于此。例如：沟道的宽长比、各个膜层的厚度和间距、各个信号线的宽度和间距，可以根据实际需要进行调整。显示基板中像素的个数和每个像素中子像素的个数也不是限定为图中所示的数量，本公开中所描述的附图仅是结构示意图，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连 接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换，“源端”和“漏端”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本说明书中三角形、矩形、梯形、五边形或六边形等并非严格意义上的，可以是近似三角形、矩形、梯形、五边形或六边形等，可以存在公差导致的一些小变形，可以存在导角、弧边以及变形等。本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
图1为一种显示装置的结构示意图。如图1所示，显示装置可以包括时序控制器、数据驱动器、扫描驱动器、发光驱动器和像素阵列，时序控制器分别与数据驱动器、扫描驱动器和发光驱动器连接，数据驱动器分别与多个数据信号线(D1到Dn)连接，扫描驱动器分别与多个扫描信号线(S1到Sm)连接，发光驱动器分别与多个发光信号线(E1到Eo)连接。像素阵列可以包括多个子像素Pxij，i和j可以是自然数，至少一个子像素Pxij可以包括电路单元和与电路单元连接的发光器件，电路单元可以包括像素驱动电路，像素驱动电路与扫描信号线、发光信号线和数据信号线连接。在示例性实施方式中，时序控制器可以将适合于数据驱动器的规格的灰度值和控制信号提供到数据驱动器，可以将适合于扫描驱动器的规格的时钟信号、扫描起始信号等提供到扫描驱动器，可以将适合于发光驱动器的规格的时钟信号、发射停止信号等提供到发光驱动器。数据驱动器可以利用从时序控制器接收的灰度值和控制信号来产生将提供到数据信号线D1、D2、D3、……和Dn的数据电压。例如，数据驱动器可以利用时钟信号对灰度值进行采样，并且以单元行为单位将与灰度值对应的数据电压施加到数据信号线D1至Dn，n可以是自然数。扫描驱动器可以通过从时序控制器接收时钟信号、扫描起始信号等来产生将提供到扫描信号线S1、S2、S3、……和Sm的扫描信号。例如，扫描驱动器可以将具有导通电平脉冲的扫描信号顺序地提供到扫描信号线S1至Sm。例如，扫描驱动器可以被构造为移位寄存器的形式，并且可以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产生扫描信号，m可以是自然数。发光驱动器可以通过从时序控制器接收时钟信号、发射停止信号等来产生将提供到发光信号线E1、E2、E3、……和Eo的发射信号。例如，发光驱动器可以将具有截止电平脉冲的发射信号顺序地提供到发光信号线E1至Eo。例如，发光驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以截止电平脉冲形式提供的发射停止信号传输到下一级电路的方式产生发射信号，o可以是自然数。
图2为一种显示基板的结构示意图。如图2所示，显示基板可以包括显示区域100、位于显示区域100一侧的绑定区域200以及位于显示区域100其它侧的边框区域300。在示例性实施方式中，显示区域100可以是平坦的 区域，包括组成像素阵列的多个子像素Pxij，多个子像素Pxij配置为显示动态图片或静止图像，显示区域100可以称为有效区域(AA)。在示例性实施方式中，显示基板可以采用柔性基板，因而显示基板可以是可变形的，例如卷曲、弯曲、折叠或卷起。
在示例性实施方式中，绑定区域200可以包括沿着远离显示区域100的方向依次设置的扇出区、弯折区、驱动芯片区和绑定引脚区。扇出区连接到显示区域100，可以至少包括多条数据扇出线，多条数据扇出线被配置为以扇出(Fanout)走线方式连接显示区域的数据信号线。弯折区连接到扇出区，可以包括设置有凹槽的复合绝缘层，被配置为使绑定区域弯折到显示区域的背面。驱动芯片区可以至少包括集成电路(Integrated Circuit，简称IC)，被配置为与多条数据扇出线连接。绑定引脚区可以至少包括多个绑定焊盘(Bonding Pad)，被配置为与外部的柔性线路板(Flexible Printed Circuit，简称FPC)绑定连接。
在示例性实施方式中，边框区域300可以包括沿着远离显示区域100的方向依次设置的电路区、电源线区、裂缝坝区和切割区。电路区连接到显示区域100，可以至少包括栅极驱动电路，栅极驱动电路与显示区域100中像素驱动电路的第一扫描线、第二扫描线和发光控制线连接。电源线区连接到电路区，可以至少包括边框电源引线，边框电源引线沿着平行于显示区域边缘的方向延伸，与显示区域100中的阴极连接。裂缝坝区连接到电源线区，可以至少包括在复合绝缘层上设置的多个裂缝。切割区连接到裂缝坝区，可以至少包括在复合绝缘层上设置的切割槽，切割槽配置为在显示基板的所有膜层制备完成后，切割设备分别沿着切割槽进行切割。
在示例性实施方式中，绑定区域200中的扇出区和边框区域300中的电源线区可以设置有第一隔离坝和第二隔离坝，第一隔离坝和第二隔离坝可以沿着平行于显示区域边缘的方向延伸，形成环绕显示区域100的环形结构，显示区域边缘是显示区域绑定区域或者边框区域一侧的边缘。
图3为一种显示基板中显示区域的平面结构示意图。如图3所示，显示基板可以包括以矩阵方式排布的多个像素单元P，至少一个像素单元P可以包括出射第一颜色光线的第一子像素P1、出射第二颜色光线的第二子像素 P2和出射第三颜色光线的第三子像素P3和第四子像素P4。每个电路单元可以均包括电路单元和发光器件，电路单元可以至少包括像素驱动电路，像素驱动电路分别与扫描信号线、发光信号线和数据信号线连接，像素驱动电路被配置为在扫描信号线和发光信号线的控制下，接收数据信号线传输的数据电压，向发光器件输出相应的电流。每个电路单元中的发光器件分别与所在子像素的像素驱动电路连接，发光器件被配置为响应所在子像素的像素驱动电路输出的电流发出相应亮度的光。
在示例性实施方式中，第一子像素P1可以是出射红色光线的红色子像素(R)，第二子像素P2可以是出射蓝色光线的蓝色子像素(B)，第三子像素P3和第四子像素P4可以是出射绿色光线的绿色子像素(G)。在示例性实施方式中，子像素的形状可以是矩形状、菱形、五边形或六边形，四个子像素可以采用钻石形(Diamond)方式排列，形成RGBG像素排布。在其它示例性实施方式中，四个子像素可以采用水平并列、竖直并列或正方形等方式排列，本公开在此不做限定。
在示例性实施方式中，像素单元可以包括三个子像素，三个子像素可以采用水平并列、竖直并列或品字等方式排列，本公开在此不做限定。
图4为一种显示基板中显示区域的剖面结构示意图，示意了显示区域中四个子像素的结构。如图4所示，在垂直于显示基板的平面上，显示基板可以包括设置在基底101上的驱动电路层102、设置在驱动电路层102远离基底101一侧的发光结构层103以及设置在发光结构层103远离基底101一侧的封装结构层104。在一些可能的实现方式中，显示基板可以包括其它膜层，如触控结构层等，本公开在此不做限定。
在示例性实施方式中，基底101可以是柔性基底，或者可以是刚性基底。驱动电路层102可以包括多个电路单元，每个电路单元可以至少包括由多个晶体管和存储电容构成的像素驱动电路。发光结构层103可以包括多个发光器件，每个发光器件可以至少包括阳极301、像素定义层302、有机发光层303和阴极304，阳极301与像素驱动电路连接，有机发光层303与阳极301连接，阴极304与有机发光层303连接，有机发光层303在阳极301和阴极304驱动下出射相应颜色的光线。封装结构层104可以包括叠设的第一 封装层401、第二封装层402和第三封装层403，第一封装层401和第三封装层403可以采用无机材料，第二封装层402可以采用有机材料，第二封装层402设置在第一封装层401和第三封装层403之间，形成无机材料/有机材料/无机材料叠层结构，可以保证外界水汽无法进入发光结构层103。
在示例性实施方式中，有机发光层可以包括发光层(EML)以及如下任意一层或多层：空穴注入层(HIL)、空穴传输层(HTL)、电子阻挡层(EBL)、、空穴阻挡层(HBL)、电子传输层(ETL)和电子注入层(EIL)。在示例性实施方式中，所有子像素的空穴注入层、空穴传输层、电子阻挡层、空穴阻挡层、电子传输层和电子注入层中的一层或多层可以是连接在一起的共通层，相邻电路单元的发光层可以有少量的交叠，或者可以是相互隔离的。
图5为一种像素驱动电路的等效电路示意图。在示例性实施方式中，像素驱动电路可以是3T1C、4T1C、5T1C、5T2C、6T1C、7T1C或8T1C结构。如图5所示，像素驱动电路可以包括8个晶体管(第一晶体管T1至第八晶体管T8)和1个存储电容C，像素驱动电路分别与9个信号线(数据信号线D、第一扫描信号线S1、第二扫描信号线S2、第三扫描信号线S3、发光信号线E、第一初始信号线INIT1、第二初始信号线INIT1、第一电源线VDD和第二电源线VSS)连接。
在示例性实施方式中，像素驱动电路可以包括第一节点N1、第二节点N2和第三节点N3。其中，第一节点N1分别与第三晶体管T3的第一极、第四晶体管T4的第二极和第五晶体管T5的第二极连接，第二节点N2分别与第八晶体管T8的第二极、第三晶体管T3的控制极和存储电容C的第二端连接，第三节点N3分别与第二晶体管T2的第二极、第三晶体管T3的第二极和第六晶体管T6的第一极连接。
在示例性实施方式中，存储电容C的第一端与第一电源线VDD连接，存储电容C的第二端与第二节点N2连接，即存储电容C的第二端与第三晶体管T3的控制极连接。
在示例性实施方式中，第一晶体管T1的控制极与第二扫描信号线S2连接，第一晶体管T1的第一极与第一初始信号线INIT1连接，第一晶体管T1 的第二极与第八晶体管T8的第一极连接。第八晶体管T8的控制极与第三扫描信号线S3连接，第八晶体管T8的第一极与第一晶体管T1的第二极连接，第八晶体管T8的第二极与第二节点N2连接。当导通电平扫描信号施加到第二扫描信号线S2和第三扫描信号线S3时，第一晶体管T1和第八晶体管T8将第一初始化电压传输到存储电容C的第二端，实现存储电容C的初始化。
在示例性实施方式中，第二晶体管T2的控制极与第一扫描信号线S1连接，第二晶体管T2的第一极与第一晶体管T1的第二极和第八晶体管T8的第一极连接，第二晶体管T2的第二极与第三节点N3连接。当导通电平扫描信号施加到第一扫描信号线S1和第三扫描信号线S3时，第二晶体管T2和第八晶体管T8使第三晶体管T3的控制极与第三晶体管T3的第二极连接。
在示例性实施方式中，第三晶体管T3的控制极与第二节点N2连接，即第三晶体管T3的控制极与存储电容C的第二端连接，第三晶体管T3的第一极与第一节点N1连接，第三晶体管T3的第二极与第三节点N3连接。第三晶体管T3可以称为驱动晶体管，第三晶体管T3根据其控制极与第一极之间的电位差来确定在第一电源线VDD与发光器件之间流动的驱动电流的大小。
在示例性实施方式中，第四晶体管T4的控制极与第一扫描信号线S1连接，第四晶体管T4的第一极与数据信号线D连接，第四晶体管T4的第二极与第一节点N1连接。当导通电平扫描信号施加到第一扫描信号线S1和第三扫描信号线S3时，第四晶体管T4使数据信号线D的数据电压输入到第一节点N1。
在示例性实施方式中，第五晶体管T5的控制极与发光信号线E连接，第五晶体管T5的第一极与第一电源线VDD连接，第五晶体管T5的第二极与第一节点N1连接。第六晶体管T6的控制极与发光信号线E连接，第六晶体管T6的第一极与第三节点N3连接，第六晶体管T6的第二极与发光器件的第一极连接。当导通电平发光信号施加到发光信号线E时，第五晶体管T5和第六晶体管T6通过在第一电源线VDD与发光器件之间形成驱动电流路径而使发光器件发光。
在示例性实施方式中，第七晶体管T7的控制极与第二扫描信号线S2连接，第七晶体管T7的第一极与第二初始信号线INIT2连接，第七晶体管T7 的第二极与发光器件的第一极连接。当导通电平扫描信号施加到第二扫描信号线S2时，第七晶体管T7将第二初始电压传输到发光器件的第一极，以使发光器件的第一极中累积的电荷量初始化或释放发光器件的第一极中累积的电荷量。
在示例性实施方式中，发光器件可以是OLED，包括叠设的第一极(阳极)、有机发光层和第二极(阴极)，或者可以是QLED，包括叠设的第一极(阳极)、量子点发光层和第二极(阴极)。
在示例性实施方式中，发光器件的第二极与第二电源线VSS连接，第二电源线VSS的信号为持续提供的低电平信号，第一电源线VDD的信号为持续提供的高电平信号。
在示例性实施方式中，第一晶体管T1至第八晶体管T8可以是P型晶体管，或者可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。在一些可能的实现方式中，第一晶体管T1至第八晶体管T8可以包括P型晶体管和N型晶体管。
在示例性实施方式中，第一晶体管T1至第八晶体管T8可以采用低温多晶硅晶体管，或者可以采用氧化物晶体管，或者可以采用低温多晶硅晶体管和金属氧化物晶体管。低温多晶硅晶体管的有源层采用低温多晶硅(Low Temperature Poly-Silicon，简称LTPS)，金属氧化物晶体管的有源层采用金属氧化物半导体(Oxide)。低温多晶硅晶体管具有迁移率高、充电快等优点，氧化物晶体管具有漏电流低等优点，将低温多晶硅晶体管和金属氧化物晶体管集成在一个显示基板上，形成低温多晶氧化物(Low Temperature Polycrystalline Oxide，简称LTPO)显示基板，可以利用两者的优势，可以实现低频驱动，可以降低功耗，可以提高显示品质。
图6为一种像素驱动电路的工作时序图。下面通过图5示例的像素驱动电路的工作过程说明本公开示例性实施方式，图5中的像素驱动电路包括8个晶体管(第一晶体管T1至第八晶体管T8)和1个存储电容C，第一晶体管T1至第七晶体管T7均为P型晶体管，第八晶体管T8为N型晶体管。在示例性实施方式中，像素驱动电路的工作过程可以包括：
第一阶段A1，称为复位阶段，第二扫描信号线S2的信号为低电平信号，第一扫描信号线S1、第三扫描信号线S3和发光信号线E的信号为高电平信号。第二扫描信号线S2的信号为低电平信号使第一晶体管T1导通，第三扫描信号线S3的信号为高电平信号使第八晶体管T8导通，第一初始信号线INIT1的信号通过第一晶体管T1和第八晶体管T8提供至第二节点N2，对存储电容C进行初始化(复位)，清除存储电容中原有电荷。第二扫描信号线S2的信号为低电平信号，使第七晶体管T7导通，第二初始信号线INIT2的信号提供至OLED的第一极，对OLED的第一极进行初始化(复位)，清空其内部的预存电压，完成初始化，确保OLED不发光。第一扫描信号线S1和发光信号线E的信号为高电平信号，使第二晶体管T2、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7断开，此阶段OLED不发光。
第二阶段A2、称为数据写入阶段或者阈值补偿阶段，第一扫描信号线S1的信号为低电平信号，第二扫描信号线S2、第三扫描信号线S3和发光信号线E的信号为高电平信号，数据信号线D输出数据电压。此阶段由于存储电容C的第二端为低电平，因此第三晶体管T3导通。第一扫描信号线S1的信号为低电平信号使第二晶体管T2和第四晶体管T4导通，第三扫描信号线S3的信号为高电平信号使第八晶体管T8导通。第二晶体管T2、第四晶体管T4和第八晶体管T8导通使得数据信号线D输出的数据电压经过第一节点N1、导通的第三晶体管T3、第三节点N3、导通的第二晶体管T2、导通的第八晶体管T8提供至第二节点N2，并将数据信号线D输出的数据电压与第三晶体管T3的阈值电压之差充入存储电容C，存储电容C的第二端(第二节点N2)的电压为Vd-|Vth|，Vd为数据信号线D输出的数据电压，Vth为第三晶体管T3的阈值电压。第二扫描信号线S2的信号为高电平信号，使第一晶体管T1和第七晶体管T7断开。发光信号线E的信号为高电平信号，使第五晶体管T5和第六晶体管T6断开。
第三阶段A3、称为发光阶段，发光信号线E和第三扫描信号线S3的信号为低电平信号，第一扫描信号线S1和第二扫描信号线S2的信号为高电平信号。发光信号线E的信号为低电平信号，使第五晶体管T5和第六晶体管 T6导通，第一电源线VDD输出的电源电压通过导通的第五晶体管T5、第三晶体管T3和第六晶体管T6向OLED的第一极提供驱动电压，驱动OLED发光。
在像素驱动电路驱动过程中，流过第三晶体管T3(驱动晶体管)的驱动电流由其栅电极和第一极之间的电压差决定。由于第二节点N2的电压为Vdata-|Vth|，因而第三晶体管T3的驱动电流为：
I＝K*(Vgs-Vth) 2＝K*[(Vdd-Vd+|Vth|)-Vth] 2＝K*[(Vdd-Vd] 2
其中，I为流过第三晶体管T3的驱动电流，也就是驱动OLED的驱动电流，K为常数，Vgs为第三晶体管T3的栅电极和第一极之间的电压差，Vth为第三晶体管T3的阈值电压，Vd为数据信号线D输出的数据电压，Vdd为第一电源线VDD输出的电源电压。
随着OLED显示技术的发展，消费者对显示产品显示效果的要求越来越高，极窄边框成为显示产品发展的新趋势，因此边框的窄化甚至无边框设计在OLED显示产品设计中越来越受到重视。一种显示基板中，由于绑定区域中集成电路和绑定焊盘的信号线需要通过数据连接线以扇出方式才能引入到较宽的显示区域，使得扇形区占用空间较大，导致下边框的宽度较大。
本公开示例性实施例提供了一种显示基板，采用数据连接线位于显示区域(Fanout in AA，简称FIAA)结构，多条数据连接线的第一端与绑定区域的集成电路对应连接，多条数据连接线的第二端从绑定区域延伸到显示区域，与显示区域中的多条数据信号线对应连接。由于绑定区域中不需要设置扇形状的斜线，因而缩减了扇出区的宽度，有效减小了下边框宽度。
在示例性实施方式中，本公开示例性实施例显示基板可以包括设置在基底上的驱动电路层、设置在驱动电路层远离基底一侧的发光结构层以及设置在发光结构层远离基底一侧的封装结构层。在平行于显示基板的平面内，显示基板可以至少包括显示区域、位于显示区域一侧的绑定区域和位于显示区域其它侧的边框区域。在示例性实施例中，显示区域的驱动电路层可以包括构成多个单元行和多个单元列的多个电路单元，至少一个电路单元可以包括像素驱动电路，像素驱动电路被配置为向所连接的发光器件输出相应的电流。显示区域的发光结构层可以包括构成像素阵列的多个子像素，至少一个子像 素可以包括发光器件，发光器件与对应电路单元的像素驱动电路连接，发光器件被配置为响应所连接的像素驱动电路输出的电流发出相应亮度的光。
在示例性实施例中，本公开中所说的子像素，是指按照发光器件划分的区域，本公开中所说的电路单元，是指按照像素驱动电路划分的区域。在示例性实施例中，子像素在基底上正投影的位置与电路单元在基底上正投影的位置可以是对应的，或者，子像素在基底上正投影的位置与电路单元在基底上正投影的位置可以是不对应的。
在示例性实施例中，本公开示例性实施例显示基板可以包括设置在基底上的遮挡导电层和设置在所述遮挡导电层远离所述基底一侧的功能结构层，所述遮挡导电层至少包括第一连接线，所述功能结构层至少包括第二连接线和数据信号线；在平行于所述显示基板的平面内，所述显示基板包括形成多个单元行和多个单元列的多个电路单元，至少一个电路单元包括像素驱动电路，所述数据信号线与一个单元列的多个像素驱动电路连接，所述数据信号线被配置为向所述像素驱动电路提供数据信号；所述第二连接线与所述第一连接线连接，所述数据信号线与所述第二连接线连接。
在示例性实施方式中，所述功能结构层包括多个导电层，所述第二连接线和所述数据信号线设置在不同的导电层，所述第二连接线通过第一搭接过孔与所述第一连接线连接，所述数据信号线通过第二搭接过孔与所述第二连接线连接。
在示例性实施方式中，在平行于所述显示基板的平面上，所述显示基板包括显示区域和位于所述显示区域第二方向一侧的绑定区域，所述绑定区域至少包括引出线；所述第一连接线的第一端与所述引出线连接，所述第一连接线的第二端延伸到所述显示区域后，通过所述第一搭接过孔与所述第二连接线的第一端连接，所述第二连接线的第二端沿着第一方向延伸后，通过所述第二搭接过孔与所述数据信号线连接，所述第一方向与所述第二方向交叉。
在示例性实施方式中，所述像素驱动电路包括存储电容和多个晶体管；在垂直于所述显示基板的平面上，所述功能结构层至少包括设置在所述遮挡导电层远离所述基底一侧的第一导电层、第二导电层、第三导电层、第四导电层和第五导电层，所述第一导电层至少包括存储电容的第一极板和多个晶 体管的栅电极，所述第二导电层至少包括存储电容的第二极板，所述第四导电层至少包括所述第二连接线，所述第五导电层至少包括所述数据信号线。
在示例性实施方式中，所述多个晶体管包括至少一个多晶硅晶体管和至少一个氧化物晶体管，所述功能结构层还包括第一半导体层和第二半导体层，所述第一半导体层设置在所述遮挡导电层和第一导电层之间，所述第一半导体层包括所述多晶硅晶体管的有源层，所述第二半导体层设置在所述第二导电层和第三导电层之间，所述第二半导体层包括所述氧化物晶体管的有源层。
图7a和图7b为本公开示例性实施例两种数据连接线的结构示意图，数据连接线采用FIAA结构。在平行于显示基板的平面内，显示基板可以包括显示区域100、位于显示区域100一侧的绑定区域200以及位于显示区域100其它侧的边框区域300，显示区域100可以至少包括多个电路单元、多条数据信号线60、多条数据连接线70，绑定区域200可以至少包括引出线区210，引出线区210可以包括多条引出线220。
在示例性实施方式中，多个电路单元可以形成多个单元行和多个单元列，每个单元行可以包括沿着第一方向X依次设置的多个电路单元，多个单元行可以沿着第二方向Y依次设置，每个单元列可以包括沿着第二方向Y依次设置的多个电路单元，多个单元列可以沿着第一方向X依次设置，第一方向X与第二方向Y交叉。在示例性实施方式中，第二方向Y可以是数据信号线的延伸方向(竖直方向)，第一方向X可以与第二方向Y垂直。
在示例性实施方式中，数据信号线60可以为沿着第二方向Y延伸的线形状，多条数据信号线60在第一方向X上以设定的间隔依次设置，每条数据信号线60与一个单元列中多个电路单元的像素驱动电路连接。
在示例性实施方式中，多条数据连接线70可以位于显示区域靠近绑定区域200一侧的区域，多条数据连接线70的第一端与引出线区210的多条引出线220对应连接，多条数据连接线70的第二端向着显示区域10的方向延伸后，与多条数据信号线60对应连接，使得显示区域100中的多条数据信号线60通过显示区域100中的多条数据连接线70与绑定区域200中的多条引出线220对应连接。
在示例性实施方式中，显示区域中的数据连接线的数量与数据信号线的 数量可以相同，每条数据信号线通过一条数据连接线与一条引出线对应连接。或者，显示区域中的数据连接线的数量可以小于数据信号线的数量，显示区域中的一部分数据信号线通过数据连接线与引出线对应连接，另一部分数据信号线与引出线直接连接，本公开在此不做限定。
图8为本公开示例性实施例一种数据连接线与数据信号线连接的示意图。如图8所示，在示例性实施方式中，数据连接线70可以包括第一连接线71和第二连接线72，第一连接线71的形状可以为主体部分沿着第二方向Y延伸的线形状，第二连接线72的形状可以为主体部分沿着第一方向X延伸的线形状，数据信号线60可以为沿着第二方向Y延伸的线形状。
本公开中，A沿着B方向延伸是指，A可以包括主要部分和与主要部分连接的次要部分，主要部分是线、线段或条形状体，主要部分沿着B方向伸展，且主要部分沿着B方向伸展的长度大于次要部分沿着其它方向伸展的长度。以下描述中所说的“A沿着B方向延伸”均是指“A的主体部分沿着B方向延伸”。在示例性实施方式中，第二方向Y可以是从显示区域指向绑定区域的方向，第二方向Y的反方向可以是从绑定区域指向显示区域的方向。
在示例性实施方式中，显示基板可以包括设置在基底上的遮挡导电层和设置在遮挡导电层远离基底一侧的功能结构层，第一连接线71可以设置在遮挡导电层中，数据信号线60和第二连接线72可以设置在功能结构层中。
在示例性实施方式中，功能结构层可以包括多个导电层，第二连接线72和数据信号线60可以设置在不同的导电层，第二连接线通过第一搭接过孔K1与第一连接线71连接，数据信号线60可以通过第二搭接过孔K2与第二连接线72连接。
在示例性实施方式中，第一连接线71可以设置在相邻的单元列之间。
在示例性实施方式中，第一连接线71的第一端与引出线区210的引出线220连接，第一连接线71的第二端沿着第二方向Y的反方向向着显示区域100延伸后，通过第一搭接过孔K1与第二连接线72的第一端连接，第二连接线72的第二端沿着第一方向X或者第一方向X的反方向延伸后，通过第二搭接过孔K2与数据信号线60连接。
在示例性实施方式中，第一连接线71靠近第二连接线72的端部(远离 绑定区域的端部)可以连接有第一连接块，第一连接块的形状可以为沿着第二方向Y延伸的条形状，第一连接块在基底上的正投影与第二连接线72在基底上的正投影至少部分交叠，第二连接线72通过第一搭接过孔K1与第一连接块连接。
在示例性实施方式中，第二连接线72靠近第一连接线71的端部连接有第二连接块，第二连接块的形状可以为沿着第二方向Y延伸的条形状，第二连接块在基底上的正投影与第一连接线71在基底上的正投影至少部分交叠，第二连接块通过第一搭接过孔K1与第一连接线71连接。
在示例性实施方式中，第一连接块在基底上的正投影与第二连接块在基底上的正投影至少部分交叠，第二连接块通过第一搭接过孔K1与第一连接块连接。
在示例性实施方式中，第二连接线72可以至少包括第一子线、第二子线、第三子线和第四子线，第一子线的第一端与第一连接线71的第二端连接，第一子线的第二端沿着第二方向Y的反方向延伸后，与第二子线的第一端连接，第二子线的第二端沿着第一方向X或者第一方向X的反方向延伸后，与第三子线的第一端连接，第三子线的第二端沿着第二方向Y延伸后，与第四子线的第一端连接，第四子线的第二端沿着第一方向X或者第一方向X的反方向延伸后，与数据信号线60连接。
在示例性实施方式中，第一子线可以设置在相邻的单元列之间。
在示例性实施方式中，第二子线的形状可以为沿着第一方向X或者第一方向X的反方向延伸的折线，可以包括至少一个向着绑定区域方向凸出的凸出段。
在示例性实施方式中，第三子线可以设置在相邻的单元列之间。
在示例性实施方式中，功能结构层可以至少包括设置在遮挡导电层远离基底一侧的第一导电层、第二导电层、第三导电层、第四导电层和第五导电层，第一导电层可以至少包括存储电容的第一极板和多个晶体管的栅电极，第二导电层可以至少包括存储电容的第二极板，第四导电层可以至少包括第二连接线72，第五导电层可以至少包括数据信号线60。
在示例性实施方式中，像素驱动电路的多个晶体管可以包括至少一个多晶硅晶体管和至少一个氧化物晶体管，功能结构层还可以包括第一半导体层和第二半导体层，第一半导体层可以设置在遮挡导电层和第一导电层之间，第一半导体层可以包括多晶硅晶体管的有源层，第二半导体层可以设置在第二导电层和第三导电层之间，第二半导体层可以包括氧化物晶体管的有源层。
在示例性实施方式中，功能结构层还可以多个绝缘层，多个绝缘层可以分别设置在：第一导电层与第一半导体层之间，第一半导体层与第二导电层之间，第二导电层与第二半导体层之间，第二半导体层与第三导电层之间，第三导电层与第四导电层之间，第四导电层与第五导电层之间。
在示例性实施方式中，数据连接线与数据信号线的连接方式可以采用图7a所示方式，或者，可以采用图7b所示方式，本公开在此不做限定。
下面通过显示基板的制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多8种，本公开不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。本公开示例性实施方式中，“B的正投影位于A的正投影的范围之内”或者“A的正投影包含B的正投影”是指，B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
在示例性实施方式中，以10个电路单元(2个单元行5个单元列)为例，显示基板的制备过程可以包括如下操作。
(1)形成遮挡导电层图案。在示例性实施方式中，形成遮挡导电层图案 可以包括：在基底上沉积遮挡薄膜，通过图案化工艺对遮挡薄膜进行图案化，在基底上形成遮挡导电层图案，如图9a和图9b所示，图9a示意了设置第一连接线区域的遮挡导电层结构，图9b示意了没有设置第一连接线区域的遮挡导电层结构。
图9a所示，在设置第一连接线的区域，遮挡导电层图案可以至少包括第一连接线71、遮挡电极80和第一遮挡连接线81。
在示例性实施方式中，遮挡电极80的形状可以为矩形状，可以设置在每个电路单元中，遮挡电极80被配置为对像素驱动电路的驱动晶体管进行遮挡，减少光线对驱动晶体管电学特性的影响。此外，遮挡电极80还可以被配置为抑制碰撞电离产生的电子在沟道内部的聚集与减弱沟道焦耳热的聚集等。
在示例性实施方式中，第一遮挡连接线81的形状可以为沿着第二方向Y延伸的直线状，第一遮挡连接线81被配置为与一个单元列中的多个遮挡电极80连接。本公开通过将第一遮挡连接线设置成纵向连接遮挡电极，不仅可以为第一连接线留出较大的走线空间，而且可以减少对第一半导体层平坦度的影响，提高晶体管的电学性能。
在示例性实施方式中，第一连接线71的形状可以为沿着第二方向Y延伸的条形状，第一连接线71的第一端与绑定区域中的引出线连接，第一连接线71的第二端从绑定区域延伸到显示区域后，与后续形成的第二连接线连接。
在示例性实施方式中，第一连接线71的第二端(远离绑定区域的端部)设置有第一连接块71-1，第一连接块71-1的形状可以为沿着第二方向Y延伸的条形状，且与第一连接线71连接，第一连接块71-1被配置为通过后续形成的第一搭接过孔与第二连接线连接。
在示例性实施方式中，第一连接线71可以设置在相邻的单元列之间，即第一连接线71可以设置在第一方向X相邻的电路单元之间。例如，一条第一连接线71可以设置在第N+1列的电路单元与第N+1列的电路单元之间。又如，另一条第一连接线71可以设置在第N+2列的电路单元与第N+3列的 电路单元之间。
图9b所示，在没有设置第一连接线的区域，遮挡导电层图案可以至少包括第一连接线71、遮挡电极80、第一遮挡连接线81和第二遮挡连接线82。
在示例性实施方式中，没有设置第一连接线区域中的遮挡电极80和第一遮挡连接线81与设置第一连接线区域的遮挡电极80和第一遮挡连接线81可以基本上相同。
在示例性实施方式中，第二遮挡连接线82的的形状可以为沿着第一X方向Y延伸的直线状，第二遮挡连接线82被配置为与一个单元行中的多个遮挡电极80连接。
本公开通过将第一遮挡连接线设置成纵向连接遮挡电极，将第二遮挡连接线设置成横向连接遮挡电极，因而可以形成网状连通结构的遮挡层网络，有利于提高晶体管的电学性能。
在示例性实施方式中，遮挡导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)、钛(Ti)和钼(Mo)中的任意一种或多种，或上述金属的合金材料，可以是单层结构，或者多层复合结构。
在示例性实施方式中，遮挡导电层可以采用Ti-Al-Ti的多层复合结构，第一钛层(底层)的厚度可以约为40nm至60nm，铝层的厚度可以约为250nm至550nm，第二钛层(上层)的厚度可以约为20nm至40nm。例如，第一钛层(底层)的厚度可以约为50nm，铝层的厚度可以约为450nm，第二钛层(上层)的厚度可以约为30nm。
(2)形成第一半导体层图案。在示例性实施方式中，形成第一半导体层图案可以包括：在基底上依次沉积第一绝缘薄膜和第一半导体薄膜，通过图案化工艺对第一半导体薄膜进行图案化，形成覆盖基底的第一绝缘层，以及设置在第一绝缘层上的第一半导体层图案，如图10所示。
在示例性实施方式中，第一半导体层图案可以包括设置在每个电路单元的第一晶体管T1的第一有源层11至第七晶体管T7的第七有源层17，且电路单元中的第一有源层11至第七有源层17为相互连接的一体结构。
在示例性实施方式中，在第一方向X上，第二有源层12和第六有源层 16可以位于本电路单元中第三有源层13的同一侧，第四有源层14、第五有源层15和第七有源层17可以位于本电路单元中第三有源层13的同一侧，第二有源层12和第四有源层14可以位于本电路单元的第三有源层13的不同侧。在第二方向Y上，第M行电路单元中第一有源层11、第二有源层12和第四有源层14可以位于本电路单元中第三有源层13远离第M+1行电路单元的一侧，第M行电路单元中的第五有源层15、第六有源层16和第七有源层17可以位于本电路单元中第三有源层13靠近第M+1行电路单元的一侧。
在示例性实施方式中，第三有源层13的形状可以呈“Ω”字形，第一有源层11、第二有源层12、第四有源层14至第七有源层17的形状可以呈“I”字形。
在示例性实施方式中，第三有源层13在基底上的正投影可以位于遮挡电极80在基底上的正投影的范围之内。
在示例性实施方式中，每个晶体管的有源层可以包括第一区、第二区以及位于第一区和第二区之间的沟道区。在示例性实施方式中，第一有源层11的第二区11-2可以作为第二有源层12的第一区12-1，第三有源层13的第一区13-1可以同时作为第四有源层14的第二区14-2和第五有源层15的第二区15-2，第三有源层13的第二区13-2可以同时作为第二有源层12的第二区12-2和第六有源层16的第一区16-1，第六有源层16的第二区16-2可以同时作为第七有源层17的第二区17-2，第一有源层11的第一区11-1、第四有源层14的第一区14-1、第五有源层15的第一区15-1和第七有源层17的第一区17-1可以单独设置。
在示例性实施方式中，一个单元行中，相邻两个电路单元中的第五有源层15的第一区15-1可以相互连接。例如，第N-2列的第五有源层15的第一区15-1和第N-1列的第五有源层15的第一区15-1相互连接，第N列的第五有源层15的第一区15-1和第N+1列的第五有源层15的第一区15-1相互连接。由于每个电路单元中的第五有源层的第一区被配置为与后续形成的第一电源线连接，通过将相邻电路单元的第五有源层的第一区形成相互连接的一体结构，可以保证相邻电路单元的第五晶体管T5的第一极具有相同的电位，有利于提高面板的均一性，避免显示基板的显示不良，保证显示基板的显示 效果。
在示例性实施方式中，一个单元行中相邻两个电路单元中的第七有源层17的第一区17-1可以相互连接。例如，第N-1列的第七有源层17的第一区17-1和第N列的第七有源层17的第一区17-1相互连接，第N+1列的第七有源层17的第一区17-1和第N+2列的第七有源层17的第一区17-1相互连接。由于每个电路单元中的第七有源层的第一区被配置为与后续形成的第二初始信号线连接，通过将相邻电路单元的第七有源层的第一区形成相互连接的一体结构，可以保证相邻电路单元的第七有源层的第一区具有相同的电位，有利于提高面板的均一性，避免显示基板的显示不良，保证显示基板的显示效果。
在示例性实施方式中，第一半导体层可以采用多晶硅(p-Si)，即第一晶体管至第七晶体管为LTPS薄膜晶体管。在示例性实施方式中，通过图案化工艺对第一半导体薄膜进行图案化，可以包括：先在第一绝缘薄膜上形成非晶硅(a-si)薄膜，对非晶硅薄膜进行脱氢处理，对脱氢处理后的非晶硅薄膜进行结晶处理，形成多晶硅薄膜。随后，对多晶硅薄膜进行图案化，形成第一半导体层图案。
(3)形成第一导电层图案。在示例性实施方式中，形成第一导电层图案可以包括：在形成前述图案的基底上，依次沉积第二绝缘薄膜和第一导电薄膜，通过图案化工艺对第一导电薄膜进行图案化，形成覆盖第一半导体层图案的第二绝缘层，以及设置在第二绝缘层上的第一导电层图案，如图11a和图11b所示，图11b为图11a中第一导电层的平面示意图。在示例性实施方式中，第一导电层可以称为第一栅金属(GATE1)层。
在示例性实施方式中，每个电路单元的第一导电层图案至少包括：第一扫描信号线21、第二扫描信号线22、发光控制线23和存储电容的第一极板24。
在示例性实施方式中，第一极板24的形状可以为矩形状，矩形状的角部可以设置倒角，第一极板24在基底上的正投影与第三晶体管T3的第三有源层在基底上的正投影至少部分交叠。在示例性实施方式中，第一极板24可以同时作为存储电容的一个极板和第三晶体管T3的栅电极。
在示例性实施方式中，第一扫描信号线21的形状可以为主体部分沿着第一方向X延伸的线形状，第M行电路单元中的第一扫描信号线21可以位于本电路单元的第一极板24远离第M+1行电路单元的一侧，第一扫描信号线21与本电路单元的第二有源层相重叠的区域作为第二晶体管T2的栅电极，第一扫描信号线21与本电路单元的第四有源层相重叠的区域作为第四晶体管T4的栅电极。
在示例性实施方式中，第二扫描信号线22的形状可以为主体部分沿着第一方向X延伸的折线状，第M行电路单元中的第二扫描信号线22可以位于本电路单元的第一极板24靠近第M+1行电路单元的一侧，第二扫描信号线22上连接有向着远离第一极板24方向延伸的栅极块22-1，第二扫描信号线22与本电路单元的第七有源层相重叠的区域作为第七晶体管T7的栅电极，栅极块22-1与下一行电路单元的第一有源层相重叠的区域作为第一晶体管T1的栅电极。
在示例性实施方式中，第M行电路单元中的第二扫描信号线22同时驱动第M行电路单元中的第七晶体管T7和第M+1行电路单元中的第一晶体管T1。
在示例性实施方式中，发光控制线23的形状可以为主体部分沿着第一方向X延伸的线形状，发光控制线23可以位于第一极板24与第二扫描信号线22之间，发光控制线23与本电路单元的第五有源层相重叠的区域作为第五晶体管T5的栅电极，发光控制线23与本电路单元的第六有源层相重叠的区域作为第六晶体管T6的栅电极。
在示例性实施方式中，形成第一导电层图案后，可以利用第一导电层作为遮挡，对第一半导体层进行导体化处理，被第一导电层遮挡区域的第一半导体层形成第一晶体管T1至第七晶体管T7的沟道区域，未被第一导电层遮挡区域的第一半导体层被导体化，即第一晶体管T1至第七有源层的第一区和第二区均被导体化。
(4)形成第二导电层图案。在示例性实施方式中，形成第二导电层图案可以包括：在形成前述图案的基底上，依次沉积第三绝缘薄膜和第二导电薄膜，采用图案化工艺对第二导电薄膜进行图案化，形成覆盖第一导电层的第 三绝缘层，以及设置在第三绝缘层上的第二导电层图案，如图12a和图12b所示，图12b为图12a中第二导电层的平面示意图。在示例性实施方式中，第二导电层可以称为第二栅金属(GATE2)层。
在示例性实施方式中，每个电路单元的第二导电层图案至少包括：第三遮挡连接线31、存储电容的第二极板32和极板连接线33。
在示例性实施方式中，第二极板32的轮廓可以为矩形状，矩形状的角部可以设置倒角，第二极板32在基底上的正投影与第一极板24在基底上的正投影至少部分交叠，第二极板32可以作为存储电容的另一个极板，第一极板24和第二极板32构成像素驱动电路的存储电容。
在示例性实施方式中，极板连接线33可以设置在第二极板32第一方向X的一侧或者第一方向X的反方向的一侧，使得一个单元行中相邻两个电路单元中的第二极板32相互连接。例如，第N-1列的第二极板32和第N列的第二极板32可以通过极板连接线33相互连接。又如，第N列的第二极板32和第N+1列的第二极板32通过极板连接线33相互连接。由于每个电路单元中的第二极板32与后续形成的第一电源线连接，通过将相邻电路单元的第二极板32形成相互连接的一体结构，一体结构的第二极板32可以复用为电源信号线，可以保证一单元行中的多个第二极板32具有相同的电位，有利于提高面板的均一性，避免显示基板的显示不良，保证显示基板的显示效果。
在示例性实施方式中，第二极板32上设置有开口34，开口34的形状可以为矩形状，可以位于第二极板32的中部，使第二极板32形成环形结构。开口34暴露出覆盖第一极板24的第三绝缘层，且第一极板24在基底上的正投影包含开口34在基底上的正投影。在示例性实施方式中，开口34被配置为容置后续形成的第一过孔，第一过孔位于开口34内并暴露出第一极板24，使后续形成的第一晶体管T1的第二极与第一极板24连接。
在示例性实施方式中，第三遮挡连接线31的形状可以为主体部分沿着第一方向X延伸的线形状，第M行电路单元中的第三遮挡连接线31可以位于本电路单元的第二极板32远离第M+1行电路单元的一侧。
在示例性实施方式中，第M行电路单元中的第三遮挡连接线31可以位于本电路单元的第一扫描信号线21远离第二极板32的一侧。第三遮挡连接 线31可以为非等宽度的直线，第三遮挡连接线31与后续形成的第八有源层相重叠位置的宽度可以大于其它位置的宽度，较宽位置的第三遮挡连接线31可以作为第八晶体管的下栅电极，同时作为第八晶体管的遮挡层，以遮挡第八晶体管的沟道区域，保证氧化物第八晶体管的电学性能。
(5)形成第二半导体层图案。在示例性实施方式中，形成第二半导体层图案可以包括：在形成前述图案的基底上，依次沉积第四绝缘薄膜和第二半导体薄膜，通过图案化工艺对第二半导体薄膜进行图案化，形成覆盖基底的第四绝缘层，以及设置在第四绝缘层上的第二半导体层图案，如图13a和图13b所示，图13b为图13a中第二半导体层的平面示意图。
在示例性实施方式中，每个电路单元的第二半导体层图案至少包括：第八晶体管T8的第八有源层18。
在示例性实施方式中，第八有源层18的形状可以呈“I”字形，第八有源层18在基底上的正投影与第三遮挡连接线31在基底上的正投影至少部分交叠。
在示例性实施方式中，第八有源层18的第一区18-1可以位于第三遮挡连接线31远离第二极板32的一侧，第八有源层18的第二区12-2可以位于第三遮挡连接线31靠近第二极板32的一侧。
在示例性实施方式中，第二半导体层可以采用氧化物，即第八晶体管T8为氧化物晶体管。在示例性实施方式中，第二半导体薄膜可以采用氧化铟镓锌(IGZO)，氧化铟镓锌(IGZO)的电子迁移率高于非晶硅。
(6)形成第三导电层图案。在示例性实施方式中，形成第三导电层图案可以包括：在形成前述图案的基底上，依次沉积第五绝缘薄膜和第三导电薄膜，采用图案化工艺对第三导电薄膜进行图案化，形成覆盖第二半导体层的第五绝缘层，以及设置在第五绝缘层上的第三导电层图案，如图14a和图14b所示，图14b为图14a中第三导电层的平面示意图。在示例性实施方式中，第三导电层可以称为第三栅金属(GATE3)层。
在示例性实施方式中，每个电路单元的第三导电层图案至少包括：第三扫描信号线41和第一初始信号线42。
在示例性实施方式中，第三扫描信号线41的形状可以为主体部分沿着第一方向X延伸的线形状，第M行电路单元中的第三扫描信号线41可以位于本电路单元的第一扫描信号线21远离第M+1行电路单元的一侧，每个电路单元的第三扫描信号线41与第八有源层相重叠的区域作为第八晶体管T8的上栅电极。
在示例性实施方式中，第一初始信号线42的形状可以为主体部分沿着第一方向X延伸的线形状，第M行电路单元中的第一初始信号线42可以位于本电路单元的第三扫描信号线41远离第M+1行电路单元的一侧，第一初始信号线42被配置为通过后续形成的第一晶体管T1的第一极与第一有源层的第一区连接。
(7)形成第六绝缘层图案。在示例性实施方式中，形成第六绝缘层图案可以包括：在形成前述图案的基底上，沉积第六绝缘薄膜，采用图案化工艺对第六绝缘薄膜进行图案化，形成覆盖第三导电层的第六绝缘层，第六绝缘层上设置有多个过孔，如图15所示。
在示例性实施方式中，每个电路单元的多个过孔至少包括：第一过孔V1、第二过孔V2、第三过孔V3、第四过孔V4、第五过孔V5、第六过孔V6、第七过孔V7、第八过孔V8、第九过孔V9、第十过孔V10和第十一过孔V11。
在示例性实施方式中，第一过孔V1在基底上的正投影位于开口34在基底上的正投影的范围之内，第一过孔V1内的第六绝缘层、第五绝缘层、第四绝缘层和第三绝缘层被刻蚀掉，暴露出第一极板24的表面，第一过孔V1配置为使后续形成的第八晶体管T8的第二极通过该过孔与第一极板24连接。
在示例性实施方式中，第二过孔V2位于第二极板32在基底上的正投影的范围之内，第二过孔V2内的第六绝缘层、第五绝缘层和第四绝缘层被刻蚀掉，暴露出第二极板32的表面，第二过孔V2被配置为使后续形成的第五晶体管T5的第一极通过该过孔与第二极板32连接。
在示例性实施方式中，第三过孔V3在基底上的正投影位于第五有源层的第一区在基底上的正投影的范围之内，第三过孔V3内的第六绝缘层、第五绝缘层、第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第五有 源层的第一区的表面，第三过孔V3被配置为使后续形成的第五晶体管T5的第一极通过该过孔与第五有源层的第一区连接。
在示例性实施方式中，第四过孔V4在基底上的正投影位于第六有源层的第二区(也是第七有源层的第二区)在基底上的正投影的范围之内，第四过孔V4内的第六绝缘层、第五绝缘层、第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第六有源层的第二区的表面，第四过孔V4被配置为使后续形成的第六晶体管T6的第二极(也是第七晶体管T7的第二极)通过该过孔与第六有源层的第二区(也是第七有源层的第二区)连接。
在示例性实施方式中，第五过孔V5在基底上的正投影位于第四有源层的第一区在基底上的正投影的范围之内，第五过孔V5内的第六绝缘层、第五绝缘层、第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第四有源层的第一区的表面，第五过孔V5被配置为使后续形成的第四晶体管T4的第一极通过该过孔与第四有源层的第一区连接。
在示例性实施方式中，第六过孔V6在基底上的正投影位于第八有源层的第一区在基底上的正投影的范围之内，第六过孔V6内的第六绝缘层和第五绝缘层被刻蚀掉，暴露出第八有源层的第一区的表面，第六过孔V6被配置为使后续形成的第八晶体管T8的第一极通过该过孔与第八有源层的第一区连接。
在示例性实施方式中，第七过孔V7在基底上的正投影位于第七有源层的第一区在基底上的正投影的范围之内，第七过孔V7内的第六绝缘层、第五绝缘层、第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第七有源层的第一区的表面，第七过孔V7被配置为使后续形成的第二初始信号线通过该过孔与第七有源层的第一区连接。
在示例性实施方式中，第八过孔V8在基底上的正投影位于第一有源层的第一区在基底上的正投影的范围之内，第八过孔V8内的第六绝缘层、第五绝缘层、第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第一有源层的第一区的表面，第八过孔V8被配置为使后续形成的第一晶体管T1的第一极通过该过孔与第一有源层的第一区连接。
在示例性实施方式中，第九过孔V9在基底上的正投影位于第八有源层 的第二区在基底上的正投影的范围之内，第九过孔V9内的第六绝缘层和第五绝缘层被刻蚀掉，暴露出第八有源层的第二区的表面，第九过孔V9被配置为使后续形成的第八晶体管T8的第二极通过该过孔与第八有源层的第二区连接。
在示例性实施方式中，第十过孔V10在基底上的正投影位于第一有源层的第二区(也是第二有源层的第一区)在基底上的正投影的范围之内，第十过孔V10内的第六绝缘层、第五绝缘层、第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第一有源层的第二区的表面，第十过孔V10被配置为使后续形成的第一晶体管T1的第二极(也是第二晶体管T2的第一极)通过该过孔与第一有源层的第二区(也是第二有源层的第一区)连接。
在示例性实施方式中，第十一过孔V11在基底上的正投影位于第一初始信号线42在基底上的正投影的范围之内，第十一过孔V11内的第六绝缘层被刻蚀掉，暴露出第一初始信号线42的表面，第十一过孔V11被配置为使后续形成的第一晶体管T1的第一极通过该过孔与第一初始信号线42连接。
在示例性实施方式中，第六绝缘层上设置有多个过孔还可以包括第十二过孔V12，第十二过孔V12在基底上的正投影位于第一连接线71的第一连接块71-1在基底上的正投影的范围之内，第十二过孔V12内的第六绝缘层、第五绝缘层、第四绝缘层、第三绝缘层、第二绝缘层和第一绝缘层被刻蚀掉，暴露出第一连接块71-1的表面，第十二过孔V12可以作为本公开的第一搭接过孔，第十二过孔V12被配置为使后续形成的第二连接线通过该过孔与第一连接块71-1连接。
在示例性实施方式中，第十二过孔V12可以为多个，多个第十二过孔V12可以沿着第二方向Y依次设置，以增加第一连接线和第二连接线连接的可靠性。
(8)形成第四导电层图案。在示例性实施方式中，形成第四导电层可以包括：在形成前述图案的基底上，沉积第四导电薄膜，采用图案化工艺对第四导电薄膜进行图案化，形成设置在第六绝缘层上的第四导电层，如图16a和图16b所示，图16b为图16a中第四导电层的平面示意图。在示例性实施方式中，第四导电层可以称为第一源漏金属(SD1)层。
在示例性实施方式中，每个电路单元的第四导电层至少包括：第一连接电极51、第二连接电极52、第三连接电极53、第四连接电极54、第五连接电极55、第六连接电极56和第二初始信号线57。
在示例性实施方式中，第一连接电极51的形状可以为主体部分沿着第二方向Y延伸的条形形，第一连接电极51的第一端通过第一过孔V1与第一极板24连接，第一连接电极51的第二端通过第九过孔V9与第八有源层的第二区连接，使第一极板24和第八晶体管T8的第二极具有相同的电位。在示例性实施方式中，第一连接电极51可以作为第八晶体管T8的第二极。
在示例性实施方式中，第二连接电极52的形状可以为矩形状，第二连接电极52的第一端通过第十一过孔V11与第一初始信号线42连接，第二连接电极52的第二端通过第八过孔V8与第一有源层的第一区连接，使第一初始信号线42传输的第一初始电压写入第一晶体管T1的第一极。在示例性实施方式中，第二连接电极52可以作为第一晶体管T1的第一极。
在示例性实施方式中，第三连接电极53的形状可以为矩形状，第三连接电极53通过第五过孔V5与第四有源层的第一区连接。在示例性实施方式中，第三连接电极53可以作为第四晶体管T4的第一极，第三连接电极53被配置为与后续形成的数据信号线连接。
在示例性实施方式中，第四连接电极54的形状可以为多边形状，第四连接电极54的第一端通过第二过孔V2与第二极板32连接，第四连接电极54的第二端通过第三过孔V3与第五有源层的第一区连接。在示例性实施方式中，第四连接电极54可以作为第五晶体管T5的第一极，实现了电路单元中第五晶体管T5的第一极和存储电容的第二极板32具有相同的电位，第四连接电极54被配置为与后续形成的第一电源线连接。
在示例性实施方式中，每个单元行中，第N-2列的第四连接电极54和第N-1列的第四连接电极54可以为相互连接的一体结构，第N列的第四连接电极54和第N+1列的第四连接电极54可以为相互连接的一体结构。在示例性实施方式中，由于每个电路单元中的第四连接电极54与后续形成的第一电源线连接，通过将相邻电路单元的第四连接电极54形成相互连接的一体结构，可以保证相邻电路单元的第四连接电极54具有相同的电位，因而使得相 邻电路单元中第五晶体管T5的第一极具有相同的电位，相邻电路单元中存储电容的第二极板32具有相同的电位，有利于提高面板的均一性，避免显示基板的显示不良，保证显示基板的显示效果。
在示例性实施方式中，第五连接电极55的形状可以为矩形状，第五连接电极55的第一端通过第十过孔V10与第一有源层的第二区连接，第五连接电极55的第二端通过第六过孔V6与第八有源层的第一区连接。在示例性实施方式中，第五连接电极55可以同时作为第一晶体管T1的第二极、第二晶体管T2的第一极和第八晶体管T8的第一极。
在示例性实施方式中，第六连接电极56的形状可以为矩形状，第六连接电极56通过第四过孔V4与第六有源层的第二区(也是第七有源层的第二区)连接。在示例性实施方式中，第六连接电极56可以同时作为第六晶体管T6的第二极和第七晶体管T7的第二极，第六连接电极56被配置为与后续形成的阳极连接电极连接。
在示例性实施方式中，第二初始信号线57的形状可以为主体部分沿着第一方向X延伸的直线状，第二初始信号线57通过一单元行中的多个第七过孔V7与多个第七有源层的第一区连接，将第二初始电压写入一单元行中多个第七晶体管T7。在示例性实施方式中，由于第二初始信号线57与一个单元行中所有的第七有源层的第一区连接，可以保证一个单元行中所有的第七晶体管T7的第一极具有相同的电位，有利于提高面板的均一性，避免显示基板的显示不良，保证显示基板的显示效果。
在示例性实施方式中，第四导电层还可以包括第二连接线72，第二连接线72的第一端通过第十二过孔V12与第一连接线71连接，第二连接线72的第二端与相应电路单元中的第三连接电极53连接，因而实现了位于第四导电层中的第二连接线72与位于遮挡导电层中的第一连接线71连接。
在示例性实施方式中，至少一个第二连接线72可以包括第二连接块72-1以及依次连接的多条子线，多条子线可以至少包括第一子线72-A、第二子线72-B、第三子线72-C和第四子线72-D。
在示例性实施方式中，第二连接块72-1的形状可以为沿着第二方向Y延伸的条形状，且与第二连接线72连接，第二连接块72-1在基底上的正投 影与第一连接线71的第一连接块71-1在基底上的正投影至少部分交叠，第二连接块72-1通过第十二过孔V12与第一连接块71-1连接，因而实现了第一连接线71与第二连接线72的连接。
在示例性实施方式中，第一子线72-A的第一端与第二连接块72-1连接，第一子线72-A的第二端沿着第二方向Y的反方向延伸后，与第二子线72-B的第一端连接。第二子线72-B的第二端沿着第一方向X或者第一方向X的反方向延伸后，与第三子线72-C的第一端连接。第三子线72-C的第二端沿着第二方向Y延伸后，与第四子线72-D的第一端连接。第四子线72-D的第二端沿着第一方向X或者第一方向X的反方向延伸后，与第三连接电极53连接。
在示例性实施方式中，第二连接块72-1、第一子线72-A、第二子线72-B、第三子线72-C、第四子线72-D和第三连接电极53可以为相互连接的一体结构。
在示例性实施方式中，第一子线72-A可以设置在相邻的单元列之间，即第一子线72-A可以设置在第一方向X相邻的电路单元之间。
在示例性实施方式中，第二子线72-B可以为沿着第一方向X延伸的折线状，第二子线72-B在基底上的正投影与第二扫描信号线22在基底上的正投影至少部分交叠，第二子线72-B在基底上的正投影与第一初始信号线42在基底上的正投影至少部分交叠。
在示例性实施方式中，第二子线72-B可以包括至少一个向着绑定区域方向凸出的凸出段72-E，凸出段72-E的形状可以是梯形状。
在示例性实施方式中，第三子线72-C可以设置在相邻的单元列之间，即第三子线72-C可以设置在第一方向X相邻的电路单元之间。
(9)形成第一平坦层图案。在示例性实施方式中，形成第一平坦层图案可以包括：在形成前述图案的基底上，先沉积第七绝缘薄膜，然后涂覆第一平坦薄膜，采用图案化工艺对第一平坦薄膜和第七绝缘薄膜进行图案化，形成覆盖第四导电层图案的第七绝缘层以及设置在第七绝缘层上的第一平坦层，第一平坦层上设置有多个过孔，如图17所示。
在示例性实施方式中，每个电路单元中的多个过孔至少包括：第二十一过孔V21、第二十二过孔V22和第二十三过孔V23。
在示例性实施方式中，第二十一过孔V21在基底上的正投影位于第三连接电极53在基底上的正投影的范围之内，第二十一过孔V21内的第一平坦层和第七绝缘层被刻蚀掉，暴露出第三连接电极53的表面，第二十一过孔V21被配置为使后续形成的数据信号线通过该过孔与第三连接电极53连接，第二十一过孔V21可以作为本公开的第二搭接过孔。
在示例性实施方式中，第二十二过孔V22在基底上的正投影位于第四连接电极54在基底上的正投影的范围之内，第二十二过孔V22内的第一平坦层和第七绝缘层被刻蚀掉，暴露出第四连接电极54的表面，第二十二过孔V22被配置为使后续形成的第一电源线该过孔与第四连接电极54连接。
在示例性实施方式中，第二十三过孔V23在基底上的正投影位于第六连接电极56在基底上的正投影的范围之内，第二十三过孔V23内的第一平坦层和第七绝缘层被刻蚀掉，暴露出第六连接电极56的表面，第二十三过孔V232被配置为使后续形成的阳极连接电极该过孔与第六连接电极56连接。
(10)形成第五导电层图案。在示例性实施方式中，形成第五导电层可以包括：在形成前述图案的基底上，沉积第五导电薄膜，采用图案化工艺对第五导电薄膜进行图案化，形成设置在第一平坦层上的第五导电层，如图18a至图18d所示，图18a为形成一种第五导电层图案后的示意图，图18b为图18a中第五导电层的平面示意图，图18c为形成另一种第五导电层图案后的示意图，图18d为图18c中第五导电层的平面示意图。在示例性实施方式中，第五导电层可以称为第二源漏金属(SD2)层。
如图18a和图18b所示，每个电路单元的第五导电层至少包括：数据信号线60、阳极连接电极61和第一电源线62。
在示例性实施方式中，数据信号线60的形状可以为主体部分沿着第二方向Y延伸的直线形，数据信号线60通过第二十一过孔V21与第三连接电极53连接。由于第三连接电极53通过过孔与第四有源层的第一区连接，因而实现了数据信号线60与第四晶体管T4的第一极的连接，数据信号线60可以将数据信号写入第四晶体管T4的第一极。同时，由于部分电路单元中的 第三连接电极53与第二连接线72连接，第二连接线72通过过孔与第一连接线71连接，第一连接线71与绑定区域的引出线连接，引出线与集成电路连接，因而实现了数据信号线60通过第一连接线71、第二连接线72和引出线与绑定区域的集成电路连接，集成电路可以将数据信号出输给数据信号线60。
在示例性实施方式中，阳极连接电极61的形状可以为矩形状，阳极连接电极61通过第二十三过孔V23与第六连接电极56连接，阳极连接电极61被配置为与后续形成的阳极连接。
在示例性实施方式中，第一电源线62的形状可以为主体部分沿着第二方向Y延伸的折线形，第一电源线62通过第二十二过孔V22与第四连接电极54连接。由于第四连接电极54分别通过过孔与第二极板32和第五有源层的第一区连接，因而实现了第一电源线62可以将第一电源信号写入第五晶体管T5的第一极，且第五晶体管T5的第一极和存储电容的第二极板具有相同的电位。
在示例性实施方式中，由于单元行中相邻电路单元的第四连接电极54为相互连接的一体结构，因而相邻的第一电源线62与同一个第四连接电极54连接，因而使得相邻的第一电源线62具有相同的电位，有利于提高面板的均一性，避免显示基板的显示不良，保证显示基板的显示效果。
在示例性实施方式中，第一电源线62可以为非等宽度的折线，不仅可以便于像素结构的布局，而且可以降低第一电源线与数据信号线之间的寄生电容。
在示例性实施方式中，第一电源线62在基底上的正投影可以与第一连接电极51在基底上的正投影至少部分交叠，使得第一电源线62可以作为屏蔽电极，可以有效屏蔽数据电压跳变对像素驱动电路中关键节点的影响，避免了数据电压跳变影响像素驱动电路的关键节点的电位，提高了显示效果。
在示例性实施方式中，第一电源线62在基底上的正投影可以与第二连接电极52在基底上的正投影至少部分交叠，第一电源线62在基底上的正投影可以与第五连接电极55在基底上的正投影至少部分交叠。
如图18c和图18d所示，每个电路单元中第五导电层的结构与图18a和 图18b所示结构基本上相近，所不同的是，一个单元行中相邻两个电路单元中的第一电源线62可以相互连接，在两个单元列中形成一体结构的第一电源线62。例如，第N-1列的第一电源线62和第N列的第一电源线62可以为相互连接的一体结构。又如，第N+1列的第一电源线62和第N+2列的第一电源线62可以为相互连接的一体结构。本公开通过将相邻电路单元的第一电源线62设置成相互连接的一体结构，不仅可以有利于提高面板的均一性，避免显示基板的显示不良，而且可以有效遮挡连接第一连接线和第二连接线的第一搭接过孔，避免因搭接过孔导致的散光，保证显示基板的显示品质和显示效果。
(11)形成第二平坦层图案。在示例性实施方式中，形成第二平坦层图案可以包括：在形成前述图案的基底上，涂覆第二平坦薄膜，采用图案化工艺对第二平坦薄膜进行图案化，形成覆盖第五导电层图案的第二平坦层，第二平坦层上设置有多个过孔，如图19所示。
在示例性实施方式中，每个电路单元中的过孔至少包括第三十一过孔V31。
在示例性实施方式中，第三十一过孔V31在基底上的正投影位于阳极连接电极61在基底上的正投影的范围之内，第三十一过孔V31内的第二平坦层被去掉，暴露出阳极连接电极61的表面，第三十一过孔V31被配置为使后续形成的阳极通过该过孔与阳极连接电极61连接。
至此，在基底上制备完成驱动电路层。在平行于显示基板的平面内，驱动电路层可以包括多个电路单元，每个电路单元可以包括像素驱动电路，以及与像素驱动电路连接的第一扫描信号线、第二扫描信号线、第三扫描信号线、发光控制线、数据信号线、第一电源线、第一初始信号线和第二初始信号线。
在垂直于显示基板的平面内，所述驱动电路层可以包括在基底上依次设置的遮挡导电层、第一绝缘层、第一半导体层、第二绝缘层、第一导电层、第三绝缘层、第二导电层、第四绝缘层、第二半导体层、第五绝缘层、第三导电层、第六绝缘层、第四导电层、第七绝缘层、第一平坦层、第五导电层、第二平坦层。遮挡导电层可以至少包括第一连接线，第一半导体层可以至少 包括第一晶体管至第七晶体管的有源层，第一导电层可以至少包括第一晶体管至第七晶体管的栅电极和存储电容的第一极板，第二导电层可以至少包括存储电容的第二极板和第八晶体管的下栅电极，第二半导体层可以至少包括第八晶体管的有源层，第三导电层可以至少包括第八晶体管的上栅电极，第四导电层可以至少包括第二连接线以及多个晶体管的第一极和第二极，第二连接线通过第一搭接过孔与第一连接线连接，第五导电层可以至少包括数据信号线和第一电源线，数据信号线通过第二搭接过孔与第二连接线连接。
在示例性实施方式中，基底可以是柔性基底，或者可以是刚性基底。刚性基底可以包括但不限于玻璃、石英中的一种或多种，柔性衬底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。在示例性实施方式中，柔性基底可以包括在玻璃载板上叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层。第一、第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一、第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基底的抗水氧能力，第一、第二无机材料层也称为阻挡(Barrier)层，半导体层的材料可以采用非晶硅(a-si)。
在示例性实施方式中，第一导电层、第二导电层、第三导电层、第四导电层和第五导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层、第五绝缘层、第六绝缘层和第七绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。第一绝缘层可以称为缓冲(Buffer)层，第二绝缘层、第三绝缘层、第四绝缘层和第五绝缘层可以称为栅绝缘(GI)层，第六绝缘层可以称为层间绝缘(ILD)层，第七绝缘层可以称为钝化(PVX)层。第一平坦层和第二平坦层可以采用有机材料，如树脂等。
在示例性实施方式中，一个单元行中相邻两个电路单元中的像素驱动电路可以相对于第一中心线基本上镜像对称，第一中心线是位于相邻两个电路单元之间且沿着第二方向Y延伸的直线。例如，第N-1列的像素驱动电路和第N列的像素驱动电路可以相对于第一中心线镜像对称。又如，第N列的像素驱动电路和第N+1列的像素驱动电路可以相对于第一中心线镜像对称。
在示例性实施方式中，相邻两个电路单元中的像素驱动电路可以相对于第一中心线基本上镜像对称可以包括如下任意一种或多种：一个单元行中相邻两个电路单元中的第一半导体层可以相对于第一中心线镜像对称，一个单元行中相邻两个电路单元中的第一导电层可以相对于第一中心线镜像对称，一个单元行中相邻两个电路单元中的第二导电层可以相对于第一中心线镜像对称，一个单元行中相邻两个电路单元中的第二半导体层可以相对于第一中心线镜像对称，一个单元行中相邻两个电路单元中的第三导电层可以相对于第一中心线镜像对称，一个单元行中相邻两个电路单元中的第五导电层可以相对于第一中心线镜像对称。
在示例性实施方式中，除了第一连接线，一个单元行中相邻两个电路单元中的遮挡导电层可以相对于第一中心线镜像对称。除了第二连接线，一个单元行中相邻两个电路单元中的第四导电层可以相对于第一中心线镜像对称。
在示例性实施方式中，制备完成驱动电路层后，可以在驱动电路层上制备发光结构层，发光结构层的制备过程可以包括如下操作。
(12)形成阳极导电层图案。在示例性实施方式中，形成阳极导电层图案可以包括：在形成前述图案的基底上，沉积阳极导电薄膜，采用图案化工艺对阳极导电薄膜进行图案化，形成设置在第三平坦层上的阳极导电层，阳极导电层可以至少包括多个阳极图案，如图20a和图20b所示，图20b为图20a中阳极导电层的平面示意图。
在示例性实施方式中，阳极导电层采用单层结构，如氧化铟锡ITO或氧化铟锌IZO，或者可以采用多层复合结构，如ITO/Ag/ITO等。
在示例性实施方式中，多个阳极图案可以包括红色发光器件的第一阳极301A、蓝色发光器件的第二阳极301B、第一绿色发光器件的第三阳极301C 和第二绿色发光器件的第四阳极301D，第一阳极301A可以位于出射红色光线的红色子像素，第二阳极301B可以位于出射蓝色光线的蓝色子像素，第三阳极301C可以位于出射绿色光线的第一绿色子像素，第四阳极301D可以位于出射绿色光线的第二绿色子像素。
在示例性实施方式中，第一阳极301A和第二阳极301B可以沿着第一方向X依次设置，第三阳极301C和第四阳极301D可以沿着第一方向X依次设置，第三阳极301C和第四阳极301D可以设置在第一阳极301A和第二阳极301B第二方向Y的一侧。或者，第一阳极301A和第二阳极301B可以沿着第二方向Y依次设置，第三阳极301C和第四阳极301D可以沿着第二方向Y依次设置，第三阳极301C和第四阳极301D可以设置在第一阳极301A和第二阳极301B第一方向X的一侧。
在示例性实施方式中，第一阳极301A、第二阳极301B、第三阳极301C和第四阳极301D可以分别通过第三十一过孔V31与对应电路单元的阳极连接电极61连接，一个像素单元中四个子像素的阳极形状和面积可以相同，或者可以不同。
在示例性实施方式中，第一阳极301A、第二阳极301B、第三阳极301C和第四阳极301D中的至少一个可以包括相互连接的阳极主体部和阳极连接部，阳极主体部的形状可以为矩形状，矩形状的角部可以设置圆弧状的倒角，阳极连接部的形状可以为沿着第一方向X或者第二方向Y延伸的条形状，阳极连接部通过第三十一过孔V31与阳极连接电极61连接。由于阳极连接电极61通过过孔与与第六有源层的第二区(也是第七有源层的第二区)连接，因而可以实现阳极与第六晶体管T6的第二极和第七晶体管T7的第二极的连接。
在示例性实施方式中，可以根据搭接过孔的位置适应性调整相应阳极的位置和形状，利用阳极对搭接过孔进行有效遮挡，避免因搭接过孔导致的散光。例如，对于一些未能被第一电源线遮挡的第一搭接过孔，可以调整第一搭接过孔所在区域的阳极的位置和形状，在阳极上设置遮挡凸起，遮挡凸起向着第一搭接过孔所在位置延伸，遮挡凸起在基底上的正投影包含第一搭接过孔在基底上的正投影，实现对第一搭接过孔的遮挡。
在示例性实施方式中，后续制备流程可以包括：先形成像素定义层图案，然后采用蒸镀或喷墨打印工艺形成有机发光层，然后在有机发光层上形成阴极，然后形成封装结构层，封装结构层可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可以采用无机材料，第二封装层可以采用有机材料，第二封装层设置在第一封装层和第三封装层之间，可以保证外界水汽无法进入发光结构层。
一种采用FIAA结构的显示基板需要增加第三源漏金属层(SD3)，且将第一连接线和第二连接线设置在第三源漏金属层中。研究发现，由于第一连接线和第二连接线不可避免地会与阳极重叠，使得各个区域的阳极平坦性不一致，存在阳极高度差，不仅会导致大视角色偏，而且会导致熄屏水印等不良。
本公开提供的显示基板，第一连接线设置在遮挡导电层，第二连接线设置在第四导电层，数据信号线设置在第五导电层，数据信号线通过过孔与第二连接线连接，第二连接线通过过孔与第一连接线连接，实现了集成电路通过第一连接线和第二连接线将数据信号提供给数据信号线，可以有效缩减绑定区域中引出线区的宽度，可以有效减小下边框宽度，有利于实现全面屏。本公开示例性实施例将第一连接线设置在遮挡导电层，第二连接线设置在第四导电层，由于第一连接线和阳极之间设置有多个无机绝缘层和2个平坦层，第二连接线和阳极之间设置有至少2个平坦层，有机材料的平坦层比较厚，因而第一连接线和第二连接线不会影响阳极的平坦性，可以避免阳极高度差，可以保证各个区域中发光器件的发光性能基本上相同，不仅避免了大视角色偏，而且避免了熄屏水印等不良，提高了显示基板的品质。本公开示例性实施例不需要设置第三源漏金属层，不仅简化了显示基板的结构，而且节省了两次图案化工艺(第三源漏金属层图案化和第三平坦性图案化)，最大限度地节约了生产成本。本公开的制备工艺可以很好地与现有制备工艺兼容，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。
本公开前述所示结构及其制备过程仅仅是一种示例性说明，在示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺，本公开在此不做限定。
在示例性实施方式中，本公开显示基板可以应用于具有像素驱动电路的其它显示装置中，如如量子点显示等，本公开在此不做限定。
本公开还提供一种显示基板的制备方法，以制作上述实施例提供的显示基板。在示例性实施方式中，在平行于所述显示基板的平面内，所述显示基板包括形成多个单元行和多个单元列的多个电路单元，至少一个电路单元包括像素驱动电路，所述制备方法可以包括：
在基底上形成遮挡导电层，所述遮挡导电层至少包括第一连接线；
在所述遮挡导电层上形成功能结构层，所述功能结构层至少包括第二连接线和数据信号线，所述数据信号线与一个单元列的多个像素驱动电路连接，所述数据信号线被配置为向所述像素驱动电路提供数据信号，所述第二连接线与所述第一连接线连接，所述数据信号线通与所述第二连接线连接。
本公开还提供一种显示装置，显示装置包括前述的显示基板。显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，本发明实施例并不以此为限。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本发明。任何所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (20)

  1. 一种显示基板，包括设置在基底上的遮挡导电层和设置在所述遮挡导电层远离所述基底一侧的功能结构层，所述遮挡导电层至少包括第一连接线，所述功能结构层至少包括数据信号线和第二连接线；在平行于所述显示基板的平面内，所述显示基板包括形成多个单元行和多个单元列的多个电路单元，至少一个电路单元包括像素驱动电路，所述数据信号线与一个单元列的多个像素驱动电路连接，所述数据信号线被配置为向所述像素驱动电路提供数据信号；所述第二连接线与所述第一连接线连接，所述数据信号线与所述第二连接线连接。
  2. 根据权利要求1所述的显示基板，其中，所述功能结构层包括多个导电层，所述第二连接线和所述数据信号线设置在不同的导电层，所述第二连接线通过第一搭接过孔与所述第一连接线连接，所述数据信号线通过第二搭接过孔与所述第二连接线连接。
  3. 根据权利要求2所述的显示基板，其中，在平行于所述显示基板的平面上，所述显示基板包括显示区域和位于所述显示区域第二方向一侧的绑定区域，所述绑定区域至少包括引出线；所述第一连接线的第一端与所述引出线连接，所述第一连接线的第二端延伸到所述显示区域后，通过所述第一搭接过孔与所述第二连接线的第一端连接，所述第二连接线的第二端沿着第一方向延伸后，通过所述第二搭接过孔与所述数据信号线连接，所述第一方向与所述第二方向交叉。
  4. 根据权利要求3所述的显示基板，其中，所述第一连接线靠近所述第二连接线的端部设置有第一连接块，所述第一连接块在所述基底上的正投影与所述第二连接线在所述基底上的正投影至少部分交叠，所述第二连接线通过所述第一搭接过孔与所述第一连接块连接。
  5. 根据权利要求3所述的显示基板，其中，所述第二连接线靠近所述第一连接线的端部设置有第二连接块，所述第二连接块在所述基底上的正投影与所述第一连接线在所述基底上的正投影至少部分交叠，所述第二连接块通过所述第一搭接过孔与所述第一连接线连接。
  6. 根据权利要求3所述的显示基板，其中，所述第一连接线靠近所述第二连接线的端部设置有第一连接块，所述第一连接块在所述基底上的正投影与所述第二连接块在所述基底上的正投影至少部分交叠，所述第二连接块通过所述第一搭接过孔与所述第一连接块连接。
  7. 根据权利要求3所述的显示基板，其中，所述第二连接线至少包括第一子线、第二子线、第三子线和第四子线，所述第一子线的第一端与所述第一连接线的第二端连接，所述第一子线的第二端沿着所述单元列的方向延伸后，与所述第二子线的第一端连接，所述第二子线的第二端沿着所述单元行的方向延伸后，与所述第三子线的第一端连接，所述第三子线的第二端沿着所述单元列的方向延伸后，与所述第四子线的第一端连接，所述第四子线的第二端沿着所述单元行的方向延伸后，与所述数据信号线连接。
  8. 根据权利要求7所述的显示基板，其中，所述第一子线设置在相邻的单元列之间。
  9. 根据权利要求7所述的显示基板，其中，所述第二子线的形状为沿着所述单元行方向延伸的折线，所述第二子线包括至少一个向着所述绑定区域方向凸出的凸出段。
  10. 根据权利要求7所述的显示基板，其中，所述第三子线设置在相邻的单元列之间。
  11. 根据权利要求7所述的显示基板，其中，所述像素驱动电路至少包括数据写入晶体管，所述功能结构层还包括数据写入晶体管的第一极，至少一个电路单元中，所述第四子线与所述数据写入晶体管的第一极连接，所述数据信号线通过所述第二搭接过孔与所述数据写入晶体管的第一极连接。
  12. 根据权利要求11所述的显示基板，其中，所述第四子线和所述数据写入晶体管的第一极同层设置，且为相互连接的一体结构。
  13. 根据权利要求7所述的显示基板，其中，所述功能结构层还包括第一初始信号线，所述第一初始信号线被配置为向所述像素驱动电路提供第一初始信号，所述第二子线在所述基底上的正投影与所述第一初始信号线在所述基底上的正投影至少部分交叠。
  14. 根据权利要求1所述的显示基板，其中，所述第一连接线设置在相邻的单元列之间。
  15. 根据权利要求1所述的显示基板，其中，所述遮挡导电层还包括遮挡电极和第一遮挡连接线，所述遮挡电极设置在所述电路单元，所述第一遮挡连接线与一个单元列中的多个遮挡电极连接。
  16. 根据权利要求1所述的显示基板，其中，所述遮挡导电层包括叠设的第一钛层、铝层和第二钛层，所述第一钛层的厚度为40nm至60nm，所述铝层的厚度为250nm至550nm，所述第二钛层的厚度为20nm至40nm。
  17. 根据权利要求1至16任一项所述的显示基板，其中，所述像素驱动电路包括存储电容和多个晶体管；在垂直于所述显示基板的平面上，所述功能结构层至少包括设置在所述遮挡导电层远离所述基底一侧的第一导电层、第二导电层、第三导电层、第四导电层和第五导电层，所述第一导电层至少包括存储电容的第一极板和多个晶体管的栅电极，所述第二导电层至少包括存储电容的第二极板，所述第四导电层至少包括所述第二连接线，所述第五导电层至少包括所述数据信号线。
  18. 根据权利要求17所述的显示基板，其中，所述多个晶体管包括至少一个多晶硅晶体管和至少一个氧化物晶体管，所述功能结构层还包括第一半导体层和第二半导体层，所述第一半导体层设置在所述遮挡导电层和第一导电层之间，所述第一半导体层包括所述多晶硅晶体管的有源层，所述第二半导体层设置在所述第二导电层和第三导电层之间，所述第二半导体层包括所述氧化物晶体管的有源层。
  19. 一种显示装置，包括如权利要求1至18任一项所述的显示基板。
  20. 一种显示基板的制备方法，在平行于所述显示基板的平面内，所述显示基板包括形成多个单元行和多个单元列的多个电路单元，至少一个电路单元包括像素驱动电路，所述制备方法包括：
    在基底上形成遮挡导电层，所述遮挡导电层至少包括第一连接线；
    在所述遮挡导电层上形成功能结构层，所述功能结构层至少包括第二连接线和数据信号线，所述数据信号线与一个单元列的多个像素驱动电路连接， 所述数据信号线被配置为向所述像素驱动电路提供数据信号，所述第二连接线与所述第一连接线连接，所述数据信号线通与所述第二连接线连接。
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CN114220834A (zh) * 2021-12-09 2022-03-22 武汉华星光电半导体显示技术有限公司 显示面板
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CN114497151A (zh) * 2022-01-12 2022-05-13 武汉华星光电半导体显示技术有限公司 一种显示面板

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CN111326560A (zh) * 2020-01-23 2020-06-23 京东方科技集团股份有限公司 显示基板和显示装置
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