WO2024060082A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

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Publication number
WO2024060082A1
WO2024060082A1 PCT/CN2022/120286 CN2022120286W WO2024060082A1 WO 2024060082 A1 WO2024060082 A1 WO 2024060082A1 CN 2022120286 W CN2022120286 W CN 2022120286W WO 2024060082 A1 WO2024060082 A1 WO 2024060082A1
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WIPO (PCT)
Prior art keywords
line
area
sub
substrate
display
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PCT/CN2022/120286
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English (en)
French (fr)
Inventor
刘畅畅
石领
陈立强
田学伟
崔国意
吴俣
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/120286 priority Critical patent/WO2024060082A1/zh
Priority to CN202280003235.9A priority patent/CN118076990A/zh
Publication of WO2024060082A1 publication Critical patent/WO2024060082A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters

Definitions

  • This article relates to but is not limited to the field of display technology, and specifically relates to a display substrate, a preparation method thereof, and a display device.
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diodes
  • TFT thin film transistors
  • the present disclosure provides a display substrate, including a display area, a side frame area located on at least one side of the display area in a first direction, and a binding area located on one side of the display area in a second direction.
  • the frame area at least includes a first frame area and a second frame area, the first frame area is located on a side of the second frame area close to the binding area, and the first direction intersects the second direction;
  • the display substrate includes a base and a driving circuit layer disposed on the base.
  • the base includes at least a first connection line.
  • the driving circuit layer at least includes a data signal line and a second connection line.
  • the second connection line The data signal line is connected to the first connecting line through a first overlapping via hole, and the data signal line is connected to the second connecting line through a second overlapping via hole.
  • the first overlapping via hole is provided on the first connecting line.
  • the display substrate includes a first center line, which is a straight line bisecting the display area in the second direction and extending along the first direction, and the first center line is a straight line bisecting the display area in the second direction and extending along the first direction.
  • the first frame area is located on the side of the first center line close to the binding area, and the first connection line and the second connection line are located on the side of the first center line close to the binding area.
  • the display substrate includes a second center line, which is a straight line bisecting the display area in the first direction and extending along the second direction; along In the direction away from the first centerline, the distance between the plurality of second overlapping vias and the second centerline gradually increases. Along the direction away from the second centerline, the distance between the plurality of second overlapping vias and the second centerline gradually increases. The distance between the via holes and the first centerline gradually increases; or, along the direction away from the first centerline, the distance between the plurality of second overlapping via holes and the second centerline gradually increases. The distance between the plurality of second overlapping vias and the first centerline gradually decreases along the direction away from the second centerline.
  • the binding area at least includes a lead wire, a first end of the lead wire is connected to the integrated circuit in the binding area, and a second end of the lead wire is connected to the third
  • the first end of a connecting line is connected, and the second end of the first connecting line extends from the binding area through the display area to the first frame area, and is connected with the first overlapping via hole.
  • the first end of the second connection line is connected, and the second end of the second connection line extends from the first frame area to the display area and is connected to the data through the second overlapping via hole.
  • the side frame area includes an encapsulation area and a non-encapsulation area divided by an encapsulation line.
  • the encapsulation line is a boundary where the encapsulation structure layer covers the side frame area.
  • the encapsulation area is provided on the The packaging line is on a side close to the display area, the non-encapsulation area is provided on a side of the packaging line away from the display area, and the first overlapping via is provided in the non-encapsulation area.
  • the driving circuit layer at least includes a first conductive layer, a second conductive layer and a third conductive layer sequentially disposed on the substrate, and the second connection line is disposed on the first conductive layer. layer or the second conductive layer, the data signal line is provided in the third conductive layer.
  • the first connection line includes at least a first sub-line and a second sub-line, a first end of the second sub-line is connected to the leading line of the binding area, and the second sub-line
  • the second end of the sub-line extends to the display area along the second direction and is connected to the first end of the first sub-line.
  • the second end of the first sub-line extends along the first After the direction extends to the first frame area, it is connected to the first end of the second connection line through the first overlapping via hole.
  • the orthographic projection of the first sub-line on the substrate is the same as the second connection line. Orthographic projections on the substrate at least partially overlap.
  • the extension length of the plurality of second connection lines gradually increases, or the extension length of the second connection lines gradually decreases.
  • the driving circuit layer includes circuit units constituting a plurality of unit rows and a plurality of unit columns, at least one circuit unit includes a pixel driving circuit, and at least one pixel driving circuit includes a storage capacitor and a plurality of transistors, so The orthographic projection of the first connection line and the second connection line on the substrate does not overlap with the orthographic projection of the storage capacitor and the plurality of transistors on the substrate.
  • the display substrate includes a plurality of lead wire groups, and at least one lead wire group includes k first sub-lines and k first sub-lines correspondingly connected to the k first sub-lines through k first overlapping vias.
  • Second connection lines, k second connection lines are connected to k data signal lines through k second overlapping vias, k is a positive integer greater than or equal to 1; in the display area, at least one lead group is provided between adjacent rows of cells.
  • the distance between the i-th lead group and the i+1-th lead group is equal to the distance between the i+1-th lead group and the i+2-th lead group, i is a positive integer greater than or equal to 1 and less than or equal to N-2, and N is the number of lead groups.
  • k is 2, and the spacing between the two second overlapping vias in the i-th lead group is equal to the spacing between the two second overlapping vias in the i+1th lead group.
  • the side frame area at least includes a gate circuit area, and the gate circuit area includes a plurality of gate circuit groups arranged sequentially along the second direction, and adjacent gate circuit groups A wiring area is provided between them.
  • at least one lead group is provided in the wiring area;
  • at least one gate circuit group includes m scanning gate circuits arranged sequentially along the second direction. and n light-emitting gate circuits arranged sequentially along the second direction, the n light-emitting gate circuits are arranged on the side of the m scanning gate circuits away from the display area, m is greater than or equal to 2 is a positive integer, n is a positive integer greater than or equal to 1.
  • At least one scan gate circuit includes a plurality of scan transistors and a scan storage capacitor
  • at least one light-emitting gate circuit includes a plurality of light-emitting transistors and a light-emitting storage capacitor
  • in at least one lead group, the first sub-section The orthographic projection of the line and the second connection line on the substrate does not overlap with the orthographic projection of the scanning transistor, the scanning storage capacitor, the light-emitting transistor and the light-emitting storage capacitor on the substrate.
  • the gate circuit area further includes at least one start signal line and at least one clock signal line extending along the second direction.
  • the orthographic projection of the first sub-line on the substrate does not overlap with the orthographic projection of the second connection line on the substrate.
  • the first sub-line in the side frame area outside the first overlapping area, for the first sub-line and the second connection line transmitting the same data signal, the first sub-line is on the substrate.
  • the orthographic projection of the second connection line at least partially overlaps with the orthographic projection of the second connection line on the substrate.
  • At least one first sub-line or at least one second connection line is provided with a resistance compensation structure, and the resistance compensation structure is provided on a side of the gate circuit area away from the display area.
  • the present disclosure also provides a display device, including the aforementioned display substrate.
  • the present disclosure also provides a method for preparing a display substrate, which includes a display area, a side frame area located on at least one side of the display area in a first direction, and a side frame area located on at least one side of the display area in a second direction.
  • a side binding area, the side frame area at least includes a first frame area and a second frame area, the first frame area is located on the side of the second frame area close to the binding area, the first The direction intersects the second direction;
  • the preparation method includes:
  • the substrate including at least a first connection line
  • a driving circuit layer is formed on the substrate.
  • the driving circuit layer at least includes a data signal line and a second connection line.
  • the second connection line is connected to the first connection line through a first overlapping via hole.
  • the data signal line is connected to the second connection line through a second overlapping via hole, and the first overlapping via hole is provided in the first frame area.
  • Figure 1 is a schematic structural diagram of a display device
  • Figure 2 is a schematic structural diagram of a display substrate
  • Figure 3 is a schematic plan view of a display area in a display substrate
  • Figure 4 is a schematic cross-sectional structural diagram of a display area in a display substrate
  • Figure 5 is an equivalent circuit schematic diagram of a pixel driving circuit
  • Figure 6 is a schematic plan view of a display substrate according to an exemplary embodiment of the present disclosure.
  • Figure 7 is a schematic structural diagram of the first connecting line in Figure 6;
  • FIG8 is a schematic structural diagram of the second connecting line in FIG6;
  • Figure 9 is a schematic plan view of another display substrate according to an exemplary embodiment of the present disclosure.
  • Figure 10 is a schematic plan view of another display substrate according to an exemplary embodiment of the present disclosure.
  • Figure 11 is a schematic structural diagram of a side frame area according to an exemplary embodiment of the present disclosure.
  • Figure 12 is a schematic cross-sectional structural diagram of an overlapping via hole according to an exemplary embodiment of the present disclosure
  • FIGS. 13A and 13B are schematic planar structural diagrams of a data connection line according to an embodiment of the present disclosure
  • FIGS. 14A and 14B are schematic diagrams showing a substrate after forming a substrate according to an embodiment of the present disclosure
  • 15A and 15B are schematic diagrams showing a semiconductor layer formed on a substrate according to an embodiment of the present disclosure.
  • 16A and 16B are schematic diagrams showing the formation of the first conductive layer in the substrate according to an embodiment of the present disclosure
  • 17A and 17B are schematic diagrams showing a first overlapping via hole formed in a substrate according to an embodiment of the present disclosure
  • 18A and 18B are schematic diagrams showing a second conductive layer formed on a substrate according to an embodiment of the present disclosure
  • 19A and 19B are schematic diagrams showing a fourth insulating layer formed on a substrate according to an embodiment of the present disclosure.
  • 20A and 20B are schematic diagrams showing a third conductive layer formed on a substrate according to an embodiment of the present disclosure
  • Figure 21 is a schematic structural diagram of the first overlapping area according to an exemplary embodiment of the present disclosure.
  • Figure 22 is a schematic structural diagram of a resistance compensation structure according to an exemplary embodiment of the present disclosure.
  • 10A first flexible layer
  • 10B first barrier layer
  • 10C second flexible layer
  • 10D the second barrier layer
  • 11 the first active layer
  • 12 the second active layer
  • 21 First scanning signal line
  • 22 Silicond scanning signal line
  • 23 Light-emitting control line
  • 43 The third connection electrode; 44—The first power line; 60—Data signal line;
  • the first connection block 80—The second connection line; 81—Resistance compensation structure;
  • 102 Drive circuit layer
  • 103 Light-emitting structure layer
  • 104 Packaging structure layer
  • 220 lead line
  • 300 frame area
  • 310 side frame area
  • 310A packetaging area
  • 310B non-packaging area
  • 311 gate circuit area
  • 320 Upper frame area
  • 330 Scanning gate circuit
  • 340 Light-emitting gate circuit
  • start signal line 351—light-emitting start signal line
  • 352 scan start signal line
  • 360 clock signal line
  • 361 first clock signal line
  • 362 second clock signal line
  • the scale of the drawings in this disclosure can be used as a reference in actual processes, but is not limited thereto.
  • the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs.
  • the number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures.
  • the figures described in the present disclosure are only structural schematic diagrams, and one mode of the present disclosure is not limited to the figures. The shape or numerical value shown in the figure.
  • connection should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements.
  • connection should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements.
  • a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode.
  • the transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, channel region, and source electrode .
  • the channel region refers to the region through which current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and the “drain electrode” are sometimes interchanged. Therefore, in this specification, the “source electrode” and the “drain electrode” may be interchanged, and the “source terminal” and the “drain terminal” may be interchanged.
  • electrical connection includes a case where constituent elements are connected together through an element having some electrical effect.
  • component having some electrical function There is no particular limitation on the “component having some electrical function” as long as it can transmit and receive electrical signals between the connected components.
  • elements having some electrical function include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.
  • parallel refers to a state in which the angle formed by two straight lines is -10° or more and 10° or less. Therefore, it also includes a state in which the angle is -5° or more and 5° or less.
  • vertical refers to a state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore includes an angle of 85° or more and 95° or less.
  • film and “layer” may be interchanged.
  • conductive layer may sometimes be replaced by “conductive film.”
  • insulating film may sometimes be replaced by “insulating layer”.
  • triangles, rectangles, trapezoids, pentagons or hexagons are not strictly defined, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc., and may have some small deformations caused by tolerances, and may have chamfers, arc edges and deformations, etc.
  • "About" in this disclosure means that the limits are not strictly defined, and the values within the range of process and measurement errors are allowed.
  • Figure 1 is a schematic structural diagram of a display device.
  • the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array.
  • the timing controller is connected to the data driver, the scan driver, and the light-emitting driver respectively.
  • the data driver is connected to a plurality of data signal lines. (D1 to Dn) are connected, the scanning driver is connected to a plurality of scanning signal lines (S1 to Sm), and the light-emitting driver is connected to a plurality of light-emitting signal lines (E1 to Eo).
  • the pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, and at least one sub-pixel Pxij may include a circuit unit and a light-emitting unit connected to the circuit unit.
  • the circuit unit may include at least a pixel driving circuit, and the pixel driving circuit is connected to the scanning signal respectively. lines, data signal lines and light-emitting signal lines.
  • the timing controller may provide a gray value and a control signal suitable for the specifications of the data driver to the data driver, and may provide a clock signal, a scan start signal, and the like suitable for the specifications of the scan driver to the scan driver.
  • the driver can provide a clock signal, an emission stop signal, and the like suitable for the specifications of the light-emitting driver to the light-emitting driver.
  • the data driver may generate data voltages to be provided to the data signal lines D1, D2, D3, . . . and Dn using the grayscale values and control signals received from the timing controller. For example, the data driver may sample a grayscale value using a clock signal, and apply a data voltage corresponding to the grayscale value to the data signal lines D1 to Dn in units of pixel rows, where n may be a natural number.
  • the scan driver may generate scan signals to be supplied to the scan signal lines S1, S2, S3, . . .
  • the scan driver may sequentially supply scan signals having on-level pulses to the scan signal lines S1 to Sm.
  • the scan driver may be configured in the form of a shift register, and may generate the scan signal in a manner that sequentially transmits a scan start signal provided in the form of an on-level pulse to a next-stage circuit under the control of a clock signal, m can be a natural number.
  • the light-emitting driver may generate emission signals to be provided to the light-emitting signal lines E1, E2, E3, . . . and Eo by receiving a clock signal, an emission stop signal, or the like from the timing controller.
  • the light-emitting driver may sequentially provide emission signals with off-level pulses to the light-emitting signal lines E1 to Eo.
  • the light-emitting driver may be configured in the form of a shift register, and may generate the emission signal in a manner that sequentially transmits an emission stop signal provided in the form of a cut-off level pulse to a next-stage circuit under the control of a clock signal, o Can be a natural number.
  • FIG. 2 is a schematic structural diagram of a display substrate.
  • the display substrate may include a display area 100 , a binding area 200 located on one side of the display area 100 , and a frame area 300 located on other sides of the display area 100 .
  • the display area 100 may be a flat area including a plurality of sub-pixels Pxij constituting a pixel array, the plurality of sub-pixels Pxij are configured to display dynamic pictures or still images, and the display area 100 may be called an active area (AA).
  • the display substrate may be deformable, such as curled, bent, folded, or rolled.
  • the bonding area 200 may include a fan-out area, a bending area, a driver chip area, and a bonding pin area that are sequentially arranged in a direction away from the display area 100 .
  • the fan-out area is connected to the display area 100 and may include at least a plurality of data fan-out lines.
  • the plurality of data fan-out lines are configured to connect data signal lines of the display area in a fan-out (Fanout) wiring manner.
  • the bending area is connected to the fan-out area and may include a composite insulating layer provided with grooves configured to bend the binding area to the back of the display area.
  • the driver chip area may at least include an integrated circuit (Integrated Circuit, IC for short) configured to be connected to multiple data fan-out lines.
  • the bonding pin area may include at least a plurality of bonding pins (Bonding Pad), configured to be bonded to an external flexible circuit board (Flexible Printed Circuit, referred to as FPC).
  • the frame area 300 may include a circuit area, a power line area, a crack dam area, and a cutting area sequentially arranged in a direction away from the display area 100 .
  • the circuit area is connected to the display area 100 and may include at least a gate driving circuit connected to the first scanning signal line, the second scanning signal line and the light emission control line of the pixel driving circuit in the display area 100 .
  • the power line area is connected to the circuit area and may include at least a frame power line.
  • the frame power line extends in a direction parallel to the edge of the display area and is connected to the cathode in the display area 100 .
  • the crack dam area is connected to the power line area and may include at least a plurality of cracks provided on the composite insulation layer.
  • the cutting area is connected to the crack dam area and may at least include cutting grooves provided on the composite insulating layer. The cutting grooves are configured such that after all film layers of the display substrate are prepared, the cutting equipment cuts along the cutting grooves respectively.
  • the fan-out area in the binding area 200 and the power line area in the border area 300 may be provided with at least a first isolation dam and a second isolation dam, and the first isolation dam and the second isolation dam may extend in a direction parallel to the edge of the display area to form an annular structure surrounding the display area 100, and the edge of the display area is the edge of the display area close to the binding area or close to the border area.
  • Figure 3 is a schematic plan view of a display area in a display substrate.
  • the display substrate may include a plurality of pixel units P arranged in a matrix.
  • At least one pixel unit P may include a first sub-pixel P1 that emits light of a first color, and a second sub-pixel that emits light of a second color.
  • Pixel P2, third sub-pixel P3 and fourth sub-pixel P4 emitting light of the third color.
  • Each sub-pixel may include a circuit unit and a light-emitting unit.
  • the circuit unit may include at least a pixel driving circuit. The pixel driving circuit is connected to the scanning signal line, the data signal line and the light-emitting signal line respectively.
  • the pixel driving circuit is configured to operate between the scanning signal line and the light-emitting signal line. Under the control of the light-emitting signal line, it receives the data voltage transmitted by the data signal line and outputs the corresponding current to the light-emitting unit.
  • the light-emitting unit in each sub-pixel is respectively connected to the pixel driving circuit of the sub-pixel, and the light-emitting unit is configured to emit light of corresponding brightness in response to the current output by the connected pixel driving circuit.
  • the first sub-pixel P1 may be a red sub-pixel (R) emitting red light
  • the second sub-pixel P2 may be a blue sub-pixel (B) emitting blue light
  • the third sub-pixel P3 and the fourth sub-pixel P4 may be green sub-pixels (G) emitting green light.
  • the shape of the sub-pixels may be rectangular, rhombus, pentagonal or hexagonal
  • the four sub-pixels may be arranged in a diamond shape to form an RGBG pixel arrangement.
  • the four sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement or a square arrangement, etc., which is not limited in the present disclosure.
  • a pixel unit may include three sub-pixels, and the three sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, or a triangular arrangement, which is not limited in the present disclosure.
  • FIG. 4 is a schematic cross-sectional structural diagram of a display area in a display substrate, illustrating the structure of four sub-pixels in the display area.
  • the display substrate may include a driving circuit layer 102 disposed on a substrate 101 , a light-emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the substrate 101 , and a light-emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the substrate 101 .
  • the structural layer 103 is away from the packaging structural layer 104 on one side of the substrate 101.
  • the display substrate may include other film layers, such as touch structure layers, etc., which are not limited in this disclosure.
  • substrate 101 may be a flexible substrate, or may be a rigid substrate.
  • the driving circuit layer 102 may include a plurality of circuit units, and the circuit units may include at least a pixel driving circuit.
  • the light-emitting structure layer 103 may have at least a plurality of light-emitting units.
  • the light-emitting unit may at least include an anode, an organic light-emitting layer, and a cathode.
  • the organic light-emitting layer emits light of corresponding colors under the driving of the anode and the cathode.
  • the packaging structure layer 104 may include a stacked first packaging layer, a second packaging layer, and a third packaging layer.
  • the first packaging layer and the third packaging layer may be made of inorganic materials, and the second packaging layer may be made of organic materials.
  • the layer is arranged between the first encapsulation layer and the third encapsulation layer to form an inorganic material/organic material/inorganic material stack structure, which can ensure that external water and oxygen cannot enter the light-emitting structure layer 103.
  • the organic light-emitting layer may include an emitting layer (EML) and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), Hole blocking layer (HBL), electron transport layer (ETL) and electron injection layer (EIL).
  • EML emitting layer
  • HIL hole injection layer
  • HTL hole transport layer
  • EBL electron blocking layer
  • HBL Hole blocking layer
  • ETL electron transport layer
  • EIL electron injection layer
  • one or more of the hole injection layer, hole transport layer, electron blocking layer, hole blocking layer, electron transport layer and electron injection layer of all sub-pixels may be connected together Common layer, the light-emitting layers of adjacent sub-pixels may have a small amount of overlap, or may be isolated from each other.
  • Figure 5 is an equivalent circuit schematic diagram of a pixel driving circuit.
  • the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure.
  • the pixel driving circuit may include 7 transistors (first transistor T1 to seventh transistor T7) and 1 storage capacitor C.
  • the pixel driving circuit is respectively connected to 6 signal lines (data signal line D, first scanning The signal line S1, the second scanning signal line S2, the light emitting signal line E, the initial signal line INIT and the first power supply line VDD) are connected.
  • the pixel driving circuit may include a first node N1, a second node N2, and a third node N3.
  • the first node N1 is respectively connected to the first pole of the third transistor T3, the second pole of the fourth transistor T4 and the second pole of the fifth transistor T5, and the second node N2 is respectively connected to the second pole of the first transistor,
  • the first electrode of the second transistor T2 and the gate electrode of the third transistor T3 are connected to the second terminal of the storage capacitor C.
  • the third node N3 is respectively connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3 and The first pole of the sixth transistor T6 is connected.
  • the first end of the storage capacitor C is connected to the first power line VDD, and the second end of the storage capacitor C is connected to the second node N2, that is, the second end of the storage capacitor C is connected to the third transistor T3. Gate electrode connection.
  • the gate electrode of the first transistor T1 is connected to the second scanning signal line S2, the first electrode of the first transistor T1 is connected to the initial signal line INIT, and the second electrode of the first transistor T1 is connected to the second node N2.
  • the first transistor T1 transmits an initial voltage to the gate electrode of the third transistor T3 to initialize the charge amount of the gate electrode of the third transistor T3.
  • the gate electrode of the second transistor T2 is connected to the first scanning signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3.
  • the second transistor T2 connects the gate electrode of the third transistor T3 to the second electrode.
  • the gate electrode of the third transistor T3 is connected to the second node N2, that is, the gate electrode of the third transistor T3 is connected to the second end of the storage capacitor C, and the first electrode of the third transistor T3 is connected to the first node N1.
  • the second pole of T3 is connected to the third node N3.
  • the third transistor T3 may be called a driving transistor, and the third transistor T3 determines the amount of the driving current flowing between the first power supply line VDD and the second power supply line VSS according to the potential difference between its gate electrode and the first electrode.
  • the gate electrode of the fourth transistor T4 is connected to the first scanning signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1.
  • the fourth transistor T4 may be called a switching transistor, a scanning transistor, or the like. When the on-level scanning signal is applied to the first scanning signal line S1, the fourth transistor T4 causes the data voltage of the data signal line D to be input to the pixel driving circuit.
  • the gate electrode of the fifth transistor T5 is connected to the light-emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1.
  • the gate electrode of the sixth transistor T6 is connected to the light-emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting unit EL.
  • the fifth transistor T5 and the sixth transistor T6 may be called light emitting transistors.
  • the fifth and sixth transistors T5 and T6 cause the light-emitting unit EL to emit light by forming a driving current path between the first power supply line VDD and the second power supply line VSS.
  • the gate electrode of the seventh transistor T7 is connected to the second scanning signal line S2, the first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting unit EL.
  • the seventh transistor T7 transmits the initial voltage to the first pole of the light-emitting unit EL to initialize the amount of charge accumulated in the first pole of the light-emitting unit EL or The amount of charge accumulated in the first pole of the light-emitting unit EL is released.
  • the light-emitting unit EL may be an OLED including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or may be a QLED including a stacked first electrode (anode). ), quantum dot light-emitting layer and second electrode (cathode).
  • the second pole of the light-emitting unit EL is connected to the second power line VSS, the signal of the second power line VSS is a continuously provided low-level signal, and the signal of the first power line VDD is a continuously provided high-level signal. level signal.
  • the first to seventh transistors T1 to T7 may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel drive circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the product yield. In some possible implementations, the first to seventh transistors T1 to T7 may include P-type transistors and N-type transistors.
  • the first to seventh transistors T1 to T7 may employ low-temperature polysilicon thin film transistors, or may employ oxide thin film transistors, or may employ low-temperature polysilicon thin film transistors and oxide thin film transistors.
  • the active layer of low-temperature polysilicon thin film transistors uses low temperature polysilicon (LTPS), and the active layer of oxide thin film transistors uses oxide semiconductor (Oxide).
  • LTPS low temperature polysilicon
  • Oxide oxide semiconductor
  • Low-temperature polysilicon thin film transistors have the advantages of high mobility and fast charging, and oxide thin film transistors have the advantages of low leakage current.
  • Low-temperature polysilicon thin film transistors and oxide thin film transistors are integrated on a display substrate to form low-temperature polycrystalline oxide (Low Temperature Polycrystalline Oxide (LTPO for short) display substrate can take advantage of the advantages of both to achieve low-frequency driving, reduce power consumption, and improve display quality.
  • LTPO Low Temperature Polycrystalline Oxide
  • the working process of the pixel drive circuit can include:
  • the first phase A1 is called the reset phase.
  • the signal of the second scanning signal line S2 is a low-level signal, and the signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals.
  • the signal of the second scanning signal line S2 is a low-level signal, causing the first transistor T1 and the seventh transistor T7 to be turned on.
  • the first transistor T1 is turned on so that the initial voltage of the initial signal line INIT is provided to the second node N2 to initialize the storage capacitor C and clear the original data voltage in the storage capacitor.
  • the seventh transistor T7 is turned on so that the initial voltage of the initial signal line INIT is provided to the first pole of the OLED, initializing (resetting) the first pole of the OLED, clearing its internal prestored voltage, and completing the initialization.
  • the signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals, causing the second transistor T2, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 to be turned off. At this stage, the OLED does not emit light.
  • the second stage A2 is called the data writing stage or the threshold compensation stage.
  • the signal of the first scanning signal line S1 is a low-level signal
  • the signals of the second scanning signal line S2 and the light-emitting signal line E are high-level signals
  • the data The signal line D outputs the data voltage.
  • the third transistor T3 is turned on.
  • the signal of the first scanning signal line S1 is a low-level signal, causing the second transistor T2 and the fourth transistor T4 to be turned on.
  • the second transistor T2 and the fourth transistor T4 are turned on so that the data voltage output by the data signal line D is provided to the second transistor through the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2.
  • Node N2 and the difference between the data voltage output by the data signal line D and the threshold voltage of the third transistor T3 is charged into the storage capacitor C.
  • the voltage at the second end (second node N2) of the storage capacitor C is Vd-
  • the signal of the second scanning signal line S2 is a high-level signal, causing the first transistor T1 and the seventh transistor T7 to be turned off.
  • the signal of the light-emitting signal line E is a high-level signal, causing the fifth transistor T5 and the sixth transistor T6 to be turned off.
  • the third stage A3 is called the light-emitting stage.
  • the signal of the light-emitting signal line E is a low-level signal, and the signals of the first scanning signal line S1 and the second scanning signal line S2 are high-level signals.
  • the signal of the light-emitting signal line E is a low-level signal, causing the fifth transistor T5 and the sixth transistor T6 to be turned on.
  • the power supply voltage output by the first power supply line VDD passes through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6.
  • the transistor T6 provides a driving voltage to the first pole of the OLED to drive the OLED to emit light.
  • the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the second node N2 is Vdata-
  • I is the driving current flowing through the third transistor T3, that is, the driving current that drives the OLED
  • K is a constant
  • Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3
  • Vth is the third transistor T3.
  • Vd is the data voltage output by the data signal line D
  • Vdd is the power supply voltage output by the first power supply line VDD.
  • the data fan-out lines are set in the fan-out area of the binding area. Since the width of the fan-out area is smaller than the width of the display area, the data fan-out lines need to be introduced into the wider display area through fan-out routing. The greater the width difference between the display area and the binding area, the more oblique fan-out lines in the fan-shaped area, and the larger the space occupied by the fan-shaped area. In addition, as the resolution of the display screen gradually increases, the occupied width of the fan-out line will gradually increase, making it more difficult to design a narrower bottom border, which has been maintained at around 2.0mm.
  • the display substrate may include a display area, a side frame area located on at least one side of the display area in a first direction, and a binding area located on one side of the display area in a second direction, the side frame area It includes at least a first frame area and a second frame area, the first frame area is located on a side of the second frame area close to the binding area, the first direction intersects the second direction; in the vertical direction
  • the display substrate includes a base and a driving circuit layer disposed on the base, the base at least includes a first connection line, and the driving circuit
  • the layer at least includes a data signal line and a second connection line.
  • the second connection line is connected to the first connection line through a first overlapping via hole.
  • the data signal line is connected to the third connection line through
  • the first connection line and the second connection line constitute a data connection line
  • the first end of the data connection line is connected to the integrated circuit in the binding area
  • the second end of the data connection line extends behind the display area. , connected correspondingly to the data signal line. Since there is no need to set fan-shaped diagonal lines in the binding area, the width of the fan-out area is reduced, effectively reducing the width of the bottom border.
  • the display substrate may further include an upper frame area located on a side of the display area away from the binding area, and the side frame area and the upper frame area constitute a frame area of the display substrate.
  • the display substrate may further include a light emitting structure layer disposed on a side of the driving circuit layer away from the substrate and an encapsulation structure layer disposed on a side of the light emitting structure layer away from the substrate.
  • the driving circuit layer may include circuit units constituting a plurality of unit rows and a plurality of unit columns, at least one circuit unit may include a pixel driving circuit, and the pixel driving circuit is configured to output a corresponding current to the connected light emitting unit.
  • the light emitting structure layer may include a plurality of light emitting units constituting a light emitting array, at least one light emitting unit may include a light emitting device, the light emitting device is connected to the pixel driving circuit of the corresponding circuit unit, and the light emitting device is configured to emit light of corresponding brightness in response to the current output by the connected pixel driving circuit.
  • the circuit unit mentioned in the present disclosure refers to the area divided according to the pixel driving circuit
  • the light-emitting unit mentioned in the present disclosure refers to the area divided according to the light-emitting device.
  • the orthographic projection position of the light-emitting unit on the substrate may correspond to the orthographic projection position of the circuit unit on the substrate, or the orthographic projection position of the light-emitting unit on the substrate corresponds to the orthographic projection position of the circuit unit on the substrate. The positions may not correspond.
  • the display substrate includes a first center line, which is a straight line bisecting the display area in the second direction and extending along the first direction, and the first center line is a straight line bisecting the display area in the second direction and extending along the first direction.
  • the first frame area is located on the side of the first center line close to the binding area, and the first connection line and the second connection line are located on the side of the first center line close to the binding area.
  • the display substrate includes a second center line, which is a straight line bisecting the display area in the first direction and extending along the second direction; along Away from the second centerline, the distance between the second overlapping via hole and the first centerline gradually increases, or the distance between the second overlapping via hole and the first centerline The distance between them gradually decreases.
  • the binding area at least includes a lead wire, a first end of the lead wire is connected to the integrated circuit in the binding area, and a second end of the lead wire is connected to the third
  • the first end of a connecting line is connected, and the second end of the first connecting line extends from the binding area through the display area to the first frame area, and is connected with the first overlapping via hole.
  • the first end of the second connection line is connected, and the second end of the second connection line extends from the first frame area to the display area and is connected to the data through the second overlapping via hole.
  • the side frame area includes an encapsulation area and a non-encapsulation area divided by an encapsulation line.
  • the encapsulation line is a boundary where the encapsulation structure layer covers the side frame area.
  • the encapsulation area is provided on the The packaging line is on a side close to the display area, the non-encapsulation area is provided on a side of the packaging line away from the display area, and the first overlapping via is provided in the non-encapsulation area.
  • the driving circuit layer at least includes a first conductive layer, a second conductive layer and a third conductive layer sequentially disposed on the substrate, and the second connection line is disposed on the first conductive layer. layer or the second conductive layer, the data signal line is provided in the third conductive layer.
  • Figure 6 is a schematic plan view of a display substrate according to an exemplary embodiment of the present disclosure.
  • the data connection line in the display substrate adopts a FIAA structure.
  • Figure 7 is a schematic structural view of the first connection line in Figure 6.
  • Figure 8 is a schematic view of the structure of the first connection line in Figure 6.
  • the display substrate may include a display area 100, a binding area 200 located on one side of the display area 100 in the second direction Y, and a frame area 300 located on other sides of the display area 100. .
  • the display area 100 may include at least a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns.
  • the plurality of circuit units arranged sequentially along the first direction X may be referred to as unit rows.
  • a plurality of circuit units arranged sequentially along the second direction Y may be called a unit column.
  • the plurality of unit rows and the plurality of unit columns constitute a circuit unit array arranged in an array.
  • the first direction X intersects with the second direction Y.
  • the display area 100 may also include a plurality of data signal lines 60.
  • the shape of the data signal lines 60 may be a line shape with the main part extending along the second direction Y.
  • the plurality of data signal lines 60 may be arranged in a set direction along the first direction X. The intervals are set sequentially.
  • At least one circuit unit may include a pixel driving circuit, and each data signal line 60 is connected to the pixel driving circuits of a plurality of circuit units in one unit column.
  • the second direction Y may be an extending direction of the data signal line 60 (vertical direction)
  • the first direction X may be perpendicular to the second direction Y (horizontal direction).
  • a extending along direction B means that A may include a main part and a secondary part connected to the main part.
  • the main part is a line, line segment or bar-shaped body, the main part extends along direction B, and the main part
  • the length extending in direction B is greater than the length of the secondary portion extending in other directions.
  • “A extends along direction B” means "the main body part of A extends along direction B".
  • the second direction Y may be a direction from the display area to the binding area, and the opposite direction of the second direction Y may be a direction from the binding area to the display area.
  • the binding area 200 may at least include a lead line area 201 and a bending area 202 that are sequentially arranged in a direction away from the display area 100 .
  • the lead line area 201 may include a plurality of lead lines 220 .
  • the lead lines 220 The first end of the lead wire 220 is connected to the integrated circuit in the bonding area 200 , and the second end of the lead wire 220 extends to the lead wire area 201 through the bending area 202 .
  • the frame area 300 may include a side frame area 310 located on one or both sides of the display area 100 in the first direction X, and an upper frame area 320 located on a side of the display area 100 away from the binding area 200.
  • the frame area 310 may include at least a gate driving circuit
  • the upper frame area 320 may include at least a test circuit.
  • the frame area 300 may include an encapsulation area and a non-encapsulation area divided by an encapsulation line, and the encapsulation line may be a boundary where the encapsulation structure layer covers the frame area 300 .
  • the side frame area 310 may include a packaging area 310A and a non-packaging area 310B divided by the packaging line FX.
  • the side of the packaging line FX close to the display area 100 is the packaging area 310A, and the packaging line FX is far away from the display area 100.
  • One side is the non-encapsulation area 310B, that is, the non-encapsulation area 310B may be located on the side of the encapsulation area 310A away from the display area 100 .
  • the side frame area 310 may include a first frame area 310-1 and a second frame area 310-2 arranged sequentially along the second direction Y, and the first frame area 310-1 may be located on the second frame area.
  • Area 310-2 is adjacent to the side of binding area 200.
  • the display substrate may further include a plurality of first connection lines 70 and second connection lines 80 , and the first connection lines 70 and the second connection lines 80 constitute data connection lines.
  • the first ends of the plurality of first connection lines 70 are correspondingly connected to the plurality of lead lines 220 in the lead line area 201 , and the second ends of the plurality of first connection lines 70 extend from the lead line area 201 to the display area 100 and from the display area 201 to the display area 100 .
  • the area 100 extends to the first frame area 310-1 in the side frame area 310, it is connected to the first ends of the plurality of second connection lines 80 through the first overlapping via holes DV1.
  • the second ends of the plurality of second connection lines 80 extend from the first frame area 310-1 to the display area 100, they are correspondingly connected to the plurality of data signal lines 60 through the second overlapping vias DV2, forming a first overlapping via.
  • the hole DV1 is provided in the first frame area 310 - 1 and the second overlapping via hole DV2 is provided in the data connection line structure of the display area 100 .
  • the lead-out line 220 is connected to the integrated circuit in the bonding area 200
  • the first connection line 70 is connected to the lead-out line 220
  • the second connection line 80 is connected to the first connection line 70
  • the data signal line 60 It is connected to the second connection line 80, so the data signal line 60 in the display area is connected to the integrated circuit in the binding area through the second connection line 80, the first connection line 70 and the lead line 220, realizing the integration of the integrated circuit to the data signal.
  • Line 60 provides the data signal. Since there is no need to set fan-shaped diagonal lines in the binding area, the width of the fan-out area is reduced, which can effectively reduce the width of the bottom border.
  • the number of data connection lines may be the same as the number of data signal lines, or the number of data connection lines may be less than the number of data signal lines, which is not limited by the present disclosure.
  • a plurality of first overlapping vias DV1 may be respectively provided in the non-packaging area 310B of the side frame area 310 , that is, a plurality of first overlapping vias DV1 may be respectively provided in the packaging line FX away from the display area 100 side.
  • a plurality of first overlapping vias DV1 may also be respectively provided between the packaging line FX of the side frame area 310 and the first isolation dam 410 (or the second isolation dam 420).
  • the present disclosure can avoid the growing dark spots caused by the overlapping via holes compared to arranging the first overlapping via holes in the display area. , referred to as GDS) problem.
  • the display substrate may include a first center line O1 , and the first center line O1 may be a straight line bisecting the display area 100 in the second direction Y and extending along the first direction X.
  • the first border area 310-1 may be located on a side of the first center line O1 close to the binding area 200, so that the plurality of first overlapping vias DV1 and the plurality of second overlapping vias DV2 are all located on a side of the first center line O1 close to the binding area 200, and the plurality of first connecting wires 70 and the plurality of second connecting wires 80 are all located on a side of the first center line O1 close to the binding area 200.
  • the present disclosure arranges the first overlapping vias, the second overlapping vias, the first connecting wires and the second connecting wires on a side close to the binding area, which can effectively reduce the transmission path of the data signal, effectively reduce the load of the data signal, and reduce the rising edge/falling edge (Tr/Tf) of the data signal, thereby facilitating the realization of a narrow border with a high refresh rate, compared with arranging the second overlapping vias in the upper border area.
  • the first connection line 70 may include a first sub-line 71 and a second sub-line 72 connected to each other.
  • the shape of the first sub-line 71 may be a line shape extending along the first direction X.
  • the shape of the two sub-lines 72 may be a line shape extending along the second direction Y.
  • the first ends of the plurality of second sub-lines 72 are correspondingly connected to the plurality of lead-out lines 220 in the lead-out line area 201 , and the second ends of the plurality of second sub-lines 72 extend from the lead-out line area 201 along the second direction Y to the display. After the area 100, it is connected to the first ends of the plurality of first sub-lines 71.
  • the first sub-line 71 may be perpendicular to the data signal line 60
  • the second sub-line 72 may be parallel to the data signal line 60 .
  • the first extension length of the first sub-line 71 may be less than or equal to 0.5*the display area width
  • the second extension length of the second sub-line 72 may be less than or equal to 0.5*the display area length.
  • the length may be the size of the first sub-line 71 in the first direction X
  • the width of the display area may be the size of the display area in the first direction It may be the size of the display area in the second direction Y.
  • the orthographic projection of the first sub-line 71 on the substrate is the same as the orthographic projection of the second connection line 80 on the substrate.
  • the orthographic projections of the first sub-line 71 and the second connection line 80 at least partially overlap to form an upper and lower stacked wiring of the first sub-line 71 and the second connection line 80 to reduce the parasitic capacitance of transmitting data signals.
  • a second center line O2 may be included, and the second center line O2 may be a straight line bisecting the display area 100 in the first direction X and extending along the second direction Y.
  • the plurality of second sub-lines 72 may be disposed in an area close to the second center line O2.
  • the orthographic projection of the at least one second sub-line 72 on the display substrate plane is not the same as the orthographic projection of the at least one data signal line 60 on the display substrate plane. overlap.
  • the extension lengths of the plurality of second sub-lines 72 gradually decrease, and along the direction away from the first center line O1, the extension lengths of the plurality of first sub-lines 71 are gradually reduced.
  • the extended length gradually decreases.
  • the extension length refers to the dimension along the extension direction.
  • a plurality of first overlapping vias DV1 may be arranged sequentially along the second direction Y, and a plurality of first overlapping vias DV1 may be located along the second direction Y. on a straight line extending in direction Y.
  • the extension lengths of the plurality of second connection lines 80 may gradually decrease along the direction away from the first center line O1.
  • the distance between the plurality of second overlapping vias DV2 and the second center line O2 may gradually increase along the direction away from the first center line O1.
  • the distance between the plurality of second overlapping via holes DV2 and the first center line O1 can gradually increase, forming diagonally arranged second overlapping via holes DV2 in the display area 100.
  • the second overlapping via holes DV2 are arranged from the lower left to the upper right direction.
  • the second overlapping via holes DV2 are arranged from the lower right to the upper left direction.
  • the shapes of the first overlapping via DV1 and the second overlapping via DV2 may include any one or more of the following: triangle, rectangle, pentagon , hexagon, circle and oval.
  • the display substrate may include a substrate and a driving circuit layer disposed on the substrate.
  • the substrate may at least include a first connection line 70
  • the driving circuit layer may at least include a data signal line 60 and a second connection line 80.
  • the first connection line 70 connects to
  • the second connection line 80 is connected to the data signal line 60 through the second overlapping via DV2 located in the display area 100 .
  • the substrate may include at least a first flexible layer, a second flexible layer, and a base conductive layer (SD0) disposed between the first flexible layer and the second flexible layer, and the first connection line 70 may be disposed on in the base conductive layer.
  • SD0 base conductive layer
  • At least one pixel driving circuit may include a storage capacitor and a plurality of transistors.
  • the driving circuit layer may at least include a first conductive layer, a second conductive layer and a third conductive layer sequentially arranged in a direction away from the substrate.
  • the first plate of the storage capacitor may be disposed in the first conductive layer (GATE1).
  • the second electrode plate may be disposed in the second conductive layer (GATE2), and the data signal line 60 may be disposed in the third conductive layer (SD1).
  • the orthographic projection of the first sub-line 71 on the substrate does not overlap with the orthographic projection of the storage capacitor and the plurality of transistors on the substrate, and the orthographic projection of the second sub-line 72 on the substrate does not overlap.
  • the projection does not overlap with the orthographic projection of the storage capacitor and the plurality of transistors on the substrate, and the orthographic projection of the second connecting line on the substrate does not overlap with the orthographic projection of the storage capacitor and the plurality of transistors on the substrate,
  • the second connection line 80 may be disposed in the first conductive layer, the second connection line 80 may be connected to the first connection line 70 through a first overlapping via DV1 , and the data signal line 60 may be connected to the second connection line 80 through a second overlapping via DV2 .
  • the second connection line 80 may be disposed in the second conductive layer, the second connection line 80 may be connected to the first connection line 70 through the first overlapping via DV1, and the data signal line 60 It can be connected to the second connection line 80 through two overlapping vias DV2.
  • FIG. 9 is a schematic plan view of another display substrate according to an exemplary embodiment of the present disclosure.
  • the main structure of the display substrate of this embodiment is basically the same as that of the display substrate shown in FIG. 6 , except that the arrangement of the plurality of second overlapping vias DV2 in the display area 100 The way is different.
  • the extension lengths of the plurality of second sub-lines 72 gradually decrease, and along the direction away from the first center line O1, the extension lengths of the plurality of first sub-lines 71 are gradually reduced.
  • the extended length gradually decreases.
  • the extension length of the plurality of second connection lines 80 gradually increases.
  • the distance between the plurality of second overlapping vias DV2 and the second center line O2 may gradually decrease along the direction away from the first center line O1 .
  • the distance between the plurality of second overlapping vias DV2 and the first centerline O1 can be gradually reduced, forming diagonally arranged second overlapping vias DV2 in the display area 100.
  • the second overlapping via holes DV2 are arranged from the upper left to the lower right direction, and in the right area of the display area 100, the second overlapping via holes DV2 are arranged from the upper right to the lower left direction.
  • FIG. 10 is a schematic plan view of another display substrate according to an exemplary embodiment of the present disclosure, and only illustrates the structure of the second connection line.
  • the display substrate may include a plurality of lead wire groups 90, and at least one lead wire group 90 may include k first sub-lines (not shown) and k first overlapping vias DV1 and k-th One sub-line is correspondingly connected to k second connection lines 80, and the k second connection lines 80 are correspondingly connected to k data signal lines 60 through k second overlapping vias DV2, and k is a positive integer greater than or equal to 1.
  • the main structure of the display substrate of this embodiment is basically the same as that of the display substrate shown in FIG. 6 . The difference is that the lead group 90 in the display substrate shown in FIG. 6 includes a first sub-section. This embodiment shows that the lead group 90 in the substrate includes two first sub-lines and two second connection lines.
  • a plurality of lead wire groups 90 may be sequentially disposed along the second direction Y, and each lead wire group 90 may be disposed between adjacent unit rows.
  • 2, 3 or 4 unit rows may be provided between adjacent lead groups 90 in the second direction Y.
  • the distance between the i-th lead group and the i+1-th lead group may be equal to the distance between the i+1-th lead group and the i+2-th lead group, That is, a plurality of lead groups 90 are arranged at equal intervals along the second direction Y, i is a positive integer greater than or equal to 1 and less than or equal to N-2, and N is the number of lead groups.
  • the lead group 90 shown in Figure 6 includes a first sub-line and a second connecting line 80
  • the spacing between adjacent first sub-lines is the same, and multiple first sub-lines are arranged at equal intervals along the second direction Y
  • the spacing between adjacent second connecting lines 80 is the same, and multiple second connecting lines 80 are arranged at equal intervals along the second direction Y
  • the spacing between multiple first overlapping vias DV1 is the same, and multiple first overlapping vias DV1 are arranged at equal intervals along the second direction Y
  • the spacing between multiple second overlapping vias DV2 is the same
  • multiple second overlapping vias DV2 are arranged at equal intervals along the oblique direction
  • multiple second overlapping vias DV2 can be located on the same straight line extending along the oblique direction.
  • the difference in extension length between the jth first sub-line and the j+1th first sub-line may be equal to the difference in extension length between the j+1th first sub-line and the j+2th first sub-line, that is, the extension lengths of the plurality of first sub-lines are an arithmetic series, and j is a positive integer greater than or equal to 1 and less than or equal to N-2.
  • the difference in extension length between the j-th second connection line 80 and the j+1-th second connection line 80 may be equal to the j+1-th second connection line 80.
  • the difference in extension length between the line 80 and the j+2nd second connection line 80 that is, the extension lengths of the plurality of second connection lines 80 is an arithmetic series.
  • the difference in extension length between the first sub-line and the second connection line 80 in the i-th lead group may be equal to the first sub-line and the second connecting line 80 in the i+1-th lead group.
  • the difference in extension length between the two connecting lines 80 may be equal to the first sub-line and the second connecting line 80 in the i+1-th lead group.
  • the lead group 90 as shown in FIG. 10 includes two first sub-lines and two second connection lines 80, and one of the two first sub-lines in the i-th lead group
  • the spacing between the two first sub-lines in the i+1th lead group may be equal to the spacing between the two second connecting lines 80 in the i+1th lead group.
  • the spacing between the second connecting lines 80 and the spacing between the two first overlapping vias DV1 in the i-th lead group may be equal to the spacing between the two first overlapping vias DV1 in the i+1th lead group.
  • the spacing between the two second overlapping vias DV2 in the i-th lead group can be equal to the spacing between the two second overlapping vias DV2 in the i+1th lead group, multiple second overlapping vias DV2 is arranged with variable pitch along the oblique direction, and the plurality of second overlapping vias DV2 are not on the same straight line extending along the oblique direction.
  • the difference in the extension lengths of the two first sub-lines in the i-th lead group may be equal to the difference in the extension lengths of the two first sub-lines in the i+1-th lead group.
  • the difference between the extended lengths of the two second connection wires 80 in the i-th lead group may be equal to the difference between the extended lengths of the two second connection wires 80 in the (i+1)-th lead group.
  • the difference in extension length between the j-th first sub-line and the j+1-th first sub-line may be equal to the j+1-th first sub-line and the j+1-th first sub-line.
  • the difference in extension length between j+2 first sub-lines, that is, the extension lengths of multiple first sub-lines is an arithmetic series.
  • the difference in extension length between the j-th second connection line 80 and the j+1-th second connection line 80 may be equal to the j+1-th second connection line.
  • the difference in extension length between 80 and the j+2 second connection line 80 that is, the extension lengths of the plurality of second connection lines 80 is an arithmetic series.
  • the distance between the j-th first sub-line and the j+1-th first sub-line is not equal to the j+1-th first sub-line and the j+2-th first sub-line.
  • the spacing between the first sub-lines, the spacing between the j-th second connecting line 80 and the j+1-th second connecting line 80 is not equal to the j+1-th second connecting line 80 and the j+-th second connecting line 80 The distance between the two second connecting lines 80.
  • Figure 11 is a schematic structural diagram of a side frame area according to an exemplary embodiment of the present disclosure.
  • the side frame area 310 of the frame area 300 may be located on one side or both sides of the first direction X of the display area 100 , and the side frame area 310 may include a package made of The packaging area 310A and the non-encapsulation area 310B are divided by line FX.
  • the packaging line FX can be the boundary of the side frame area 310 covered by the packaging structure layer.
  • the side of the packaging line FX close to the display area 100 is the packaging area 310A, and the packaging line FX is far away from the display area.
  • One side of 100 is the non-encapsulation area 310B.
  • the packaging area 310A may include at least a gate circuit area 311 and an isolation dam area 312 that are sequentially arranged in a direction away from the display area.
  • the gate circuit area 311 may be provided with a plurality of gate circuit groups arranged sequentially along the second direction Y, and a routing area is provided between adjacent gate circuit groups in the second direction Y, that is, along the second direction Y , multiple gate circuit groups and multiple wiring areas are alternately arranged, and multiple wiring areas are respectively provided with multiple lead groups 90 .
  • At least one gate circuit group may include m scanning gate circuits (Gate GOA) 330 sequentially arranged in a direction parallel to the edge of the display area and sequentially arranged in a direction parallel to the edge of the display area.
  • n light-emitting gate circuits (EM GOA) 340 the n light-emitting gate circuits 340 can be disposed on the side of the m scanning gate circuits 330 away from the display area 100, m can be a positive integer greater than or equal to 2, n Can be a positive integer greater than or equal to 1.
  • the gate circuit group may include two scanning gate circuits 330 and one light-emitting gate circuit 340, and the wire group 90 may be disposed between every two scanning gate circuits 330 and between each light-emitting gate circuit 340. .
  • the scan gate circuit 330 may include at least a plurality of scan transistors and a scan capacitor
  • the light emitting gate circuit 340 may include at least a plurality of light emitting transistors and a light emitting capacitor, the scan transistor, the scan capacitor, the light emitting transistor, and the light emitting capacitor. It can be prepared simultaneously with the transistors and storage capacitors in the pixel driving circuit of the display area.
  • the isolation dam area 312 may be provided with at least a first isolation dam 410 and a second isolation dam 420, and the first isolation dam 410 and the second isolation dam 420 may extend in a direction parallel to the edge of the display area, And connected with the first isolation dam and the second isolation dam in the binding area and the upper frame area to form a ring structure surrounding the display area.
  • the first isolation dam 410 and the second isolation dam 420 may be prepared simultaneously with the light emitting structure layer of the display area.
  • the non-encapsulation area 310B may at least include a crack dam area 313 and a cutting area 314 sequentially arranged in a direction away from the display area.
  • the crack dam area 313 may at least include a plurality of cracks provided on the composite insulating layer to form a crack dam.
  • the crack dam is configured to reduce the stress on the display area during the cutting process and intercept the propagation of cracks toward the display area.
  • the cutting area 314 may be connected to the crack dam area and may at least include cutting grooves provided on the composite insulating layer. The cutting grooves are configured such that after all film layers of the display substrate are prepared, the cutting equipment cuts along the cutting grooves respectively.
  • a plurality of first overlapping vias DV1 may be disposed in the non-packaging area 310B of the side frame area 310 and may be disposed between the isolation dam area 312 and the crack dam area 313 .
  • the first sub-line 71 in the plurality of lead groups 90 extends from the display area 100 to the side frame area 310 (first frame area), passes through the gate circuit area 311 and the isolation dam area 312 in sequence, and is connected to the second connection line 80 through the first overlapping via DV1 in the non-packaging area 310B.
  • the second connection line 80 passes through the isolation dam area 312 and the gate circuit area 311 in sequence and returns to the display area 100, and is then connected to the data signal line through the second overlapping via (not shown).
  • the orthographic projection of the first sub-line 71 on the substrate is at least partially the same as the orthographic projection of the second connection line 80 on the substrate. Overlap to form upper and lower stacked wiring of the first connection line 70 and the second connection line 80 in the side frame area 310, effectively reducing the parasitic capacitance of transmitting data signals.
  • the layout design can be implemented through layout design.
  • a wiring area is provided between adjacent gate circuit groups in the second direction Y.
  • the lead group 90 can be arranged in the area where the wiring area is located, so that the first sub-line 71 and the second connection line 80 in the lead group 90 can be avoided.
  • the orthographic projection of each transistor and capacitor in the scanning gate circuit and the light-emitting gate circuit, the first sub-line 71 and the second connecting line 80 on the substrate, and the orthographic projection of the scanning transistor and scanning capacitor of the scanning gate circuit 330 on the substrate There is no overlap.
  • the orthographic projection of the first sub-line 71 and the second connection line 80 on the substrate does not overlap with the orthographic projection of the light-emitting transistor and the light-emitting capacitor of the light-emitting gate circuit 340 on the substrate. This can prevent data signals from affecting the scanning gate.
  • the electrical characteristics of the scanning gate circuit and the light-emitting gate circuit ensure the working stability and reliability of the scanning gate circuit and the light-emitting gate circuit.
  • At least one wiring area may be provided with one lead group 90 , or two lead groups 90 may be provided, or multiple lead groups 90 may be provided, and one lead group 90 may at least transmit the same data signal.
  • at least one wiring area may be provided with a first sub-line 71 and a second connection line 80 to provide data signals for one data signal line of each sub-pixel.
  • at least one wiring area can be provided with three first sub-lines 71 and three second connection lines 80, which is 3 of a pixel unit.
  • the data signal lines provide data signals.
  • At least one wiring area may be provided with 4 first sub-lines 71 and 4 second connection lines.
  • 80 provides data signals for four data signal lines of a pixel unit.
  • the gate circuit area 311 may also include at least one start signal (STV) line 350 and at least one clock signal (GOA Clock) line 360, and the shape of these signal lines may be along a line parallel to the display area. A line shape extending in the direction of the edge may be provided on the side of the light-emitting gate circuit 340 away from the display area.
  • the start signal line 350 may include a signal line that transmits a scan start signal (GSTV) and a light emitting start signal (ESTV)
  • the clock signal line 360 may include a signal line that transmits a first clock signal (ECK) and A signal line that transmits the second clock signal (ECB).
  • the gate circuit region 311 may also include at least one constant level signal line (not shown), such as a second level signal line (VGH) and a first level signal line (VGL).
  • the gate circuit area 311 includes the first gate circuit area and the second gate circuit area, wherein the first gate circuit area includes at least one scan gate circuit 330, a transmission Scanning start signal (GSTV) and clock signal line 360, the clock signal line 360 may include a signal line transmitting a first clock signal (ECK) and a second clock signal (ECB).
  • the first gate circuit area may also include at least one constant level signal line, such as a second level signal line (VGH) and a first level signal line (VGL).
  • the second gate circuit area includes at least one light-emitting gate circuit 340, a signal line that transmits a light-emitting start signal (ESTV), and a clock signal line 360.
  • the clock signal line 360 may include a first clock signal (ECK) and a second clock signal. Clock signal (ECB) signal line.
  • the second gate circuit area may also include at least one constant level signal line, such as a second level signal line (VGH) and a first level signal line (VGL).
  • the gate circuit region 311 may further include at least one start signal (STV) line 350 and at least one clock signal (GOA Clock) line 360.
  • STV start signal
  • GOA Clock clock signal
  • at least part of the signal lines may be disposed between the light-emitting gate circuit 340 and the scanning gate circuit 330 .
  • the first gate circuit area may also include at least one constant level signal line, such as a second level signal line (VGH) and a first level signal line (VGL).
  • the at least one constant level signal line may be disposed on between the light-emitting gate circuit 340 and the scanning gate circuit 330.
  • the first sub-line 71 and the second connecting line 80 in the lead group 90 are in the shape of laterally extending lines, and the start signal line 350 and the clock signal line 360 are in the shape of vertically extending lines, the first sub-line 71 and the second connecting line 80 will pass under the start signal line 350 and the clock signal line 360, and the orthographic projections of the first sub-line 71 and the second connecting line 80 on the substrate have a first overlapping area with the orthographic projections of the start signal line 350 and the clock signal line 360 on the substrate.
  • the orthographic projection of the first sub-line 71 on the substrate does not overlap with the orthographic projection of the second connection line 80 on the substrate, and in the first overlapping area Outside the side frame area, for the first sub-line 71 and the second connection line 80 that transmit the same data signal, the orthographic projection of the first sub-line 71 on the substrate and the orthographic projection of the second connection line 80 on the substrate at least partially intersect.
  • the first sub-line 71 and/or the second connecting line 80 can avoid each other by bending, so that the first sub-line 71 located in the first overlapping area and the second connecting line 80 can avoid each other by bending.
  • the two connecting lines 80 do not overlap.
  • the first sub-line 71 and the second connection line 80 in the lead group 90 may be provided with a resistance compensation structure, and the resistance compensation structure is configured as The resistance of the first sub-line 71 and the second connection line 80 is reduced, and the resistance difference caused by the different lengths of the connection lines in different lead groups 90 can be adjusted.
  • FIG. 12 is a schematic cross-sectional structural diagram of an overlapping via hole according to an exemplary embodiment of the present disclosure.
  • the display substrate may at least include a driving circuit layer 102 disposed on the substrate 101 .
  • the substrate 101 may include at least a first flexible layer 10A, a second flexible layer 10C, and a base conductive layer disposed between the first flexible layer 10A and the second flexible layer 10C.
  • the base conductive layer may at least include The first connection line 70.
  • the driving circuit layer 102 may at least include a data signal line 60 and a second connection line 80.
  • the second connection line 80 is connected to the first connection line 70 through the first overlapping via hole DV1, and the data signal line 60 passes through the second overlapping via hole.
  • DV2 is connected to the second connection line 80 .
  • the driving circuit layer 102 may include at least a first insulating layer 91 , a semiconductor layer, a second insulating layer 92 , a first conductive layer, a third insulating layer 93 , and a second conductive layer that are sequentially disposed on the substrate 101 . layer, a fourth insulating layer 94 and a third conductive layer.
  • the semiconductor layer may at least include an active layer of a plurality of transistors of the pixel driving circuit
  • the first conductive layer may at least include gate electrodes of the plurality of transistors and a first plate of the storage capacitor
  • the second conductive layer may at least include a second connection line.
  • the third conductive layer may at least include a data signal line 60 and first and second poles of a plurality of transistors.
  • the substrate 101 may further include a first barrier layer 10B and a second barrier layer 10D.
  • the first barrier layer 10B is disposed between the first flexible layer 10A and the base conductive layer.
  • the second barrier layer 10D is disposed between The second flexible layer 10C is away from the side of the first flexible layer 10A.
  • the second connection line 80 covers the first connection line 70 exposed at the bottom of the first overlapping via hole DV1 and covers the flexible layer and the plurality of inorganic layers exposed on the inner side wall of the first overlapping via hole DV1 , and the second connection line 80 covers the third insulation layer outside the first overlapping via DV1.
  • FIGS. 13A and 13B are schematic planar structural diagrams of a data connection line according to an exemplary embodiment of the present disclosure.
  • FIG. 13A is a schematic planar structural diagram of area B in FIG. 6
  • FIG. 13B is a schematic planar structural diagram of area C in FIG. 6 .
  • Each lead group includes two first sub-lines 71 and two second connection lines 80 .
  • the display area 100 may include a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns.
  • At least one circuit unit may include a pixel driving circuit.
  • the driving circuit may at least include a plurality of transistors and a storage capacitor.
  • the data signal line 60 is connected to a plurality of pixel driving circuits of one unit column, and the data signal line 60 is configured to provide a data signal to the pixel driving circuit.
  • the sub-line groups may be disposed between adjacent circuit rows, and the distances between adjacent sub-line groups in the second direction Y may be substantially equal.
  • one sub-line group can be set between the N-1th row and the N-th row, and another sub-line group can be set between the N+1th row and the N+2th row.
  • the space can contain two circuit rows.
  • the distance between the two first sub-lines 71 in the sub-line group located between the N-1th row and the N-th row may be equal to the distance between the N+1th row and the N+2-th row.
  • the distance between the two first sub-lines 71 in the sub-line group between rows, the distance between the two second connecting lines 80 in the sub-line group between the N-1th row and the N-th row may be equal to the distance between the two second connection lines 80 in the sub-line group between the N+1th row and the N+2th row.
  • the second sub-line 72 may be disposed in the display area 100 .
  • the shape of the second sub-line 72 may be a line shape in which the main body portion extends along the second direction Y.
  • the first sub-line 71 and the second connection line 80 may be disposed in the display area 100 and the side frame area 310, and the first overlapping via DV1 connecting the first sub-line 71 and the second connection line 80 It can be provided in the side frame area 310 (the first frame area), and the first overlapping via DV1 can be provided on the side of the packaging line FX away from the display area 100 to connect the second connection line 80 and the second connection line 80 of the data signal line 60 .
  • the overlapping via DV2 may be provided in the display area 100 .
  • the distance between the two second overlapping vias DV2 in the sub-line group between the N-1th row and the Nth row may be equal to the distance between the N+1th row and the Nth row.
  • the pixel driving circuit of at least one circuit unit may include at least a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T6.
  • the orthographic projection of the transistor T7 and the storage capacitor, the two first sub-lines 71 and the two second connection lines 80 in the lead group on the substrate is the same as the orthographic projection of the first to seventh transistors T1 to T7 and the storage capacitor on the substrate.
  • the orthographic projection of the two second overlapping vias DV2 in the lead group on the substrate does not overlap with the orthographic projection of the first to seventh transistors T1 to T7 and the storage capacitor on the substrate.
  • the two first sub-lines 71 and the two second connection lines 80 in the lead group may be located between the fifth transistor T5 and the sixth transistor T6 in the N-1th row and the seventh transistor T6 in the N-th row.
  • the two second overlapping vias DV2 in the lead group may be located between the fifth and sixth transistors T5 and T6 of the N-1th row and the seventh transistor T7 of the Nth row.
  • the orthographic projection of the second sub-line 72 on the substrate does not overlap with the orthographic projection of the first plate and the second substrate of the storage capacitor on the substrate, and the orthographic projection of the second sub-line 72 on the substrate does not overlap.
  • the projection does not overlap with the orthographic projection of the third transistor T3 on the substrate.
  • two second sub-lines 72 may be provided in at least one unit column.
  • the two second sub-lines 72 may be respectively located on both sides of the unit column in the first direction X, and at least one second sub-line 72 is located on
  • the orthographic projection on the substrate at least partially overlaps the orthographic projection of the data signal line 60 on the substrate.
  • the following is an exemplary description through the preparation process of the display substrate.
  • the "patterning process” mentioned in this disclosure includes processes such as coating of photoresist, mask exposure, development, etching, and stripping of photoresist for metal materials, inorganic materials, or transparent conductive materials.
  • organic materials it includes Processes such as coating of organic materials, mask exposure and development.
  • Deposition can use any one or more of sputtering, evaporation, and chemical vapor deposition.
  • Coating can use any one or more of spraying, spin coating, and inkjet printing.
  • Etching can use dry etching and wet etching. Any one or more of them, this disclosure is not limited here.
  • Thin film refers to a thin film produced by depositing, coating or other processes of a certain material on a substrate. If the "thin film” does not require a patterning process during the entire production process, the “thin film” can also be called a “layer.” If the "thin film” requires a patterning process during the entire production process, it will be called a “thin film” before the patterning process and a “layer” after the patterning process. The “layer” after the patterning process contains at least one "pattern”. “A and B are arranged on the same layer” mentioned in this disclosure means that A and B are formed simultaneously through the same patterning process, and the “thickness” of the film layer is the size of the film layer in the direction perpendicular to the display substrate.
  • the orthographic projection of B is within the range of the orthographic projection of A
  • the orthographic projection of A includes the orthographic projection of B means that the boundary of the orthographic projection of B falls within the orthographic projection of A. within the bounds of A, or the bounds of the orthographic projection of A overlap with the bounds of the orthographic projection of B.
  • this exemplary embodiment shows that the preparation process of the substrate may include the following operations.
  • preparing the substrate may include: first coating a layer of first flexible material on a glass carrier, curing the film to form a first flexible layer 10A. Then, a first barrier film and a base conductive film are sequentially deposited on the first flexible layer 10A, and the base conductive film is patterned through a patterning process to form a first barrier (Barrier) layer covering the first flexible layer, and is disposed on the first flexible layer 10A. A base conductive layer pattern on the barrier layer. Then, a layer of second flexible material is coated and cured to form a film to form a second flexible layer covering the pattern of the base conductive layer.
  • Figure 14A is a schematic plan view of area B in Figure 6, and Figure 14B is area C in Figure 6.
  • the base conductive layer may be referred to as a 0th source-drain metal (SDO) layer.
  • SDO source-drain metal
  • the base conductive layer pattern may include at least a plurality of first sub-lines 71 provided in the display area 100 and the side frame area 310 , and a plurality of second sub-lines 72 provided in the display area 100 .
  • the shape of the first sub-line 71 may be a line shape with the main body extending along the first direction X
  • the shape of the second sub-line 72 may be a line shape with the main body extending along the second direction Y.
  • the shape of the second sub-line 72 The first end is connected to the lead wire in the binding area.
  • the second end of the second sub-line 72 extends from the binding area to the display area 100 and is connected to the first end of the first sub-line 71 .
  • the first sub-line 71 The second end extends from the display area 100 to the side frame area 310 .
  • the end of the first sub-line 71 away from the display area 100 (the second end of the first sub-line 71) is provided with a first connection block 73, and the shape of the first connection block 73 may be a rectangle,
  • the first connection block 73 is connected to the first sub-line 71 , and the first connection block 73 is configured to be connected to a subsequently formed second connection line through a first overlapping via hole.
  • first sub-line 71 , the second sub-line 72 , and the first connection block 73 may be an integral structure connected to each other.
  • the first connection block 73 may be disposed on a side of the packaging line FX away from the display area, and the plurality of first connection blocks 73 may be located on a straight line extending along the second direction Y.
  • a plurality of second sub-lines 72 may be arranged at intervals along the first direction
  • the present disclosure does not limit the two sides of the first direction X.
  • the sub-line group may include two first sub-lines 71 , the sub-line group may be disposed between adjacent circuit rows, and the distance between adjacent sub-line groups in the second direction Y may be substantially Equally, two circuit rows can be included between adjacent sub-line groups.
  • the distance between the two first sub-lines 71 in the sub-line group located between the N-1th row and the N-th row may be equal to the distance between the N+1th row and the N+2-th row.
  • the first connection block 73 on the first sub-line 71 may be disposed on a side of the first sub-line 71 away from the other first sub-line 71 as much as possible. Increase the spacing between the two first overlapping vias to improve connection reliability.
  • materials of the first flexible layer and the second flexible layer may include, but are not limited to, polyethylene terephthalate, ethylene terephthalate, polyether ether ketone, polystyrene , one or more of polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.
  • the materials of the first barrier layer and the second barrier layer may include but are not limited to any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, Multiple layers or composite layers are used to improve the water and oxygen resistance of the substrate.
  • the base conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals.
  • the base conductive layer can be made of metal molybdenum.
  • the base conductive layer may adopt a titanium/aluminum/titanium (Ti/Al/Ti) composite structure, which is beneficial to reducing the resistance of the first connection line.
  • Ti/Al/Ti titanium/aluminum/titanium
  • Exemplary embodiments of the present disclosure display substrates, by arranging a base conductive layer between double flexible layers of the base, and the base conductive layer includes a first connection line that implements a fan-out function in the display area and the frame area, which is beneficial to reducing the binding area. width to achieve narrow borders.
  • forming the semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on a substrate, patterning the semiconductor film through a patterning process, forming a first insulating layer covering the substrate, and disposing on The semiconductor layer pattern on the first insulating layer is shown in Figures 15A and 15B.
  • Figure 15A is a schematic plan view of the area B in Figure 6
  • Figure 15B is a schematic plan view of the area C in Figure 6.
  • the semiconductor layer pattern of each circuit unit in the display area may include at least the first active layer 11 of the first transistor T1 to the seventh active layer 17 of the seventh transistor T7, and the connection line 18,
  • the first active layer 11 to the seventh active layer 17 are an integral structure connected to each other.
  • the sixth active layer 16 of the circuit unit in the N-th unit row and the row circuit in the N+1-th unit row The seventh active layers 17 in the cells are connected to each other by connecting lines 18 .
  • the second active layer 12 and the sixth active layer 16 may be located on the same side of the third active layer 13 in the present circuit unit, the fourth active layer 14 and the fifth active layer 15 may be located on the same side of the third active layer 13 in the present circuit unit, and the second active layer 12 and the fourth active layer 14 may be located on different sides of the third active layer 13 in the present circuit unit.
  • the first active layer 11, the second active layer 12, the fourth active layer 14 and the seventh active layer 17 may be located on a side of the third active layer 13 in the present circuit unit in the opposite direction of the second direction Y, and the fifth active layer 15 and the sixth active layer 16 may be located on a side of the third active layer 13 in the present circuit unit in the second direction Y.
  • the first active layer 11 may be in an "n" shape
  • the second active layer 12 and the fifth active layer 15 may be in an "L” shape
  • the third active layer 13 may be in an "L” shape.
  • the shapes of the fourth active layer 14, the sixth active layer 16 and the seventh active layer 17 can be in the shape of "I”.
  • the active layer of each transistor may include a first region, a second region, and a channel region between the first region and the second region.
  • the first region 11-1 of the first active layer may serve as the first region 17-1 of the seventh active layer
  • the second region 11-2 of the first active layer may serve as the second
  • the first region 12-1 of the active layer and the first region 13-1 of the third active layer can simultaneously serve as the second region 14-2 of the fourth active layer and the second region 15- of the fifth active layer.
  • the second area 13-2 of the third active layer can simultaneously serve as the second area 12-2 of the second active layer and the first area 16-1 of the sixth active layer.
  • the sixth area in this circuit unit has The second area 16-2 of the active layer can be used as the second area 17-2 of the seventh active layer, the first area 14-1 of the fourth active layer, and the first area 14-1 of the fifth active layer in the next row of circuit units.
  • Zone 15-1 can be set individually.
  • the orthographic projection of the first sub-line 71 on the substrate does not overlap with the orthographic projection of the first to seventh active layers 11 to 17 on the substrate, and the first sub-line 71 is on the substrate.
  • the orthographic projection of the connecting line 18 at least partially overlaps with the orthographic projection of the connecting line 18 on the substrate.
  • the orthographic projection of the second sub-line 72 on the substrate does not overlap with the orthographic projection of the third active layer 13 on the substrate, and the orthographic projection of the second sub-line 72 on the substrate does not overlap with the connecting line 18 Orthographic projections on the substrate at least partially overlap.
  • forming the first conductive layer pattern may include: depositing a second insulating film and a first conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the first conductive film by a patterning process, forming a second insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer, as shown in FIGS. 16A and 16B, where FIG. 16A is a schematic diagram of a planar structure of region B in FIG. 6, and FIG. 16B is a schematic diagram of a planar structure of region C in FIG. 6.
  • the first conductive layer may be referred to as a first gate metal (GATE1) layer.
  • the first conductive layer pattern of each circuit unit in the display area at least includes: a first scanning signal line 21, a second scanning signal line 22, a light emitting control line 23, and a first plate 24 of a storage capacitor. .
  • the shape of the first plate 24 may be a rectangle, and the corners of the rectangle may be chamfered.
  • the orthographic projections of the layers on the substrate at least partially overlap.
  • the first plate 24 may simultaneously serve as a plate of the storage capacitor and a gate electrode of the third transistor T3.
  • the shape of the first scanning signal line 21 may be a line shape with the main body extending along the first direction X, and the first scanning signal line 21 may be located in the second direction of the first plate 24 of the circuit unit. The side in the opposite direction of Y.
  • the first scanning signal line 21 of each circuit unit is provided with a gate block, the first end of the gate block is connected to the first scanning signal line 21 , and the second end of the gate block extends in a direction away from the first plate 24 .
  • the area where the first scanning signal line 21 and the gate block overlap with the second active layer of this circuit unit serves as the gate electrode of the second transistor T2 of the double-gate structure.
  • the first scanning signal line 21 and the fourth active layer of this circuit unit The area where the active layers overlap serves as the gate electrode of the fourth transistor T4.
  • the shape of the second scanning signal line 22 may be a line shape with the main part extending along the first direction X, and the second scanning signal line 22 may be located away from the first scanning signal line 21 of the circuit unit.
  • the area where the second scanning signal line 22 overlaps with the first active layer of this circuit unit serves as the gate electrode of the first transistor T1 of the double-gate structure.
  • the second scanning signal line 22 and this circuit unit The overlapping area of the seventh active layer of the cell serves as the gate electrode of the seventh transistor T7.
  • the shape of the light-emitting control line 23 may be a line shape with the main body extending along the first direction X, and the light-emitting control line 23 may be located on one side of the first plate 24 of the circuit unit in the second direction Y. , the area where the light-emitting control line 23 overlaps with the fifth active layer of this circuit unit serves as the gate electrode of the fifth transistor T5, and the area where the light-emitting control line 23 overlaps with the sixth active layer of this circuit unit serves as the sixth transistor. Gate electrode of T6.
  • the first scanning signal line 21 , the second scanning signal line 22 and the light emitting control line 23 may be designed with equal widths, or may be designed with unequal widths, may be straight lines, or may be polygonal lines, not only It facilitates the layout of the pixel structure and can reduce the parasitic capacitance between signal lines. This disclosure is not limited here.
  • the orthographic projection of the first sub-line 71 on the substrate is the same as the orthographic projection of the first scanning signal line 21 , the second scanning signal line 22 , the light-emitting control line 23 and the first plate 24 of the storage capacitor on the substrate. There is no overlap in the orthographic projection, and the orthographic projection of the second sub-line 72 on the substrate does not overlap with the orthographic projection of the first plate 24 of the storage capacitor on the substrate.
  • the first conductive layer can be used as a shield to perform a conductive process on the semiconductor layer, and the semiconductor layer in the area blocked by the first conductive layer forms the first to seventh transistors T1 to T1.
  • the channel region of the transistor T7 and the semiconductor layer in the region not blocked by the first conductive layer are conductive, that is, the first and second regions of the first to seventh active layers of the first transistor T1 are all conductive.
  • forming the first overlapping via pattern may include: depositing a third insulating film on the substrate on which the foregoing pattern is formed, patterning the third insulating film using a patterning process, and forming a layer covering the first conductive film.
  • the third insulating layer of the third insulating layer has a plurality of first overlapping vias DV1 formed on the third insulating layer, as shown in Figures 17A and 17B.
  • Figure 17A is a schematic plan view of area B in Figure 6
  • Figure 17B is a schematic diagram of the planar structure of area B in Figure 6. Schematic diagram of the planar structure of the middle C area.
  • a plurality of first overlapping vias DV1 may be disposed on a side of the packaging line FX away from the display area 100 , that is, the first overlapping vias DV1 may be disposed in the non-packaging area within the side frame area 310 .
  • the orthographic projection of the first overlapping via DV1 on the substrate may be located within the range of the orthographic projection of the first connection block 73 on the substrate, and the third insulation in the first overlapping via DV1 layer, the second insulating layer, the first insulating layer, the second barrier layer and the second flexible layer are removed to expose the surface of the first connection block 73, and the first overlapping via DV1 is configured to enable the subsequently formed second
  • the connecting wire is connected to the first connecting block 73 through the via hole.
  • the plurality of first overlapping vias DV1 may be located on a straight line extending along the second direction Y, and the shape of the first overlapping vias DV1 may be any one or more of the following: triangular , rectangle, pentagon, hexagon, circle and oval.
  • forming the second conductive layer pattern may include: depositing a second conductive film on the substrate on which the foregoing pattern is formed, patterning the second conductive film using a patterning process, and forming a second conductive film on the third insulating layer.
  • the second conductive layer pattern is shown in Figures 18A and 18B.
  • Figure 18A is a schematic plan view of the area B in Figure 6
  • Figure 18B is a schematic plan view of the area C in Figure 6.
  • the second conductive layer may be referred to as a second gate metal (GATE2) layer.
  • the second conductive layer pattern of each circuit unit in the display area includes at least an initial signal line 31 , a second plate 32 of a storage capacitor, and a shielding electrode 33 .
  • the shape of the initial signal line 31 can be a line shape in which the main part extends along the first direction X.
  • the initial signal line 31 can be located on the side of the second scanning signal line 22 of the circuit unit away from the first scanning signal line 21.
  • the initial signal line 31 is configured to be connected to the first electrode of the first transistor T1 (also the first electrode of the seventh transistor T7) formed subsequently.
  • the outline of the second electrode plate 32 may be rectangular, and the corners of the rectangular shape may be chamfered.
  • the orthographic projection of the second electrode plate 32 on the base is consistent with the orthographic projection of the first electrode plate 24 on the base.
  • the orthographic projection at least partially overlaps, the second plate 32 can serve as another plate of the storage capacitor, and the first plate 24 and the second plate 32 constitute the storage capacitor of the pixel driving circuit.
  • the second electrode plate 32 is provided with an opening.
  • the opening may be rectangular in shape and may be located in the middle of the second electrode plate 32 so that the second electrode plate 32 forms an annular structure.
  • the opening exposes the third insulating layer covering the first electrode plate 24 , and the orthographic projection of the first electrode plate 24 on the substrate includes the orthographic projection of the opening on the substrate.
  • the opening is configured to accommodate a subsequently formed first via hole.
  • the first via hole is located in the opening and exposes the first plate 24 , so that the second electrode of the subsequently formed first transistor T1 is connected to the first via hole.
  • the first plate 24 is connected.
  • the second plates 32 in two adjacent sub-pixels in a unit row may be connected to each other through plate connection lines.
  • the second plate 32 in each circuit unit is connected to the first power line formed subsequently, the second plate 32 of adjacent circuit units are formed into an integrated body connected to each other through the plate connection line.
  • the integrated structure of the second plate can be reused as a power signal line, which can ensure that multiple second plates in a unit row have the same potential, which is beneficial to improving the uniformity of the panel and avoiding poor display of the display substrate. Ensure the display effect of the display substrate.
  • the shape of the shielding electrode 33 may be a straight line extending along the first direction X, and the shielding electrode 33 may be disposed between the first scanning signal line 21 and the second scanning signal line 22 .
  • the shielding electrode 33 The orthographic projection of the first end of the shield electrode 33 on the substrate at least partially overlaps with the orthographic projection of the portion of the second active layer located between the two gate electrodes on the substrate, and the orthographic projection of the second end of the shield electrode 33 on the substrate overlaps with The orthographic projection of the second area of the first active layer on the substrate at least partially overlaps, and the shielding electrode 33 is connected to the subsequently formed first power line and is configured to shield a key node of the pixel driving circuit.
  • the second conductive layer pattern may further include a plurality of second connection lines 80 .
  • the shape of the second connection line 80 may be a line shape with the main body extending along the second direction Y.
  • the first end of the second connection line 80 (the end far away from the display area 100) is provided with a second connection block 82.
  • a third connection block 83 is provided at the second end of the connection line 80 (located at the end of the display area 100).
  • the shapes of the second connection block 82 and the third connection block 83 may be rectangular, the second connection block 82 is connected to the first connection block 73 through the first overlapping via DV1, and the third connection block 83 is configured to connect with subsequently formed data signal lines.
  • the plurality of second connection blocks 82 of the plurality of second connection lines 80 may be located on a straight line extending along the second direction Y, and the plurality of third connection blocks of the plurality of second connection lines 80 83 may be located in different unit columns to connect data signal lines of different unit columns respectively.
  • the area of the second connection block 82 may be smaller than the area of the first connection block 73 , and the orthographic projection of the second connection block 82 on the substrate may be within the range of the orthographic projection of the first connection block 73 on the substrate. within.
  • the second connection block 82 covers the exposed first connection block 73 at the inner bottom of the first overlapping via hole DV1 and covers the exposed flexible layer and a plurality of inorganic inner walls of the first overlapping via hole DV1 layer, and the second connection block 82 covers the third insulation layer outside the first overlapping via DV1.
  • the orthographic projection of the second connection line 80 on the substrate is the same as the orthographic projection of the first sub-line 71 on the substrate.
  • the orthographic projections on the first sub-line 71 and the second connection line 80 at least partially overlap to form upper and lower stacked traces of the first sub-line 71 and the second connection line 80 to reduce the parasitic capacitance of transmitting data signals.
  • the orthographic projection of the second connection line 80 on the substrate may be located within the range of the orthographic projection of the first sub-line 71 on the substrate.
  • the distance between the two second connection lines 80 in the sub-line group between the N-1th row and the Nth row may be equal to the distance between the N+1th row and the N+2th row.
  • the distance between the two second connecting lines 80 in the sub-line group between rows may be equal to the distance between the N+1th row and the N+2th row.
  • the orthographic projection of the first sub-line 71 on the substrate does not overlap with the orthographic projection of the initial signal line 31, the second plate 32 of the storage capacitor and the shielding electrode 33 on the substrate, and the second connection line
  • the orthographic projection of 80 on the substrate does not overlap with the orthographic projection of the initial signal line 31, the second plate 32 of the storage capacitor and the shield electrode 33 on the substrate.
  • the orthographic projection of the second sub-line 72 on the substrate does not overlap with the orthographic projection of the storage capacitor.
  • the orthographic projection of the second plate 32 on the substrate does not overlap.
  • forming the fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate on which the foregoing pattern is formed, patterning the fourth insulating film using a patterning process, and forming a pattern covering the second conductive layer.
  • the fourth insulating layer is provided with multiple via holes, as shown in Figures 19A and 19B.
  • Figure 19A is a schematic plan view of the area B in Figure 6, and
  • Figure 19B is a plan view of the area C in Figure 6. Schematic diagram.
  • the plurality of via holes of each circuit unit in the display area at least include: a first via hole V1, a second via hole V2, a third via hole V3, a fourth via hole V4, and a fifth via hole.
  • V5 the sixth via V6, the seventh via V7, the eighth via V8 and the ninth via V9.
  • the orthographic projection of the first via hole V1 on the substrate is within the range of the orthographic projection of the opening on the substrate, and the fourth insulating layer and the third insulating layer in the first via hole V1 are etched removed, exposing the surface of the first plate 24, and the first via hole V1 is configured to allow the second electrode of the subsequently formed first transistor T1 (also the first electrode of the second transistor T2) to pass through the via hole and connect to the first electrode. Plate 24 is connected.
  • the orthographic projection of the second via hole V2 on the substrate is within the range of the orthographic projection of the second electrode plate 32 on the substrate, and the fourth insulating layer in the second via hole V2 is etched away. , exposing the surface of the second electrode plate 32 , and the second via hole V2 is configured to allow the subsequently formed first power line to be connected to the second electrode plate 32 through the via hole.
  • the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the first region of the fifth active layer on the substrate, and the fourth insulating layer in the third via hole V3 , the third insulating layer and the second insulating layer are etched away, exposing the surface of the first region of the fifth active layer, and the third via hole V3 is configured to allow the subsequently formed first power line to pass through the via hole and The first area of the fifth active layer is connected.
  • the orthographic projection of the fourth via V4 on the substrate is located within the range of the orthographic projection of the second area of the sixth active layer (also the second area of the seventh active layer) on the substrate.
  • the fourth insulating layer, the third insulating layer and the second insulating layer in the fourth via hole V4 are etched away, exposing the surface of the second region of the sixth active layer, and the fourth via hole V4 is configured to make
  • the second electrode of the subsequently formed sixth transistor T6 (also the second electrode of the seventh transistor T7) is connected to the second region of the sixth active layer through the via hole.
  • the orthographic projection of the fifth via hole V5 on the substrate is located within the range of the orthographic projection of the first region of the fourth active layer on the substrate, and the fourth insulating layer in the fifth via hole V5 , the third insulating layer and the second insulating layer are etched away, exposing the surface of the first region of the fourth active layer, and the fifth via hole V5 is configured to allow the subsequently formed data signal line to pass through the via hole and the third insulating layer.
  • the first zone of the four active layers is connected.
  • the orthographic projection of the sixth via V6 on the substrate is located within the range of the orthographic projection of the second area of the first active layer (also the first area of the second active layer) on the substrate.
  • the fourth insulating layer, the third insulating layer and the second insulating layer in the sixth via hole V6 are etched away, exposing the surface of the second region of the first active layer, and the sixth via hole V6 is configured to make
  • the second electrode of the subsequently formed first transistor T1 (also the first electrode of the second transistor T2) is connected to the second region of the first active layer (also the first region of the second active layer) through the via hole.
  • the orthographic projection of the seventh via hole V7 on the substrate is located within the range of the orthographic projection of the first region of the first active layer (also the first region of the seventh active layer) on the substrate.
  • the fourth insulating layer, the third insulating layer and the second insulating layer in the seventh via hole V7 are etched away, exposing the first area surface of the first active layer, and the seventh via hole V7 is configured to make
  • the first electrode of the subsequently formed first transistor T1 (also the first electrode of the seventh transistor T7) is connected to the first region of the first active layer (also the first region of the seventh active layer) through the via hole.
  • the orthographic projection of the eighth via hole V8 on the substrate is within the range of the orthographic projection of the initial signal line 31 on the substrate, and the fourth insulating layer in the eighth via hole V8 is etched away, The surface of the initial signal line 31 is exposed, and the eighth via hole V8 is configured so that the first pole of the subsequently formed first transistor T1 (also the first pole of the seventh transistor T7) is connected to the initial signal line 31 through the via hole. .
  • the orthographic projection of the ninth via hole V9 on the substrate is within the range of the orthographic projection of the shield electrode 33 on the substrate, and the fourth insulating layer in the ninth via hole V9 is etched away, exposing Out of the surface of the shield electrode 33, the ninth via hole V9 is configured so that the first power supply line formed later is connected to the shield electrode 33 through the via hole.
  • there may be a plurality of ninth via holes V9 and the plurality of ninth via holes V9 may be arranged sequentially along the second direction Y to improve connection reliability.
  • the fourth insulation layer may also be provided with a plurality of second overlapping vias DV2, and the plurality of second overlapping vias DV2 may be provided in some circuit units.
  • the orthographic projection of the second overlapping via hole DV2 on the substrate is located within the range of the orthographic projection of the third connecting block 83 of the second connecting line 80 on the substrate.
  • the fourth insulating layer in the second overlapping via hole DV2 is After etching away, the surface of the third connection block 83 is exposed, and the second overlapping via hole DV2 is configured to allow the subsequently formed data signal line to be connected to the second connection line 80 through the via hole.
  • the distance between the two second overlapping vias DV2 in the sub-line group between the N-1th row and the Nth row may be equal to the distance between the N+1th row and the Nth row.
  • the second overlapping vias DV2 are located in the right direction on the substrate. The projection does not overlap with the orthographic projection of the first lap via on the substrate.
  • forming the third conductive layer may include: depositing a third conductive film on the substrate on which the foregoing pattern is formed, patterning the third conductive film using a patterning process, and forming a layer disposed on the fourth insulating layer.
  • the third conductive layer is as shown in Figures 20A and 20B.
  • Figure 20A is a schematic plan view of the area B in Figure 6, and
  • Figure 20B is a schematic plan view of the area C in Figure 6.
  • the third conductive layer may be referred to as a first source-drain metal (SD1) layer.
  • SD1 first source-drain metal
  • the third conductive layer of each circuit unit in the display area includes at least: a first connection electrode 41 , a second connection electrode 42 , a third connection electrode 43 , a first power supply line 44 and a data signal line 60 .
  • the first connection electrode 41 may be in the shape of a strip having a main portion extending along the second direction Y.
  • the first end of the first connection electrode 41 is connected to the first electrode plate 24 through the first via hole V1
  • the second end of the first connection electrode 41 is connected to the second region of the first active layer (also the first region of the second active layer) through the sixth via hole V6, so that the first electrode plate 24, the second region of the first active layer, and the first region of the second active layer have the same potential.
  • the first connection electrode 41 may simultaneously serve as the second electrode of the first transistor T1 and the first electrode of the second transistor T2.
  • the shape of the second connection electrode 42 may be a strip shape with a main body portion extending along the second direction Y, and the first end of the second connection electrode 42 is connected to the initial signal line 31 through the eighth via hole V8 , the second end of the second connection electrode 42 is connected to the first region of the first active layer (also the first region of the seventh active layer) through the seventh via hole V7.
  • the second connection electrode 42 may simultaneously serve as the first electrode of the first transistor T1 and the first electrode of the seventh transistor T7.
  • the shape of the third connection electrode 43 may be a block shape, and the third connection electrode 43 communicates with the second area of the sixth active layer (also the second area of the seventh active layer) through the fourth via hole V4. area) connection.
  • the third connection electrode 43 may serve as the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 at the same time, and the third connection electrode 43 may serve as an anode connection electrode configured to be connected to the subsequently formed anode connection.
  • the shape of the third connection electrode 43 of each circuit unit may be different to connect the corresponding anode.
  • the shape of the first power line 44 can be a straight line with the main part extending along the second direction Y.
  • the first power line 44 is connected to the second electrode 32 through the second via V2.
  • the first power line 44 is connected to the first area of the fifth active layer through the third via V3.
  • the first power line 44 is connected to the shielding electrode 33 through the ninth via V9, thereby realizing the writing of the power signal into the first electrode of the fifth transistor T5, and the second electrode 32, the shielding electrode 33 and the first electrode of the fifth transistor T5 have the same potential.
  • the shape of the data signal line 60 may be a straight line with the main part extending along the second direction Y, and the data signal line 60 is connected to the first area of the fourth active layer through the fifth via V5, Writing the data signal to the first pole of the fourth transistor T4 is achieved.
  • the data signal line 60 of each unit column is also connected to the second connection line 80 through the second overlapping via DV2. Since the second connection line 80 is connected to the first connection line 70 through the first overlapping via hole, the data signal line 60 of the display area 100 is led out to the binding area through the first connection line 70 and the second connection line 80 line connection.
  • the orthographic projection of the first sub-line 71 on the substrate does not overlap with the orthographic projections of the first connecting electrode 41, the second connecting electrode 42 and the third connecting electrode 43 on the substrate, and the orthographic projection of the second connecting line 80 on the substrate does not overlap with the orthographic projections of the first connecting electrode 41, the second connecting electrode 42 and the third connecting electrode 43 on the substrate.
  • the orthographic projection of the at least one second sub-line 72 on the substrate at least partially overlaps the orthographic projection of the data signal line 60 on the substrate, and the orthographic projection of the at least one second sub-line 72 on the substrate overlaps with that of the data signal line 60 .
  • Orthographic projections of the first connection electrode 41 and the second connection electrode 42 on the substrate do not overlap.
  • the subsequent preparation process may include processes such as forming a first planar layer, and the drive circuit layer is prepared on the glass carrier.
  • the driving circuit layer of the display area may include a plurality of circuit units, each circuit unit may include a pixel driving circuit, and the pixel driving circuits are respectively connected to the first scanning signal line 21 , the second scanning signal line 22, the light emission control line 23, the initial signal line 31, the first power supply line 44 and the data signal line 60 are connected.
  • the driving circuit layer of the display area and the side frame area may also include a plurality of first connection lines 70 and a plurality of second connection lines 80.
  • the data signal line 60 connects to the second connection line 80 through the second overlapping via hole DV2.
  • the connection line 80 is connected to the first connection line 70 through the first overlapping via hole DV1.
  • the driving circuit layer may be disposed on the substrate on a plane perpendicular to the display substrate.
  • the substrate may include a stacked first flexible layer 10A, a first barrier layer 10B, a base conductive layer, a second flexible layer 10C and a second barrier layer 10D.
  • the base conductive layer may at least include a first layer located in the display area and the side frame area.
  • Connection line 70 (first sub-line and second sub-line connected to each other).
  • the driving circuit layer may include at least a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer and a third conductive layer sequentially arranged on the substrate.
  • the semiconductor layer may include at least the active layers of the first to seventh transistors, and the first conductive layer may include at least the first scanning signal line 21, the second scanning signal line 22, the light emitting control line 23 and the first plate of the storage capacitor. 24.
  • the second conductive layer may include at least the initial signal line 31, the second plate 32 of the storage capacitor, the shield electrode 33 and the second connection line 80.
  • the second connection line 80 is connected to the first through the first overlapping via DV1.
  • the third conductive layer may include at least a first connection electrode 41, a second connection electrode 42, a third connection electrode 43, a first power supply line 44 and a data signal line 60.
  • the data signal line 60 is connected to the second connection electrode through the second overlapping hole DV2. Connect the cable 80.
  • the first conductive layer, the second conductive layer and the third conductive layer may be made of metal materials, such as any one of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo).
  • metal materials such as any one of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo).
  • metal materials such as any one of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo).
  • metal materials such as any one of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo).
  • AlNd aluminum-neodymium alloy
  • MoNb molybdenum-niobium alloy
  • the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON). Can be single layer, multi-layer or composite layer.
  • the first insulating layer may be called a buffer layer
  • the second insulating layer and the third insulating layer may be called gate insulating (GI) layers
  • the fourth insulating layer may be called an interlayer insulating (ILD) layer.
  • the semiconductor layer can be made of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), six Materials such as thiophene or polythiophene, that is, embodiments of the present invention are suitable for thin film transistors manufactured based on oxide (Oxide) technology, silicon technology or organic technology.
  • a-IGZO amorphous indium gallium zinc oxide
  • ZnON zinc oxynitride
  • IZTO indium zinc tin oxide
  • a-Si amorphous silicon
  • p-Si polycrystalline silicon
  • six Materials such as thiophene or polythiophene, that is, embodiments of the present invention are suitable for thin film transistors manufactured based on oxide (Oxide) technology, silicon technology or organic technology.
  • a light-emitting structure layer and a packaging structure layer can be sequentially prepared on the driving circuit layer.
  • Preparing the light-emitting structure layer may include: first forming an anode conductive layer, which may at least include a plurality of anode patterns. Then a pixel definition layer is formed, and a pixel opening is provided on the pixel definition layer of each circuit unit. The pixel definition layer in the pixel opening is removed, exposing the anode of the circuit unit. An evaporation or inkjet printing process is then used to form an organic light-emitting layer, and then a cathode is formed on the organic light-emitting layer.
  • the packaging structure layer may include a stacked first packaging layer, a second packaging layer, and a third packaging layer.
  • the first packaging layer and the third packaging layer may be made of inorganic materials, and the second packaging layer may be made of organic materials. It is arranged between the first encapsulation layer and the third encapsulation layer to ensure that external water and oxygen cannot enter the light-emitting structure layer.
  • the packaging structure layer may be formed in the display area and the frame area, and the packaging structure layer in the frame area may be located on a side of the packaging line FX close to the display area.
  • Figure 21 is a schematic structural diagram of the first overlapping area according to an exemplary embodiment of the present disclosure.
  • the frame area of the display substrate may include at least a light emitting start signal (ESTV) line 351, a scanning start signal (GSTV) line 352, a first clock signal (ECK) line 361 and a second clock signal (ECB) line. ) line 361.
  • the shape of these signal lines may be a line shape extending along the second direction Y, and may be provided in the gate circuit area.
  • the light-emitting start signal line 351, the scanning start signal line 352, the first clock signal line 361 and the second clock signal line 361 is a vertically extending line shape, so the first sub-line 71 and the second connection line 80 are connected from the light-emitting start signal line 351, the scanning start signal line 352, the first clock signal line 361 and the second clock signal line 361 passing underneath, the orthographic projection of the first sub-line 71 and the second connection line 80 on the substrate is the same as the light-emitting start signal line 351, the scanning start signal line 352, the first clock signal line 361 and the second clock signal line 361 There is a first area of overlap in the orthographic projection on the substrate.
  • the orthographic projection of the first sub-line 71 on the substrate does not overlap with the orthographic projection of the second connection line 80 on the substrate.
  • the present disclosure can ensure that the light-emitting start signal line 351, the scanning start signal line 352, the first clock signal line 361 and the second clock signal The line 361 will not have a large slope due to the first sub-line and the second connecting line provided below, which can avoid short circuits caused by metal residues at the slope and improve process quality.
  • various means may be used to prevent the first sub-line 71 and the second connection line 80 located in the first overlapping area from overlapping.
  • the first sub-line 71 and/or the second connection line 80 can avoid each other by bending the wiring.
  • the first sub-line 71 and/or the second connection line 80 can avoid each other by narrowing the line width, which is not limited in this disclosure.
  • the orthographic projection of the first sub-line 71 on the substrate is the same as that of the second connection line 80 .
  • Orthographic projections of the two connecting lines 80 on the substrate at least partially overlap.
  • Figure 22 is a schematic structural diagram of a resistance compensation structure according to an exemplary embodiment of the present disclosure.
  • the first sub-line and the second connection line in the lead group may be provided with a resistance compensation structure, and the resistance compensation structure is configured to reduce the first sub-line and the resistance of the second connecting wire, and can adjust the resistance difference caused by the different lengths of the connecting wires in different lead groups.
  • the resistance compensation structure 81 can be disposed on one side of the second connection line 80 in the second direction Y, and the two ends of the resistance compensation structure 81 are connected to the second connection line 80 respectively. connect.
  • the resistance compensation structure 81 may be arranged in the same layer as the second connection line 80 , or may be arranged in a different layer from the second connection line 80 , and there may be between two ends of the resistance compensation structure 81 It can be arranged in a linear shape, a polygonal shape or a wavy shape, which is not limited in this disclosure.
  • the display substrate provided by the present invention by setting a base conductive layer between the double flexible layers of the base, the base conductive layer includes a first connecting line, and the first connecting line is connected to the data signal line through the second connecting line, thereby realizing data routing in the display area, reducing the width of the lower frame, and facilitating the realization of full-screen display.
  • a first lapped via hole for connecting a first connecting line with a second connecting line is arranged in an upper frame area.
  • the display substrate provided by the exemplary embodiment of the present disclosure by arranging the first lapped via hole, the second lapped via hole, the first connecting line and the second connecting line on the side close to the binding area, can effectively reduce the transmission path of the data signal, effectively reduce the load of the data signal, and reduce the rising edge/falling edge (Tr/Tf) of the data signal, which is conducive to achieving a narrow frame with a high refresh rate.
  • the present disclosure can effectively ensure the process quality of opening the first lapped via hole by arranging the first lapped via hole outside the isolation dam, and the deeper first lapped via hole has little effect on the film structure of the display area, occupies less space, and has low production cost.
  • the preparation process of the present disclosure can be well compatible with the existing preparation process, the process is simple to implement, easy to implement, high production efficiency, low production cost, and high yield rate.
  • the display substrate may include a blocking conductive layer.
  • the second connection line may be provided in the shielding conductive layer or the first conductive layer, which is not limited in this disclosure.
  • the display substrate of the present disclosure can be applied to other display devices with pixel driving circuits, such as quantum dot displays, etc., and the disclosure is not limited here.
  • the present disclosure also provides a method for preparing a display substrate to produce the display substrate provided in the above embodiments.
  • the display substrate includes a display area, a side frame area located on at least one side of the display area in a first direction, and a binding area located on one side of the display area in a second direction, and the side frame area
  • the area at least includes a first frame area and a second frame area, the first frame area is located on a side of the second frame area close to the binding area, and the first direction intersects the second direction;
  • the preparation method may include:
  • the substrate including at least a first connection line
  • a driving circuit layer is formed on the substrate.
  • the driving circuit layer at least includes a data signal line and a second connection line.
  • the second connection line is connected to the first connection line through a first overlapping via hole.
  • the data signal line is connected to the second connection line through a second overlapping via hole, and the first overlapping via hole is provided in the first frame area.
  • the present disclosure also provides a display device, which includes the aforementioned display substrate.
  • the display device can be: a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function, which is not limited in the present disclosure.

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Abstract

一种显示基板及其制备方法、显示装置。显示基板包括显示区域(100)、绑定区域(200)和侧边框区(310)，侧边框区(310)至少包括第一边框区(310-1)和第二边框区(310-2)，第一边框区(310-1)位于第二边框区(310-2)靠近绑定区域(200)的一侧；显示基板包括基底(101)和驱动电路层(102)，基底(101)至少包括第一连接线(70)，驱动电路层(102)至少包括数据信号线(60)和第二连接线(80)，第二连接线(80)通过第一搭接过孔(DV1)与第一连接线(70)连接，数据信号线(60)通过第二搭接过孔(DV2)与第二连接线(80)连接，第一搭接过孔(DV1)设置在第一边框区(310-1)。

Description

显示基板及其制备方法、显示装置 技术领域
本文涉及但不限于显示技术领域，具体涉及一种显示基板及其制备方法、显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)和量子点发光二极管(Quantum-dot Light Emitting Diodes，简称QLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。随着显示技术的不断发展，以OLED或QLED为发光器件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的柔性显示装置(Flexible Display)已成为目前显示领域的主流产品。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
一方面，本公开提供了一种显示基板，包括显示区域、位于所述显示区域第一方向至少一侧的侧边框区和位于所述显示区域第二方向一侧的绑定区域，所述侧边框区至少包括第一边框区和第二边框区，所述第一边框区位于所述第二边框区靠近所述绑定区域的一侧，所述第一方向与所述第二方向交叉；所述显示基板包括基底和设置在所述基底上的驱动电路层，所述基底至少包括第一连接线，所述驱动电路层至少包括数据信号线和第二连接线，所述第二连接线通过第一搭接过孔与所述第一连接线连接，所述数据信号线通过第二搭接过孔与所述第二连接线连接，所述第一搭接过孔设置在所述第一边框区。
在示例性实施方式中，所述显示基板包括第一中心线，所述第一中心线为在所述第二方向上平分所述显示区域且沿着所述第一方向延伸的直线，所 述第一边框区位于所述第一中心线靠近所述绑定区域的一侧，所述第一连接线和第二连接线位于所述第一中心线靠近所述绑定区域的一侧。
在示例性实施方式中，所述显示基板包括第二中心线，所述第二中心线为在所述第一方向上平分所述显示区域且沿着所述第二方向延伸的直线；沿着远离所述第一中心线的方向，多个第二搭接过孔与所述第二中心线之间的距离逐渐增加，沿着远离所述第二中心线的方向，多个第二搭接过孔与所述第一中心线之间的距离逐渐增加；或者，沿着远离所述第一中心线的方向，多个第二搭接过孔与所述第二中心线之间的距离逐渐减小，沿着远离所述第二中心线的方向，多个第二搭接过孔与所述第一中心线之间的距离逐渐减小。
在示例性实施方式中，所述绑定区域至少包括引出线，所述引出线的第一端与所述绑定区域中的集成电路对应连接，所述引出线的第二端与所述第一连接线的第一端连接，所述第一连接线的第二端从所述绑定区域经过所述显示区域延伸到所述第一边框区后，通过所述第一搭接过孔与所述第二连接线的第一端连接，所述第二连接线的第二端从所述第一边框区延伸到所述显示区域后，通过所述第二搭接过孔与所述数据信号线连接。
在示例性实施方式中，所述侧边框区包括由封装线划分的封装区和非封装区，所述封装线是封装结构层覆盖所述侧边框区的边界，所述封装区设置在所述封装线靠近所述显示区域的一侧，所述非封装区设置在所述封装线远离所述显示区域的一侧，所述第一搭接过孔设置在所述非封装区。
在示例性实施方式中，所述驱动电路层至少包括在所述基底上依次设置的第一导电层、第二导电层和第三导电层，所述第二连接线设置在所述第一导电层或者所述第二导电层中，所述数据信号线设置在所述第三导电层中。
在示例性实施方式中，所述第一连接线至少包括第一子线和第二子线，所述第二子线的第一端与所述绑定区域的引出线连接，所述第二子线的第二端沿着所述第二方向延伸到所述显示区域后，与所述第一子线的第一端连接，所述第一子线的第二端沿着所述第一方向延伸到所述第一边框区后，通过所述第一搭接过孔与所述第二连接线的第一端连接。
在示例性实施方式中，在所述显示区域，对于传输相同数据信号的第一子线和第二连接线，所述第一子线在所述基底上的正投影与所述第二连接线在所述基底上的正投影至少部分交叠。
在示例性实施方式中，沿着所述第二方向，多条第二连接线的延伸长度逐渐增加，或者，所述第二连接线的延伸长度逐渐减小。
在示例性实施方式中，所述驱动电路层包括构成多个单元行和多个单元列的电路单元，至少一个电路单元包括像素驱动电路，至少一个像素驱动电路包括存储电容和多个晶体管，所述第一连接线和第二连接线在所述基底上的正投影与所述存储电容和多个晶体管在所述基底上的正投影没有交叠。
在示例性实施方式中，所述显示基板包括多个引线组，至少一个引线组包括k条第一子线和通过k个第一搭接过孔与k条第一子线对应连接的k条第二连接线，k条第二连接线通过k个第二搭接过孔与k条数据信号线对应连接，k为大于或等于1的正整数；在所述显示区域，至少一个引线组设置在相邻的单元行之间。
在示例性实施方式中，沿着所述第二方向，第i引线组与第i+1引线组之间的距离，等于第i+1引线组与第i+2引线组之间的距离，i为大于或等于1、小于或等于N-2的正整数，N为引线组的数量。
在示例性实施方式中，k为2，第i引线组中两个第二搭接过孔之间的间距，等于第i+1引线组中两个第二搭接过孔之间的间距。
在示例性实施方式中，所述侧边框区至少包括栅极电路区，所述栅极电路区包括沿着所述第二方向依次设置的多个栅极电路组，相邻的栅极电路组之间设置有走线区，在所述侧边框区，至少一个引线组设置在所述走线区；至少一个栅极电路组包括沿着所述第二方向依次设置的m个扫描栅极电路和沿着所述第二方向依次设置的n个发光栅极电路，所述n个发光栅极电路设置在所述m个扫描栅极电路远离所述显示区域的一侧，m为大于或等于2的正整数，n为大于或等于1的正整数。
在示例性实施方式中，至少一个扫描栅极电路包括多个扫描晶体管和扫描存储电容，至少一个发光栅极电路包括多个发光晶体管和发光存储电容， 至少一个引线组中，所述第一子线和第二连接线在所述基底上的正投影与所述扫描晶体管、扫描存储电容、发光晶体管和发光存储电容在所述基底上的正投影没有交叠。
在示例性实施方式中，所述栅极电路区还包括沿着所述第二方向延伸的至少一条起始信号线和至少一条时钟信号线，至少一个引线组中，所述第一子线和第二连接线在所述基底上的正投影与所述起始信号线和时钟信号线在基底上的正投影存在第一交叠区域。
在示例性实施方式中，在所述第一交叠区域，所述第一子线在所述基底上的正投影与所述第二连接线在所述基底上的正投影没有交叠。
在示例性实施方式中，在所述第一交叠区域以外的所述侧边框区，对于传输相同数据信号的第一子线和第二连接线，所述第一子线在所述基底上的正投影与所述第二连接线在所述基底上的正投影至少部分交叠。
在示例性实施方式中，至少一条第一子线或者至少一条第二连接线设置有电阻补偿结构，所述电阻补偿结构设置在所述栅极电路区远离所述显示区域的一侧。
另一方面，本公开还提供了一种显示装置，包括前述的显示基板。
又一方面，本公开还提供了一种显示基板的制备方法，所述显示基板包括显示区域、位于所述显示区域第一方向至少一侧的侧边框区和位于所述显示区域第二方向一侧的绑定区域，所述侧边框区至少包括第一边框区和第二边框区，所述第一边框区位于所述第二边框区靠近所述绑定区域的一侧，所述第一方向与所述第二方向交叉；所述制备方法包括：
形成基底，所述基底至少包括第一连接线；
在所述基底上形成驱动电路层，所述驱动电路层至少包括数据信号线和第二连接线，所述第二连接线通过第一搭接过孔与所述第一连接线连接，所述数据信号线通过第二搭接过孔与所述第二连接线连接，所述第一搭接过孔设置在所述第一边框区。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1为一种显示装置的结构示意图；
图2为一种显示基板的结构示意图；
图3为一种显示基板中显示区域的平面结构示意图；
图4为一种显示基板中显示区域的剖面结构示意图；
图5为一种像素驱动电路的等效电路示意图；
图6为本公开示例性实施例一种显示基板的平面结构示意图；
图7为图6中第一连接线的结构示意图；
图8为图6中第二连接线的结构示意图；
图9为本公开示例性实施例另一种显示基板的平面结构示意图；
图10为本公开示例性实施例又一种显示基板的平面结构示意图；
图11为本公开示例性实施例一种侧边框区的结构示意图；
图12为本公开示例性实施例一种搭接过孔的剖面结构示意图；
图13A和图13B为本公开实施例一种数据连接线的平面结构示意图；
图14A和图14B为本公开实施例显示基板中形成基底后的示意图；
图15A和图15B为本公开实施例显示基板中形成半导体层后的示意图；
图16A和图16B为本公开实施例显示基板中形成第一导电层后的示意图；
图17A和图17B为本公开实施例显示基板中形成第一搭接过孔后的示意图；
图18A和图18B为本公开实施例显示基板中形成第二导电层后的示意图；
图19A和图19B为本公开实施例显示基板中形成第四绝缘层后的示意图；
图20A和图20B为本公开实施例显示基板中形成第三导电层后的示意图；
图21为本公开示例性实施例第一重叠区的结构示意图；
图22为本公开示例性实施例电阻补偿结构的结构示意图。
附图标记说明:
10A—第一柔性层；     10B—第一阻挡层；     10C—第二柔性层；
10D—第二阻挡层；     11—第一有源层；      12—第二有源层；
13—第三有源层；      14—第四有源层；      15—第五有源层；
16—第六有源层；      17—第七有源层；      18—连接线；
21—第一扫描信号线；  22—第二扫描信号线；  23—发光控制线；
24—第一极板；        31—初始信号线；      32—第二极板；
33—屏蔽电极；        41—第一连接电极；    42—第二连接电极；
43—第三连接电极；    44—第一电源线；      60—数据信号线；
70—第一连接线；      71—第一子线；        72—第二子线；
73—第一连接块；      80—第二连接线；      81—电阻补偿结构；
82—第二连接块；      83—第三连接块；      90—引线组；
91—第一绝缘层；      92—第二绝缘层；      93—第三绝缘层；
94—第四绝缘层；      100—显示区域；       101—基底；
102—驱动电路层；     103—发光结构层；     104—封装结构层；
200—绑定区域；       201—引出线区；       202—弯折区；
220—引出线；         300—边框区域；       310—侧边框区；
310A—封装区；        310B—非封装区；      311—栅极电路区；
312—隔离坝区；       313—裂缝坝区；       314—切割区；
320—上边框区；       330—扫描栅极电路；   340—发光栅极电路；
350—起始信号线；     351—发光起始信号线； 352—扫描起始信号线；
360—时钟信号线；     361—第一时钟信号线； 362—第二时钟信号线；
410—第一隔离坝；     420—第二隔离坝。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图 对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
本公开中的附图比例可以作为实际工艺中的参考，但不限于此。例如：沟道的宽长比、各个膜层的厚度和间距、各个信号线的宽度和间距，可以根据实际需要进行调整。显示基板中像素的个数和每个像素中子像素的个数也不是限定为图中所示的数量，本公开中所描述的附图仅是结构示意图，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流 过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换，“源端”和“漏端”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本说明书中三角形、矩形、梯形、五边形或六边形等并非严格意义上的，可以是近似三角形、矩形、梯形、五边形或六边形等，可以存在公差导致的一些小变形，可以存在导角、弧边以及变形等。本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
图1为一种显示装置的结构示意图。如图1所示，显示装置可以包括时序控制器、数据驱动器、扫描驱动器、发光驱动器和像素阵列，时序控制器分别与数据驱动器、扫描驱动器和发光驱动器连接，数据驱动器分别与多个数据信号线(D1到Dn)连接，扫描驱动器分别与多个扫描信号线(S1到Sm)连接，发光驱动器分别与多个发光信号线(E1到Eo)连接。像素阵列可以包括多个子像素Pxij，i和j可以是自然数，至少一个子像素Pxij可以包括电路单元和与电路单元连接的发光单元，电路单元可以至少包括像素驱动 电路，像素驱动电路分别与扫描信号线、数据信号线和发光信号线连接。在示例性实施方式中，时序控制器可以将适合于数据驱动器的规格的灰度值和控制信号提供到数据驱动器，可以将适合于扫描驱动器的规格的时钟信号、扫描起始信号等提供到扫描驱动器，可以将适合于发光驱动器的规格的时钟信号、发射停止信号等提供到发光驱动器。数据驱动器可以利用从时序控制器接收的灰度值和控制信号来产生将提供到数据信号线D1、D2、D3、……和Dn的数据电压。例如，数据驱动器可以利用时钟信号对灰度值进行采样，并且以像素行为单位将与灰度值对应的数据电压施加到数据信号线D1至Dn，n可以是自然数。扫描驱动器可以通过从时序控制器接收时钟信号、扫描起始信号等来产生将提供到扫描信号线S1、S2、S3、……和Sm的扫描信号。例如，扫描驱动器可以将具有导通电平脉冲的扫描信号顺序地提供到扫描信号线S1至Sm。例如，扫描驱动器可以被构造为移位寄存器的形式，并且可以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产生扫描信号，m可以是自然数。发光驱动器可以通过从时序控制器接收时钟信号、发射停止信号等来产生将提供到发光信号线E1、E2、E3、……和Eo的发射信号。例如，发光驱动器可以将具有截止电平脉冲的发射信号顺序地提供到发光信号线E1至Eo。例如，发光驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以截止电平脉冲形式提供的发射停止信号传输到下一级电路的方式产生发射信号，o可以是自然数。
图2为一种显示基板的结构示意图。如图2所示，显示基板可以包括显示区域100、位于显示区域100一侧的绑定区域200以及位于显示区域100其它侧的边框区域300。在示例性实施方式中，显示区域100可以是平坦的区域，包括组成像素阵列的多个子像素Pxij，多个子像素Pxij配置为显示动态图片或静止图像，显示区域100可以称为有效区域(AA)。在示例性实施方式中，显示基板可以是可变形的，例如卷曲、弯曲、折叠或卷起。
在示例性实施方式中，绑定区域200可以包括沿着远离显示区域100的方向依次设置的扇出区、弯折区、驱动芯片区和绑定引脚区。扇出区连接到显示区域100，可以至少包括多条数据扇出线，多条数据扇出线被配置为以 扇出(Fanout)走线方式连接显示区域的数据信号线。弯折区连接到扇出区，可以包括设置有凹槽的复合绝缘层，被配置为使绑定区域弯折到显示区域的背面。驱动芯片区可以至少包括集成电路(Integrated Circuit，简称IC)，被配置为与多条数据扇出线连接。绑定引脚区可以至少包括多个绑定引脚(Bonding Pad)，被配置为与外部的柔性线路板(Flexible Printed Circuit，简称FPC)绑定连接。
在示例性实施方式中，边框区域300可以包括沿着远离显示区域100的方向依次设置的电路区、电源线区、裂缝坝区和切割区。电路区连接到显示区域100，可以至少包括栅极驱动电路，栅极驱动电路与显示区域100中像素驱动电路的第一扫描信号线、第二扫描信号线和发光控制线连接。电源线区连接到电路区，可以至少包括边框电源走线，边框电源走线沿着平行于显示区域边缘的方向延伸，与显示区域100中的阴极连接。裂缝坝区连接到电源线区，可以至少包括在复合绝缘层上设置的多个裂缝。切割区连接到裂缝坝区，可以至少包括在复合绝缘层上设置的切割槽，切割槽配置为在显示基板的所有膜层制备完成后，切割设备分别沿着切割槽进行切割。
在示例性实施方式中，绑定区域200中的扇出区和边框区域300中的电源线区可以至少设置有第一隔离坝和第二隔离坝，第一隔离坝和第二隔离坝可以沿着平行于显示区域边缘的方向延伸，形成环绕显示区域100的环形结构，显示区域边缘是显示区域靠近绑定区域或者靠近边框区域一侧的边缘。
图3为一种显示基板中显示区域的平面结构示意图。如图3所示，显示基板可以包括以矩阵方式排布的多个像素单元P，至少一个像素单元P可以包括出射第一颜色光线的第一子像素P1、出射第二颜色光线的第二子像素P2、出射第三颜色光线的第三子像素P3和第四子像素P4。每个子像素可以均包括电路单元和发光单元，电路单元可以至少包括像素驱动电路，像素驱动电路分别与扫描信号线、数据信号线和发光信号线连接，像素驱动电路被配置为在扫描信号线和发光信号线的控制下，接收数据信号线传输的数据电压，向发光单元输出相应的电流。每个子像素中的发光单元分别与所在子像素的像素驱动电路连接，发光单元被配置为响应所连接的像素驱动电路输出的电流发出相应亮度的光。
在示例性实施方式中，第一子像素P1可以是出射红色光线的红色子像素(R)，第二子像素P2可以是出射蓝色光线的蓝色子像素(B)，第三子像素P3和第四子像素P4可以是出射绿色光线的绿色子像素(G)。在示例性实施方式中，子像素的形状可以是矩形状、菱形、五边形或六边形，四个子像素可以采用钻石形(Diamond)方式排列，形成RGBG像素排布。在其它示例性实施方式中，四个子像素可以采用水平并列、竖直并列或正方形等方式排列，本公开在此不做限定。
在示例性实施方式中，像素单元可以包括三个子像素，三个子像素可以采用水平并列、竖直并列或品字等方式排列，本公开在此不做限定。
图4为一种显示基板中显示区域的剖面结构示意图，示意了显示区域中四个子像素的结构。如图4所示，在垂直于显示基板的平面上，显示基板可以包括设置在基底101上的驱动电路层102、设置在驱动电路层102远离基底101一侧的发光结构层103以及设置在发光结构层103远离基底101一侧的封装结构层104。在一些可能的实现方式中，显示基板可以包括其它膜层，如触控结构层等，本公开在此不做限定。
在示例性实施方式中，基底101可以是柔性基底，或者可以是刚性基底。驱动电路层102可以包括多个电路单元，电路单元可以至少包括像素驱动电路。发光结构层103可以至少多个发光单元，发光单元可以至少包括阳极、有机发光层和阴极，有机发光层在阳极和阴极的驱动下出射相应颜色的光线。封装结构层104可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可以采用无机材料，第二封装层可以采用有机材料，第二封装层设置在第一封装层和第三封装层之间，形成无机材料/有机材料/无机材料叠层结构，可以保证外界水氧无法进入发光结构层103。
在示例性实施方式中，有机发光层可以包括发光层(EML)以及如下任意一层或多层：空穴注入层(HIL)、空穴传输层(HTL)、电子阻挡层(EBL)、、空穴阻挡层(HBL)、电子传输层(ETL)和电子注入层(EIL)。在示例性实施方式中，所有子像素的空穴注入层、空穴传输层、电子阻挡层、空穴阻挡层、电子传输层和电子注入层中的一层或多层可以是连接在一起的共通层，相邻子像素的发光层可以有少量的交叠，或者可以是相互隔离的。
图5为一种像素驱动电路的等效电路示意图。在示例性实施方式中，像素驱动电路可以是3T1C、4T1C、5T1C、5T2C、6T1C、7T1C或8T1C结构。如图5所示，像素驱动电路可以包括7个晶体管(第一晶体管T1到第七晶体管T7)和1个存储电容C，像素驱动电路分别与6个信号线(数据信号线D、第一扫描信号线S1、第二扫描信号线S2、发光信号线E、初始信号线INIT和第一电源线VDD)连接。
在示例性实施方式中，像素驱动电路可以包括第一节点N1、第二节点N2和第三节点N3。其中，第一节点N1分别与第三晶体管T3的第一极、第四晶体管T4的第二极和第五晶体管T5的第二极连接，第二节点N2分别与第一晶体管的第二极、第二晶体管T2的第一极、第三晶体管T3的栅电极和存储电容C的第二端连接，第三节点N3分别与第二晶体管T2的第二极、第三晶体管T3的第二极和第六晶体管T6的第一极连接。
在示例性实施方式中，存储电容C的第一端与第一电源线VDD连接，存储电容C的第二端与第二节点N2连接，即存储电容C的第二端与第三晶体管T3的栅电极连接。
第一晶体管T1的栅电极与第二扫描信号线S2连接，第一晶体管T1的第一极与初始信号线INIT连接，第一晶体管的第二极与第二节点N2连接。当导通电平扫描信号施加到第二扫描信号线S2时，第一晶体管T1将初始电压传输到第三晶体管T3的栅电极，以使第三晶体管T3的栅电极的电荷量初始化。
第二晶体管T2的栅电极与第一扫描信号线S1连接，第二晶体管T2的第一极与第二节点N2连接，第二晶体管T2的第二极与第三节点N3连接。当导通电平扫描信号施加到第一扫描信号线S1时，第二晶体管T2使第三晶体管T3的栅电极与第二极连接。
第三晶体管T3的栅电极与第二节点N2连接，即第三晶体管T3的栅电极与存储电容C的第二端连接，第三晶体管T3的第一极与第一节点N1连接，第三晶体管T3的第二极与第三节点N3连接。第三晶体管T3可以称为驱动晶体管，第三晶体管T3根据其栅电极与第一极之间的电位差来确定在第一电源线VDD与第二电源线VSS之间流动的驱动电流的量。
第四晶体管T4的栅电极与第一扫描信号线S1连接，第四晶体管T4的第一极与数据信号线D连接，第四晶体管T4的第二极与第一节点N1连接。第四晶体管T4可以称为开关晶体管、扫描晶体管等，当导通电平扫描信号施加到第一扫描信号线S1时，第四晶体管T4使数据信号线D的数据电压输入到像素驱动电路。
第五晶体管T5的栅电极与发光信号线E连接，第五晶体管T5的第一极与第一电源线VDD连接，第五晶体管T5的第二极与第一节点N1连接。第六晶体管T6的栅电极与发光信号线E连接，第六晶体管T6的第一极与第三节点N3连接，第六晶体管T6的第二极与发光单元EL的第一极连接。第五晶体管T5和第六晶体管T6可以称为发光晶体管。当导通电平发光信号施加到发光信号线E时，第五晶体管T5和第六晶体管T6通过在第一电源线VDD与第二电源线VSS之间形成驱动电流路径而使发光单元EL发光。
第七晶体管T7的栅电极与第二扫描信号线S2连接，第七晶体管T7的第一极与初始信号线INIT连接，第七晶体管T7的第二极与发光单元EL的第一极连接。当导通电平扫描信号施加到第二扫描信号线S2时，第七晶体管T7将初始电压传输到发光单元EL的第一极，以使发光单元EL的第一极中累积的电荷量初始化或释放发光单元EL的第一极中累积的电荷量。
在示例性实施方式中，发光单元EL可以是OLED，包括叠设的第一极(阳极)、有机发光层和第二极(阴极)，或者可以是QLED，包括叠设的第一极(阳极)、量子点发光层和第二极(阴极)。
在示例性实施方式中，发光单元EL的第二极与第二电源线VSS连接，第二电源线VSS的信号为持续提供的低电平信号，第一电源线VDD的信号为持续提供的高电平信号。
在示例性实施方式中，第一晶体管T1到第七晶体管T7可以是P型晶体管，或者可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。在一些可能的实现方式中，第一晶体管T1到第七晶体管T7可以包括P型晶体管和N型晶体管。
在示例性实施方式中，第一晶体管T1到第七晶体管T7可以采用低温多 晶硅薄膜晶体管，或者可以采用氧化物薄膜晶体管，或者可以采用低温多晶硅薄膜晶体管和氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅(Low Temperature Poly-Silicon，简称LTPS)，氧化物薄膜晶体管的有源层采用氧化物半导体(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点，将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示基板上，形成低温多晶氧化物(Low Temperature Polycrystalline Oxide，简称LTPO)显示基板，可以利用两者的优势，可以实现低频驱动，可以降低功耗，可以提高显示品质。
下面以7个晶体管均为P型晶体管为例，像素驱动电路的工作过程可以包括：
第一阶段A1，称为复位阶段，第二扫描信号线S2的信号为低电平信号，第一扫描信号线S1和发光信号线E的信号为高电平信号。第二扫描信号线S2的信号为低电平信号使第一晶体管T1和第七晶体管T7导通。第一晶体管T1导通使得初始信号线INIT的初始电压提供至第二节点N2，对存储电容C进行初始化，清除存储电容中原有数据电压。第七晶体管T7导通使得初始信号线INIT的初始电压提供至OLED的第一极，对OLED的第一极进行初始化(复位)，清空其内部的预存电压，完成初始化。第一扫描信号线S1和发光信号线E的信号为高电平信号，使第二晶体管T2、第四晶体管T4、第五晶体管T5和第六晶体管T6断开，此阶段OLED不发光。
第二阶段A2、称为数据写入阶段或者阈值补偿阶段，第一扫描信号线S1的信号为低电平信号，第二扫描信号线S2和发光信号线E的信号为高电平信号，数据信号线D输出数据电压。此阶段由于存储电容C的第二端为低电平，因此第三晶体管T3导通。第一扫描信号线S1的信号为低电平信号使第二晶体管T2和第四晶体管T4导通。第二晶体管T2和第四晶体管T4导通使得数据信号线D输出的数据电压经过第一节点N1、导通的第三晶体管T3、第三节点N3、导通的第二晶体管T2提供至第二节点N2，并将数据信号线D输出的数据电压与第三晶体管T3的阈值电压之差充入存储电容C，存储电容C的第二端(第二节点N2)的电压为Vd-|Vth|，Vd为数据信号线D输出的数据电压，Vth为第三晶体管T3的阈值电压。第二扫描信号线S2的信号 为高电平信号，使第一晶体管T1和第七晶体管T7断开。发光信号线E的信号为高电平信号，使第五晶体管T5和第六晶体管T6断开。
第三阶段A3、称为发光阶段，发光信号线E的信号为低电平信号，第一扫描信号线S1和第二扫描信号线S2的信号为高电平信号。发光信号线E的信号为低电平信号，使第五晶体管T5和第六晶体管T6导通，第一电源线VDD输出的电源电压通过导通的第五晶体管T5、第三晶体管T3和第六晶体管T6向OLED的第一极提供驱动电压，驱动OLED发光。
在像素驱动电路驱动过程中，流过第三晶体管T3(驱动晶体管)的驱动电流由其栅电极和第一极之间的电压差决定。由于第二节点N2的电压为Vdata-|Vth|，因而第三晶体管T3的驱动电流为：
I＝K*(Vgs-Vth) 2＝K*[(Vdd-Vd+|Vth|)-Vth] 2＝K*[(Vdd-Vd] 2
其中，I为流过第三晶体管T3的驱动电流，也就是驱动OLED的驱动电流，K为常数，Vgs为第三晶体管T3的栅电极和第一极之间的电压差，Vth为第三晶体管T3的阈值电压，Vd为数据信号线D输出的数据电压，Vdd为第一电源线VDD输出的电源电压。
随着OLED显示技术的发展，消费者对显示产品显示效果的要求越来越高，极窄边框成为显示产品发展的新趋势，因此边框的窄化甚至无边框设计在OLED显示产品设计中越来越受到重视。一种显示基板中，数据扇出线设置在绑定区域的扇出区，由于扇出区的宽度小于显示区域的宽度，因而数据扇出线需要通过扇出走线方式才能引入到较宽的显示区域，显示区域与绑定区域的宽度差距越大，扇形区中斜向扇出线越多，扇形区占用空间越大。此外，随着显示屏分辨率逐渐增加，扇出线的占用宽度会逐渐增加，导致下边框的窄化设计难度较大，下边框一直维持在2.0mm左右。
本公开示例性实施例提供了一种显示基板，采用数据连接线位于显示区域(Fanout in AA，简称FIAA)结构。在示例性实施方式中，显示基板可以包括显示区域、位于所述显示区域第一方向至少一侧的侧边框区和位于所述显示区域第二方向一侧的绑定区域，所述侧边框区至少包括第一边框区和第二边框区，所述第一边框区位于所述第二边框区靠近所述绑定区域的一侧， 所述第一方向与所述第二方向交叉；在垂直于所述显示基板的平面上(即在显示基板的厚度方向)，所述显示基板包括基底和设置在所述基底上的驱动电路层，所述基底至少包括第一连接线，所述驱动电路层至少包括数据信号线和第二连接线，所述第二连接线通过第一搭接过孔与所述第一连接线连接，所述数据信号线通过第二搭接过孔与所述第二连接线连接，所述第一搭接过孔设置在所述第一边框区。
在示例性实施方式中，第一连接线和第二连接线构成数据连接线，数据连接线的第一端与绑定区域的集成电路对应连接，数据连接线的第二端延伸到显示区域后，与数据信号线对应连接。由于绑定区域中不需要设置扇形状的斜线，因而缩减了扇出区的宽度，有效减小了下边框宽度。
在示例性实施方式中，显示基板还可以包括位于显示区域远离绑定区域一侧的上边框区，侧边框区和上边框区构成显示基板的边框区域。
在示例性实施方式中，在垂直于显示基板的平面上，显示基板还可以包括设置在驱动电路层远离基底一侧的发光结构层以及设置在发光结构层远离基底一侧的封装结构层。驱动电路层可以包括构成多个单元行和多个单元列的电路单元，至少一个电路单元可以包括像素驱动电路，像素驱动电路被配置为向所连接的发光单元输出相应的电流。发光结构层可以包括构成发光阵列的多个发光单元，至少一个发光单元可以包括发光器件，发光器件与对应电路单元的像素驱动电路连接，发光器件被配置为响应所连接的像素驱动电路输出的电流发出相应亮度的光。
在示例性实施方式中，本公开中所说的电路单元，是指按照像素驱动电路划分的区域，本公开中所说的发光单元，是指按照发光器件划分的区域。在示例性实施方式中，发光单元在基底上正投影的位置与电路单元在基底上正投影的位置可以是对应的，或者，发光单元在基底上正投影的位置与电路单元在基底上正投影的位置可以是不对应的。
在示例性实施方式中，所述显示基板包括第一中心线，所述第一中心线为在所述第二方向上平分所述显示区域且沿着所述第一方向延伸的直线，所述第一边框区位于所述第一中心线靠近所述绑定区域的一侧，所述第一连接线和第二连接线位于所述第一中心线靠近所述绑定区域的一侧。
在示例性实施方式中，所述显示基板包括第二中心线，所述第二中心线为在所述第一方向上平分所述显示区域且沿着所述第二方向延伸的直线；沿着远离所述所述第二中心线，所述第二搭接过孔与所述第一中心线之间的距离逐渐增加，或者，所述第二搭接过孔与所述第一中心线之间的距离逐渐减小。
在示例性实施方式中，所述绑定区域至少包括引出线，所述引出线的第一端与所述绑定区域中的集成电路对应连接，所述引出线的第二端与所述第一连接线的第一端连接，所述第一连接线的第二端从所述绑定区域经过所述显示区域延伸到所述第一边框区后，通过所述第一搭接过孔与所述第二连接线的第一端连接，所述第二连接线的第二端从所述第一边框区延伸到所述显示区域后，通过所述第二搭接过孔与所述数据信号线连接。
在示例性实施方式中，所述侧边框区包括由封装线划分的封装区和非封装区，所述封装线是封装结构层覆盖所述侧边框区的边界，所述封装区设置在所述封装线靠近所述显示区域的一侧，所述非封装区设置在所述封装线远离所述显示区域的一侧，所述第一搭接过孔设置在所述非封装区。
在示例性实施方式中，所述驱动电路层至少包括在所述基底上依次设置的第一导电层、第二导电层和第三导电层，所述第二连接线设置在所述第一导电层或者所述第二导电层中，所述数据信号线设置在所述第三导电层中。
图6为本公开示例性实施例一种显示基板的平面结构示意图，显示基板中的数据连接线采用FIAA结构，图7为图6中第一连接线的结构示意图，图8为图6中第二连接线的结构示意图。在示例性实施方式中，在平行于显示基板的平面上，显示基板可以包括显示区域100、位于显示区域100第二方向Y一侧的绑定区域200以及位于显示区域100其它侧的边框区域300。
如图6至图8所示，显示区域100可以至少包括构成多个单元行和多个单元列的多个电路单元，沿着第一方向X依次设置的多个电路单元可以称为单元行，沿着第二方向Y依次设置的多个电路单元可以称为单元列，多个单元行和多个单元列构成阵列排布的电路单元阵列，第一方向X与第二方向Y交叉。显示区域100还可以包括多条数据信号线60，数据信号线60的形状可以为主体部分沿着第二方向Y延伸的线形状，多条数据信号线60在第一 方向X上以设定的间隔依次设置。至少一个电路单元可以包括像素驱动电路，每条数据信号线60与一个单元列中多个电路单元的像素驱动电路连接。在示例性实施方式中，第二方向Y可以是数据信号线60的延伸方向(竖直方向)，第一方向X可以与第二方向Y垂直(水平方向)。
本公开中，A沿着B方向延伸是指，A可以包括主要部分和与主要部分连接的次要部分，主要部分是线、线段或条形状体，主要部分沿着B方向伸展，且主要部分沿着B方向伸展的长度大于次要部分沿着其它方向伸展的长度。以下描述中所说的“A沿着B方向延伸”均是指“A的主体部分沿着B方向延伸”。在示例性实施方式中，第二方向Y可以是从显示区域指向绑定区域的方向，第二方向Y的反方向可以是从绑定区域指向显示区域的方向。
在示例性实施方式中，绑定区域200可以至少包括沿着远离显示区域100的方向依次设置的引出线区201和弯折区202，引出线区201可以包括多条引出线220，引出线220的第一端与绑定区域200中的集成电路连接，引出线220的第二端经过弯折区202延伸到引出线区201。
在示例性实施方式中，边框区域300可以包括位于显示区域100第一方向X一侧或者两侧的侧边框区310、以及位于显示区域100远离绑定区域200一侧的上边框区320，侧边框区310可以至少包括栅极驱动电路，上边框区320可以至少包括测试电路。
在示例性实施方式中，边框区域300可以包括由封装线划分的封装区和非封装区，封装线可以是封装结构层覆盖边框区域300的边界。对于侧边框区310，侧边框区310可以包括由封装线FX划分的封装区310A和非封装区310B，封装线FX靠近显示区域100的一侧为封装区310A，封装线FX远离显示区域100的一侧为非封装区310B，即非封装区310B可以位于封装区310A远离显示区域100的一侧。
在示例性实施方式中，侧边框区310可以包括沿着第二方向Y依次设置的第一边框区310-1和第二边框区310-2，第一边框区310-1可以位于第二边框区310-2靠近绑定区域200的一侧。
在示例性实施方式中，显示基板还可以包括多条第一连接线70和第二连接线80，第一连接线70和第二连接线80构成数据连接线。多条第一连接线 70的第一端与引出线区201的多条引出线220对应连接，多条第一连接线70的第二端从引出线区201延伸到显示区域100，并从显示区域100延伸到侧边框区310中的第一边框区310-1后，通过第一搭接过孔DV1与多条第二连接线80的第一端对应连接。多条第二连接线80的第二端从第一边框区310-1延伸到显示区域100后，通过第二搭接过孔DV2与多条数据信号线60对应连接，形成第一搭接过孔DV1设置在第一边框区310-1、第二搭接过孔DV2设置在显示区域100的数据连接线结构。
在示例性实施方式中，由于引出线220与绑定区域200中的集成电路连接，第一连接线70与引出线220连接，第二连接线80与第一连接线70连接，数据信号线60与第二连接线80连接，因而显示区域中的数据信号线60通过第二连接线80、第一连接线70和引出线220与绑定区域中的集成电路连接，实现了集成电路向数据信号线60提供数据信号。由于绑定区域中不需要设置扇形状的斜线，因而缩减了扇出区的宽度，可以有效减小下边框宽度。
在示例性实施方式中，数据连接线的数量与数据信号线的数量可以相同，或者，数据连接线的数量可以小于数据信号线的数量，本公开在此不做限定。
在示例性实施方式中，多个第一搭接过孔DV1可以分别设置在侧边框区310的非封装区310B，即多个第一搭接过孔DV1分别设置在封装线FX远离显示区域100的一侧。本公开通过将多个第一搭接过孔设置在边框区域的非封装区，相比于将第一搭接过孔设置在显示区域，可以避免搭接过孔导致的不断扩大的暗点(Growing Dark Spot，简称GDS)问题。
在示例性实施方式中，多个第一搭接过孔DV1也可以分别设置在侧边框区310的封装线FX和第一隔离坝410(或者第二隔离坝420)之间。本公开通过将多个第一搭接过孔设置在边框区域区，相比于将第一搭接过孔设置在显示区域，可以避免搭接过孔导致的不断扩大的暗点(Growing Dark Spot，简称GDS)问题。
在示例性实施方式中，所述显示基板可以包括第一中心线O1，第一中心线O1可以为在第二方向Y上平分显示区域100且沿着第一方向X延伸的直线。
在示例性实施方式中，第一边框区310-1可以位于第一中心线O1靠近 绑定区域200的一侧，使得多个第一搭接过孔DV1和多个第二搭接过孔DV2均位于第一中心线O1靠近绑定区域200的一侧，多条第一连接线70和多条第二连接线80均位于第一中心线O1靠近绑定区域200的一侧。本公开通过将第一搭接过孔、第二搭接过孔、第一连接线和第二连接线设置在靠近绑定区域的一侧，相比于第二搭接过孔设置在上边框区，可以有效减少数据信号的传输路径，有效降低数据信号的负载，降低数据信号的上升沿/下降沿(Tr/Tf)，有利于实现高刷新频率的窄边框。
在示例性实施方式中，第一连接线70可以包括相互连接的第一子线71和第二子线72，第一子线71的形状可以为沿着第一方向X延伸的线形状，第二子线72的形状可以为沿着第二方向Y延伸的线形状。多条第二子线72的第一端与引出线区201的多条引出线220对应连接，多条第二子线72的第二端从引出线区201沿着第二方向Y延伸到显示区域100后，与多条第一子线71的第一端对应连接。多条第一子线71的第二端沿着第一方向X从显示区域100延伸到第一边框区310-1后，通过多个第一搭接过孔DV1与多条第二连接线80的第一端对于对应连接。多条第二连接线80的第二端沿着第一方向X从第一边框区310-1延伸到显示区域100后，通过多个第二搭接过孔DV2与多条数据信号线60对应连接。在示例性实施方式中，第一子线71可以与数据信号线60垂直，第二子线72可以与数据信号线60平行。
在示例性实施方式中，第一子线71的第一延伸长度可以小于或等于0.5*显示区域宽度，第二子线72的第二延伸长度可以小于或等于0.5*显示区域长度，第一延伸长度可以是第一子线71第一方向X的尺寸，显示区域宽度可以是显示区域第一方向X的尺寸，第二延伸长度可以是第二子线72第二方向Y的尺寸，显示区域长度可以是显示区域第二方向Y的尺寸。
在示例性实施方式中，在显示区域100，对于传输相同数据信号的第一子线71和第二连接线80，第一子线71在基底上的正投影与第二连接线80在基底上的正投影至少部分交叠，形成第一子线71和第二连接线80的上下叠层走线，以降低传输数据信号的寄生电容。
在示例性实施方式中，可以包括第二中心线O2，第二中心线O2可以为在第一方向X上平分显示区域100且沿着第二方向Y延伸的直线。多条第二 子线72可以设置在靠近第二中心线O2的区域，至少一条第二子线72在显示基板平面上的正投影与至少一条数据信号线60在显示基板平面上的正投影没有交叠。
在示例性实施方式中，沿着远离第二中心线O2的方向，多条第二子线72的延伸长度逐渐减小，沿着远离第一中心线O1的方向，多条第一子线71的延伸长度逐渐减小。在示例性实施方式中，延伸长度是指沿着延伸方向的尺寸。
在示例性实施方式中，在第一边框区310-1，多个第一搭接过孔DV1可以沿着第二方向Y依次设置，多个第一搭接过孔DV1可以位于沿着第二方向Y延伸的一条直线上。
在示例性实施方式中，沿着远离第一中心线O1的方向，多条第二连接线80的延伸长度可以逐渐减小。
在示例性实施方式中，在显示区域100，沿着远离第一中心线O1的方向，多个第二搭接过孔DV2与第二中心线O2之间的距离可以逐渐增加，沿着远离第二中心线O2的方向，多个第二搭接过孔DV2与第一中心线O1之间的距离可以逐渐增加，在显示区域100形成斜向排布的第二搭接过孔DV2。在显示区域100左侧区域，第二搭接过孔DV2从左下向右上方向排布，在显示区域100右侧区域，第二搭接过孔DV2从右下向左上方向排布。
在示例性实施方式中，在平行于显示基板的平面上，第一搭接过孔DV1和第二搭接过孔DV2的形状可以包括如下任意一种或多种：三角形、矩形、五边形、六边形、圆形和椭圆形。
在示例性实施方式中，在垂直于显示基板的平面上，显示基板可以包括基底以及设置在基底上的驱动电路层。基底可以至少包括第一连接线70，驱动电路层可以至少包括数据信号线60和第二连接线80，第一连接线70通过位于第一边框区310-1的第一搭接过孔DV1与第二连接线80连接，第二连接线80通过位于显示区域100的第二搭接过孔DV2与数据信号线60连接。
在示例性实施方式中，基底可以至少包括第一柔性层、第二柔性层以及设置在第一柔性层和第二柔性层之间的基底导电层(SD0)，第一连接线70 可以设置在基底导电层中。
在示例性实施方式中，至少一个像素驱动电路可以包括存储电容和多个晶体管。驱动电路层可以至少包括沿着远离基底方向依次设置的第一导电层、第二导电层和第三导电层，存储电容的第一极板可以设置在第一导电层(GATE1)中，存储电容的第二极板可以设置在第二导电层(GATE2)中，数据信号线60可以设置在第三导电层(SD1)中。
在示例性实施方式中，在显示区域100，第一子线71在基底上的正投影与存储电容和多个晶体管在基底上的正投影没有交叠，第二子线72在基底上的正投影与存储电容和多个晶体管在基底上的正投影没有交叠，第二连接线在基底上的正投影与存储电容和多个晶体管在基底上的正投影没有交叠，
在一种示例性实施方式中，第二连接线80可以设置在第一导电层中，第二连接线80可以通过第一搭接过孔DV1与第一连接线70连接，数据信号线60可以通过二搭接过孔DV2与第二连接线80连接。
在另一种示例性实施方式中，第二连接线80可以设置在第二导电层中，第二连接线80可以通过第一搭接过孔DV1与第一连接线70连接，数据信号线60可以通过二搭接过孔DV2与第二连接线80连接。
图9为本公开示例性实施例另一种显示基板的平面结构示意图。在示例性实施方式中，本实施例显示基板的主体结构与图6所示显示基板的主体结构基本上相同，所不同的是，显示区域100中多个第二搭接过孔DV2的排布方式不同。
在示例性实施方式中，沿着远离第二中心线O2的方向，多条第二子线72的延伸长度逐渐减小，沿着远离第一中心线O1的方向，多条第一子线71的延伸长度逐渐减小。
在示例性实施方式中，沿着远离第一中心线O1的方向(即从第一中心线O1到绑定区域的方向)，多条第二连接线80的延伸长度逐渐增加。
在示例性实施方式中，在显示区域100，沿着远离第一中心线O1的方向，多个第二搭接过孔DV2与第二中心线O2之间的距离可以逐渐减小，沿着远离第二中心线O2的方向，多个第二搭接过孔DV2与第一中心线O1之间的 距离可以逐渐减小，在显示区域100形成斜向排布的第二搭接过孔DV2。在显示区域100左侧区域，第二搭接过孔DV2从左上向右下方向排布，在显示区域100右侧区域，第二搭接过孔DV2从右上向左下方向排布。
图10为本公开示例性实施例又一种显示基板的平面结构示意图，仅示意了第二连接线的结构。在示例性实施方式中，显示基板可以包括多个引线组90，至少一个引线组90可以包括k条第一子线(未示出)以及通过k个第一搭接过孔DV1与k条第一子线对应连接的k条第二连接线80，k条第二连接线80通过k个第二搭接过孔DV2与k条数据信号线60对应连接，k为大于或等于1的正整数。在示例性实施方式中，本实施例显示基板的主体结构与图6所示显示基板的主体结构基本上相同，所不同的是，图6所示显示基板中的引线组90包括一条第一子线和一条第二连接线，本实施例显示基板中的引线组90包括两条第一子线和两条第二连接线。
在示例性实施方式中，在显示区域100，多个引线组90可以沿着第二方向Y依次设置，每个引线组90可以设置在相邻的单元行之间。
在示例性实施方式中，第二方向Y相邻的引线组90之间，可以设置有2个、3个或者4个单元行。
在示例性实施方式中，沿着第二方向Y，第i引线组与第i+1引线组之间的距离，可以等于第i+1引线组与第i+2引线组之间的距离，即多个引线组90沿着第二方向Y等间距排布，i为大于或等于1、小于或等于N-2的正整数，N为引线组的数量。
在示例性实施方式中，k为1时，即如图6所示的引线组90包括一条第一子线和一条第二连接线80，相邻第一子线之间的间距相同，多条第一子线沿着第二方向Y等间距排布，相邻第二连接线80之间的间距相同，多条第二连接线80沿着第二方向Y等间距排布，多个第一搭接过孔DV1之间的间距相同，多个第一搭接过孔DV1沿着第二方向Y等间距排布，多个第二搭接过孔DV2之间的间距相同，多个第二搭接过孔DV2沿着斜向方向等间距排布，多个第二搭接过孔DV2可以位于沿着斜向方向延伸的同一条直线上。
在示例性实施方式中，k为1时，第j条第一子线与第j+1条第一子线之间的延伸长度之差，可以等于第j+1条第一子线与第j+2条第一子线之间的 延伸长度之差，即多条第一子线的延伸长度为等差级数，j为大于或等于1、小于或等于N-2的正整数。
在示例性实施方式中，k为1时，第j条第二连接线8 0与第j+1条第二连接线80之间的延伸长度之差，可以等于第j+1条第二连接线80与第j+2条第二连接线80之间的延伸长度之差，即多条第二连接线80的延伸长度为等差级数。
在示例性实施方式中，k为1时，第i引线组中第一子线与第二连接线80之间的延伸长度之差，可以等于第i+1引线组中第一子线与第二连接线80之间的延伸长度之差。
在示例性实施方式中，k为2时，即如图10所示的引线组90包括两条第一子线和两条第二连接线80，第i引线组中两条第一子线之间的间距可以等于第i+1引线组中两条第一子线之间的间距，第i引线组中两条第二连接线80之间的间距可以等于第i+1引线组中两条第二连接线80之间的间距，第i引线组中两个第一搭接过孔DV1之间的间距可以等于第i+1引线组中两个第一搭接过孔DV1之间的间距，第i引线组中两个第二搭接过孔DV2之间的间距可以等于第i+1引线组中两个第二搭接过孔DV2之间的间距，多个第二搭接过孔DV2沿着斜向方向变间距排布，多个第二搭接过孔DV2不在沿着斜向方向延伸的同一条直线上。
在示例性实施方式中，k为2时，第i引线组中两条第一子线的延伸长度之差，可以等于第i+1引线组中两条第一子线的延伸长度之差。
在示例性实施方式中，k为2时，第i引线组中两条第二连接线80的延伸长度之差，可以等于第i+1引线组中两条第二连接线80的延伸长度之差。
在示例性实施方式中，k为2时，第j条第一子线与第j+1条第一子线之间的延伸长度之差，可以等于第j+1条第一子线与第j+2条第一子线之间的延伸长度之差，即多条第一子线的延伸长度为等差级数。
在示例性实施方式中，k为2时，第j条第二连接线80与第j+1条第二连接线80之间的延伸长度之差，可以等于第j+1条第二连接线80与第j+2条第二连接线80之间的延伸长度之差，即多条第二连接线80的延伸长度为等差级数。
在示例性实施方式中，k为2时，第j条第一子线与第j+1条第一子线之间的间距，不等于第j+1条第一子线与第j+2条第一子线之间的间距，第j条第二连接线80与第j+1条第二连接线80之间的间距，不等于第j+1条第二连接线80与第j+2条第二连接线80之间的间距。
图11为本公开示例性实施例一种侧边框区的结构示意图。如图6和图11所示，在平行于显示基板的平面上，边框区域300的侧边框区310可以位于显示区域100第一方向X的一侧或者两侧，侧边框区310可以包括由封装线FX划分的封装区310A和非封装区310B，封装线FX可以是封装结构层覆盖侧边框区310的边界，封装线FX靠近显示区域100的一侧为封装区310A，封装线FX远离显示区域100的一侧为非封装区310B。
在示例性实施方式中，封装区310A可以至少包括沿着远离显示区域方向依次设置的栅极电路区311和隔离坝区312。栅极电路区311可以设置有沿着第二方向Y依次设置的多个栅极电路组，第二方向Y相邻的栅极电路组之间设置有走线区，即沿着第二方向Y，多个栅极电路组和多个走线区交替设置，多个走线区分别设置多个引线组90。
在示例性实施方式中，至少一个栅极电路组可以包括沿着平行于显示区域边缘的方向依次设置的m个扫描栅极电路(Gate GOA)330和沿着平行于显示区域边缘的方向依次设置的n个发光栅极电路(EM GOA)340，n个发光栅极电路340可以设置在m个扫描栅极电路330远离显示区域100的一侧，m可以为大于或等于2的正整数，n可以为大于或等于1的正整数。例如，栅极电路组可以包括2个扫描栅极电路330和1个发光栅极电路340，引线组90可以设置在每2个扫描栅极电路330之间以及每个发光栅极电路340之间。
在示例性实施方式中，扫描栅极电路330可以至少包括多个扫描晶体管和扫描电容，发光栅极电路340可以至少包括多个发光晶体管和发光电容，扫描晶体管、扫描电容、发光晶体管和发光电容可以与显示区域的像素驱动电路中的晶体管和存储电容同步制备。
在示例性实施方式中，隔离坝区312可以至少设置有第一隔离坝410和第二隔离坝420，第一隔离坝410和第二隔离坝420可以沿着平行于显示区 域边缘的方向延伸，且与绑定区域和上边框区的第一隔离坝和第二隔离坝连接，形成环绕显示区域的环形结构。在示例性实施方式中，第一隔离坝410和第二隔离坝420可以与显示区域的发光结构层同步制备。
在示例性实施方式中，非封装区310B可以至少包括沿着远离显示区域方向依次设置的裂缝坝区313和切割区314。裂缝坝区313可以至少包括在复合绝缘层上设置的多个裂缝，形成裂缝坝，裂缝坝被配置为在切割过程中减小显示区域的受力，截断裂纹向显示区域方向传递。切割区314可以连接到裂缝坝区，可以至少包括在复合绝缘层上设置的切割槽，切割槽配置为在显示基板的所有膜层制备完成后，切割设备分别沿着切割槽进行切割。
在示例性实施方式中，多个第一搭接过孔DV1可以设置在侧边框区310的非封装区310B，且可以设置在隔离坝区312和裂缝坝区313之间。
在示例性实施方式中，多个引线组90中的第一子线71从显示区域100延伸到侧边框区310(第一边框区)，依次经过栅极电路区311和隔离坝区312后，在非封装区310B通过第一搭接过孔DV1与第二连接线80连接，第二连接线80则依次经过隔离坝区312和栅极电路区311返回到显示区域100后，通过第二搭接过孔(未示出)与数据信号线连接。
在示例性实施方式中，对于传输相同数据信号的第一子线71和第二连接线80，第一子线71在基底上的正投影与第二连接线80在基底上的正投影至少部分交叠，以在侧边框区310形成第一连接线70和第二连接线80的上下叠层走线，有效降低传输数据信号的寄生电容。
在示例性实施方式中，在不影响扫描栅极电路和发光栅极电路正常工作情况下(即扫描栅极电路和发光栅极电路中各个晶体管和电容的尺寸保持正常)，可以通过布局设计在第二方向Y相邻的栅极电路组之间设置走线区，引线组90可以设置在走线区所在区域，使得引线组90中的第一子线71和第二连接线80可以避开扫描栅极电路和发光栅极电路中各个晶体管和电容，第一子线71和第二连接线80在基底上的正投影与扫描栅极电路330的扫描晶体管和扫描电容在基底上的正投影没有交叠，第一子线71和第二连接线80在基底上的正投影与发光栅极电路340的发光晶体管和发光电容在基底上的正投影没有交叠，可以避免数据信号影响扫描栅极电路和发光栅极电路的电 学特性，保证扫描栅极电路和发光栅极电路的工作稳定性和可靠性。
在示例性实施方式中，至少一个走线区可以设置一个引线组90，或者，可以设置2个引线组90，或者，可以设置多个引线组90，一个引线组90可以至少包括传输相同数据信号的一条第一子线71和一条第二连接线80。例如，至少一个走线区可以设置一条第一子线71和一条第二连接线80，为每个子像素的1条数据信号线提供数据信号。又如，对于包括红色子像素、蓝色子像素和绿色子像素的像素单元，至少一个走线区可以设置3条第一子线71和3条第二连接线80，为一个像素单元的3条数据信号线提供数据信号。再如，对于包括红色子像素、蓝色子像素、第一绿色子像素和第二绿色子像素的像素单元，至少一个走线区可以设置4条第一子线71和4条第二连接线80，为一个像素单元的4条数据信号线提供数据信号。
在示例性实施方式中，栅极电路区311还可以包括至少一条起始信号(STV)线350和至少一条时钟信号(GOA Clock)线360，这些信号线的形状可以为沿着平行于显示区域边缘的方向延伸的线形状，可以设置在发光栅极电路340远离显示区域的一侧。在示例性实施方式中，起始信号线350可以包括传输扫描起始信号(GSTV)和传输发光起始信号(ESTV)的信号线，时钟信号线360可以包括传输第一时钟信号(ECK)和传输第二时钟信号(ECB)的信号线。当然，栅极电路区311还可以包括至少一条恒定电平信号线(未示出)，如第二电平信号线(VGH)和第一电平信号线(VGL)。
在示例性实施方式中，栅极电路区311包括所述第一栅极电路区和所述第二栅极电路区，其中所述第一栅极电路区包括至少一个扫描栅极电路330、传输扫描起始信号(GSTV)和时钟信号线360，时钟信号线360可以包括传输第一时钟信号(ECK)和传输第二时钟信号(ECB)的信号线。当然，第一栅极电路区还可以包括至少一条恒定电平信号线，如第二电平信号线(VGH)和第一电平信号线(VGL)。第二栅极电路区包括至少一个发光栅极电路340、传输发光起始信号(ESTV)的信号线和时钟信号线360，时钟信号线360可以包括传输第一时钟信号(ECK)和传输第二时钟信号(ECB)的信号线。当然，第二栅极电路区还可以包括至少一条恒定电平信号线，如第二电平信号线(VGH)和第一电平信号线(VGL)。在示例性实施方式中， 栅极电路区311还可以包括至少一条起始信号(STV)线350和至少一条时钟信号(GOA Clock)线360。其中，至少部分信号线可以设置在发光栅极电路340和扫描栅极电路330之间。当然，第一栅极电路区还可以包括至少一条恒定电平信号线，如第二电平信号线(VGH)和第一电平信号线(VGL)，至少一条恒定电平信号线可以设置在发光栅极电路340和扫描栅极电路330之间。
在示例性实施方式中，由于引线组90中的第一子线71和第二连接线80为横向延伸的线形状，而起始信号线350和时钟信号线360为竖向延伸的线形状，因而第一子线71和第二连接线80会从起始信号线350和时钟信号线360的下方穿过，第一子线71和第二连接线80在基底上的正投影与起始信号线350和时钟信号线360在基底上的正投影存在第一交叠区域。
在示例性实施方式中，在第一交叠区域，可以设置第一子线71在基底上的正投影与第二连接线80在基底上的正投影没有交叠，而在第一交叠区域以外的侧边框区，对于传输相同数据信号的第一子线71和第二连接线80，第一子线71在基底上的正投影与第二连接线80在基底上的正投影至少部分交叠。
在示例性实施方式中，在第一交叠区域，第一子线71和/或第二连接线80可以通过弯折方式相互避让，使得位于第一交叠区域的第一子线71与第二连接线80不交叠。本公开通过在第一交叠区域设置第一子线与第二连接线不交叠，可以保证起始信号线和时钟信号线不会因为下方设置第一子线与第二连接线而存在较大爬坡，可以避免因爬坡处金属残留导致短路，提高工艺质量。
在示例性实施方式中，在栅极电路区311远离显示区域100的一侧，引线组90中的第一子线71和第二连接线80可以设置有电阻补偿结构，电阻补偿结构被配置为减小第一子线71和第二连接线80的电阻，并可以调整因不同引线组90中连接线长度不同导致的电阻差异。
图12为本公开示例性实施例一种搭接过孔的剖面结构示意图。如图12所示，在垂直于显示基板的平面上，显示基板可以至少包括设置在基底101上的驱动电路层102。在示例性实施方式中，基底101可以至少包括第一柔 性层10A、第二柔性层10C以及设置在第一柔性层10A和第二柔性层10C之间的基底导电层，基底导电层可以至少包括第一连接线70。驱动电路层102可以至少包括数据信号线60和第二连接线80，第二连接线80通过第一搭接过孔DV1与第一连接线70连接，数据信号线60通过第二搭接过孔DV2与第二连接线80连接。
在示例性实施方式中，驱动电路层102可以至少包括在基底101上依次设置的第一绝缘层91、半导体层、第二绝缘层92、第一导电层、第三绝缘层93、第二导电层、第四绝缘层94和第三导电层。半导体层可以至少包括像素驱动电路的多个晶体管的有源层，第一导电层可以至少包括多个晶体管的栅电极和存储电容的第一极板，第二导电层可以至少包括第二连接线80和存储电容的第二极板，第三导电层可以至少包括数据信号线60以及多个晶体管的第一极和第二极。
在示例性实施方式中，基底101还可以包括第一阻挡层10B和第二阻挡层10D，第一阻挡层10B设置在第一柔性层10A和基底导电层之间，第二阻挡层10D设置在第二柔性层10C远离第一柔性层10A的一侧。
在示例性实施方式中，第二连接线80覆盖第一搭接过孔DV1底部暴露出的第一连接线70以及覆盖第一搭接过孔DV1内侧壁暴露出的柔性层和多个无机层，且第二连接线80覆盖第一搭接过孔DV1外侧的第三绝缘层。
图13A和图13B为本公开示例性实施例一种数据连接线的平面结构示意图，图13A为图6中B区域的平面结构示意图，图13B为图6中C区域的平面结构示意图。其中，每个引线组包括两条第一子线71和两条第二连接线80。如图13A和图13B所示，在平行于显示基板的平面上，显示区域100可以包括构成多个单元行和多个单元列的多个电路单元，至少一个电路单元可以包括像素驱动电路，像素驱动电路可以至少包括多个晶体管和存储电容，数据信号线60与一个单元列的多个像素驱动电路连接，数据信号线60被配置为向像素驱动电路提供数据信号。
在示例性实施方式中，子线组可以设置在相邻的电路行之间，第二方向Y相邻的子线组之间的距离可以基本上相等。例如，一个子线组可以设置在第N-1行和第N行之间，另一个子线组可以设置在第N+1行和第N+2行之 间，相邻的子线组之间可以包括两个电路行。
在示例性实施方式中，位于第N-1行和第N行之间的子线组中的两条第一子线71之间的距离，可以等于位于第N+1行和第N+2行之间的子线组中的两条第一子线71之间的距离，位于第N-1行和第N行之间的子线组中的两条第二连接线80之间的距离，可以等于位于第N+1行和第N+2行之间的子线组中的两条第二连接线80之间的距离。
在示例性实施方式中，第二子线72可以设置在显示区域100，第二子线72的形状可以为主体部分沿着第二方向Y延伸的线形状，第二子线72的第一端与绑定区域中的引出线连接，第二子线72的第二端从绑定区域延伸到显示区域100后，与第一子线71的第一端连接。
在示例性实施方式中，第一子线71和第二连接线80可以设置在显示区域100和侧边框区310，连接第一子线71和第二连接线80的第一搭接过孔DV1可以设置在侧边框区310(第一边框区)，且第一搭接过孔DV1可以设置在封装线FX远离显示区域100的一侧，连接第二连接线80和数据信号线60的第二搭接过孔DV2可以设置在显示区域100。
在示例性实施方式中，位于第N-1行和第N行之间的子线组中的两个第二搭接过孔DV2之间的距离，可以等于位于第N+1行和第N+2行之间的子线组中的两个第二搭接过孔DV2之间的距离。
在示例性实施方式中，至少一个电路单元的像素驱动电路可以至少包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7和存储电容，引线组中的两条第一子线71和两条第二连接线80在基底上的正投影与第一晶体管T1至第七晶体管T7和存储电容在基底上的正投影没有交叠，引线组中的两个第二搭接过孔DV2在基底上的正投影与第一晶体管T1至第七晶体管T7和存储电容在基底上的正投影没有交叠。
在示例性实施方式中，引线组中的两条第一子线71和两条第二连接线80可以位于第N-1行的第五晶体管T5和第六晶体管T6与第N行的第七晶体管T7之间，引线组中的两个第二搭接过孔DV2可以位于第N-1行的第五 晶体管T5和第六晶体管T6与第N行的第七晶体管T7之间。
在示例性实施方式中，第二子线72在基底上的正投影与存储电容的第一极板和第二基板在基底上的正投影没有交叠，第二子线72在基底上的正投影与第三晶体管T3在基底上的正投影没有交叠。
在示例性实施方式中，至少一个单元列中可以设置两条第二子线72，两条第二子线72可以分别位于单元列第一方向X的两侧，至少一条第二子线72在基底上的正投影与数据信号线60在基底上的正投影至少部分交叠。
下面通过显示基板的制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开在此不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。本公开示例性实施方式中，“B的正投影位于A的正投影的范围之内”或者“A的正投影包含B的正投影”是指，B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
在示例性实施方式中，本示例性实施例显示基板的制备过程可以包括如下操作。
(1)制备基底。在示例性实施方式中，制备基底可以包括：先在玻璃载板上涂布一层第一柔性材料，固化成膜后形成第一柔性层10A。然后在第一柔性层10A上依次沉积第一阻挡薄膜和基底导电薄膜，通过图案化工艺对基底导电薄膜进行图案化，形成覆盖第一柔性层的第一阻挡(Barrier)层，以及设置在第一阻挡层上的基底导电层图案。然后再涂布一层第二柔性材料， 固化成膜后形成覆盖基底导电层图案的第二柔性层。然后，再沉积第二阻挡薄膜，形成覆盖第二柔性层的第二阻挡层，如14A和图14B所示，图14A为图6中B区域的平面结构示意图，图14B为图6中C区域的平面结构示意图。在示例性实施方式中，基底导电层可以称为第0源漏金属(SD0)层。
在示例性实施方式中，基底导电层图案可以至少包括设置在显示区域100和侧边框区310的多条第一子线71、以及设置在显示区域100的多条第二子线72。第一子线71的形状可以为主体部分沿着第一方向X延伸的线形状，第二子线72的形状可以为主体部分沿着第二方向Y延伸的线形状，第二子线72的第一端与绑定区域中的引出线连接，第二子线72的第二端从绑定区域延伸到显示区域100后，与第一子线71的第一端连接，第一子线71的第二端从显示区域100延伸到侧边框区310。
在示例性实施方式中，第一子线71远离显示区域100的端部(第一子线71的第二端)设置有第一连接块73，第一连接块73的形状可以为矩形状，第一连接块73与第一子线71连接，第一连接块73被配置为通过第一搭接过孔与后续形成的第二连接线连接。
在示例性实施方式中，第一子线71、第二子线72和第一连接块73可以为相互连接的一体结构。
在示例性实施方式中，第一连接块73可以设置在封装线FX远离显示区域的一侧，多个第一连接块73可以位于一条沿着第二方向Y延伸的直线上。
在示例性实施方式中，多条第二子线72可以沿着第一方向X间隔设置，至少一个单元列中可以设置两条第二子线72，两条第二子线72可以分别位于单元列第一方向X的两侧，本公开在此不做限定。
在示例性实施方式中，子线组可以包括两条第一子线71，子线组可以设置在相邻的电路行之间，第二方向Y相邻的子线组之间的距离可以基本上相等，相邻的子线组之间可以包括两个电路行。
在示例性实施方式中，位于第N-1行和第N行之间的子线组中的两条第一子线71之间的距离，可以等于位于第N+1行和第N+2行之间的子线组中的两条第一子线71之间的距离。
在示例性实施方式中，至少一个子线组中，第一子线71上的第一连接块73可以设置在该第一子线71远离另一条第一子线71的一侧，可以尽可能增加两个第一搭接过孔之间的间距，提高连接可靠性。
在示例性实施方式中，第一柔性层和第二柔性层的材料可以包括但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。第一阻挡层和第二阻挡层的材料可以包括但不限于硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层，用于提高基底的抗水氧能力。基底导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或多种，或上述金属的合金材料。例如，基底导电层可以采用金属钼。
在示例性实施方式中，基底导电层可以采用钛/铝/钛(Ti/Al/Ti)的复合结构，有利于降低第一连接线的电阻。
本公开示例性实施例显示基板，通过在基底的双柔性层之间设置基底导电层，基底导电层包括在显示区域和边框区域实现扇出功能的第一连接线，有利于减小绑定区域的宽度，实现窄边框。
(2)形成半导体层图案。在示例性实施方式中，形成半导体层图案可以包括：在基底上依次沉积第一绝缘薄膜和半导体薄膜，通过图案化工艺对半导体薄膜进行图案化，形成覆盖基底的第一绝缘层，以及设置在第一绝缘层上的半导体层图案，如图15A和图15B所示，图15A为图6中B区域的平面结构示意图，图15B为图6中C区域的平面结构示意图。
在示例性实施方式中，显示区域中每个电路单元的半导体层图案可以至少包括第一晶体管T1的第一有源层11至第七晶体管T7的第七有源层17、以及连接线18，第一有源层11至第七有源层17为相互连接的一体结构，在第二方向Y上，第N单元行中电路单元的第六有源层16与第N+1单元行中行电路单元中的第七有源层17通过连接线18相互连接。
在示例性实施方式中，在第一方向X上，第二有源层12和第六有源层16可以位于本电路单元中第三有源层13的同一侧，第四有源层14和第五有 源层15可以位于本电路单元中第三有源层13的同一侧，第二有源层12和第四有源层14可以位于本电路单元的第三有源层13的不同侧。在第二方向Y上，第一有源层11、第二有源层12、第四有源层14和第七有源层17可以位于本电路单元中第三有源层13第二方向Y的反方向的一侧，第五有源层15和第六有源层16可以位于本电路单元中第三有源层13第二方向Y的一侧。
在示例性实施方式中，第一有源层11的形状可以呈“n”字形，第二有源层12和第五有源层15的形状可以呈“L”字形，第三有源层13的形状可以呈“Ω”字形，第四有源层14、第六有源层16和第七有源层17的形状可以呈“I”字形。
在示例性实施方式中，每个晶体管的有源层可以包括第一区、第二区以及位于第一区和第二区之间的沟道区。在示例性实施方式中，第一有源层的第一区11-1可以作为第七有源层的第一区17-1，第一有源层的第二区11-2可以作为第二有源层的第一区12-1，第三有源层的第一区13-1可以同时作为第四有源层的第二区14-2和第五有源层的第二区15-2，第三有源层的第二区13-2可以同时作为第二有源层的第二区12-2和第六有源层的第一区16-1，本电路单元中第六有源层的第二区16-2可以作为下一行电路单元中第七有源层的第二区17-2，第四有源层的第一区14-1和第五有源层的第一区15-1可以单独设置。
在示例性实施方式中，第一子线71在基底上的正投影与第一有源层11至第七有源层17在基底上的正投影没有交叠，第一子线71在基底上的正投影与连接线18在基底上的正投影至少部分交叠。
在示例性实施方式中，第二子线72在基底上的正投影与第三有源层13在基底上的正投影没有交叠，第二子线72在基底上的正投影与连接线18在基底上的正投影至少部分交叠。
(3)形成第一导电层图案。在示例性实施方式中，形成第一导电层图案可以包括：在形成前述图案的基底上，依次沉积第二绝缘薄膜和第一导电薄膜，通过图案化工艺对第一导电薄膜进行图案化，形成覆盖半导体层图案的第二绝缘层，以及设置在第二绝缘层上的第一导电层图案，如图16A和图16B所示，图16A为图6中B区域的平面结构示意图，图16B为图6中C区域 的平面结构示意图。在示例性实施方式中，第一导电层可以称为第一栅金属(GATE1)层。
在示例性实施方式中，显示区域中每个电路单元的第一导电层图案至少包括：第一扫描信号线21、第二扫描信号线22、发光控制线23和存储电容的第一极板24。
在示例性实施方式中，第一极板24的形状可以为矩形状，矩形状的角部可以设置倒角，第一极板24在基底上的正投影与第三晶体管T3的第三有源层在基底上的正投影至少部分交叠。在示例性实施方式中，第一极板24可以同时作为存储电容的一个极板和第三晶体管T3的栅电极。
在示例性实施方式中，第一扫描信号线21的形状可以为主体部分沿着第一方向X延伸的线形状，第一扫描信号线21可以位于本电路单元的第一极板24第二方向Y的反方向的一侧。每个电路单元的第一扫描信号线21设置有栅极块，栅极块的第一端与第一扫描信号线21连接，栅极块的第二端向着远离第一极板24的方向延伸。第一扫描信号线21和栅极块与本电路单元的第二有源层相重叠的区域作为双栅结构的第二晶体管T2的栅电极，第一扫描信号线21与本电路单元的第四有源层相重叠的区域作为第四晶体管T4的栅电极。
在示例性实施方式中，第二扫描信号线22的形状可以为主体部分沿着第一方向X延伸的线形状，第二扫描信号线22可以位于本电路单元的第一扫描信号线21远离第一极板24的一侧，第二扫描信号线22与本电路单元的第一有源层相重叠的区域作为双栅结构的第一晶体管T1的栅电极，第二扫描信号线22与本电路单元的第七有源层相重叠的区域作为第七晶体管T7的栅电极。
在示例性实施方式中，发光控制线23的形状可以为主体部分沿着第一方向X延伸的线形状，发光控制线23可以位于本电路单元的第一极板24第二方向Y的一侧，发光控制线23与本电路单元的第五有源层相重叠的区域作为第五晶体管T5的栅电极，发光控制线23与本电路单元的第六有源层相重叠的区域作为第六晶体管T6的栅电极。
在示例性实施方式中，第一扫描信号线21、第二扫描信号线22和发光 控制线23可以为等宽度设计，或者可以为非等宽度设计，可以为直线，或者可以为折线，不仅可以便于像素结构的布局，而且可以降低信号线之间的寄生电容，本公开在此不做限定。
在示例性实施方式中，第一子线71在基底上的正投影与第一扫描信号线21、第二扫描信号线22、发光控制线23和存储电容的第一极板24在基底上的正投影没有交叠，第二子线72在基底上的正投影与存储电容的第一极板24在基底上的正投影没有交叠。
在示例性实施方式中，形成第一导电层图案后，可以利用第一导电层作为遮挡，对半导体层进行导体化处理，被第一导电层遮挡区域的半导体层形成第一晶体管T1至第七晶体管T7的沟道区域，未被第一导电层遮挡区域的半导体层被导体化，即第一晶体管T1至第七有源层的第一区和第二区均被导体化。
(4)形成第一搭接过孔图案。在示例性实施方式中，形成第一搭接过孔图案可以包括：在形成前述图案的基底上，沉积第三绝缘薄膜，采用图案化工艺对第三绝缘薄膜进行图案化，形成覆盖第一导电层的第三绝缘层，第三绝缘层上形成多个第一搭接过孔DV1，如图17A和图17B所示，图17A为图6中B区域的平面结构示意图，图17B为图6中C区域的平面结构示意图。
在示例性实施方式中，多个第一搭接过孔DV1可以设置在封装线FX远离显示区域100的一侧，即第一搭接过孔DV1可以设置在侧边框区310内的非封装区。
在示例性实施方式中，第一搭接过孔DV1在基底上的正投影可以位于第一连接块73在基底上的正投影的范围之内，第一搭接过孔DV1内的第三绝缘层、第二绝缘层、第一绝缘层、第二阻挡层和第二柔性层被去掉，暴露出第一连接块73的表面，第一搭接过孔DV1被配置为使后续形成的第二连接线通过该过孔与第一连接块73连接。
在示例性实施方式中，多个第一搭接过孔DV1可以位于一条沿着第二方向Y延伸的直线上，第一搭接过孔DV1的形状可以为如下任意一种或多种：三角形、矩形、五边形、六边形、圆形和椭圆形。
(5)形成第二导电层图案。在示例性实施方式中，形成第二导电层图案可以包括：在形成前述图案的基底上，沉积第二导电薄膜，采用图案化工艺对第二导电薄膜进行图案化，在第三绝缘层上形成第二导电层图案，如图18A和图18B所示，图18A为图6中B区域的平面结构示意图，图18B为图6中C区域的平面结构示意图。在示例性实施方式中，第二导电层可以称为第二栅金属(GATE2)层。
在示例性实施方式中，显示区域中每个电路单元的第二导电层图案至少包括：初始信号线31、存储电容的第二极板32和屏蔽电极33。
在示例性实施方式中，初始信号线31的形状可以为主体部分沿着第一方向X延伸的线形状，初始信号线31可以位于本电路单元的第二扫描信号线22远离第一扫描信号线21的一侧，初始信号线31被配置为与后续形成的第一晶体管T1的第一极(也是第七晶体管T7的第一极)连接。
在示例性实施方式中，第二极板32的轮廓可以为矩形状，矩形状的角部可以设置倒角，第二极板32在基底上的正投影与第一极板24在基底上的正投影至少部分交叠，第二极板32可以作为存储电容的另一个极板，第一极板24和第二极板32构成像素驱动电路的存储电容。
在示例性实施方式中，第二极板32上设置有开口，开口的形状可以为矩形状，可以位于第二极板32的中部，使第二极板32形成环形结构。开口暴露出覆盖第一极板24的第三绝缘层，且第一极板24在基底上的正投影包含开口在基底上的正投影。在示例性实施方式中，开口被配置为容置后续形成的第一过孔，第一过孔位于开口内并暴露出第一极板24，使后续形成的第一晶体管T1的第二极与第一极板24连接。
在示例性实施方式中，一个单元行中相邻两个子像素中的第二极板32可以通过极板连接线相互连接。在示例性实施方式中，由于每个电路单元中的第二极板32与后续形成的第一电源线连接，通过极板连接线将相邻电路单元的第二极板32形成相互连接的一体结构，一体结构的第二极板可以复用为电源信号线，可以保证一单元行中的多个第二极板具有相同的电位，有利于提高面板的均一性，避免显示基板的显示不良，保证显示基板的显示效果。
在示例性实施方式中，屏蔽电极33的形状可以为沿着第一方向X延伸 的直线状，屏蔽电极33可以设置在第一扫描信号线21和第二扫描信号线22之间，屏蔽电极33的第一端在基底上的正投影与第二有源层位于两个栅电极之间的部分在基底上的正投影至少部分交叠，屏蔽电极33的第二端在基底上的正投影与第一有源层的第二区在基底上的正投影至少部分交叠，屏蔽电极33与后续形成的第一电源线连接，被配置为屏蔽像素驱动电路的关键节点。
在示例性实施方式中，第二导电层图案还可以包括多条第二连接线80。第二连接线80的形状可以为主体部分沿着第二方向Y延伸的线形状，第二连接线80的第一端(远离显示区域100的端部)设置有第二连接块82，第二连接线80的第二端(位于显示区域100的端部)设置有第三连接块83。
在示例性实施方式中，第二连接块82和第三连接块83的形状可以为矩形状，第二连接块82通过第一搭接过孔DV1与第一连接块73连接，第三连接块83被配置为与后续形成的数据信号线连接。
在示例性实施方式中，多条第二连接线80的多个第二连接块82可以位于一条沿着第二方向Y延伸的直线上，多条第二连接线80的多个第三连接块83可以位于不同的单元列中，以分别连接不同单元列的数据信号线。
在示例性实施方式中，第二连接块82的面积可以小于第一连接块73的面积，第二连接块82在基底上的正投影可以位于第一连接块73在基底上的正投影的范围之内。
在示例性实施方式中，第二连接块82覆盖第一搭接过孔DV1内底部暴露出的第一连接块73以及覆盖第一搭接过孔DV1内侧壁暴露出的柔性层和多个无机层，且第二连接块82覆盖第一搭接过孔DV1外侧的第三绝缘层。
在示例性实施方式中，对于通过第一搭接过孔DV1相互连接的第一子线71和第二连接线80，第二连接线80在基底上的正投影与第一子线71在基底上的正投影至少部分交叠，形成第一子线71和第二连接线80的上下叠层走线，以降低传输数据信号的寄生电容。
在示例性实施方式中，第二连接线80在基底上的正投影可以位于第一子线71在基底上的正投影的范围之内。
在示例性实施方式中，位于第N-1行和第N行之间的子线组中的两条第 二连接线80之间的距离，可以等于位于第N+1行和第N+2行之间的子线组中的两条第二连接线80之间的距离。
在示例性实施方式中，第一子线71在基底上的正投影与初始信号线31、存储电容的第二极板32和屏蔽电极33在基底上的正投影没有交叠，第二连接线80在基底上的正投影与初始信号线31、存储电容的第二极板32和屏蔽电极33在基底上的正投影没有交叠，第二子线72在基底上的正投影与存储电容的第二极板32在基底上的正投影没有交叠。
(6)形成第四绝缘层图案。在示例性实施方式中，形成第四绝缘层图案可以包括：在形成前述图案的基底上，沉积第四绝缘薄膜，采用图案化工艺对第四绝缘薄膜进行图案化，形成覆盖第二导电层的第四绝缘层，第四绝缘层上设置有多个过孔，如图19A和图19B所示，图19A为图6中B区域的平面结构示意图，图19B为图6中C区域的平面结构示意图。
在示例性实施方式中，显示区域中每个电路单元的多个过孔至少包括：第一过孔V1、第二过孔V2、第三过孔V3、第四过孔V4、第五过孔V5、第六过孔V6、第七过孔V7、第八过孔V8和第九过孔V9。
在示例性实施方式中，第一过孔V1在基底上的正投影位于开口在基底上的正投影的范围之内，第一过孔V1内的第四绝缘层和第三绝缘层被刻蚀掉，暴露出第一极板24的表面，第一过孔V1被配置为使后续形成的第一晶体管T1的第二极(也是第二晶体管T2的第一极)通过该过孔与第一极板24连接。
在示例性实施方式中，第二过孔V2在基底上的正投影位于第二极板32在基底上的正投影的范围之内，第二过孔V2内的第四绝缘层被刻蚀掉，暴露出第二极板32的表面，第二过孔V2被配置为使后续形成的第一电源线通过该过孔与第二极板32连接。在示例性实施方式中，第二过孔V2可以是多个，多个第二过孔V2可以沿着第二方向Y依次设置，以提高连接可靠性。
在示例性实施方式中，第三过孔V3在基底上的正投影位于第五有源层的第一区在基底上的正投影的范围之内，第三过孔V3内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第五有源层的第一区的表面，第三过孔V3被配置为使后续形成的第一电源线通过该过孔与第五有源层的第一 区连接。
在示例性实施方式中，第四过孔V4在基底上的正投影位于第六有源层的第二区(也是第七有源层的第二区)在基底上的正投影的范围之内，第四过孔V4内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第六有源层的第二区的表面，第四过孔V4被配置为使后续形成的第六晶体管T6的第二极(也是第七晶体管T7的第二极)通过该过孔与第六有源层的第二区连接。
在示例性实施方式中，第五过孔V5在基底上的正投影位于第四有源层的第一区在基底上的正投影的范围之内，第五过孔V5内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第四有源层的第一区的表面，第五过孔V5被配置为使后续形成的数据信号线通过该过孔与第四有源层的第一区连接。
在示例性实施方式中，第六过孔V6在基底上的正投影位于第一有源层的第二区(也是第二有源层的第一区)在基底上的正投影的范围之内，第六过孔V6内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第一有源层的第二区的表面，第六过孔V6被配置为使后续形成的第一晶体管T1的第二极(也是第二晶体管T2的第一极)通过该过孔与第一有源层的第二区(也是第二有源层的第一区)连接。
在示例性实施方式中，第七过孔V7在基底上的正投影位于第一有源层的第一区(也是第七有源层的第一区)在基底上的正投影的范围之内，第七过孔V7内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出的第一有源层的第一区表面，第七过孔V7被配置为使后续形成的第一晶体管T1的第一极(也是第七晶体管T7的第一极)通过该过孔与第一有源层的第一区(也是第七有源层的第一区)连接。
在示例性实施方式中，第八过孔V8在基底上的正投影位于初始信号线31在基底上的正投影的范围之内，第八过孔V8内的第四绝缘层被刻蚀掉，暴露出初始信号线31的表面，第八过孔V8被配置为使后续形成的第一晶体管T1的第一极(也是第七晶体管T7的第一极)通过该过孔与初始信号线31连接。
在示例性实施方式中，第九过孔V9在基底上的正投影位于屏蔽电极33在基底上的正投影的范围之内，第九过孔V9内的第四绝缘层被刻蚀掉，暴露出屏蔽电极33的表面，第九过孔V9被配置为使后续形成的第一电源线通过该过孔与屏蔽电极33连接。在示例性实施方式中，第九过孔V9可以是多个，多个第九过孔V9可以沿着第二方向Y依次设置，以提高连接可靠性。
在示例性实施方式中，第四绝缘层还可以设置有多个第二搭接过孔DV2，多个第二搭接过孔DV2可以设置在部分电路单元中。第二搭接过孔DV2在基底上的正投影位于第二连接线80的第三连接块83在基底上的正投影的范围之内，第二搭接过孔DV2内的第四绝缘层被刻蚀掉，暴露出第三连接块83的表面，第二搭接过孔DV2被配置为使后续形成的数据信号线通过该过孔与第二连接线80连接。
在示例性实施方式中，位于第N-1行和第N行之间的子线组中的两个第二搭接过孔DV2之间的距离，可以等于位于第N+1行和第N+2行之间的子线组中的两个第二搭接过孔DV2之间的距离。
在示例性实施方式中，由于多个第一搭接过孔DV1设置在侧边框区，多个第二搭接过孔DV2设置在显示区域，因而第二搭接过孔DV2在基底上的正投影与第一搭接过孔在基底上的正投影没有交叠。
(7)形成第三导电层图案。在示例性实施方式中，形成第三导电层可以包括：在形成前述图案的基底上，沉积第三导电薄膜，采用图案化工艺对第三导电薄膜进行图案化，形成设置在第四绝缘层上的第三导电层，如图20A和图20B所示，图20A为图6中B区域的平面结构示意图，图20B为图6中C区域的平面结构示意图。在示例性实施方式中，第三导电层可以称为第一源漏金属(SD1)层。
在示例性实施方式中，显示区域中每个电路单元的第三导电层至少包括：第一连接电极41、第二连接电极42、第三连接电极43、第一电源线44和数据信号线60。
在示例性实施方式中，第一连接电极41的形状可以为主体部分沿着第二方向Y延伸的条形状，第一连接电极41的第一端通过第一过孔V1与第一极板24连接，第一连接电极41的第二端通过第六过孔V6与第一有源层的第 二区(也是第二有源层的第一区)连接，使第一极板24、第一有源层的第二区和第二有源层的第一区具有相同的电位。在示例性实施方式中，第一连接电极41可以同时作为第一晶体管T1的第二极和第二晶体管T2的第一极。
在示例性实施方式中，第二连接电极42的形状可以为主体部分沿着第二方向Y延伸的条形状，第二连接电极42的第一端通过第八过孔V8与初始信号线31连接，第二连接电极42的第二端通过第七过孔V7与第一有源层的第一区(也是第七有源层的第一区)连接。在示例性实施方式中，第二连接电极42可以同时作为第一晶体管T1的第一极和第七晶体管T7的第一极。
在示例性实施方式中，第三连接电极43的形状可以为块形状，第三连接电极43通过第四过孔V4与第六有源层的第二区(也是第七有源层的第二区)连接。在示例性实施方式中，第三连接电极43可以同时作为第六晶体管T6的第二极和第七晶体管T7的第二极，第三连接电极43可以作为阳极连接电极，被配置为与后续形成的阳极连接。在示例性实施方式中，各个电路单元的第三连接电极43的形状可以不同，以连接对应的阳极。
在示例性实施方式中，第一电源线44的形状可以为主体部分沿着第二方向Y延伸的直线状，一方面，第一电源线44通过第二过孔V2与第二极板32连接，另一方面，第一电源线44通过第三过孔V3与第五有源层的第一区连接，又一方面，第一电源线44通过第九过孔V9与屏蔽电极33连接，实现了将电源信号写入第五晶体管T5的第一极，且第二极板32、屏蔽电极33和第五晶体管T5的第一极具有相同的电位。
在示例性实施方式中，数据信号线60的形状可以为主体部分沿着第二方向Y延伸的直线状，数据信号线60通过第五过孔V5与第四有源层的第一区连接，实现了将数据信号写入第四晶体管T4的第一极。
在示例性实施方式中，每个单元列的数据信号线60还通过第二搭接过孔DV2与第二连接线80连接。由于第二连接线80通过第一搭接过孔与第一连接线70连接，因而实现了显示区域100的数据信号线60通过第一连接线70和第二连接线80与绑定区域的引出线的连接。
在示例性实施方式中，第一子线71在基底上的正投影与第一连接电极41、第二连接电极42和第三连接电极43在基底上的正投影没有交叠，第二 连接线80在基底上的正投影与第一连接电极41、第二连接电极42和第三连接电极43在基底上的正投影没有交叠。
在示例性实施方式中，至少一条第二子线72在基底上的正投影与数据信号线60在基底上的正投影至少部分交叠，至少一条第二子线72在基底上的正投影与第一连接电极41和第二连接电极42在基底上的正投影没有交叠。
后续制备工艺中，可以包括形成第一平坦层等工艺，在玻璃载板上制备完成驱动电路层。
在示例性实施方式中，在平行于显示基板的平面上，显示区域的驱动电路层可以包括多个电路单元，每个电路单元可以包括像素驱动电路，像素驱动电路分别与第一扫描信号线21、第二扫描信号线22、发光控制线23、初始信号线31、第一电源线44和数据信号线60连接。显示区域和侧边框区的驱动电路层还可以包括多条第一连接线70和多条第二连接线80，数据信号线60通过第二搭接过孔DV2与第二连接线80，第二连接线80通过第一搭接过孔DV1与第一连接线70连接。
在示例性实施方式中，在垂直于显示基板的平面上，驱动电路层可以设置在基底上。基底可以包括叠设的第一柔性层10A、第一阻挡层10B、基底导电层、第二柔性层10C和第二阻挡层10D，基底导电层可以至少包括位于显示区域和侧边框区的第一连接线70(相互连接的第一子线和第二子线)。驱动电路层可以至少包括在基底上依次设置的第一绝缘层、半导体层、第二绝缘层、第一导电层、第三绝缘层、第二导电层、第四绝缘层和第三导电层。半导体层可以至少包括第一晶体管至第七晶体管的有源层，第一导电层可以至少包括第一扫描信号线21、第二扫描信号线22、发光控制线23和存储电容的第一极板24，第二导电层可以至少包括初始信号线31、存储电容的第二极板32、屏蔽电极33和第二连接线80，第二连接线80通过第一搭接过孔DV1与第一连接线70连接。第三导电层可以至少包括第一连接电极41、第二连接电极42、第三连接电极43、第一电源线44和数据信号线60，数据信号线60通过第二搭接孔DV2与第二连接线80连接。
在示例性实施方式中，第一导电层、第二导电层和第三导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或 多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。第一绝缘层可以称为缓冲(Buffer)层，第二绝缘层和第三绝缘层可以称为栅绝缘(GI)层，第四绝缘层可以称为层间绝缘(ILD)层。半导体层可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩或者聚噻吩等材料，即本发明实施例适用于基于氧化物(Oxide)技术、硅技术或者有机物技术制造的薄膜晶体管。
在示例性实施方式中，制备完成驱动电路层后，可以在驱动电路层依次制备发光结构层和封装结构层。制备发光结构层可以包括：先形成阳极导电层，阳极导电层可以至少包括多个阳极图案。随后形成像素定义层，每个电路单元的像素定义层上设置有像素开口，像素开口内的像素定义层被去掉，暴露出所在电路单元的阳极。随后采用蒸镀或喷墨打印工艺形成有机发光层，然后在有机发光层上形成阴极。封装结构层可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可以采用无机材料，第二封装层可以采用有机材料，第二封装层设置在第一封装层和第三封装层之间，可以保证外界水氧无法进入发光结构层。
在示例性实施方式中，封装结构层可以形成在显示区域和边框区域，边框区域中的封装结构层可以位于封装线FX靠近显示区域的一侧。
图21为本公开示例性实施例第一重叠区的结构示意图。如图21所示，显示基板的边框区域可以至少包括发光起始信号(ESTV)线351、扫描起始信号(GSTV)线352、第一时钟信号(ECK)线361和第二时钟信号(ECB)线361，这些信号线的形状可以为沿着第二方向Y延伸的线形状，可以设置在栅极电路区。由于引线组中的第一子线71和第二连接线80为横向延伸的线形状，而发光起始信号线351、扫描起始信号线352、第一时钟信号线361和第二时钟信号线361为竖向延伸的线形状，因而第一子线71和第二连接线80会从发光起始信号线351、扫描起始信号线352、第一时钟信号线361和 第二时钟信号线361的下方穿过，第一子线71和第二连接线80在基底上的正投影与发光起始信号线351、扫描起始信号线352、第一时钟信号线361和第二时钟信号线361在基底上的正投影存在第一交叠区域。
在示例性实施方式中，在第一交叠区域，第一子线71在基底上的正投影与第二连接线80在基底上的正投影没有交叠。本公开通过在第一交叠区域设置第一子线与第二连接线不交叠，可以保证发光起始信号线351、扫描起始信号线352、第一时钟信号线361和第二时钟信号线361不会因为下方设置第一子线与第二连接线而存在较大爬坡，可以避免因爬坡处金属残留导致短路，提高工艺质量。
在示例性实施方式中，在第一交叠区域使得位于第一交叠区域的第一子线71与第二连接线80不交叠可以采用多种手段。例如，第一子线71和/或第二连接线80可以通过走线弯折方式相互避让。又如，第一子线71和/或第二连接线80可以通过将线宽变窄方式相互避让，本公开在此不做限定。
在示例性实施方式中，在第一交叠区域以外的侧边框区，对于传输相同数据信号的第一子线71和第二连接线80，第一子线71在基底上的正投影与第二连接线80在基底上的正投影至少部分交叠。
图22为本公开示例性实施例电阻补偿结构的结构示意图。在栅极电路区远离显示区域的一侧，如在隔离坝区，引线组中的第一子线和第二连接线可以设置有电阻补偿结构，电阻补偿结构被配置为减小第一子线和第二连接线的电阻，并可以调整因不同引线组中连接线长度不同导致的电阻差异。
如图22所示，以第二连接线80为例，电阻补偿结构81可以设置在第二连接线80第二方向Y的一侧，且电阻补偿结构81的两端分别与第二连接线80连接。
在示例性实施方式中，在示例性实施方式中，电阻补偿结构81可以与第二连接线80同层设置，或者可以与第二连接线80异层设置，电阻补偿结构81两端之间可以设置成直线形、折线状或者波浪状，本公开在此不做限定。
从以上描述的显示基板的结构以及制备过程可以看出，本公开提供的显示基板，通过在基底的双柔性层之间设置基底导电层，基底导电层包括第一 连接线，第一连接线通过第二连接线与数据信号线连接，在显示区域实现了数据走线，可以缩减下边框宽度，有利于实现全面屏显示。
一种采用FIAA结构的显示基板中，实现第一连接线与第二连接线连接的第一搭接过孔设置在上边框区。研究表明，由于该方案的走线较长，使得传输数据信号的路径增大2倍，不仅负载较大，而且数据信号的上升沿/下降沿很大，不利于实现高刷新频率。本公开示例性实施例提供的显示基板，通过将第一搭接过孔、第二搭接过孔、第一连接线和第二连接线设置在靠近绑定区域的一侧，相比于第二搭接过孔设置在上边框区，可以有效减少数据信号的传输路径，有效降低数据信号的负载，降低数据信号的上升沿/下降沿(Tr/Tf)，有利于实现高刷新频率的窄边框。此外，本公开通过将第一搭接过孔设置在隔离坝之外，可以有效保证开设第一搭接过孔的工艺质量，开设较深的第一搭接过孔对显示区域的膜层结构影响较小，占用空间小，生产成本低。本公开制备过程可以很好地与现有制备工艺兼容，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。
本公开前述所示结构及其制备过程仅仅是一种示例性说明，在示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺。例如，显示基板可以包括遮挡导电层。又如，第二连接线可以设置在遮挡导电层或者第一导电层中，本公开在此不做限定。
在示例性实施方式中，本公开显示基板可以应用于具有像素驱动电路的其它显示装置中，如量子点显示等，本公开在此不做限定。
本公开还提供一种显示基板的制备方法，以制作上述实施例提供的显示基板。在示例性实施方式中，所述显示基板包括显示区域、位于所述显示区域第一方向至少一侧的侧边框区和位于所述显示区域第二方向一侧的绑定区域，所述侧边框区至少包括第一边框区和第二边框区，所述第一边框区位于所述第二边框区靠近所述绑定区域的一侧，所述第一方向与所述第二方向交叉；所述制备方法可以包括：
形成基底，所述基底至少包括第一连接线；
在所述基底上形成驱动电路层，所述驱动电路层至少包括数据信号线和 第二连接线，所述第二连接线通过第一搭接过孔与所述第一连接线连接，所述数据信号线通过第二搭接过孔与所述第二连接线连接，所述第一搭接过孔设置在所述第一边框区。
本公开还提供一种显示装置，显示装置包括前述的显示基板。显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，本公开在此不做限定。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本发明。任何所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (21)

  1. 一种显示基板，包括显示区域、位于所述显示区域第一方向至少一侧的侧边框区和位于所述显示区域第二方向一侧的绑定区域，所述侧边框区至少包括第一边框区和第二边框区，所述第一边框区位于所述第二边框区靠近所述绑定区域的一侧，所述第一方向与所述第二方向交叉；所述显示基板包括基底和设置在所述基底上的驱动电路层，所述基底至少包括第一连接线，所述驱动电路层至少包括数据信号线和第二连接线，所述第二连接线通过第一搭接过孔与所述第一连接线连接，所述数据信号线通过第二搭接过孔与所述第二连接线连接，所述第一搭接过孔设置在所述第一边框区。
  2. 根据权利要求1所述的显示基板，其中，所述显示基板包括第一中心线，所述第一中心线为在所述第二方向上平分所述显示区域且沿着所述第一方向延伸的直线，所述第一边框区位于所述第一中心线靠近所述绑定区域的一侧，所述第一连接线和第二连接线位于所述第一中心线靠近所述绑定区域的一侧。
  3. 根据权利要求2所述的显示基板，其中，所述显示基板包括第二中心线，所述第二中心线为在所述第一方向上平分所述显示区域且沿着所述第二方向延伸的直线；沿着远离所述第一中心线的方向，多个第二搭接过孔与所述第二中心线之间的距离逐渐增加，沿着远离所述第二中心线的方向，多个第二搭接过孔与所述第一中心线之间的距离逐渐增加；或者，沿着远离所述第一中心线的方向，多个第二搭接过孔与所述第二中心线之间的距离逐渐减小，沿着远离所述第二中心线的方向，多个第二搭接过孔与所述第一中心线之间的距离逐渐减小。
  4. 根据权利要求1所述的显示基板，其中，所述绑定区域至少包括引出线，所述引出线的第一端与所述绑定区域中的集成电路对应连接，所述引出线的第二端与所述第一连接线的第一端连接，所述第一连接线的第二端从所述绑定区域经过所述显示区域延伸到所述第一边框区后，通过所述第一搭接过孔与所述第二连接线的第一端连接，所述第二连接线的第二端从所述第一边框区延伸到所述显示区域后，通过所述第二搭接过孔与所述数据信号线连接。
  5. 根据权利要求1所述的显示基板，其中，所述侧边框区包括由封装线划分的封装区和非封装区，所述封装线是封装结构层覆盖所述侧边框区的边界，所述封装区设置在所述封装线靠近所述显示区域的一侧，所述非封装区设置在所述封装线远离所述显示区域的一侧，所述第一搭接过孔设置在所述非封装区。
  6. 根据权利要求1所述的显示基板，其中，所述驱动电路层至少包括在所述基底上依次设置的第一导电层、第二导电层和第三导电层，所述第二连接线设置在所述第一导电层或者所述第二导电层中，所述数据信号线设置在所述第三导电层中。
  7. 根据权利要求1至6任一项所述的显示基板，其中，所述第一连接线至少包括第一子线和第二子线，所述第二子线的第一端与所述绑定区域的引出线连接，所述第二子线的第二端沿着所述第二方向延伸到所述显示区域后，与所述第一子线的第一端连接，所述第一子线的第二端沿着所述第一方向延伸到所述第一边框区后，通过所述第一搭接过孔与所述第二连接线的第一端连接。
  8. 根据权利要求7所述的显示基板，其中，在所述显示区域，对于传输相同数据信号的第一子线和第二连接线，所述第一子线在所述基底上的正投影与所述第二连接线在所述基底上的正投影至少部分交叠。
  9. 根据权利要求7所述的显示基板，其中，沿着所述第二方向，多条第二连接线的延伸长度逐渐增加，或者，所述第二连接线的延伸长度逐渐减小。
  10. 根据权利要求7所述的显示基板，其中，所述驱动电路层包括构成多个单元行和多个单元列的电路单元，至少一个电路单元包括像素驱动电路，至少一个像素驱动电路包括存储电容和多个晶体管，所述第一连接线和第二连接线在所述基底上的正投影与所述存储电容和多个晶体管在所述基底上的正投影没有交叠。
  11. 根据权利要求7所述的显示基板，其中，所述显示基板包括多个引线组，至少一个引线组包括k条第一子线和通过k个第一搭接过孔与k条第一子线对应连接的k条第二连接线，k条第二连接线通过k个第二搭接过孔 与k条数据信号线对应连接，k为大于或等于1的正整数；在所述显示区域，至少一个引线组设置在相邻的单元行之间。
  12. 根据权利要求11所述的显示基板，其中，沿着所述第二方向，第i引线组与第i+1引线组之间的距离，等于第i+1引线组与第i+2引线组之间的距离，i为大于或等于1、小于或等于N-2的正整数，N为引线组的数量。
  13. 根据权利要求12所述的显示基板，其中，k为2，第i引线组中两个第二搭接过孔之间的间距，等于第i+1引线组中两个第二搭接过孔之间的间距。
  14. 根据权利要求11所述的显示基板，其中，所述侧边框区至少包括栅极电路区，所述栅极电路区包括沿着所述第二方向依次设置的多个栅极电路组，相邻的栅极电路组之间设置有走线区，在所述侧边框区，至少一个引线组设置在所述走线区；至少一个栅极电路组包括沿着所述第二方向依次设置的m个扫描栅极电路和沿着所述第二方向依次设置的n个发光栅极电路，所述n个发光栅极电路设置在所述m个扫描栅极电路远离所述显示区域的一侧，m为大于或等于2的正整数，n为大于或等于1的正整数。
  15. 根据权利要求14所述的显示基板，其中，至少一个扫描栅极电路包括多个扫描晶体管和扫描存储电容，至少一个发光栅极电路包括多个发光晶体管和发光存储电容，至少一个引线组中，所述第一子线和第二连接线在所述基底上的正投影与所述扫描晶体管、扫描存储电容、发光晶体管和发光存储电容在所述基底上的正投影没有交叠。
  16. 根据权利要求14所述的显示基板，其中，所述栅极电路区还包括沿着所述第二方向延伸的至少一条起始信号线和至少一条时钟信号线，至少一个引线组中，所述第一子线和第二连接线在所述基底上的正投影与所述起始信号线和时钟信号线在基底上的正投影存在第一交叠区域。
  17. 根据权利要求16所述的显示基板，其中，在所述第一交叠区域，所述第一子线在所述基底上的正投影与所述第二连接线在所述基底上的正投影没有交叠。
  18. 根据权利要求17所述的显示基板，其中，在所述第一交叠区域以 外的所述侧边框区，对于传输相同数据信号的第一子线和第二连接线，所述第一子线在所述基底上的正投影与所述第二连接线在所述基底上的正投影至少部分交叠。
  19. 根据权利要求11所述的显示基板，其中，至少一条第一子线或者至少一条第二连接线设置有电阻补偿结构，所述电阻补偿结构设置在所述栅极电路区远离所述显示区域的一侧。
  20. 一种显示装置，包括如权利要求1至19任一项所述的显示基板。
  21. 一种显示基板的制备方法，所述显示基板包括显示区域、位于所述显示区域第一方向至少一侧的侧边框区和位于所述显示区域第二方向一侧的绑定区域，所述侧边框区至少包括第一边框区和第二边框区，所述第一边框区位于所述第二边框区靠近所述绑定区域的一侧，所述第一方向与所述第二方向交叉；所述制备方法包括：
    形成基底，所述基底至少包括第一连接线；
    在所述基底上形成驱动电路层，所述驱动电路层至少包括数据信号线和第二连接线，所述第二连接线通过第一搭接过孔与所述第一连接线连接，所述数据信号线通过第二搭接过孔与所述第二连接线连接，所述第一搭接过孔设置在所述第一边框区。
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CN113299220A (zh) * 2021-06-03 2021-08-24 厦门天马微电子有限公司 显示面板及其装置、驱动方法
CN114497151A (zh) * 2022-01-12 2022-05-13 武汉华星光电半导体显示技术有限公司 一种显示面板
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