WO2022160491A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

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Publication number
WO2022160491A1
WO2022160491A1 PCT/CN2021/091421 CN2021091421W WO2022160491A1 WO 2022160491 A1 WO2022160491 A1 WO 2022160491A1 CN 2021091421 W CN2021091421 W CN 2021091421W WO 2022160491 A1 WO2022160491 A1 WO 2022160491A1
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data
line
lines
lead
area
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PCT/CN2021/091421
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English (en)
French (fr)
Inventor
杜丽丽
徐元杰
王琦伟
王本莲
程羽雕
徐攀
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to US17/627,808 priority Critical patent/US20230157099A1/en
Priority to EP21922089.4A priority patent/EP4123715A4/en
Priority to CN202180001050.XA priority patent/CN115244706A/zh
Publication of WO2022160491A1 publication Critical patent/WO2022160491A1/zh

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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
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    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
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    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
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    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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Definitions

  • the present disclosure relates to, but is not limited to, the field of display technology, and more particularly, to a display substrate, a method for manufacturing the same, and a display device.
  • OLED Organic Light Emitting Diode
  • TFTs thin film transistors
  • an exemplary embodiment of the present disclosure provides a display substrate including a display area and a binding area on one side of the display area, the binding area at least including a lead area;
  • the display area includes a plurality of pieces of data line and a plurality of data fan-out lines
  • the lead area includes a plurality of lead-out lines, the orthographic projections of the plurality of data lines and the plurality of data fan-out lines on the plane of the display substrate at least partially overlap;
  • the first end of the at least one data fan-out line is The lead wire is connected, and the second end extends in a direction away from the lead area and is connected to the data wire.
  • the number of the data fanout lines is the same as the number of the data lines.
  • the display substrate in a plane parallel to a display substrate, has a first centerline that extends along a first direction and bisects a pixel column of the display area, the The first direction is parallel to the data line; on one side of the first center line, the plurality of data lines include a first data line and a second data line arranged in sequence along the second direction or the opposite direction of the second direction line, ..., the Nth data line, the second direction intersects the first direction; the plurality of data fan-out lines include a first data fan-out line, a first data fan-out line, a The second data fan-out line, ..., the Nth data fan-out line; the plurality of lead-out lines include a first lead-out line, a second lead-out line, ..., which are sequentially arranged along the second direction or the opposite direction of the second direction.
  • the Nth lead-out line; the orthographic projection of any data fan-out line on the display substrate plane has no overlapping area with the orthographic projection of other data fan-out lines on the display substrate plane; the orthographic projection of any lead-out line on the display substrate plane and other lead-out lines
  • the orthographic projection of the lines on the plane of the display substrate has no overlapping area; N is the number of data lines in the display area.
  • At least one data fan-out line includes a first line segment and a second line segment; a first end of the first line segment is connected to the outgoing line, and a second end of the first line segment is along the After extending in the second direction or the opposite direction of the second direction, it is connected with the first end of the second line segment; after the second end of the second line segment is extended in the direction away from the lead area, it is connected with the The data lines are connected; the second direction intersects with the first direction, and the first direction is parallel to the data lines.
  • the first line segment includes a lead-out segment and a first extension segment; a first end of the lead-out segment is connected to the lead-out line, and a second end of the lead-out segment faces a distance away from the lead region. After extending in the direction, it is connected with the first end of the first extension segment; after the second end of the first extension segment is extended in the second direction or the opposite direction of the second direction, it is connected with the first end of the second line segment. One end is connected, and the spacing between adjacent lead-out segments is smaller than the spacing between adjacent data lines.
  • the widths of the plurality of lead lines in the lead area are the same, the distance between adjacent lead lines is the same, and the distance between adjacent lead lines is smaller than the distance between adjacent data lines.
  • the second line segment includes a second extension segment and a connecting segment; a first end of the second extension segment is connected with a second end of the first line segment, the second extension segment After the second end of the connecting segment extends in the direction away from the lead area, it is connected to the first end of the connecting segment; after the second end of the connecting segment extends along the second direction or the opposite direction of the second direction, it passes through the via hole connected with the data line.
  • the display substrate in a plane parallel to the display substrate, has a second centerline that extends along the second direction and bisects pixel rows of the display area;
  • the via hole connecting any data fan-out line to the data line has a distance L1 from the second center line, and the distance L1 satisfies:
  • the length and distance are dimensions in the first direction.
  • a plurality of vias connecting the data fan-out lines to the data lines are located on the second center line.
  • any data fan-out line has an extension length L2 in the display area, and the extension length L2 satisfies:
  • L2i is the extension length of one data fan-out line in the display area
  • L2j is the extension length of another data fan-out line in the display area
  • the extension length of the data fan-out line is the extension of the first line segment The sum of the length and the extension length of the second line segment.
  • a plurality of via holes connecting the data fan-out lines and the data lines have different distances from the second center line.
  • the display substrate in a plane perpendicular to the display substrate, includes a first conductive layer, a second conductive layer, and a third conductive layer, and the first conductive layer and the second conductive layer are between the first conductive layer and the second conductive layer.
  • An insulating layer is provided between the second conductive layer and the third conductive layer; the data line and the data fan-out line are provided in different conductive layers.
  • the data fan-out lines include an odd-numbered data fan-out line and an even-numbered data fan-out line, the odd-numbered data fan-out lines are connected to data lines of odd-numbered columns, and the even-numbered data fan-out lines are connected to data lines of even-numbered columns ;
  • the odd-numbered data fan-out lines and the even-numbered data fan-out lines are arranged in different conductive layers.
  • the pinout includes an odd pinout and an even pinout, the odd pinout is connected to a data line of an odd column through the odd data fanout, and the even pinout passes through the even data
  • the fan-out lines are connected with the data lines of the even-numbered columns; the odd-numbered lead-out lines and the odd-numbered data fan-out lines are arranged on the same layer and are interconnected in an integrated structure, and the even-numbered lead-out lines are arranged on the same layer as the even-numbered data fan-out lines, And it is an integrated structure that is connected to each other.
  • the odd-numbered data fan-out lines are disposed in the first conductive layer, the even-numbered data fan-out lines are disposed in the second conductive layer, and the data lines are disposed in the third conductive layer;
  • the even-numbered data fan-out lines are arranged on the first conductive layer, the odd-numbered data fan-out lines are arranged on the second conductive layer, and the data lines are arranged on the third conductive layer; the first conductive layer
  • the material of the layer is the same as that of the second conductive layer.
  • the display substrate in a plane parallel to the display substrate, includes a plurality of pixel islands, and the pixel islands include a plurality of sub-pixels; in a plane perpendicular to the display substrate, the sub-pixels include an arrangement of A driving circuit layer on the substrate and a light-emitting structure layer disposed on the side of the driving circuit layer away from the substrate, the driving circuit layer includes a pixel driving circuit, and the light-emitting structure layer includes a light-emitting device connected to the pixel driving circuit ;
  • At least one pixel island includes a circuit sub-region and a wiring sub-region, wherein the circuit sub-region is provided with pixel driving circuits of a plurality of sub-pixels in the pixel island, and the data fan-out line is provided in the wiring sub-region.
  • the orthographic projection of the at least one light emitting device in the pixel island on the plane of the display substrate and the orthographic projection of the data fan-out line on the plane of the display substrate have an overlapping area.
  • a virtual fan-out line is further provided in the wiring sub-region.
  • an exemplary embodiment of the present disclosure also provides a display device including the aforementioned display substrate.
  • an exemplary embodiment of the present disclosure also provides a method for manufacturing a display substrate, the display substrate includes a display area and a binding area on one side of the display area, the binding area at least includes a lead area ; Described preparation method comprises:
  • a plurality of data lines and a plurality of data fan-out lines are formed in the display area, a plurality of lead-out lines are formed in the lead area, and the orthographic projections of the plurality of data lines and the plurality of data fan-out lines on the display substrate plane at least partially overlap;
  • the first end of at least one data fan-out line is connected to the lead-out line, and the second end extends in a direction away from the lead area and is connected to the data line.
  • 1 is a schematic structural diagram of a display device
  • FIG. 2 is a schematic plan view of a display substrate
  • FIG. 3 is a schematic plan view of a display area in a display substrate
  • FIG. 4 is a schematic cross-sectional structure diagram of a display region in a display substrate
  • FIG. 5 is a schematic diagram of an equivalent circuit of a pixel driving circuit
  • FIG. 6 is a working timing diagram of a pixel driving circuit
  • FIG. 7 is a schematic plan view of a binding area in a display substrate
  • FIG. 8 is a schematic diagram of a data fanout line in a binding area
  • FIG. 9 is a schematic plan view of a display substrate according to an exemplary embodiment of the present disclosure.
  • FIG. 10 is a side view of the substrate shown in FIG. 9;
  • FIG. 11 is a schematic structural diagram of a lead-out line and a data fan-out line according to an exemplary embodiment of the present disclosure
  • Figure 12 is an enlarged view of the C1 region in Figure 11;
  • Figure 13 is an enlarged view of the C2 region in Figure 11;
  • Figure 14 is a sectional view taken along the A-A direction in Figure 13;
  • 15 is a schematic structural diagram of another lead-out line and a data fan-out line according to an exemplary embodiment of the present disclosure
  • 16 is a schematic diagram of the arrangement of pixel islands in a display area according to an exemplary embodiment of the present disclosure
  • FIG. 17 is a schematic diagram of a compressed arrangement in a pixel island according to an exemplary embodiment of the present disclosure.
  • 18a-18b are schematic diagrams of a compression arrangement according to an exemplary embodiment of the present disclosure.
  • Figures 19a-19b are schematic diagrams of another compression arrangement according to an exemplary embodiment of the present disclosure.
  • 20 and 21 are schematic diagrams of a data fan-out line arrangement according to an exemplary embodiment of the present disclosure.
  • 100 display area
  • 101 substrate
  • 102 drive circuit layer
  • 102A transistor
  • 102B storage capacitor
  • 110 first wiring area
  • 202 bending area
  • 203 second fan-out area
  • 204 anti-static area
  • 301 anode
  • 302 pixel definition layer
  • 303 organic light-emitting layer
  • 304 cathode
  • 401 first encapsulation layer
  • 402 second encapsulation layer
  • 403 the third packaging layer; 500—binding area; 501—lead area;
  • 502 bending area
  • 503 composite circuit area
  • 600 lead wire
  • 700 data fanout line
  • 750 virtual fanout line
  • the terms “installed”, “connected” and “connected” should be construed in a broad sense. For example, it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • installed should be construed in a broad sense. For example, it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
  • a transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode .
  • the channel region refers to a region through which current mainly flows.
  • the first electrode may be the drain electrode and the second electrode may be the source electrode, or the first electrode may be the source electrode and the second electrode may be the drain electrode.
  • the functions of the "source electrode” and the “drain electrode” may be interchanged when using transistors of opposite polarities or when the direction of the current changes during circuit operation. Therefore, in this specification, “source electrode” and “drain electrode” may be interchanged with each other.
  • electrically connected includes the case where constituent elements are connected together by means of elements having some electrical function.
  • the "element having a certain electrical effect” is not particularly limited as long as it can transmit and receive electrical signals between the connected constituent elements.
  • Examples of “elements having a certain electrical effect” include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having various functions, and the like.
  • parallel refers to a state where the angle formed by two straight lines is -10° or more and 10° or less, and therefore includes a state where the angle is -5° or more and 5° or less.
  • perpendicular refers to the state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore includes the state where the angle is 85° or more and 95° or less.
  • film and “layer” are interchangeable.
  • conductive layer may be replaced by “conductive film” in some cases.
  • insulating film may be replaced with “insulating layer” in some cases.
  • FIG. 1 is a schematic structural diagram of a display device.
  • the OLED display device may include a timing controller, a data signal driver, a scan signal driver, a light-emitting signal driver, and a pixel array
  • the pixel array may include a plurality of scan signal lines (S1 to Sm), a plurality of data lines ( D1 to Dn), a plurality of light-emitting signal lines (E1 to Eo), and a plurality of sub-pixels Pxij.
  • the timing controller may supply a grayscale value and a control signal suitable for the specification of the data signal driver to the data signal driver, and may supply a clock signal, a scan start signal, etc., suitable for the specification of the scan signal driver When supplied to the scan signal driver, a clock signal, an emission stop signal, and the like suitable for the specifications of the light-emitting signal driver can be supplied to the light-emitting signal driver.
  • the data signal driver may generate data voltages to be supplied to the data lines D1 , D2 , D3 , . . . and Dn using the grayscale values and control signals received from the timing controller.
  • the data signal driver may sample grayscale values using a clock signal, and apply data voltages corresponding to the grayscale values to the data lines D1 to Dn in pixel row units, where n may be a natural number.
  • the scan signal driver may generate scan signals to be supplied to the scan signal lines S1 , S2 , S3 , . . . and Sm by receiving a clock signal, a scan start signal, and the like from the timing controller.
  • the scan signal driver may sequentially supply scan signals having on-level pulses to the scan signal lines S1 to Sm.
  • the scan signal driver may be constructed in the form of a shift register, and may generate scans in such a manner that a scan start signal supplied in the form of an on-level pulse is sequentially transmitted to the next stage circuit under the control of a clock signal signal, m can be a natural number.
  • the emission signal driver may generate emission signals to be supplied to the emission signal lines E1 , E2 , E3 , . . . and Eo by receiving a clock signal, an emission stop signal, and the like from the timing controller.
  • the emission signal driver may sequentially supply emission signals having off-level pulses to the emission signal lines E1 to Eo.
  • the light-emitting signal driver may be constructed in the form of a shift register, and may generate the light-emitting signal in such a manner that the light-emitting stop signal provided in the form of an off-level pulse is sequentially transmitted to the next stage circuit under the control of the clock signal, o can be a natural number.
  • the pixel array may include a plurality of sub-pixels Pxij, each sub-pixel Pxij may be connected to a corresponding data line, a corresponding scanning signal line and a corresponding light-emitting signal line, and i and j may be natural numbers.
  • the sub-pixel Pxij may refer to a sub-pixel in which a transistor is connected to the i-th scan signal line and to the j-th data line.
  • FIG. 2 is a schematic plan view of a display substrate.
  • the display substrate may include a display area 100 , a binding area 200 on one side of the display area 100 , and a frame area 300 on the other side of the display area 100 .
  • the display area 100 may include a plurality of sub-pixels configured to display dynamic pictures or still images
  • the binding area 200 may include data fan-out lines connecting a plurality of data lines to the integrated circuit
  • the border area 300 may include power lines for transmitting voltage signals
  • the binding area 200 and the frame area 300 may include isolation dams in a ring structure, at least one side of the frame area 300 may be a curled area formed by bending, or both the display area 100 and the frame area 300 may be bent or curved areas , the present disclosure is not limited herein.
  • the display area may include a plurality of pixel units arranged in a matrix.
  • FIG. 3 is a schematic plan view of a display area in a display substrate.
  • the display substrate may include a plurality of pixel units P arranged in a matrix, and at least one of the plurality of pixel units P includes a first sub-pixel P1 that emits light of a first color, and a first sub-pixel P1 that emits light of a second color.
  • the two sub-pixels P2 and the third sub-pixel P3 that emits light of the third color, the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 all include a pixel driving circuit and a light-emitting device.
  • the pixel driving circuits in the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 are respectively connected to the scanning signal line, the data line and the light-emitting signal line, and the pixel driving circuit is configured to connect between the scanning signal line and the light-emitting signal line.
  • the data voltage transmitted by the data line is received, and the corresponding current is output to the light-emitting device.
  • the light-emitting devices in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to the pixel driving circuit of the sub-pixel, and the light-emitting device is configured to respond to the current output by the pixel driving circuit of the sub-pixel. Brightness of light.
  • the pixel unit P may include red (R) sub-pixels, green (G) sub-pixels, and blue (B) sub-pixels, or may include red sub-pixels, green sub-pixels, and blue sub-pixels and white sub-pixels, which are not limited in this disclosure.
  • the shape of the sub-pixels in the pixel unit may be a rectangle, a diamond, a pentagon or a hexagon.
  • the pixel unit includes three sub-pixels, the three sub-pixels can be arranged horizontally, vertically, or in a zigzag manner.
  • the pixel unit includes four sub-pixels, the four sub-pixels can be arranged in a horizontal, vertical, or square manner. The arrangement is not limited in this disclosure.
  • FIG. 4 is a schematic cross-sectional structure diagram of a display area in a display substrate, illustrating the structure of three sub-pixels of an OLED display substrate.
  • the display substrate may include a driving circuit layer 102 disposed on the substrate 101 , a light emitting structure layer 103 disposed on the side of the driving circuit layer 102 away from the substrate 101 , and a light emitting structure layer 103 disposed on the light emitting
  • the structure layer 103 is away from the encapsulation layer 104 on the side of the substrate 101 .
  • the display substrate may include other film layers, such as spacer columns, etc., which are not limited in the present disclosure.
  • the substrate 101 may be a flexible substrate, or it may be a rigid substrate.
  • the driving circuit layer 102 of each sub-pixel may include a plurality of transistors and storage capacitors constituting the pixel driving circuit, and only one transistor 102A and one storage capacitor 102B are taken as an example in FIG. 4 .
  • the light-emitting structure layer 103 may include an anode 301, a pixel definition layer 302, an organic light-emitting layer 303, and a cathode 304.
  • the anode 301 is connected to the drain electrode of the driving transistor 210 through a via hole
  • the organic light-emitting layer 303 is connected to the anode 301
  • the cathode 304 is connected to the organic light-emitting
  • the layers 303 are connected, and the organic light-emitting layer 303 is driven by the anode 301 and the cathode 304 to emit light of the corresponding color.
  • the encapsulation layer 104 may include a stacked first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403.
  • the first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials, and the second encapsulation layer 402 may be made of organic materials.
  • the second encapsulation layer 402 is disposed between the first encapsulation layer 401 and the third encapsulation layer 403 to ensure that the outside water vapor cannot enter the light emitting structure layer 103 .
  • the organic light-emitting layer 303 may include a stacked hole injection layer (Hole Injection Layer, HIL for short), a hole transport layer (Hole Transport Layer, HTL for short), an electron blocking layer (Electron Block Layer, EBL), Emitting Layer (EML), Hole Block Layer (HBL), Electron Transport Layer (ETL) and Electron Injection Layer (EIL) .
  • HIL Hole Injection Layer
  • HTL Hole Transport Layer
  • EBL Electron Block Layer
  • EML Electron Transport Layer
  • EIL Electron Injection Layer
  • the hole injection layers of all subpixels may be a common layer connected together
  • the electron injection layers of all subpixels may be a common layer connected together
  • the hole transport layers of all subpixels may be A common layer connected together
  • the electron transport layer of all subpixels can be a common layer connected together
  • the hole blocking layer of all subpixels can be a common layer connected together
  • the light emitting layers of adjacent subpixels can have a small amount of The electron blocking layers of adjacent sub-pixels may overlap slightly, or may be isolated.
  • the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C or 7T1C structure.
  • FIG. 5 is a schematic diagram of an equivalent circuit of a pixel driving circuit.
  • the pixel driving circuit may include 7 transistors (first transistor T1 to seventh transistor T7 ), 1 storage capacitor C and 7 signal lines (data line D, first scan signal line S1 , second A scan signal line S2, a light emitting signal line E, an initial signal line INIT, a first power supply line VDD, and a second power supply line VSS).
  • the first end of the storage capacitor C is connected to the first power supply line VDD
  • the second end of the storage capacitor C is connected to the second node N2, that is, the second end of the storage capacitor C is connected to the third transistor T3 Control pole connection.
  • the control electrode of the first transistor T1 is connected to the second scan signal line S2, the first electrode of the first transistor T1 is connected to the initial signal line INIT, and the second electrode of the first transistor is connected to the second node N2.
  • the first transistor T1 transmits an initialization voltage to the gate of the third transistor T3 to initialize the charge amount of the gate of the third transistor T3.
  • the control electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3.
  • the second transistor T2 connects the control electrode of the third transistor T3 to the second electrode.
  • the control electrode of the third transistor T3 is connected to the second node N2, that is, the control electrode of the third transistor T3 is connected to the second end of the storage capacitor C, the first electrode of the third transistor T3 is connected to the first node N1, and the third transistor T3 is connected to the first node N1.
  • the second pole of T3 is connected to the third node N3.
  • the third transistor T3 may be referred to as a driving transistor, and the third transistor T3 determines the amount of driving current flowing between the first power supply line VDD and the second power supply line VSS according to the potential difference between its control electrode and the first electrode.
  • the control electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data line D, and the second electrode of the fourth transistor T4 is connected to the first node N1.
  • the fourth transistor T4 may be referred to as a switching transistor, a scan transistor, or the like, and enables the data voltage of the data line D to be input to the pixel driving circuit when an on-level scan signal is applied to the first scan signal line S1.
  • the control electrode of the fifth transistor T5 is connected to the light-emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1.
  • the control electrode of the sixth transistor T6 is connected to the light emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting device.
  • the fifth transistor T5 and the sixth transistor T6 may be referred to as light emitting transistors. When an on-level light emission signal is applied to the light emission signal line E, the fifth and sixth transistors T5 and T6 make the light emitting device emit light by forming a driving current path between the first power supply line VDD and the second power supply line VSS.
  • the control electrode of the seventh transistor T7 is connected to the first scan signal line S1, the first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting device.
  • the seventh transistor T7 transmits an initialization voltage to the first electrode of the light emitting device to initialize or discharge the amount of charge accumulated in the first electrode of the light emitting device to emit light The amount of charge accumulated in the first pole of the device.
  • the second pole of the light emitting device is connected to the second power supply line VSS, the signal of the second power supply line VSS is a low-level signal, and the signal of the first power supply line VDD is a continuous high-level signal.
  • the first scan signal line S1 is the scan signal line in the pixel driving circuit of the display row
  • the second scan signal line S2 is the scan signal line in the pixel driving circuit of the previous display row, that is, for the nth display row, the first scan signal
  • the line S1 is S(n)
  • the second scanning signal line S2 is S(n-1)
  • the second scanning signal line S2 of this display line is the same as the first scanning signal line S1 in the pixel driving circuit of the previous display line
  • the signal lines can reduce the signal lines of the display panel and realize the narrow frame of the display panel.
  • the first to seventh transistors T1 to T7 may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the product yield. In some possible implementations, the first to seventh transistors T1 to T7 may include P-type transistors and N-type transistors.
  • the first scan signal line S1, the second scan signal line S2, the light emitting signal line E and the initial signal line INIT extend in the horizontal direction
  • the second power supply line VSS, the first power supply line VDD and the data line D Extend vertically.
  • the light emitting device may be an organic electroluminescent diode (OLED) including a stacked first electrode (anode), an organic light emitting layer and a second electrode (cathode).
  • OLED organic electroluminescent diode
  • FIG. 6 is a working timing diagram of a pixel driving circuit. Exemplary embodiments of the present disclosure will be described below through the operation process of the pixel driving circuit illustrated in FIG. 5 .
  • the pixel driving circuit in FIG. 5 includes 7 transistors (the first transistor T1 to the sixth transistor T7 ), 1 storage capacitors C and 7 signal lines (data line D, first scanning signal line S1, second scanning signal line S2, light-emitting signal line E, initial signal line INIT, first power supply line VDD and second power supply line VSS), and the seven transistors are P-type transistor.
  • the working process of the pixel driving circuit may include:
  • the signal of the second scanning signal line S2 is a low-level signal, and the signals of the first scanning signal line S1 and the light-emitting signal line E are a high-level signal.
  • the signal of the second scanning signal line S2 is a low level signal, which turns on the first transistor T1, and the signal of the initial signal line INIT is supplied to the second node N2 to initialize the storage capacitor C and clear the original data voltage in the storage capacitor.
  • the signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals, so that the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are turned off. At this stage, the OLED Not glowing.
  • the second stage A2 is called the data writing stage or the threshold compensation stage.
  • the signal of the first scanning signal line S1 is a low-level signal
  • the signals of the second scanning signal line S2 and the light-emitting signal line E are a high-level signal
  • the data Line D outputs the data voltage.
  • the third transistor T3 is turned on.
  • the signal of the first scan signal line S1 is a low level signal, so that the second transistor T2, the fourth transistor T4 and the seventh transistor T7 are turned on.
  • the second transistor T2 and the fourth transistor T4 are turned on so that the data voltage output from the data line D is supplied to the second node through the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2 N2, and the difference between the data voltage output by the data line D and the threshold voltage of the third transistor T3 is charged into the storage capacitor C, and the voltage of the second end (second node N2) of the storage capacitor C is Vd-
  • the seventh transistor T7 is turned on so that the initial voltage of the initial signal line INIT is supplied to the first electrode of the OLED, initializes (resets) the first electrode of the OLED, clears the internal pre-stored voltage, completes the initialization, and ensures that the OLED does not emit light.
  • the signal of the second scanning signal line S2 is a high-level signal, so that the first transistor T1 is turned off.
  • the signal of the light-emitting signal line E is a high-level signal, so that the fifth transistor T5 and the sixth transistor T6 are turned off.
  • the third stage A3 is called the light-emitting stage, the signal of the light-emitting signal line E is a low-level signal, and the signals of the first scanning signal line S1 and the second scanning signal line S2 are high-level signals.
  • the signal of the light-emitting signal line E is a low-level signal, so that the fifth transistor T5 and the sixth transistor T6 are turned on, and the power supply voltage output by the first power line VDD passes through the fifth transistor T5, the third transistor T3 and the sixth transistor T5, which are turned on.
  • the transistor T6 provides a driving voltage to the first electrode of the OLED to drive the OLED to emit light.
  • the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the second node N2 is Vdata-
  • I is the driving current flowing through the third transistor T3, that is, the driving current for driving the OLED
  • K is a constant
  • Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3
  • Vth is the third transistor.
  • Vd is the data voltage output by the data line D
  • Vdd is the power supply voltage output by the first power line VDD.
  • FIG. 7 is a schematic plan view of a binding area in a display substrate
  • FIG. 8 is a schematic diagram of a data fan-out line in the binding area.
  • the binding area 200 in a plane parallel to the display substrate, is located on one side of the display area 100 , and the binding area 200 may include first fan-out areas 201 arranged in sequence along a direction away from the display area 100 . , a bending area 202 , a second fan-out area 203 , an anti-static area 204 , a driving chip area 205 and a bonding pin area 206 .
  • the first fan-out area 201 includes at least data fan-out lines, and a plurality of data fan-out lines are configured to connect data lines (Data Lines) of the display area in a fan-out (Fanout) routing manner, as shown in FIG. 8 .
  • the bending area 202 includes a composite insulating layer provided with grooves, and is configured to bend the binding area 200 to the back of the display area 100 .
  • the second fan-out area 203 includes a plurality of data fan-out lines drawn out in a fan-out routing manner.
  • the anti-static area 204 includes an anti-static circuit configured to prevent electrostatic damage to the display substrate by eliminating static electricity.
  • the driver chip area 205 includes an integrated circuit (Integrated Circuit, IC for short), which is configured to be connected with a plurality of data fan-out lines.
  • the bonding pin area 206 includes a bonding pad (Bonding Pad), which is configured to be bonded and connected to an external flexible printed circuit (Flexible Printed Circuit, FPC for short).
  • the left frame, right frame and upper frame of the display device can be controlled within 1.0mm, but the narrowing design of the lower frame (the frame on the side of the binding area) is relatively difficult and has been maintained at about 2.0mm. This is because the data fan-out line is usually set in the fan-out area of the binding area, and the fan-out area occupies a large space. Usually, the width of the binding area is smaller than the width of the display area.
  • the signal lines of the integrated circuits and the binding pads in the binding area need to be fan-out through the fan-out area to be introduced into the wider display area.
  • the display substrate includes a display area and a binding area on one side of the display area, the binding area includes at least a lead area;
  • the display area includes a plurality of data lines and a plurality of data fan-out lines
  • the lead area includes a plurality of lead lines, and the orthographic projections of the plurality of data lines and the plurality of data fan-out lines on the plane of the display substrate overlap at least partially;
  • the first end of at least one data fan-out line is connected to the lead line, and the first end of the at least one data fan-out line is connected to the lead line.
  • the two ends are extended in a direction away from the lead area and then connected to the data line.
  • the number of the data fanout lines is the same as the number of the data lines.
  • the display substrate in a plane parallel to a display substrate, has a first centerline that extends along a first direction and bisects a pixel column of the display area, the The first direction is parallel to the data line; on one side of the first center line, the plurality of data lines include a first data line and a second data line arranged in sequence along the second direction or the opposite direction of the second direction line, ..., the Nth data line, the second direction intersects the first direction; the plurality of data fan-out lines include a first data fan-out line, a first data fan-out line, a The second data fan-out line, ..., the Nth data fan-out line; the plurality of lead-out lines include a first lead-out line, a second lead-out line, ..., which are sequentially arranged along the second direction or the opposite direction of the second direction.
  • the Nth lead-out line; the orthographic projection of any data fan-out line on the display substrate plane has no overlapping area with the orthographic projection of other data fan-out lines on the display substrate plane; the orthographic projection of any lead-out line on the display substrate plane and other lead-out lines
  • the orthographic projection of the lines on the plane of the display substrate has no overlapping area; N is the number of data lines in the display area.
  • At least one data fan-out line includes a first line segment and a second line segment; a first end of the first line segment is connected to the outgoing line, and a second end of the first line segment is along the After extending in the second direction or the opposite direction of the second direction, it is connected with the first end of the second line segment; after the second end of the second line segment is extended in the direction away from the lead area, it is connected with the The data lines are connected; the second direction intersects with the first direction, and the first direction is parallel to the data lines.
  • the display substrate in a plane parallel to the display substrate, has a second centerline that extends along the second direction and bisects pixel rows of the display area;
  • the via hole connecting any data fan-out line to the data line has a distance L1 from the second center line, and the distance L1 satisfies:
  • the length and distance are dimensions in the first direction.
  • any data fan-out line has an extension length L2 in the display area, and the extension length L2 satisfies:
  • L2i is the extension length of one data fan-out line in the display area
  • L2j is the extension length of another data fan-out line in the display area
  • the extension length of the data fan-out line is the extension of the first line segment The sum of the length and the extension length of the second line segment.
  • the display substrate in a plane perpendicular to the display substrate, includes a first conductive layer, a second conductive layer, and a third conductive layer, and the first conductive layer and the second conductive layer are between the first conductive layer and the second conductive layer.
  • An insulating layer is provided between the second conductive layer and the third conductive layer; the data line and the data fan-out line are provided in different conductive layers.
  • the display substrate in a plane parallel to the display substrate, includes a plurality of pixel islands, and the pixel islands include a plurality of sub-pixels; in a plane perpendicular to the display substrate, the sub-pixels include an arrangement of A driving circuit layer on the substrate and a light-emitting structure layer disposed on the side of the driving circuit layer away from the substrate, the driving circuit layer includes a pixel driving circuit, and the light-emitting structure layer includes a light-emitting device connected to the pixel driving circuit ;
  • At least one pixel island includes a circuit sub-region and a wiring sub-region, wherein the circuit sub-region is provided with pixel driving circuits of a plurality of sub-pixels in the pixel island, and the data fan-out line is provided in the wiring sub-region.
  • the orthographic projection of the at least one light emitting device in the pixel island on the plane of the display substrate and the orthographic projection of the data fan-out line on the plane of the display substrate have an overlapping area.
  • FIG. 9 is a schematic plan view of a display substrate according to an exemplary embodiment of the present disclosure
  • FIG. 10 is a side view of the display substrate in FIG. 9
  • the display substrate 10 may include a display area 100 , a binding area 500 on the opposite side of the first direction D1 of the display area 100 , and a frame area 300 on the other side of the display area 100 .
  • the display area 100 may be a flattened area including a plurality of sub-pixels Pxij forming a pixel array to display dynamic pictures or still images
  • the display substrate may be a flexible substrate, and thus the display substrate may be deformable, Such as curling, bending, folding or rolling.
  • the bonding area 500 may include a lead area 501, a bending area 502, and a composite circuit area 503 sequentially disposed along a reverse direction of the first direction D1 (a direction away from the display area), and the lead area 501 is connected to In the display area 100 , the bending area 502 is connected to the lead area 501 , and the composite circuit area 503 is connected to the bending area 502 .
  • the lead area 501 may be provided with a plurality of lead lines, one end of the plurality of lead lines is correspondingly connected to a plurality of data lines in the display area 100, and the other end is connected to the integrated circuit of the composite circuit area 503, so that the integrated circuit Data signals are applied to the data lines through pinout lines.
  • the bending region 502 can be bent with a curvature in the third direction D3, and the surface of the composite circuit region 503 can be reversed, that is, the surface of the composite circuit region 503 facing upward can pass through the bending region 502.
  • the bending is converted to face downward, and the third direction D3 intersects the first direction D1.
  • the composite circuit region 503 may overlap the display region 100 in the third direction D3 (thickness direction).
  • the composite circuit area 503 may include an antistatic area, a driving chip area and a binding pin area, and the integrated circuit (Integrate Circuit, IC for short) 20 may be bound and connected to the driving chip area, and the flexible circuit board ( Flexible Printed Circuit (FPC for short) 30 can be bound and connected in the binding pin area.
  • the integrated circuit 20 may generate driving signals required for driving the sub-pixels, and may provide the driving signals to the sub-pixels in the display area 100 .
  • the driving signal may be a data signal for driving the luminance of the sub-pixels.
  • the integrated circuit 20 may be bonded and connected to the driving chip area through an anisotropic conductive film or other means, and the width of the integrated circuit 20 in the second direction D2 may be smaller than that of the composite circuit area 503 in the second direction D2 The width of the second direction D2 intersects the first direction D1.
  • the bonding pin area may be provided with pads including a plurality of pins (PINs), and the flexible circuit board 30 may be bonded and connected to the pads.
  • the first direction D1 may be the extension direction (column direction) of the data lines in the display area
  • the second direction D2 may be the extension direction (row direction) of the scan signal lines in the display area
  • the third direction D3 It may be a direction perpendicular to the plane of the display substrate, the first direction D1 and the second direction D2 may be perpendicular to each other, and the first direction D1 and the third direction D3 may be perpendicular to each other.
  • FIG. 11 is a schematic structural diagram of a lead-out line and a data fan-out line according to an exemplary embodiment of the present disclosure.
  • the display area 100 may include multiple sub-pixels, multiple data lines DA and multiple data fan-out lines 700
  • the lead area 501 of the binding area may include multiple lead-out lines 600 .
  • a plurality of sub-pixels in the display area 100 are arranged in a matrix manner, forming a plurality of pixel rows and a plurality of pixel columns.
  • the plurality of data lines DA in the display area 100 extend along the first direction D1 or the opposite direction of the first direction D1, and are sequentially arranged at a set interval along the second direction D2, and each data line DA is in the display area 100 Connect to all subpixels of a pixel column.
  • the plurality of lead lines 600 in the lead area 501 are sequentially arranged at a set interval along the second direction D2.
  • the first ends of the lead lines 600 are located at the edge B of the display area, and the second ends of the lead lines 600 are directed away from the display area.
  • the direction of the region extends to the bend zone.
  • the first ends of the plurality of data fan-out lines 700 in the display area 100 are located at the edge B of the display area, and are correspondingly connected to the first ends of the plurality of lead-out lines 600, and the second ends of the plurality of data fan-out lines 700 are directed away from the lead area. extend, and are correspondingly connected with a plurality of data lines DA.
  • the edge B of the display area may be an edge of the side of the display area 100 close to the lead area 501 .
  • the number of data lines, the number of data fanout lines, and the number of pinout lines are the same.
  • a plurality of lead-out lines may be arranged to be parallel to the first direction D1, that is, the lead-out lines are parallel to the data lines.
  • the widths of the plurality of lead-out lines are the same, the distance between adjacent lead-out lines is the same, and the distance between adjacent lead-out lines is smaller than the distance between adjacent data lines.
  • the display substrate has a first center line O 1 , the first center line O 1 extends along the first direction D1 and bisects a plurality of pixel columns of the display area 100 , a plurality of data lines DA, a plurality of data lines
  • the fan-out line 700 and the plurality of lead-out lines 600 may be symmetrically arranged with respect to the first center line O 1 .
  • the display area 100 has a second center line O 2 , the second center line O 2 extends along the second direction D2 and bisects a plurality of pixel rows of the display area 100 , and a plurality of sub-pixel rows in the display area 100 may be relative to the second center Line O 2 is set symmetrically.
  • the following description will be given by taking as an example that the left side of the display substrate includes N data lines, N data fan-out lines and N outgoing lines, where N is a positive integer greater than 2.
  • the N data lines may include a first data line DA1, a second data line DA2, .
  • a data fan-out line 701, a second data fan-out line 702, ..., the Nth data fan-out line 70N, the N lead-out lines may include first lead-out lines arranged in sequence along the second direction D2 or the opposite direction of the second direction D2 601, the second lead wire 602, ..., the Nth lead wire 60N.
  • the N lead-out lines may be correspondingly connected with the N data fan-out lines
  • the N data fan-out lines may be correspondingly connected with the N data lines, so that the lead-out lines provide data signals to the data lines through the data fan-out lines.
  • the first end of the i-th data fan-out line may be connected with the i-th lead-out line at the edge B of the display area, and the second end of the i-th data fan-out line extends to the edge of the display area 100 in a direction away from the lead area.
  • the second end of the data fan-out line is connected to the data line through a via hole, and the position of the via hole is the second end of the data fan-out line.
  • the second end (via hole) of any data fan-out line 700 has a distance L1 from the second center line, and the distance L1 can satisfy: L1 ⁇ 0.2*the length of the data line in the display area.
  • the length and distance L1 of the data line are the dimensions in the first direction D1.
  • the second end of any data fan-out line may be connected to the data line at the position where the second center line O 2 is located, that is, the via holes are all located on the second center line O 2 .
  • the i-th data fanout line may include a first line segment and a second line segment.
  • the first end of the first line segment is located at the edge B of the display area and is connected to the i-th lead-out line, and the second end of the first line segment extends in the opposite direction of the second direction D2 and is connected to the first end of the second line segment .
  • the second end of the second line segment extends to the vicinity of the second center line O 2 along the first direction D1, it is connected to the i-th data line.
  • the first line segment may include a lead-out segment and a first extension segment.
  • the first end of the lead-out segment is located at the edge B of the display area and is connected to the i-th lead-out line. After the second end of the lead-out segment extends along the first direction D1, it is connected to the first end of the first extension segment.
  • the spacing between adjacent data lines may be smaller than the spacing between adjacent data lines.
  • the second line segment may include a second extension segment and a connecting segment.
  • the first end of the second extension segment is connected to the second end of the first line segment. After the second end of the second extension segment extends along the first direction D1 to the vicinity of the second centerline O2 , it is connected to the first end of the connection segment. end connection. After the second end of the connection segment extends along the opposite direction of the second direction D2, it is connected to the i-th data line.
  • the extension length of the first line segment may be 0, that is, the i-th data fanout line may only include the second line segment.
  • the eight data lines may include a first data line DA1, a second data line DA2, a third data line DA3, a fourth data line DA4, a fifth data line DA5,
  • the sixth data line DA6, the seventh data line DA7 and the eighth data line DA8, the eight lead lines in the lead area 501 of the binding area may include the first lead line 601 and the second lead line arranged in sequence along the second direction D2 Line 602 , third lead line 603 , fourth lead line 604 , fifth lead line 605 , sixth lead line 606 , seventh lead line 607 , and eighth lead line 608 .
  • the first end of the i-th data fan-out line is connected with the i-th lead-out line near the edge B of the display area, and the second end of the i-th data fan-out line extends to the second center of the display area 100 in a broken line manner After the line O 2 is near, connect with the i-th data line.
  • i 1,2,...,8.
  • the first extension segment of the i-th data fan-out line and the first extension segment of the i+1-th data fan-out line may be located between different pixel rows.
  • the first extension of the first data fan-out line is located on the side of the last pixel row close to the lead area, and the first extension of the second data fan-out line may be located between the last pixel row and the penultimate pixel row.
  • the second extension segment of the i-th data fan-out line and the second extension segment of the i+1-th data fan-out line are located between different pixel columns.
  • the second extension of the first data fan-out line is located between the first pixel column and the second pixel column
  • the second extension of the second data fan-out line is located between the second pixel column and the third pixel column.
  • the exemplary embodiment shown in FIG. 12 is described by taking the example that the second extension section and the connection section of the data fan-out line are located on the right side of the corresponding data line, in the present disclosure, the second extension section and the connection section of the data fan-out line are It can be located on the left side of the corresponding data line, which is not limited in this disclosure.
  • FIG. 13 is an enlarged view of the area C2 in FIG. 11
  • FIG. 14 is a cross-sectional view taken along the line A-A in FIG. 13 .
  • the connection segment is connected, and the second end of the connection segment extends in the opposite direction of the second direction D2, and is connected to the first data line DA1, the second data line DA2, the third data line DA3 and the first data line DA1, the second data line DA2, the third data line DA3 and the first data line DA1 through the via holes respectively.
  • Four data lines DA4 are connected correspondingly.
  • the data line and the data fan-out line may be disposed in different film layers, and an insulating layer is disposed between the data line and the data fan-out line.
  • the lead-out line and the data fan-out line may be disposed in the same film layer and formed simultaneously by the same patterning process, and the lead-out line and the data fan-out line may be an integral structure connected to each other.
  • the lead-out line and the data fan-out line may be disposed in different film layers, an insulating layer is disposed therebetween, and the two are connected through via holes.
  • the data lines may include data lines of odd columns and data lines of even columns, where the data lines of odd columns are arranged in odd sub-pixel columns, and the data lines of even columns are arranged in even sub-pixel columns.
  • the data fan-out lines may include odd-numbered data fan-out lines and even-numbered data fan-out lines, the data fan-out lines connected to the data lines of odd-numbered columns are called odd-numbered data fan-out lines, and the data fan-out lines connected to the data lines of even-numbered columns are called even-numbered data fan-out lines.
  • the lead-out lines may include odd-numbered lead-out lines and even-numbered lead-out lines.
  • the lead-out lines connected with the data lines of the odd-numbered columns through the odd-numbered data fan-out lines are called odd-numbered lead-out lines
  • the lead-out lines connected with the data lines of the even-numbered columns through the even-numbered data fan-out lines are called odd-numbered lead-out lines.
  • the wires are called even pinouts.
  • the odd-numbered data fan-out lines and the even-numbered data fan-out lines may be disposed in the same film layer.
  • the odd-numbered data fan-out lines and the even-numbered data fan-out lines may be arranged in different film layers, and an insulating layer is arranged between the odd-numbered data fan-out lines and the even-numbered data fan-out lines, that is, an insulating layer is arranged between the data lines and the odd-numbered data fan-out lines.
  • An insulating layer is arranged between the data lines and the even-numbered data fan-out lines, and an insulating layer is arranged between the odd-numbered data fan-out lines and the even-numbered data fan-out lines.
  • the odd-numbered lead-out lines and the odd-numbered data fan-out lines may be disposed on the same layer and formed simultaneously by the same patterning process, and the odd-numbered lead-out lines and the odd-numbered data fan-out lines may be connected to each other in an integrated structure.
  • the even-numbered lead-out lines and the even-numbered data fan-out lines can be arranged in the same layer and formed simultaneously by the same patterning process, and the even-numbered lead-out lines and the even-numbered data fan-out lines can be an integral structure connected to each other.
  • the display substrate may include a plurality of conductive layers disposed on the substrate, and the plurality of conductive layers may include a first conductive layer, a second conductive layer and a second conductive layer disposed in sequence along the direction away from the substrate layer and a third conductive layer, the first conductive layer may include odd data fanout lines and odd lead lines, the second conductive layer may include even data fanout lines and even lead lines, and the third conductive layer may include data lines.
  • the display substrate in a plane perpendicular to the display substrate, may include a semiconductor layer and a plurality of insulating layers, and the plurality of insulating layers may include a first insulating layer 11 , a second insulating layer 11 , a second insulating layer 11 , a second insulating layer 11 , a second insulating layer 11 , a second insulating layer 10 , a The insulating layer 12 , the third insulating layer 13 and the fourth insulating layer 14 .
  • the first insulating layer 11 is disposed on the substrate 10
  • the semiconductor layer is disposed on the side of the first insulating layer 11 away from the substrate
  • the second insulating layer 12 covers the semiconductor layer
  • the first conductive layer is disposed on the second
  • the insulating layer 12 is on the side away from the substrate
  • the third insulating layer 13 covers the first conductive layer
  • the second conductive layer is arranged on the side of the third insulating layer 13 away from the substrate
  • the fourth insulating layer 14 covers the second conductive layer
  • the third insulating layer 14 covers the second conductive layer.
  • the conductive layer is disposed on the side of the fourth insulating layer 14 away from the substrate.
  • the orthographic projection of any one of the lead lines on the substrate has no overlapping area with the orthographic projections of other lead lines on the substrate, and the orthographic projection of any one of the data fan-out lines on the substrate and other data fan-out lines on the substrate
  • the orthographic projections have no overlapping areas.
  • the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer may adopt silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON) Any one or more of them can be single layer, multi-layer or composite layer.
  • the first insulating layer may be referred to as a buffer layer, and is configured to prevent impurity diffusion of ions, prevent moisture penetration, and perform a surface planarization function.
  • the third insulating layer between the first conductive layer and the second conductive layer may be referred to as a gate insulating (GI) layer, and the fourth insulating layer disposed between the second conductive layer and the third conductive layer may be referred to as a layer inter-insulation (ILD) layer.
  • GI gate insulating
  • ILD layer inter-insulation
  • the first conductive layer, the second conductive layer and the third conductive layer can be made of metal materials, such as any one of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo) or Various, or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), can be a single-layer structure, or a multi-layer composite structure, such as Ti/Al/Ti and the like.
  • metal materials such as any one of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo) or Various, or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb)
  • AlNd aluminum neodymium alloy
  • MoNb molybdenum niobium alloy
  • the semiconductor layer can be made of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), six Materials such as thiophene or polythiophene, that is, the present disclosure is applicable to transistors fabricated based on oxide technology, silicon technology or organic technology.
  • a-IGZO amorphous indium gallium zinc oxide
  • ZnON zinc oxynitride
  • IZTO indium zinc tin oxide
  • a-Si amorphous silicon
  • p-Si polycrystalline silicon
  • six Materials such as thiophene or polythiophene, that is, the present disclosure is applicable to transistors fabricated based on oxide technology, silicon technology or organic technology.
  • the active layer based on oxide technology can employ oxides containing indium and tin, oxides containing tungsten and indium, oxides containing tungsten and indium and zinc, oxides containing titanium and indium, oxides containing titanium and indium and tin , oxides containing indium and zinc, oxides containing silicon and indium and tin, oxides containing indium and gallium and zinc, etc.
  • the semiconductor layer may include active layers of a plurality of transistors
  • the first conductive layer may include scan signal lines, gate electrodes of the plurality of transistors, a first capacitor plate, odd-numbered lead-out lines and For odd-numbered data fanout lines
  • the second conductive layer may include a second capacitor plate, an even-numbered lead-out line and an even-numbered data fanout line
  • the third conductive layer may include data lines, source electrodes and drain electrodes of a plurality of transistors.
  • the first conductive layer may include odd-numbered lead lines
  • the second conductive layer may include even-numbered lead lines
  • the third conductive layer may include data lines.
  • the third insulating layer 13 and the fourth insulating layer 14 may be provided with a plurality of first via holes K1 , and the plurality of first via holes K1 are located at the ends of the odd-numbered data fan-out lines.
  • the third insulating layer 13 and the fourth insulating layer 14 in K1 are etched away, exposing the surfaces of the odd-numbered data fanout lines.
  • the first via hole K1 is configured so that the data lines of the odd-numbered columns formed subsequently are connected to the odd-numbered data fan-out lines correspondingly through the via hole.
  • a plurality of second via holes K2 may be opened on the fourth insulating layer 14 , the plurality of second via holes K2 are located at the ends of the even-numbered data fan-out lines, and the fourth insulating layer in the second via hole K2 Layer 14 is etched away, exposing the surface of the even data fanout lines.
  • the second via hole K2 is configured so that the data lines of the even-numbered columns formed subsequently are correspondingly connected to the even-numbered data fan-out lines through the via hole.
  • the "patterning process” mentioned in this disclosure includes photoresist coating, mask exposure, development, etching, stripping photoresist and other treatments, for organic materials, including Processes such as coating organic materials, mask exposure and development.
  • Deposition can use any one or more of sputtering, evaporation, chemical vapor deposition
  • coating can use any one or more of spraying, spin coating and inkjet printing
  • etching can use dry etching and wet Any one or more of the engravings are not limited in the present disclosure.
  • “Film” refers to a thin film made of a material on a substrate by deposition, coating or other processes.
  • the "thin film” may also be referred to as a "layer”. If the "thin film” needs a patterning process in the whole manufacturing process, it is called a "thin film” before the patterning process, and a “layer” after the patterning process.
  • the “layer” after the patterning process contains at least one "pattern”.
  • “A and B are arranged in the same layer” means that A and B are simultaneously formed through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate.
  • the orthographic projection of A includes the orthographic projection of B
  • the orthographic projection of B is located within the range of the orthographic projection of A
  • the edge of the display area of the orthographic projection of B falls within the range of A's orthographic projection.
  • the edge of the display area of the orthographic projection of A overlaps the edge of the display area of the orthographic projection of B.
  • the manufacturing process of the display substrate may include the following operations.
  • a semiconductor layer pattern is formed on a substrate.
  • forming the semiconductor layer pattern on the substrate may include: sequentially depositing a first insulating film and a semiconductor film on the substrate, and patterning the semiconductor film through a patterning process to form a first insulating layer covering the entire substrate , and a semiconductor layer pattern disposed on the first insulating layer, the semiconductor layer pattern including at least active layers of a plurality of transistors.
  • the substrate may be a flexible substrate.
  • forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first metal film on the substrate on which the foregoing pattern is formed, and patterning the first metal film through a patterning process to form a cover The second insulating layer of the semiconductor layer pattern, and the first conductive layer pattern disposed on the second insulating layer, the first conductive layer pattern at least includes a plurality of odd-numbered data fan-out lines, a plurality of scanning signal lines, a plurality of The gate electrode and the plurality of first capacitor electrodes of the transistor, and the plurality of odd-numbered lead-out lines located in the lead area of the bonding area, the odd-numbered data fan-out lines and the odd-numbered lead-out lines may be connected to each other in an integrated structure.
  • forming the second conductive layer pattern may include: sequentially depositing a third insulating film and a second metal film on the substrate on which the foregoing pattern is formed, and patterning the second metal film through a patterning process to form a cover A third insulating layer of the first conductive layer pattern, and a second conductive layer pattern disposed on the third insulating layer, the second conductive layer pattern at least including a plurality of even-numbered data fanout lines and a plurality of second capacitor electrodes located in the display area , and a plurality of even-numbered lead-out lines located in the lead area of the binding area, and the even-numbered data fan-out lines and the even-numbered lead-out lines may be an integral structure connected to each other.
  • a fourth insulating layer pattern is formed.
  • forming the fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate on which the aforementioned pattern is formed, patterning the fourth insulating film through a patterning process, and forming a pattern covering the second conductive layer
  • the fourth insulating layer, a plurality of via holes are opened on the fourth insulating layer, and the plurality of via holes may include: active via holes located at the positions of the plurality of active layers in the display area, and data fan-out line ends located in the display area A plurality of first vias and second vias of the portion.
  • the active vias expose the active layer, the first vias expose odd-numbered data fanout lines, and the second vias expose even-numbered data fanout lines.
  • a third conductive layer pattern is formed.
  • forming the third conductive layer pattern may include: depositing a third metal thin film on the substrate on which the aforementioned pattern is formed, patterning the third metal thin film through a patterning process, and forming a third metal thin film on the fourth insulating layer
  • the third conductive layer pattern at least includes: a plurality of data lines, source electrodes and drain electrodes of a plurality of transistors, the source electrodes and the drain electrodes are respectively connected to the corresponding active layers through active vias, and the odd-numbered columns are The data lines are connected to the odd-numbered data fan-out lines through the first via holes, and the data lines of the even-numbered columns are connected to the even-numbered data fan-out lines through the second via holes.
  • the preparation of the display substrate may further include forming a light emitting structure layer, an encapsulation layer, etc., which will not be repeated here.
  • the first conductive layer and the second conductive layer may be made of the same metal material, such as molybdenum (Mo), the width of each data fan-out line and the lead-out line is the same, and the spacing between adjacent lead-out lines All are the same, and both the width and the pitch are the dimensions of the second direction D2.
  • Mo molybdenum
  • the odd-numbered data fan-out lines are disposed in the second conductive layer.
  • the fan-out lines, the even-numbered data fan-out lines, and the data lines may be arranged in any layer, as long as the data lines and the data fan-out lines are located in different conductive layers, which is not limited in the present disclosure.
  • the structure of the display substrate and the preparation process thereof shown in the present disclosure are merely exemplary descriptions.
  • corresponding structures may be changed and patterning processes may be added or decreased according to actual needs, which are not limited in the present disclosure.
  • the binding area is provided with a fan-out area, and the data lines of the display area are drawn out through the data fan-out lines of the fan-out area. Since there are many oblique lines in the fan-shaped area, the lower frame is wider, which is not conducive to the realization of Narrow borders.
  • lead lines are set in the lead area of the binding area, and the lead lines are connected to the corresponding data lines through the data fan-out lines set in the display area, which not only realizes multiple lead lines and multiple data lines Corresponding connection of lines, and it makes it unnecessary to set a fan-shaped slash in the lead area, and the multiple lead lines are vertical lines parallel to each other, which can be directly introduced into the composite circuit area of the binding area, effectively reducing the vertical line in the lead area.
  • the length in the vertical direction greatly reduces the width of the lower frame, so that the widths of the upper frame, lower frame, left frame and right frame of the display device are similar, all of which are less than 1.0mm, which increases the screen ratio and facilitates the realization of full-screen display.
  • the resistance voltage drop (IR Drop) of the data line is effectively reduced, a more uniform screen display can be achieved, and the display quality.
  • the data lines are usually connected to the data fan-out lines at the edge of the display area, resulting in different voltage drops of the data lines outputting data signals to different sub-pixels, especially for displays with larger resolutions or larger sizes.
  • the resistance voltage drop between the sub-pixels of the first pixel row and the sub-pixels of the last pixel row is very different, causing problems such as uneven display images.
  • the lower frame is effectively reduced, and the resistance voltage drop for data transmission is effectively reduced. Realize a more uniform screen display and improve the display quality.
  • FIG. 15 is a schematic structural diagram of another lead-out line and a data fan-out line according to an exemplary embodiment of the present disclosure. As shown in FIG. 15 , a plurality of data lines, a plurality of data fan-out lines in the display area 100, and a plurality of lead lines 600 in the lead area 501 of the binding area may be symmetrically arranged with respect to the first center line O1.
  • the structures of the plurality of data lines DA and the plurality of lead-out lines 600 may be similar to those in the foregoing exemplary embodiment, which will not be repeated here.
  • 8 pinout lines may be correspondingly connected to 8 data fanout lines
  • 8 data fanout lines may be correspondingly connected to 8 data lines, so that the pinout lines provide data signals to the data lines through the data fanout lines.
  • any data fan-out line has an extension length L2 in the display area 100, and the extension length L2 may satisfy:
  • L2i is the extension length of one data fan-out line in the display area
  • L2j is the extension length of another data fan-out line in the display area.
  • the extension length of the data fan-out line may be the sum of the individual line segments constituting the data fan-out line.
  • the i-th data fanout line may include a first line segment and a second line segment.
  • the first end of the first line segment is located at the edge B of the display area and is connected to the i-th lead-out line, and the second end of the first line segment extends in the opposite direction of the second direction D2 and is connected to the first end of the second line segment .
  • the first line segment may include a lead-out segment and a first extension segment.
  • the first end of the lead-out segment is located at the edge B of the display area and is connected to the i-th lead-out line, and the second end of the lead-out segment extends along the first direction D1 and is connected to the first end of the first extension segment.
  • the second end of the first extension segment extends to the rear along the opposite direction of the second direction D2, and is connected to the first end of the second line segment.
  • the second line segment may include a second extension segment and a connecting segment.
  • the first end of the second extension segment is connected to the second end of the first line segment, and the second end of the second extension segment is connected to the first end of the connection segment after extending along the first direction D1. After the second end of the connection segment extends along the opposite direction of the second direction D2, it is connected to the i-th data line.
  • the orthographic projection of any one of the lead lines on the substrate has no overlapping area with the orthographic projections of other lead lines on the substrate, and the orthographic projection of any one of the data fan-out lines on the substrate and other data fan-out lines on the substrate
  • the orthographic projections have no overlapping areas.
  • the film layer structures of the data lines, the data fan-out lines, and the lead-out lines may be similar to those in the foregoing exemplary embodiment, and will not be repeated here.
  • the exemplary embodiments of the present disclosure can achieve the technical effects of the foregoing embodiments, including effectively reducing the width of the lower frame, effectively avoiding the size deviation of the two film layers, and effectively improving the display uniformity and display quality.
  • the extension length of different data fan-out lines is very different, the resistance of different data fan-out lines will be very different, and this resistance difference will cause display problems, such as the difference between the color on the two sides and the color in the middle, flickering screen powder, etc.
  • the resistances of the plurality of data fan-out lines are basically similar, and the difference in resistance voltage drop of the plurality of data fan-out lines is small, so that a more uniform screen display can be realized, and the display is improved. quality.
  • the arrangement of the plurality of lead lines may adopt other manners.
  • the plurality of lead wires may be arranged in a descending order of numbers along the second direction D2.
  • the plurality of lead wires can be divided into at least two lead wire groups, one lead wire group can be arranged in an increasing numbered manner along the opposite direction of the second direction D2, and the other lead wire group can be arranged along the second direction D2 according to An arrangement in which the numbers are sequentially increased, and the lead wires in the two lead wire groups are alternately arranged, which is not limited in the present disclosure.
  • FIG. 16 is a schematic diagram of the arrangement of pixel islands in a display area according to an exemplary embodiment of the present disclosure
  • FIG. 17 is a schematic diagram of a compressed arrangement of pixel islands in an exemplary embodiment of the present disclosure.
  • the display area may include a plurality of pixel islands PD regularly arranged, and each pixel island PD may include a plurality of sub-pixels.
  • at least one pixel island PD may include a circuit sub-region 800 and a wiring sub-region 900.
  • the circuit sub-region 800 is configured to accommodate pixel driving circuits of a plurality of sub-pixels in the pixel island PD.
  • the wiring sub-region 900 is configured to accommodate data fanout lines.
  • each sub-pixel may at least include a driving circuit layer disposed on the substrate and a light emitting structure layer disposed on the side of the driving circuit layer away from the substrate, and the driving circuit layer may include
  • the pixel driving circuit 40, the pixel driving circuit 40 can be composed of a plurality of transistors and storage capacitors, the light emitting structure layer can include a light emitting device 50, the light emitting device 50 can be composed of an anode, an organic light emitting layer and a cathode, the light emitting device 50 and the pixel driving circuit 40 connected to emit light with corresponding brightness under the driving of the pixel driving circuit 40 .
  • the pixel driving circuit and the light-emitting device of each sub-pixel are arranged in alignment, the light-emitting device is located directly above the pixel driving circuit of the sub-pixel, and the orthographic projection of the light-emitting device on the substrate is located on the substrate.
  • the array period of the pixel driving circuit is the same as the array period of the light emitting device. Since the plurality of sub-pixels in the display area are uniformly arranged, the plurality of pixel driving circuits in the display area are uniformly arranged, and the plurality of light emitting devices are uniformly arranged.
  • the pixel driving circuit and the light emitting device of each sub-pixel in the pixel island PD are dislocated, and the occupied area of each sub-pixel pixel driving circuit is compressed to provide accommodation space for the data fan-out line.
  • each rectangle represents an area occupied by the pixel driving circuit 40 of each subpixel
  • each hexagon represents an area occupied by the light emitting device 50 (anode) of each subpixel.
  • the plurality of light emitting devices 50 in the pixel island PD are uniformly arranged in the pixel island PD area.
  • the arrangement position and occupied area of the light-emitting device in the embodiment are the same as the traditional arrangement of the light-emitting device, which is a normal arrangement.
  • a continuous light-emitting device array is formed, which can not only ensure normal screen display, but also does not need to introduce new mask.
  • the plurality of pixel driving circuits 40 in the pixel island PD are uniformly arranged in the circuit sub-region 800.
  • the present disclosure has The arrangement position and occupied area of the pixel driving circuit in the exemplary embodiment are different from the traditional arrangement of the pixel driving circuit, which is a compressed arrangement, forming a discontinuous pixel driving circuit array in the display area.
  • the area occupied by the plurality of pixel driving circuits 40 in the pixel island PD is smaller than the area occupied by the plurality of light emitting devices 50, and a wiring sub-region 900 for accommodating data fan-out lines can be formed in the driving circuit layer.
  • one pixel island may include 4 sub-pixels.
  • the pixel driving circuit 40 of each sub-pixel and the light-emitting device 50 are positioned in alignment, the light-emitting device 50 is located directly above the pixel driving circuit 40 of the sub-pixel, and the orthographic projection of the light-emitting device 50 on the substrate is located in the pixel driving circuit 40. within the range of the orthographic projection on the substrate, as shown in Figure 18a.
  • the light emitting devices 50 are still evenly arranged in the pixel island, which is the same as the normal arrangement, but the four pixel driving circuits 40 in the pixel island are arranged in the circuit sub-region 800 in a compressed manner, so that the One wiring sub-region 900 is formed on one side of the pixel island in the first direction D1 and one side in the second direction D2, as shown in FIG. 18b.
  • the four pixel driving circuits 40 and the four light emitting devices 50 in the pixel island are dislocated, but the four pixel driving circuits 40 and the four light emitting devices 50 are connected correspondingly.
  • the pixel islands are compressed in both the first direction D1 and the second direction D2, and in the first direction D1, the width occupied by the circuit sub-region 800 may be approximately 10% to 30% of the sub-pixel width , in the second direction D2, the length occupied by the circuit sub-region 800 may be equivalent to the length of three sub-pixels.
  • one pixel island may include 8 sub-pixels.
  • the pixel driving circuit 40 of each sub-pixel and the light-emitting device 50 are positioned in alignment, the light-emitting device 50 is located directly above the pixel driving circuit 40 of the sub-pixel, and the orthographic projection of the light-emitting device 50 on the substrate is located in the pixel driving circuit 40. within the range of the orthographic projection on the substrate, as shown in Figure 19a.
  • the light emitting devices 50 are still uniformly arranged in the pixel island, which is the same as the normal arrangement, but the 8 pixel driving circuits 40 in the pixel island are arranged in the circuit sub-region 800 in a compressed manner, so that the One wiring sub-region 900 is formed on each side of the pixel island in the second direction D2, as shown in FIG. 19b.
  • the 8 pixel driving circuits 40 and the 8 light emitting devices 50 in the pixel island are dislocated, but the 8 pixel driving circuits 40 and the 8 light emitting devices 50 are connected correspondingly.
  • the pixel islands may be compressed only in the second direction D2, and in the second direction D2, the length occupied by the circuit sub-region 800 may be equivalent to the length of 7 sub-pixels.
  • the number of sub-pixels included in each pixel island in the display area may be the same, or may be different.
  • a part of the pixel islands may include 8 sub-pixels, and another part of the pixel islands may include 16 sub-pixels.
  • the size of the pixel island in the display area can be set according to actual needs, which is not limited in the present disclosure.
  • each pixel island in the display area may be the same, or may be different.
  • some pixel islands can be compressed in the first direction
  • another part of the pixel islands can be compressed in the second direction
  • another part of the pixel islands can be compressed in the first direction and the second direction
  • the circuit sub-region can be arranged on one side of the pixel island, or arranged on multiple sides of the pixel island, which is not limited in the present disclosure.
  • the wiring sub-area may be located on one side of the circuit sub-area in the first direction, or the wiring sub-area may be located on the opposite side of the first direction of the circuit sub-area, and the wiring sub-area may be located in the circuit sub-area One side of the second direction, or the wiring sub-region may be located on the opposite side of the second direction of the circuit sub-region.
  • the display area may include a plurality of regularly arranged pixel islands, each pixel island may be provided with a plurality of pixel driving circuits 40 and light emitting devices 50, and at least one pixel island may include circuit sub-areas and A wiring sub-area, a plurality of wiring sub-areas in the display area to form a wiring area.
  • the wiring area may include at least one first wiring area 110 extending along the first direction D1 and at least one second wiring area 120 extending along the second direction D2.
  • the data fan-out line 700 may be disposed within the first wiring area 110 and the second wiring area 120 .
  • the first end of the data fan-out line 700 is connected to the lead line of the lead area, and the second end of the data fan-out line 700 extends along the first wiring area 110 and the second wiring area 120 and is connected to the corresponding data line DA.
  • the wiring area formed by compressing the pixel driving circuit has a certain width, so that one first wiring area 110 or one second wiring area 120 can arrange a plurality of data fan-out lines 700, which can not only reduce the data It is difficult to arrange and design the fan-out line, and it is beneficial to control the extension length of the data fan-out line.
  • the light emitting devices 50 are uniformly arranged, which is the same as the traditional arrangement of the light emitting devices, so some of the light emitting devices 50 and the wiring area have overlapping areas, and the orthographic projection of at least one light emitting device 50 on the display substrate plane is the same as the The orthographic projection of the data fan-out line 700 on the plane of the display substrate has an overlapping area.
  • the first wiring area 110 or the second wiring area 120 in which the data fan-out line 700 is not provided may be provided with a dummy fan-out line 750, and the dummy fan-out line 750 may extend along the first direction D1, or may extend along the first direction D1.
  • the two directions D2 extend.
  • Exemplary embodiments of the present disclosure can improve the uniformity of the display substrate manufacturing process by arranging the dummy fan-out lines 750 in the idle first wiring area 110 or the second wiring area 120, thereby improving the manufacturing quality.
  • the number of virtual fan-out lines 750 provided in at least one first wiring region 110 may be the same as the number of data fan-out lines 700 provided in other first wiring regions 110 , and the virtual fan-out lines 750 provided in at least one second wiring region 120 The number of the data fan-out lines 700 may be the same as the number of the other second wiring areas 120 .
  • the exemplary embodiments of the present disclosure can achieve the technical effects of the foregoing embodiments, including effectively reducing the width of the lower frame, effectively avoiding the size deviation of the two film layers, and effectively improving the display uniformity and display quality.
  • the exemplary embodiment of the present disclosure forms a plurality of wiring areas in the display area by adopting the compressed arrangement of the pixel driving circuit, and the data fan-out lines can extend in the wiring area and connect the corresponding data It effectively reduces the difficulty of data fan-out line layout design, improves the neatness and order of data fan-out line layout, avoids redesigning sub-pixels, avoids the introduction of new masks, and effectively reduces design and production. cost.
  • Exemplary embodiments of the present disclosure also provide a method for preparing a display substrate, the display substrate includes a display area and a binding area on one side of the display area, the binding area at least includes a lead area; the preparation Methods include:
  • a plurality of data lines and a plurality of data fan-out lines are formed in the display area, a plurality of lead-out lines are formed in the lead area, and the orthographic projections of the plurality of data lines and the plurality of data fan-out lines on the display substrate plane at least partially overlap;
  • the first end of at least one data fan-out line is connected to the lead-out line, and the second end extends in a direction away from the lead area and is connected to the data line.
  • Exemplary embodiments of the present disclosure also provide a display device including the display substrate of the foregoing embodiments.
  • the display device can be: mobile phone, tablet computer, TV, monitor, notebook computer, digital photo frame, navigator, advertising panel, watch phone, e-book portable multimedia player or display screen of various products of the Internet of Things, etc. products or parts.
  • the display device may be a wearable display device, which can be worn on the human body in some ways, such as a smart watch, a smart bracelet, and the like.

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Abstract

一种显示基板及其制备方法、显示装置，显示基板包括显示区域和位于所述显示区域一侧的绑定区域，所述绑定区域至少包括引线区；所述显示区域包括多条数据线和多条数据扇出线，所述引线区包括多条引出线，多条数据线和多条数据扇出线在显示基板平面上的正投影至少部分重叠；至少一条数据扇出线的第一端与所述引出线连接，第二端向着远离引线区的方向延伸后与所述数据线连接。

Description

显示基板及其制备方法、显示装置
本申请要求于2021年1月29日提交的、申请号为PCT/CN2021/074469、发明名称为“显示基板及显示装置”的PCT申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本公开涉及但不限于显示技术领域，尤指一种显示基板及其制备方法、显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度等优点。随着显示技术的不断发展，以OLED为发光器件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的显示装置已成为目前显示领域的主流产品。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
一方面，本公开示例性实施例提供了一种显示基板，包括显示区域和位于所述显示区域一侧的绑定区域，所述绑定区域至少包括引线区；所述显示区域包括多条数据线和多条数据扇出线，所述引线区包括多条引出线，多条数据线和多条数据扇出线在显示基板平面上的正投影至少部分重叠；至少一条数据扇出线的第一端与所述引出线连接，第二端向着远离引线区的方向延伸后与所述数据线连接。
在示例性实施方式中，所述数据扇出线的数量和所述数据线的数量相同。
在示例性实施方式中，在平行于显示基板的平面内，所述显示基板具有第一中心线，所述第一中心线沿着第一方向延伸并平分所述显示区域的像素列，所述第一方向与所述数据线平行；在所述第一中心线一侧，所述多条数据线包括沿着第二方向或者第二方向的反方向依次设置的第一数据线、第二数据线、……、第N数据线，所述第二方向与第一方向交叉；所述多条数据扇出线包括沿着第二方向或者第二方向的反方向依次设置的第一数据扇出线、第二数据扇出线、……、第N数据扇出线；所述多条引出线包括沿着第二方向或者第二方向的反方向依次设置的第一引出线、第二引出线、……、第N引出线；任意一条数据扇出线在显示基板平面上的正投影与其它数据扇出线在显示基板平面上的正投影没有重叠区域；任意一条引出线在显示基板平面上的正投影与其它引出线在显示基板平面上的正投影没有重叠区域；N为所述显示区域内数据线的数量。
在示例性实施方式中，至少一条数据扇出线包括第一线段和第二线段；所述第一线段的第一端与所述引出线连接，所述第一线段的第二端沿着第二方向或者第二方向的反方向延伸后，与所述第二线段的第一端连接；所述第二线段的第二端向着远离引线区的方向延伸后，通过过孔与所述数据线连接；所述第二方向与第一方向交叉，所述第一方向与所述数据线平行。
在示例性实施方式中，所述第一线段包括引出段和第一延伸段；所述引出段的第一端与所述引出线连接，所述引出段的第二端向着远离引线区的方向延伸后，与所述第一延伸段的第一端连接；所述第一延伸段的第二端沿着第二方向或者第二方向的反方向延伸后，与所述第二线段的第一端连接，相邻引出段之间的间距小于相邻数据线之间的间距。
在示例性实施方式中，所述引线区中多条引出线的宽度相同，相邻引出线之间的间距相同，相邻引出线之间的间距小于相邻数据线之间的间距。
在示例性实施方式中，所述第二线段包括第二延伸段和连接段；所述第二延伸段的第一端与所述第一线段的第二端连接，所述第二延伸段的第二端向着远离引线区的方向延伸后，与所述连接段的第一端连接；所述连接段的第二端沿着第二方向或者第二方向的反方向延伸后，通过过孔与所述数据线 连接。
在示例性实施方式中，在平行于显示基板的平面内，所述显示基板具有第二中心线，所述第二中心线沿着所述第二方向延伸并平分所述显示区域的像素行；任意一条数据扇出线与所述数据线连接的过孔，与所述第二中心线具有距离L1，所述距离L1满足：
L1≤0.2*显示区域内数据线的长度；
其中，所述长度和距离为所述第一方向上的尺寸。
在示例性实施方式中，多个所述数据扇出线与所述数据线连接的过孔位于所述第二中心线上。
在示例性实施方式中，任意一条数据扇出线在所述显示区域内具有延伸长度L2，所述延伸长度L2满足：
|L2i-L2j|/L2i≤0.2，或者|L2i-L2j|/L2j≤0.2；
其中，L2i为所述显示区域内一条数据扇出线的延伸长度，L2j为所述显示区域内另一条数据扇出线的延伸长度，所述数据扇出线的延伸长度为所述第一线段的延伸长度和第二线段的延伸长度之和。
在示例性实施方式中，多个所述数据扇出线与所述数据线连接的过孔，与所述第二中心线的距离不同。
在示例性实施方式中，在垂直于显示基板的平面内，所述显示基板包括第一导电层、第二导电层和第三导电层，所述第一导电层和所述第二导电层之间、所述第二导电层和所述第三导电层之间均设置有绝缘层；所述数据线和数据扇出线设置在不同的导电层中。
在示例性实施方式中，所述数据扇出线包括奇数数据扇出线和偶数数据扇出线，所述奇数数据扇出线与奇数列的数据线连接，所述偶数数据扇出线与偶数列的数据线连接；所述奇数数据扇出线和偶数数据扇出线设置在不同的导电层中。
在示例性实施方式中，所述引出线包括奇数引出线和偶数引出线，所述 奇数引出线通过所述奇数数据扇出线与奇数列的数据线连接，所述偶数引出线通过所述偶数数据扇出线与偶数列的数据线连接；所述奇数引出线与所述奇数数据扇出线同层设置，且为相互连接的一体结构，所述偶数引出线与所述偶数数据扇出线同层设置，且为相互连接的一体结构。
在示例性实施方式中，所述奇数数据扇出线设置在所述第一导电层，所述偶数数据扇出线设置在所述第二导电层，所述数据线设置在所述第三导电层；或者，所述偶数数据扇出线设置在所述第一导电层，所述奇数数据扇出线设置在所述第二导电层，所述数据线设置在所述第三导电层；所述第一导电层的材料和所述第二导电层的材料相同。
在示例性实施方式中，在平行于显示基板的平面内，所述显示基板包括多个像素岛，所述像素岛包括多个子像素；在垂直于显示基板的平面内，所述子像素包括设置在基底上的驱动电路层和设置在所述驱动电路层远离基底一侧的发光结构层，所述驱动电路层包括像素驱动电路，所述发光结构层包括与所述像素驱动电路连接的发光器件；
至少一个像素岛包括电路子区和布线子区，所述电路子区设置所述像素岛中多个子像素的像素驱动电路，所述布线子区内设置所述数据扇出线。
在示例性实施方式中，所述像素岛中至少一个发光器件在显示基板平面上的正投影与所述数据扇出线在显示基板平面上的正投影存在重叠区域。
在示例性实施方式中，所述布线子区内还设置有虚拟扇出线。
另一方面，本公开示例性实施例还提供了一种显示装置，包括前述的显示基板。
又一方面，本公开示例性实施例还提供了一种显示基板的制备方法，所述显示基板包括显示区域和位于所述显示区域一侧的绑定区域，所述绑定区域至少包括引线区；所述制备方法包括：
在所述显示区域形成多条数据线和多条数据扇出线，在所述引线区形成多条引出线，多条数据线和多条数据扇出线在显示基板平面上的正投影至少部分重叠；至少一条数据扇出线的第一端与所述引出线连接，第二端向着远 离引线区的方向延伸后与所述数据线连接。
在阅读理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中各部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为一种显示装置的结构示意图；
图2为一种显示基板的平面结构示意图；
图3为一种显示基板中显示区域的平面结构示意图；
图4为一种显示基板中显示区域的剖面结构示意图；
图5为一种像素驱动电路的等效电路示意图；
图6为一种像素驱动电路的工作时序图；
图7为一种显示基板中绑定区域的平面结构示意图；
图8为一种绑定区域中数据扇出线的示意图；
图9为本公开示例性实施例一种显示基板的平面结构示意图；
图10为图9中显示基板的侧视图；
图11为本公开示例性实施例一种引出线和数据扇出线的结构示意图；
图12为图11中C1区域的放大图；
图13为图11中C2区域的放大图；
图14为图13中A-A向的剖视图；
图15为本公开示例性实施例另一种引出线和数据扇出线的结构示意图；
图16为本公开示例性实施例一种显示区域中像素岛的排布示意图；
图17为本公开示例性实施例一个像素岛中压缩排布的示意图；
图18a至图18b为本公开示例性实施例一种压缩排布的示意图；
图19a至图19b为本公开示例性实施例另一种压缩排布的示意图；
图20和图21为本公开示例性实施例一种数据扇出线排布的示意图。
附图标记说明:
10—显示基板；          11—第一绝缘层；        12—第二绝缘层；
13—第三绝缘层；        14—第四绝缘层；        20—集成电路；
30—柔性电路板；        40—像素驱动电路；      50—发光器件；
100—显示区域；         101—基底；             102—驱动电路层；
102A—晶体管；          102B—存储电容；        110—第一布线区；
120—第二布线区；       200—绑定区域；         201—第一扇出区；
202—弯折区；           203—第二扇出区；       204—防静电区；
205—驱动芯片区；       206—绑定引脚区；       300—边框区域；
301—阳极；             302—像素定义层；       303—有机发光层；
304—阴极；             401—第一封装层；       402—第二封装层；
403—第三封装层；       500—绑定区域；         501—引线区；
502—弯折区；           503—复合电路区；       600—引出线；
700—数据扇出线；       750—虚拟扇出线。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。为了保持本公开实施例的以下说明清楚且简明，本公开省略了部分已知功能和已知部件的详细说明。本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计
在附图中，有时为了明确起见，夸大表示了各构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中各部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接 在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
图1为一种显示装置的结构示意图。如图1所示，OLED显示装置可以包括时序控制器、数据信号驱动器、扫描信号驱动器、发光信号驱动器和像素阵列，像素阵列可以包括多个扫描信号线(S1到Sm)、多个数据线(D1到Dn)、多个发光信号线(E1到Eo)和多个子像素Pxij。在示例性实施方式中，时序控制器可以将适合于数据信号驱动器的规格的灰度值和控制信号提供到数据信号驱动器，可以将适合于扫描信号驱动器的规格的时钟信号、扫描起始信号等提供到扫描信号驱动器，可以将适合于发光信号驱动器的规格的时钟信号、发射停止信号等提供到发光信号驱动器。数据信号驱动器可以利用从时序控制器接收的灰度值和控制信号来产生将提供到数据线D1、D2、D3、……和Dn的数据电压。例如，数据信号驱动器可以利用时钟信号对灰度值进行采样，并且以像素行为单位将与灰度值对应的数据电压施加到数据线D1至Dn，n可以是自然数。扫描信号驱动器可以通过从时序控制器接收时钟信号、扫描起始信号等来产生将提供到扫描信号线S1、S2、S3、……和Sm的扫描信号。例如，扫描信号驱动器可以将具有导通电平脉冲的扫描信号顺序地提供到扫描信号线S1至Sm。例如，扫描信号驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产生扫描信号，m可 以是自然数。发光信号驱动器可以通过从时序控制器接收时钟信号、发射停止信号等来产生将提供到发光信号线E1、E2、E3、……和Eo的发射信号。例如，发光信号驱动器可以将具有截止电平脉冲的发射信号顺序地提供到发光信号线E1至Eo。例如，发光信号驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以截止电平脉冲形式提供的发光停止信号传输到下一级电路的方式产生发光信号，o可以是自然数。像素阵列可以包括多个子像素Pxij，每个子像素Pxij可以连接到对应的数据线、对应的扫描信号线和对应的发光信号线，i和j可以是自然数。子像素Pxij可以指其中晶体管连接到第i扫描信号线且连接到第j数据线的子像素。
图2为一种显示基板的平面结构示意图。如图2所示，显示基板可以包括显示区域100、位于显示区域100一侧的绑定区域200以及位于显示区域100其它侧的边框区域300。显示区域100可以包括配置为显示动态图片或静止图像的多个子像素，绑定区域200可以包括将多个数据线连接至集成电路的数据扇出线，边框区域300可以包括传输电压信号的电源线，绑定区域200和边框区域300可以包括环形结构的隔离坝，边框区域300的至少一侧可以是通过弯折形成的卷曲区域，或者，显示区域100和边框区域300均是弯折或弯曲的区域，本公开在此不做限定。
在示例性实施方式中，显示区域可以包括以矩阵方式排布的多个像素单元。图3为一种显示基板中显示区域的平面结构示意图。如图3所示，显示基板可以包括以矩阵方式排布的多个像素单元P，多个像素单元P的至少一个包括出射第一颜色光线的第一子像素P1、出射第二颜色光线的第二子像素P2和出射第三颜色光线的第三子像素P3，第一子像素P1、第二子像素P2和第三子像素P3均包括像素驱动电路和发光器件。第一子像素P1、第二子像素P2和第三子像素P3中的像素驱动电路分别与扫描信号线、数据线和发光信号线连接，像素驱动电路被配置为在扫描信号线和发光信号线的控制下，接收数据线传输的数据电压，向所述发光器件输出相应的电流。第一子像素P1、第二子像素P2和第三子像素P3中的发光器件分别与所在子像素的像素驱动电路连接，发光器件被配置为响应所在子像素的像素驱动电路输出的电流发出相应亮度的光。
在示例性实施方式中，像素单元P中可以包括红色(R)子像素、绿色(G)子像素和蓝色(B)子像素，或者可以包括红色子像素、绿色子像素、蓝色子像素和白色子像素，本公开在此不做限定。在示例性实施方式中，像素单元中子像素的形状可以是矩形、菱形、五边形或六边形。像素单元包括三个子像素时，三个子像素可以采用水平并列、竖直并列或品字方式排列，像素单元包括四个子像素时，四个子像素可以采用水平并列、竖直并列或正方形(Square)方式排列，本公开在此不做限定。
图4为一种显示基板中显示区域的剖面结构示意图，示意了OLED显示基板三个子像素的结构。如图4所示，在垂直于显示基板的平面上，显示基板可以包括设置在基底101上的驱动电路层102、设置在驱动电路层102远离基底101一侧的发光结构层103以及设置在发光结构层103远离基底101一侧的封装层104。在一些可能的实现方式中，显示基板可以包括其它膜层，如隔垫柱等，本公开在此不做限定。
在示例性实施方式中，基底101可以是柔性基底，或者可以是刚性基底。每个子像素的驱动电路层102可以包括构成像素驱动电路的多个晶体管和存储电容，图4中仅以一个晶体管102A和一个存储电容102B作为示例。发光结构层103可以包括阳极301、像素定义层302、有机发光层303和阴极304，阳极301通过过孔与驱动晶体管210的漏电极连接，有机发光层303与阳极301连接，阴极304与有机发光层303连接，有机发光层303在阳极301和阴极304驱动下出射相应颜色的光线。封装层104可以包括叠设的第一封装层401、第二封装层402和第三封装层403，第一封装层401和第三封装层403可以采用无机材料，第二封装层402可以采用有机材料，第二封装层402设置在第一封装层401和第三封装层403之间，可以保证外界水汽无法进入发光结构层103。
在示例性实施方式中，有机发光层303可以包括叠设的空穴注入层(Hole Injection Layer，简称HIL)、空穴传输层(Hole Transport Layer，简称HTL)、电子阻挡层(Electron Block Layer，简称EBL)、发光层(Emitting Layer，简称EML)、空穴阻挡层(Hole Block Layer，简称HBL)、电子传输层(Electron Transport Layer，简称ETL)和电子注入层(Electron Injection  Layer，简称EIL)。在示例性实施方式中，所有子像素的空穴注入层可以是连接在一起的共通层，所有子像素的电子注入层可以是连接在一起的共通层，所有子像素的空穴传输层可以是连接在一起的共通层，所有子像素的电子传输层可以是连接在一起的共通层，所有子像素的空穴阻挡层可以是连接在一起的共通层，相邻子像素的发光层可以有少量的交叠，或者可以是隔离的，相邻子像素的电子阻挡层可以有少量的交叠，或者可以是隔离的。
在示例性实施方式中，像素驱动电路可以是3T1C、4T1C、5T1C、5T2C、6T1C或7T1C结构。图5为一种像素驱动电路的等效电路示意图。如图5所示，像素驱动电路可以包括7个晶体管(第一晶体管T1到第七晶体管T7)、1个存储电容C和7个信号线(数据线D、第一扫描信号线S1、第二扫描信号线S2、发光信号线E、初始信号线INIT、第一电源线VDD和第二电源线VSS)。
在示例性实施方式中，存储电容C的第一端与第一电源线VDD连接，存储电容C的第二端与第二节点N2连接，即存储电容C的第二端与第三晶体管T3的控制极连接。
第一晶体管T1的控制极与第二扫描信号线S2连接，第一晶体管T1的第一极与初始信号线INIT连接，第一晶体管的第二极与第二节点N2连接。当导通电平扫描信号施加到第二扫描信号线S2时，第一晶体管T1将初始化电压传输到第三晶体管T3的控制极，以使第三晶体管T3的控制极的电荷量初始化。
第二晶体管T2的控制极与第一扫描信号线S1连接，第二晶体管T2的第一极与第二节点N2连接，第二晶体管T2的第二极与第三节点N3连接。当导通电平扫描信号施加到第一扫描信号线S1时，第二晶体管T2使第三晶体管T3的控制极与第二极连接。
第三晶体管T3的控制极与第二节点N2连接，即第三晶体管T3的控制极与存储电容C的第二端连接，第三晶体管T3的第一极与第一节点N1连接，第三晶体管T3的第二极与第三节点N3连接。第三晶体管T3可以称为驱动晶体管，第三晶体管T3根据其控制极与第一极之间的电位差来确定在第一电源线VDD与第二电源线VSS之间流动的驱动电流的量。
第四晶体管T4的控制极与第一扫描信号线S1连接，第四晶体管T4的第一极与数据线D连接，第四晶体管T4的第二极与第一节点N1连接。第四晶体管T4可以称为开关晶体管、扫描晶体管等，当导通电平扫描信号施加到第一扫描信号线S1时，第四晶体管T4使数据线D的数据电压输入到像素驱动电路。
第五晶体管T5的控制极与发光信号线E连接，第五晶体管T5的第一极与第一电源线VDD连接，第五晶体管T5的第二极与第一节点N1连接。第六晶体管T6的控制极与发光信号线E连接，第六晶体管T6的第一极与第三节点N3连接，第六晶体管T6的第二极与发光器件的第一极连接。第五晶体管T5和第六晶体管T6可以称为发光晶体管。当导通电平发光信号施加到发光信号线E时，第五晶体管T5和第六晶体管T6通过在第一电源线VDD与第二电源线VSS之间形成驱动电流路径而使发光器件发光。
第七晶体管T7的控制极与第一扫描信号线S1连接，第七晶体管T7的第一极与初始信号线INIT连接，第七晶体管T7的第二极与发光器件的第一极连接。当导通电平扫描信号施加到第一扫描信号线S1时，第七晶体管T7将初始化电压传输到发光器件的第一极，以使发光器件的第一极中累积的电荷量初始化或释放发光器件的第一极中累积的电荷量。
在示例性实施方式中，发光器件的第二极与第二电源线VSS连接，第二电源线VSS的信号为低电平信号，第一电源线VDD的信号为持续提供高电平信号。第一扫描信号线S1为本显示行像素驱动电路中的扫描信号线，第二扫描信号线S2为上一显示行像素驱动电路中的扫描信号线，即对于第n显示行，第一扫描信号线S1为S(n)，第二扫描信号线S2为S(n-1)，本显示行的第二扫描信号线S2与上一显示行像素驱动电路中的第一扫描信号线S1为同一信号线，可以减少显示面板的信号线，实现显示面板的窄边框。
在示例性实施方式中，第一晶体管T1到第七晶体管T7可以是P型晶体管，或者可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。在一些可能的实现方式中，第一晶体管T1到第七晶体管T7可以包括P型晶体管和N型晶体 管。
在示例性实施方式中，第一扫描信号线S1、第二扫描信号线S2、发光信号线E和初始信号线INIT沿水平方向延伸，第二电源线VSS、第一电源线VDD和数据线D沿竖直方向延伸。
在示例性实施方式中，发光器件可以是有机电致发光二极管(OLED)，包括叠设的第一极(阳极)、有机发光层和第二极(阴极)。
图6为一种像素驱动电路的工作时序图。下面通过图5示例的像素驱动电路的工作过程说明本公开示例性实施例，图5中的像素驱动电路包括7个晶体管(第一晶体管T1到第六晶体管T7)、1个存储电容C和7个信号线(数据线D、第一扫描信号线S1、第二扫描信号线S2、发光信号线E、初始信号线INIT、第一电源线VDD和第二电源线VSS)，7个晶体管均为P型晶体管。
在示例性实施方式中，像素驱动电路的工作过程可以包括：
第一阶段A1，称为复位阶段，第二扫描信号线S2的信号为低电平信号，第一扫描信号线S1和发光信号线E的信号为高电平信号。第二扫描信号线S2的信号为低电平信号，使第一晶体管T1导通，初始信号线INIT的信号提供至第二节点N2，对存储电容C进行初始化，清除存储电容中原有数据电压。第一扫描信号线S1和发光信号线E的信号为高电平信号，使第二晶体管T2、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7断开，此阶段OLED不发光。
第二阶段A2、称为数据写入阶段或者阈值补偿阶段，第一扫描信号线S1的信号为低电平信号，第二扫描信号线S2和发光信号线E的信号为高电平信号，数据线D输出数据电压。此阶段由于存储电容C的第二端为低电平，因此第三晶体管T3导通。第一扫描信号线S1的信号为低电平信号使第二晶体管T2、第四晶体管T4和第七晶体管T7导通。第二晶体管T2和第四晶体管T4导通使得数据线D输出的数据电压经过第一节点N1、导通的第三晶体管T3、第三节点N3、导通的第二晶体管T2提供至第二节点N2，并将数据线D输出的数据电压与第三晶体管T3的阈值电压之差充入存储电容C，存储电容C的第二端(第二节点N2)的电压为Vd-|Vth|，Vd为数据线D输出 的数据电压，Vth为第三晶体管T3的阈值电压。第七晶体管T7导通使得初始信号线INIT的初始电压提供至OLED的第一极，对OLED的第一极进行初始化(复位)，清空其内部的预存电压，完成初始化，确保OLED不发光。第二扫描信号线S2的信号为高电平信号，使第一晶体管T1断开。发光信号线E的信号为高电平信号，使第五晶体管T5和第六晶体管T6断开。
第三阶段A3、称为发光阶段，发光信号线E的信号为低电平信号，第一扫描信号线S1和第二扫描信号线S2的信号为高电平信号。发光信号线E的信号为低电平信号，使第五晶体管T5和第六晶体管T6导通，第一电源线VDD输出的电源电压通过导通的第五晶体管T5、第三晶体管T3和第六晶体管T6向OLED的第一极提供驱动电压，驱动OLED发光。
在像素驱动电路驱动过程中，流过第三晶体管T3(驱动晶体管)的驱动电流由其栅电极和第一极之间的电压差决定。由于第二节点N2的电压为Vdata-|Vth|，因而第三晶体管T3的驱动电流为：
I＝K*(Vgs-Vth) 2＝K*[(Vdd-Vd+|Vth|)-Vth] 2＝K*[(Vdd-Vd] 2
其中，I为流过第三晶体管T3的驱动电流，也就是驱动OLED的驱动电流，K为常数，Vgs为第三晶体管T3的栅电极和第一极之间的电压差，Vth为第三晶体管T3的阈值电压，Vd为数据线D输出的数据电压，Vdd为第一电源线VDD输出的电源电压。
图7为一种显示基板中绑定区域的平面结构示意图，图8为一种绑定区域中数据扇出线的示意图。如图7所示，在平行于显示基板的平面内，绑定区域200位于显示区域100的一侧，绑定区域200可以包括沿着远离显示区域100的方向依次设置的第一扇出区201、弯折区202、第二扇出区203、防静电区204、驱动芯片区205和绑定引脚区206。第一扇出区201至少包括数据扇出线，多条数据扇出线被配置为以扇出(Fanout)走线方式连接显示区域的数据线(Data Line)，如图8所示。弯折区202包括设置有凹槽的复合绝缘层，被配置为使绑定区域200弯折到显示区域100的背面。第二扇出区203包括以扇出走线方式引出的多条数据扇出线。防静电区204包括防静电电路，被配置为通过消除静电防止显示基板的静电损伤。驱动芯片区205包括集成电路(Integrated Circuit，简称IC)，被配置为与多条数据扇出线连 接。绑定引脚区206包括绑定焊盘(Bonding Pad)，被配置为与外部的柔性线路板(Flexible Printed Circuit，简称FPC)绑定连接。
随着OLED显示技术的发展，消费者对显示产品显示效果的要求越来越高，极窄边框成为显示产品发展的新趋势，因此边框的窄化甚至无边框设计在OLED显示产品设计中越来越受到重视。目前，显示装置的左边框、右边框和上边框可以控制在1.0mm以内，但下边框(绑定区域一侧的边框)的窄化设计难度较大，一直维持在2.0mm左右。这是因为数据扇出线通常设置在绑定区域的扇出区，而扇出区占用空间较大。通常，绑定区域的宽度小于显示区域的宽度，绑定区域中集成电路和绑定焊盘的信号线需要通过扇出区以扇出方式才能引入到较宽的显示区域，显示区域与绑定区域的宽度差距越大，扇形区中斜向扇出线越多，驱动芯片区与显示区域之间的距离就越大，则下边框就越宽，导致下边框比左边框和右边框大很多。
本公开示例性实施例提供了一种显示基板。在示例性实施方式中，显示基板包括显示区域和位于所述显示区域一侧的绑定区域，所述绑定区域至少包括引线区；所述显示区域包括多条数据线和多条数据扇出线，所述引线区包括多条引出线，多条数据线和多条数据扇出线在显示基板平面上的正投影至少部分重叠；至少一条数据扇出线的第一端与所述引出线连接，第二端向着远离引线区的方向延伸后与所述数据线连接。
在示例性实施方式中，所述数据扇出线的数量和所述数据线的数量相同。
在示例性实施方式中，在平行于显示基板的平面内，所述显示基板具有第一中心线，所述第一中心线沿着第一方向延伸并平分所述显示区域的像素列，所述第一方向与所述数据线平行；在所述第一中心线一侧，所述多条数据线包括沿着第二方向或者第二方向的反方向依次设置的第一数据线、第二数据线、……、第N数据线，所述第二方向与第一方向交叉；所述多条数据扇出线包括沿着第二方向或者第二方向的反方向依次设置的第一数据扇出线、第二数据扇出线、……、第N数据扇出线；所述多条引出线包括沿着第二方向或者第二方向的反方向依次设置的第一引出线、第二引出线、……、第N引出线；任意一条数据扇出线在显示基板平面上的正投影与其它数据扇出线在显示基板平面上的正投影没有重叠区域；任意一条引出线在显示基板 平面上的正投影与其它引出线在显示基板平面上的正投影没有重叠区域；N为所述显示区域内数据线的数量。
在示例性实施方式中，至少一条数据扇出线包括第一线段和第二线段；所述第一线段的第一端与所述引出线连接，所述第一线段的第二端沿着第二方向或者第二方向的反方向延伸后，与所述第二线段的第一端连接；所述第二线段的第二端向着远离引线区的方向延伸后，通过过孔与所述数据线连接；所述第二方向与第一方向交叉，所述第一方向与所述数据线平行。
在示例性实施方式中，在平行于显示基板的平面内，所述显示基板具有第二中心线，所述第二中心线沿着所述第二方向延伸并平分所述显示区域的像素行；任意一条数据扇出线与所述数据线连接的过孔，与所述第二中心线具有距离L1，所述距离L1满足：
L1≤0.2*显示区域内数据线的长度；
其中，所述长度和距离为所述第一方向上的尺寸。
在示例性实施方式中，任意一条数据扇出线在所述显示区域内具有延伸长度L2，所述延伸长度L2满足：
|L2i-L2j|/L2i≤0.2，或者|L2i-L2j|/L2j≤0.2；
其中，L2i为所述显示区域内一条数据扇出线的延伸长度，L2j为所述显示区域内另一条数据扇出线的延伸长度，所述数据扇出线的延伸长度为所述第一线段的延伸长度和第二线段的延伸长度之和。
在示例性实施方式中，在垂直于显示基板的平面内，所述显示基板包括第一导电层、第二导电层和第三导电层，所述第一导电层和所述第二导电层之间、所述第二导电层和所述第三导电层之间均设置有绝缘层；所述数据线和数据扇出线设置在不同的导电层中。
在示例性实施方式中，在平行于显示基板的平面内，所述显示基板包括多个像素岛，所述像素岛包括多个子像素；在垂直于显示基板的平面内，所述子像素包括设置在基底上的驱动电路层和设置在所述驱动电路层远离基底 一侧的发光结构层，所述驱动电路层包括像素驱动电路，所述发光结构层包括与所述像素驱动电路连接的发光器件；
至少一个像素岛包括电路子区和布线子区，所述电路子区设置所述像素岛中多个子像素的像素驱动电路，所述布线子区内设置所述数据扇出线。
在示例性实施方式中，所述像素岛中至少一个发光器件在显示基板平面上的正投影与所述数据扇出线在显示基板平面上的正投影存在重叠区域。
图9为本公开示例性实施例一种显示基板的平面结构示意图，图10为图9中显示基板的侧视图。如图9和图10所示，显示基板10可以包括显示区域100、位于显示区域100第一方向D1的反方向一侧的绑定区域500以及位于显示区域100其它侧的边框区域300。在示例性实施方式中，显示区域100可以是平坦化区域，包括组成像素阵列的多个子像素Pxij，以显示动态图片或静止图像，显示基板可以采用柔性基板，因而显示基板可以是可变形的，例如卷曲、弯曲、折叠或卷起。
在示例性实施方式中，绑定区域500可以包括沿着第一方向D1的反方向(远离显示区域方向)依次设置的引线区501、弯折区502和复合电路区503，引线区501连接到显示区域100，弯折区502连接到引线区501，复合电路区503连接到弯折区502。
在示例性实施方式中，引线区501可以设置多条引出线，多条引出线的一端与显示区域100中的多条数据线对应连接，另一端连接复合电路区503的集成电路，使得集成电路通过引出线将数据信号施加到数据线。
在示例性实施方式中，弯折区502可以在第三方向D3上以一曲率弯曲，可以将复合电路区503的表面反转，即复合电路区503朝向上方的表面可以通过弯折区502的弯曲转换成面朝向下方，第三方向D3与第一方向D1交叉。在示例性实施方式中，当弯折区502被弯曲时，复合电路区503可以在第三方向D3(厚度方向)上与显示区域100重叠。
在示例性实施方式中，复合电路区503可以包括防静电区、驱动芯片区和绑定引脚区，集成电路(Integrate Circuit，简称IC)20可以绑定连接在驱动芯片区，柔性电路板(Flexible Printed Circuit，简称FPC)30可以绑定连 接在绑定引脚区。在示例性实施方式中，集成电路20可以产生用于驱动子像素所需的驱动信号，并且可以将驱动信号提供给在显示区域100中的子像素。例如，驱动信号可以是驱动子像素发光亮度的数据信号。在示例性实施方式中，集成电路20可以通过各向异性导电膜或者其它方式绑定连接在驱动芯片区，集成电路20在第二方向D2上的宽度可以小于复合电路区503在第二方向D2上的宽度，第二方向D2与第一方向D1交叉。在示例性实施方式中，绑定引脚区可以设置包括多个引脚(PIN)的焊盘，柔性电路板30可以绑定连接到焊盘上。
在示例性实施方式中，第一方向D1可以是显示区域中数据线的延伸方向(列方向)，第二方向D2可以是显示区域中扫描信号线的延伸方向(行方向)，第三方向D3可以是垂直于显示基板平面的方向，第一方向D1和第二方向D2可以相互垂直，第一方向D1和第三方向D3可以相互垂直。
图11为本公开示例性实施例一种引出线和数据扇出线的结构示意图。如图11所示，显示区域100可以包括多个子像素、多条数据线DA和多条数据扇出线700，绑定区域的引线区501可以包括多条引出线600。在示例性实施方式中，显示区域100中的多个子像素以矩阵方式排布，形成多个像素行和多个像素列。显示区域100中的多条数据线DA沿着第一方向D1或者第一方向D1的反方向延伸，并沿着第二方向D2以设定的间隔顺序设置，每条数据线DA在显示区域100与一个像素列的所有子像素连接。引线区501的多条引出线600沿着第二方向D2以设定的间隔顺序设置，多条引出线600的第一端位于显示区域边缘B，多条引出线600的第二端向着远离显示区域的方向延伸到弯折区。显示区域100中的多条数据扇出线700的第一端位于显示区域边缘B，与多条引出线600的第一端对应连接，多条数据扇出线700的第二端向着远离引线区的方向延伸，并与多条数据线DA对应连接。在示例性实施方式中，显示区域边缘B可以是显示区域100靠近引线区501一侧的边缘。
在示例性实施方式中，数据线的数量、数据扇出线的数量和引出线的数量相同。
在示例性实施方式中，多条引出线可以设置成均与第一方向D1平行， 即引出线与数据线平行。
在示例性实施方式中，多条引出线的宽度相同，相邻引出线之间的间距相同，相邻引出线之间的间距小于相邻数据线之间的间距。
在示例性实施方式中，显示基板具有第一中心线O 1，第一中心线O 1沿着第一方向D1延伸并平分显示区域100的多个像素列，多条数据线DA、多条数据扇出线700和多条引出线600可以相对于第一中心线O 1对称设置。显示区域100具有第二中心线O 2，第二中心线O 2沿着第二方向D2延伸并平分显示区域100的多个像素行，显示区域100中的多个子像素行可以相对于第二中心线O 2对称设置。下面以显示基板左侧包括N条数据线、N条数据扇出线和N条引出线为例进行说明，N为大于2的正整数。
在示例性实施方式中，N条数据线可以包括沿着第二方向D2依次设置的第一数据线DA1、第二数据线DA2、……、第N数据线，N条数据扇出线可以包括第一数据扇出线701、第二数据扇出线702、……、第N数据扇出线70N，N条引出线可以包括沿着第二方向D2或者第二方向D2的反方向依次设置的第一引出线601、第二引出线602、……、第N引出线60N。
在示例性实施方式中，N条引出线可以与N条数据扇出线对应连接，N条数据扇出线可以与N条数据线对应连接，使得引出线通过数据扇出线将数据信号提供给数据线。
在示例性实施方式中，第i数据扇出线的第一端可以在显示区域边缘B与第i引出线连接，第i数据扇出线的第二端向着远离引线区的方向延伸到显示区域100的第二中心线O 2附近后，与第i数据线连接，i＝1，2，…….，N。
在示例性实施方式中，数据扇出线的第二端通过过孔与数据线实现连接，过孔位置即为数据扇出线的第二端。任意一条数据扇出线700的第二端(过孔)与所述第二中心线具有距离L1，距离L1可以满足：L1≤0.2*显示区域内数据线的长度。其中，数据线的长度和距离L1为第一方向D1上的尺寸。
在示例性实施方式中，任意一条数据扇出线的第二端可以在第二中心线O 2所在位置与数据线连接，即过孔均位于第二中心线O 2上。
在示例性实施方式中，第i数据扇出线可以包括第一线段和第二线段。第一线段的第一端位于显示区域边缘B，与第i引出线连接，第一线段的第二端沿着第二方向D2的反方向延伸后，与第二线段的第一端连接。第二线段的第二端沿着第一方向D1延伸到第二中心线O 2附近后，与第i数据线连接。
在示例性实施方式中，第一线段可以包括引出段和第一延伸段。引出段的第一端位于显示区域边缘B，与第i引出线连接，引出段的第二端沿着第一方向D1延伸后，与第一延伸段的第一端连接，相邻引出段之间的间距可以小于相邻数据线之间的间距。第一延伸段的第二端沿着第二方向D2的反方向延伸到第i像素列与第i+1像素列之间后，与第二线段的第一端连接。
在示例性实施方式中，第二线段可以包括第二延伸段和连接段。第二延伸段的第一端与第一线段的第二端连接，第二延伸段的第二端沿着第一方向D1延伸到第二中心线O 2附近后，与连接段的第一端连接。连接段的第二端沿着第二方向D2的反方向延伸后，与第i数据线连接。
在示例性实施方式中，第一线段的延伸长度可以为0，即第i数据扇出线可以仅包括第二线段。
在示例性实施方式中，第k数据扇出线的多个线段可以形成向第二中心线O 2延伸的折线，第k数据扇出线的第一延伸段与第二中心线O 2的距离可以大于第k+1数据扇出线的第一延伸段与第二中心线O 2的距离，第k数据扇出线的第二延伸段与第一中心线O 1的距离可以大于第k+1数据扇出线的第二延伸段与第一中心线O 1的距离，k＝1，…….，N-1。
图12为图11中C1区域的放大图，示意了N＝8时引出线和数据扇出线的排布结构。图12所示，8条数据线可以包括沿着第二方向D2依次设置的第一数据线DA1、第二数据线DA2、第三数据线DA3、第四数据线DA4、第五数据线DA5、第六数据线DA6、第七数据线DA7和第八数据线DA8，绑定区域的引线区501的8条引出线可以包括沿着第二方向D2依次设置的第一引出线601、第二引出线602、第三引出线603、第四引出线604、第五引出线605、第六引出线606、第七引出线607和第八引出线608。
在示例性实施方式中，第i数据扇出线的第一端在显示区域边缘B附近与第i引出线连接，第i数据扇出线的第二端以折线方式延伸到显示区域100中第二中心线O 2附近后，与第i数据线连接。i＝1，2，……，8。
在示例性实施方式中，第i数据扇出线的第一延伸段与第i+1数据扇出线的第一延伸段可以位于不同的像素行之间。例如，第一数据扇出线的第一延伸段位于最后一像素行靠近引线区的一侧，第二数据扇出线的第一延伸段可以位于最后一像素行与倒数第二像素行之间。
在示例性实施方式中，第i数据扇出线的第二延伸段与第i+1数据扇出线的第二延伸段位于不同的像素列之间。例如，第一数据扇出线的第二延伸段位于第一像素列与第二像素列之间，第二数据扇出线的第二延伸段位于第二像素列与第三像素列之间。
虽然图12所示示例性实施例以数据扇出线的第二延伸段和连接段位于对应数据线的右侧为例进行了说明，但本公开中，数据扇出线的第二延伸段和连接段可以位于对应数据线的左侧，本公开在此不做限定。
图13为图11中C2区域的放大图，图14为图13中A-A向的剖视图。图13所示，第一数据扇出线701、第二数据扇出线702、第三数据扇出线703和第四数据扇出线704的第二延伸段沿着第一方向D1延伸后，分别与相应的连接段的第一端连接，连接段的第二端沿着第二方向D2的反方向延伸后，分别通过过孔与第一数据线DA1、第二数据线DA2、第三数据线DA3和第四数据线DA4对应连接。
在示例性实施方式中，数据线和数据扇出线可以设置在不同的膜层中，且数据线与数据扇出线之间设置有绝缘层。
在示例性实施方式中，引出线和数据扇出线可以设置在相同的膜层中，且通过同一次图案化工艺同时形成，引出线和数据扇出线可以是相互连接的一体结构。
在示例性实施方式中，引出线和数据扇出线可以设置在不同的膜层中，两者之间设置有绝缘层，两者通过过孔实现连接。
在示例性实施方式中，数据线可以包括奇数列的数据线和偶数列的数据 线，奇数列的数据线设置在奇数子像素列，偶数列的数据线设置在偶数子像素列。相应地，数据扇出线可以包括奇数数据扇出线和偶数数据扇出线，与奇数列的数据线连接的数据扇出线称为奇数数据扇出线，与偶数列的数据线连接的数据扇出线称为偶数数据扇出线。相应地，引出线可以包括奇数引出线和偶数引出线，通过奇数数据扇出线与奇数列的数据线连接的引出线称为奇数引出线，通过偶数数据扇出线与偶数列的数据线连接的引出线称为偶数引出线。
在示例性实施方式中，奇数数据扇出线与偶数数据扇出线可以设置在相同的膜层中。或者，奇数数据扇出线与偶数数据扇出线可以设置在不同的膜层中，奇数数据扇出线与偶数数据扇出线之间设置有绝缘层，即数据线与奇数数据扇出线之间设置有绝缘层，数据线与偶数数据扇出线之间设置有绝缘层，奇数数据扇出线与偶数数据扇出线之间设置有绝缘层。
在示例性实施方式中，奇数引出线与奇数数据扇出线可以同层设置，且通过同一次图案化工艺同时形成，奇数引出线和奇数数据扇出线可以是相互连接的一体结构。偶数引出线与偶数数据扇出线可以同层设置，且通过同一次图案化工艺同时形成，偶数引出线和偶数数据扇出线可以是相互连接的一体结构。
图14所示，在垂直于显示基板的平面内，显示基板可以包括设置在基底上的多个导电层，多个导电层可以包括沿着远离基底方向依次设置的第一导电层、第二导电层和第三导电层，第一导电层可以包括奇数数据扇出线和奇数的引出线，第二导电层可以包括偶数数据扇出线和偶数引出线，第三导电层可以包括数据线。
在示例性实施方式中，在垂直于显示基板的平面内，显示基板可以包括半导体层和多个绝缘层，多个绝缘层可以包括沿着远离基底方向依次设置的第一绝缘层11、第二绝缘层12、第三绝缘层13和第四绝缘层14。在示例性实施方式中，第一绝缘层11设置在基底10上，半导体层设置在第一绝缘层11远离基底的一侧，第二绝缘层12覆盖半导体层，第一导电层设置在第二绝缘层12远离基底的一侧，第三绝缘层13覆盖第一导电层，第二导电层设置在第三绝缘层13远离基底的一侧，第四绝缘层14覆盖第二导电层，第三 导电层设置在第四绝缘层14远离基底的一侧。
在示例性实施方式中，任意一条引出线在基底上的正投影与其它引出线在基底上的正投影没有重叠区域，任意一条数据扇出线在基底上的正投影与其它数据扇出线在基底上的正投影没有重叠区域。
在示例性实施方式中，第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。第一绝缘层可以称为缓冲(Buffer)层，配置为防止离子的杂质扩散，防止水分渗透，并且执行表面平坦化功能，设置在半导体层和第一导电层之间的第二绝缘层、设置在第一导电层和第二导电层之间的第三绝缘层可以称为栅绝缘(GI)层，设置在第二导电层和第三导电层之间的第四绝缘层可称之为层间绝缘(ILD)层。第一导电层、第二导电层和第三导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)、钛(Ti)和钼(Mo)中的任意一种或多种，或者上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Ti/Al/Ti等。半导体层可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩或聚噻吩等材料，即本公开适用于基于氧化物(Oxide)技术、硅技术或有机物技术制造的晶体管。基于氧化物技术的有源层可以采用包含铟和锡的氧化物、包含钨和铟的氧化物、包含钨和铟和锌的氧化物、包含钛和铟的氧化物、包含钛和铟和锡的氧化物、包含铟和锌的氧化物、包含硅和铟和锡的氧化物、包含铟和镓和锌的氧化物等。
在示例性实施方式中，在显示区域，半导体层可以包括多个晶体管的有源层，第一导电层可以包括扫描信号线、多个晶体管的栅电极、第一电容极板、奇数引出线和奇数数据扇出线，第二导电层可以包括第二电容极板、偶数引出线和偶数数据扇出线，第三导电层可以包括数据线、多个晶体管的源电极和漏电极。在绑定区域，第一导电层可以包括奇数引出线，第二导电层可以包括偶数引出线，第三导电层可以包括数据线。
在示例性实施方式中，第三绝缘层13和第四绝缘层14上可以开设有多个第一过孔K1，多个第一过孔K1位于奇数数据扇出线的端部，第一过孔 K1内的第三绝缘层13和第四绝缘层14被刻蚀掉，暴露出奇数数据扇出线的表面。第一过孔K1配置为使后续形成的奇数列的数据线通过该过孔与奇数数据扇出线对应连接。
在示例性实施方式中，第四绝缘层14上可以开设有多个第二过孔K2，多个第二过孔K2位于偶数数据扇出线的端部，第二过孔K2内的第四绝缘层14被刻蚀掉，暴露出偶数数据扇出线的表面。第二过孔K2配置为使后续形成的偶数列的数据线通过该过孔与偶数数据扇出线对应连接。
下面通过显示基板的一种制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。本公开示例性实施例中，“A的正投影包含B的正投影”或“B的正投影位于“A的正投影范围之内”，是指B的正投影的显示区域边缘落入A的正投影的显示区域边缘范围内，或者A的正投影的显示区域边缘与B的正投影的显示区域边缘重叠。
在一种示例性实施方式中，显示基板的制备过程可以包括如下操作。
(1)在基底上形成半导体层图案。在示例性实施方式中，在基底上形成半导体层图案可以包括：在基底上依次沉积第一绝缘薄膜和半导体薄膜，通过图案化工艺对半导体薄膜进行图案化，形成覆盖整个基底的第一绝缘层，以及设置在第一绝缘层上的半导体层图案，半导体层图案至少包括多个晶体管的有源层。在示例性实施方式中，基底可以是柔性基底。
(2)形成第一导电层图案。在示例性实施方式中，形成第一导电层图案可以包括：在形成前述图案的基底上依次沉积第二绝缘薄膜和第一金属薄膜，通过图案化工艺对第一金属薄膜进行图案化，形成覆盖半导体层图案的第二绝缘层，以及设置在第二绝缘层上的第一导电层图案，第一导电层图案至少包括位于显示区域的多条奇数数据扇出线、多条扫描信号线、多个晶体管的栅电极和多个第一电容电极，以及位于绑定区域引线区的多条奇数的引出线，奇数数据扇出线和奇数的引出线可以是相互连接的一体结构。
(3)形成第二导电层图案。在示例性实施方式中，形成第二导电层图案可以包括：在形成前述图案的基底上依次沉积第三绝缘薄膜和第二金属薄膜，通过图案化工艺对第二金属薄膜进行图案化，形成覆盖第一导电层图案的第三绝缘层，以及设置在第三绝缘层上的第二导电层图案，第二导电层图案至少包括位于显示区域的多条偶数数据扇出线和多个第二电容电极，以及位于绑定区域引线区的多条偶数的引出线，偶数数据扇出线和偶数的引出线可以是相互连接的一体结构。
(4)形成第四绝缘层图案。在示例性实施方式中，形成第四绝缘层图案可以包括：在形成前述图案的基底上沉积第四绝缘薄膜，通过图案化工艺对第四绝缘薄膜进行图案化，形成覆盖第二导电层图案的第四绝缘层，第四绝缘层上开设有多个过孔，多个过孔可以包括：位于显示区域的多个有源层所在位置的有源过孔，以及位于显示区域的数据扇出线端部的多个第一过孔和第二过孔。有源过孔暴露出有源层，第一过孔暴露出奇数数据扇出线，第二过孔暴露出偶数数据扇出线。
(5)形成第三导电层图案。在示例性实施方式中，形成第三导电层图案可以包括：在形成前述图案的基底上沉积第三金属薄膜，通过图案化工艺对第三金属薄膜进行图案化，在第四绝缘层上形成第三导电层图案，第三导电层图案至少包括：多条数据线、多个晶体管的源电极和漏电极，源电极和漏电极分别通过有源过孔与对应的有源层连接，奇数列的数据线通过第一过孔与奇数数据扇出线连接，偶数列的数据线通过第二过孔与偶数数据扇出线连接。
在示例性实施方式中，显示基板制备还可以包括形成发光结构层、封装 层等，这里不再赘述。
在示例性实施方式中，第一导电层和第二导电层可以采用相同的金属材料，如钼(Mo)，每条数据扇出线和引出线的宽度均相同，相邻引出线之间的间距均相同，宽度和间距均是第二方向D2的尺寸。
虽然前述示例性实施例以奇数数据扇出线设置在第一导电层、偶数数据扇出线设置在第二导电层以及数据线设置在第三导电层为例进行了说明，但本公开中，奇数数据扇出线、偶数数据扇出线和数据线可以设置在任意层中，只要保证数据线与数据扇出线位于不同的导电层中即可，本公开在此不做限定。
本公开所示显示基板的结构及其制备过程仅仅是一种示例性说明，在示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺，本公开在此不做限定。
一种显示基板中，绑定区域设置有扇出区，显示区域的数据线通过扇出区的数据扇出线引出，由于扇形区中斜向线较多，因而使得下边框较宽，不利于实现窄边框。本公开示例性实施例中，在绑定区域的引线区中设置引出线，引出线通过设置在显示区域内的数据扇出线与对应的数据线连接，不仅实现了多条引出线与多条数据线的对应连接，而且使得引线区中不需要设置扇形状的斜线，多条引出线为相互平行的竖直线，可以直接引入到绑定区域的复合电路区，有效减小了引线区竖直方向的长度，大大缩减了下边框宽度，使得显示装置的上边框、下边框、左边框和右边框的宽度相近，均为1.0mm以下，提高了屏占比，有利于实现全面屏显示。
本公开示例性实施例中，通过设置数据扇出线与数据线在显示区域的第二中心线附近连接，有效降低了数据线的电阻压降(IR Drop)，可以实现更加均匀的屏幕显示，提高了显示品质。一种显示基板中，数据线通常是在显示区域边缘处与数据扇出线连接，因而造成数据线向不同子像素输出数据信号的压降不同，特别是对于分辨率较大或尺寸较大的显示装置，第一像素行的子像素和最后一像素行的子像素之间电阻压降差异很大，造成显示画面不均等问题。本公开通过将数据扇出线设置在显示区域内，且在每一列子像素的中间位置通过过孔与数据线连接，在有效减小下边框的同时，有效降低了 传输数据的电阻压降，可以实现更加均匀的屏幕显示，提高了显示品质。
图15为本公开示例性实施例另一种引出线和数据扇出线的结构示意图。如图15所示，显示区域100中的多条数据线、多条数据扇出线以及绑定区域的引线区501中的多条引出线600可以相对于第一中心线O 1对称设置。
在示例性实施方式中，多条数据线DA和多条引出线600的结构可以与前述示例性实施例相近，这里不再赘述。
在示例性实施方式中，8条引出线可以与8条数据扇出线对应连接，8条数据扇出线可以与8条数据线对应连接，使得引出线通过数据扇出线将数据信号提供给数据线。
在示例性实施方式中，任意一条数据扇出线在显示区域100内具有延伸长度L2，延伸长度L2可以满足：
|L2i-L2j|/L2i≤0.2，或者|L2i-L2j|/L2j≤0.2；
其中，L2i为显示区域内一条数据扇出线的延伸长度，L2j为显示区域内另一条数据扇出线的延伸长度。
在示例性实施方式中，对于折线状的数据扇出线，数据扇出线的延伸长度可以是组成数据扇出线的各个线段之和。
下面以显示基板左侧包括8(即N＝8)条数据线DA、8条数据扇出线700和8条引出线600为例进行说明。
在示例性实施方式中，第i数据扇出线可以包括第一线段和第二线段。第一线段的第一端位于显示区域边缘B，与第i引出线连接，第一线段的第二端沿着第二方向D2的反方向延伸后，与第二线段的第一端连接。第二线段的第二端沿着第一方向D1延伸后，与第i数据线连接，i＝1，2，…….，8。
在示例性实施方式中，第一线段可以包括引出段和第一延伸段。引出段的第一端位于显示区域边缘B，与第i引出线连接，引出段的第二端沿着第一方向D1延伸后，与第一延伸段的第一端连接。第一延伸段的第二端沿着第二方向D2的反方向延伸到后，与第二线段的第一端连接。
在示例性实施方式中，第二线段可以包括第二延伸段和连接段。第二延伸段的第一端与第一线段的第二端连接，第二延伸段的第二端沿着第一方向D1延伸后，与连接段的第一端连接。连接段的第二端沿着第二方向D2的反方向延伸后，与第i数据线连接。
在示例性实施方式中，第i数据扇出线的延伸长度L2i＝引出段沿着第一方向D1的延伸长度+第一延伸段沿着第二方向D2的反方向的延伸长度+第二延伸段沿着第一方向D1的延伸长度+连接段沿着第二方向D2的反方向的延伸长度。
在示例性实施方式中，任意一条引出线在基底上的正投影与其它引出线在基底上的正投影没有重叠区域，任意一条数据扇出线在基底上的正投影与其它数据扇出线在基底上的正投影没有重叠区域。
本示例性实施例中，数据线、数据扇出线和引出线的膜层结构可以与前述示例性实施例相近，这里不再赘述。
本公开示例性实施例可以实现前述实施例的技术效果，包括有效缩减了下边框宽度，有效避免了两个膜层的尺寸偏差，有效提高了显示均一性和显示品质。当不同数据扇出线的延伸长度相差很大时，会使得不同数据扇出线的电阻差异很大，这种电阻差异会造成显示问题，如两边颜色与中间颜色差异、闪烁画面发粉等。本公开通过设置数据扇出线的延伸长度基本上相近，使得多条数据扇出线的电阻基本上相近，多条数据扇出线的电阻压降差异很小，可以实现更加均匀的屏幕显示，提高了显示品质。
虽然前述示例性实施例以多条引出线沿着第二方向D2按照编号依次递增的排布方式进行了说明，但本公开中，多条引出线的排布方式可以采用其它方式。例如，多条引出线可以采用沿着第二方向D2按照编号依次递减的排布方式。又如，多条引出线可以分为至少两个引线组，一个引线组可以沿着第二方向D2的反方向按照编号依次递增的排布方式，另一个引线组可以沿着第二方向D2按照编号依次递增的排布方式，且两个引线组中的引出线交替设置，本公开在此不做限定。
图16为本公开示例性实施例一种显示区域中像素岛的排布示意图，图 17为本公开示例性实施例一个像素岛中压缩排布的示意图。如图16和图17所示，显示区域可以包括规则排布的多个像素岛PD，每个像素岛PD可以包括多个子像素。在平行于显示基板的平面内，至少一个像素岛PD可以包括电路子区800和布线子区900，电路子区800配置为容置该像素岛PD中多个子像素的像素驱动电路，布线子区900配置为容置数据扇出线。
在示例性实施方式中，在垂直于显示基板的平面上，每个子像素可以至少包括设置在基底上的驱动电路层以及设置在驱动电路层远离基底一侧的发光结构层，驱动电路层可以包括像素驱动电路40，像素驱动电路40可以由多个晶体管和存储电容构成，发光结构层可以包括发光器件50，发光器件50可以由阳极、有机发光层和阴极构成，发光器件50与像素驱动电路40连接，在像素驱动电路40的驱动下发出相应亮度的光。
一种显示基板中，每个子像素的像素驱动电路和发光器件采用对位设置的方式，发光器件位于本子像素的像素驱动电路的正上方，发光器件在基底上的正投影位于像素驱动电路在基底上的正投影的范围之内，即像素驱动电路的阵列周期与发光器件的阵列周期相同。由于显示区域中的多个子像素均匀排布，因而显示区域中的多个像素驱动电路均匀排布，多个发光器件均匀排布。本公开示例性实施例中，像素岛PD内每个子像素的像素驱动电路和发光器件错位设置，利用压缩每个子像素像素驱动电路的占用面积，为数据扇出线提供容置空间。
图16和图17中，每个矩形表示每个子像素的像素驱动电路40所占用的区域，每个六边形表示每个子像素的发光器件50(阳极)所占用的区域。在示例性实施方式中，像素岛PD内的多个发光器件50在像素岛PD区域内均匀排布，与发光器件在像素岛PD区域内均匀设置的传统排布方式相比，本公开示例性实施例发光器件的设置位置和占用面积与发光器件传统排布方式相同，为正常排布，在显示区域内，形成一种连续的发光器件阵列，不仅可以保证正常的画面显示，而且不需要引入新的掩膜板。在示例性实施方式中，像素岛PD内的多个像素驱动电路40在电路子区800内均匀排布，与像素驱动电路在像素岛PD区域内均匀设置的传统排布方式相比，本公开示例性实施例像素驱动电路的设置位置和占用面积与像素驱动电路传统排布方式不 同，为压缩排布，在显示区域内，形成一种非连续的像素驱动电路阵列。这样，像素岛PD内多个像素驱动电路40所占用的区域小于多个发光器件50所占用的区域，可以在驱动电路层中形成容置数据扇出线的布线子区900。
图18a至图18b为本公开示例性实施例一种压缩排布的示意图。在示例性实施方式中，一个像素岛可以包括4个子像素。正常排布时，每个子像素的像素驱动电路40和发光器件50对位设置，发光器件50位于本子像素的像素驱动电路40的正上方，发光器件50在基底上的正投影位于像素驱动电路40在基底上的正投影的范围之内，如图18a所示。本公开示例性实施例压缩排布时，发光器件50仍在像素岛内均匀设置，与正常排布相同，但像素岛中的4个像素驱动电路40被压缩设置在电路子区800内，从而在像素岛第一方向D1的一侧和第二方向D2的一侧均形成一个布线子区900，如图18b所示。这样，像素岛内的4个像素驱动电路40和4个发光器件50错位设置，但4个像素驱动电路40和4个发光器件50对应连接。
在示例性实施方式中，像素岛在第一方向D1和第二方向D2均进行了压缩，在第一方向D1，电路子区800所占用的宽度可以约为子像素宽度的10％至30％，在第二方向D2，电路子区800所占用的长度可以与3个子像素的长度相当。
图19a至图19b为本公开示例性实施例另一种压缩排布的示意图。在示例性实施方式中，一个像素岛可以包括8个子像素。正常排布时，每个子像素的像素驱动电路40和发光器件50对位设置，发光器件50位于本子像素的像素驱动电路40的正上方，发光器件50在基底上的正投影位于像素驱动电路40在基底上的正投影的范围之内，如图19a所示。本公开示例性实施例压缩排布时，发光器件50仍在像素岛内均匀设置，与正常排布相同，但像素岛中的8个像素驱动电路40被压缩设置在电路子区800内，从而在像素岛第二方向D2的一侧均形成一个布线子区900，如图19b所示。这样，像素岛内的8个像素驱动电路40和8个发光器件50错位设置，但8个像素驱动电路40和8个发光器件50对应连接。
在示例性实施方式中，像素岛可以仅在第二方向D2进行了压缩，在第二方向D2，电路子区800所占用的长度可以与7个子像素的长度相当。
在示例性实施方式中，显示区域内各个像素岛所包含子像素的数量可以相同，或者可以不同。例如，显示区域内的多个像素岛中，一部分像素岛可以包括8个子像素，另一部分像素岛可以包括16个子像素。显示区域内像素岛的大小可以根据实际需要进行进行设置，本公开在此不做限定。
在示例性实施方式中，显示区域内各个像素岛的压缩方式可以相同，或者可以不同。例如，显示区域内的多个像素岛中，一部分像素岛可以在第一方向进行压缩，另一部分像素岛可以在第二方向进行压缩，又一部分像素岛可以在第一方向和第二方向进行压缩，电路子区可以设置在像素岛的一侧，或者设置在像素岛的多侧，本公开在此不做限定。
在示例性实施方式中，布线子区可以位于电路子区第一方向的一侧，或者，布线子区可以位于电路子区第一方向的反方向的一侧，布线子区可以位于电路子区第二方向的一侧，或者，布线子区可以位于电路子区第二方向的反方向的一侧。
图20和图21为本公开示例性实施例一种数据扇出线排布的示意图。如图20和图21所示，显示区域可以包括规则排布的多个像素岛，每个像素岛内可以设置多个像素驱动电路40和发光器件50，至少一个像素岛可以包括电路子区和布线子区，多个布线子区在显示区域内组成布线区。在示例性实施方式中，布线区可以包括至少一个沿着第一方向D1延伸的第一布线区110和至少一个沿着第二方向D2延伸的第二布线区120。
在示例性实施方式中，数据扇出线700可以设置在第一布线区110和第二布线区120内。数据扇出线700的第一端与引线区的引出线连接，数据扇出线700的第二端沿着第一布线区110和第二布线区120延伸，并与相应的数据线DA对应连接。
在示例性实施方式中，通过压缩像素驱动电路所形成的布线区具有一定的宽度，因而一个第一布线区110或一个第二布线区120可以布置多条数据扇出线700，不仅可以减小数据扇出线排布设计的难度，而且有利于控制数据扇出线的延伸长度。
在示例性实施方式中，发光器件50为均匀排布，与发光器件传统排布方 式相同，因而部分发光器件50与布线区存在重叠区域，至少一个发光器件50在显示基板平面上的正投影与数据扇出线700在显示基板平面上的正投影存在重叠区域。
在示例性实施方式中，未设置数据扇出线700的第一布线区110或第二布线区120可以设置虚拟扇出线750，虚拟扇出线750可以沿着第一方向D1延伸，或者可以沿着第二方向D2延伸。本公开示例性实施例通过在闲置的第一布线区110或第二布线区120内设置虚拟扇出线750，可以提高显示基板制备工艺的均匀性，进而提高制备质量。
在示例性实施方式中，至少一个第一布线区110设置虚拟扇出线750的数量可以与其它第一布线区110设置数据扇出线700的数量相同，至少一个第二布线区120设置虚拟扇出线750的数量可以与其它第二布线区120设置数据扇出线700的数量相同。
本公开示例性实施例可以实现前述实施例的技术效果，包括有效缩减了下边框宽度，有效避免了两个膜层的尺寸偏差，有效提高了显示均一性和显示品质。本公开示例性实施例在保证正常画面显示的前提下，通过采用像素驱动电路压缩排布方式，在显示区域内形成了多个布线区，数据扇出线可以在布线区内延伸并连接相应的数据线，有效减小了数据扇出线排布设计的难度，提高了数据扇出线排布的整齐和有序，避免了重新设计子像素，避免了引入新的掩膜板，有效降低了设计和生产成本。
本公开示例性实施例还提供了一种显示基板的制备方法，所述显示基板包括显示区域和位于所述显示区域一侧的绑定区域，所述绑定区域至少包括引线区；所述制备方法包括：
在所述显示区域形成多条数据线和多条数据扇出线，在所述引线区形成多条引出线，多条数据线和多条数据扇出线在显示基板平面上的正投影至少部分重叠；至少一条数据扇出线的第一端与所述引出线连接，第二端向着远离引线区的方向延伸后与所述数据线连接。
本公开示例性实施例还提供了一种显示装置，包括前述实施例的显示基板。显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数 码相框、导航仪、广告面板、手表电话、电子书便携式多媒体播放器或物联网各种产品的显示屏等任何具有显示功能的产品或部件。在示例性实施方式中，显示装置可以为穿戴式显示装置，能通过某些方式佩戴在人体上，如智能手表、智能手环等。
本公开中的附图只涉及本公开涉及到的结构，其他结构可参考通常设计。在不冲突的情况下，本公开的实施例即实施例中的特征可以相互组合以得到新的实施例。
本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本公开的权利要求的范围当中。

Claims (20)

  1. 一种显示基板，包括显示区域和位于所述显示区域一侧的绑定区域，所述绑定区域至少包括引线区；所述显示区域包括多条数据线和多条数据扇出线，所述引线区包括多条引出线，多条数据线和多条数据扇出线在显示基板平面上的正投影至少部分重叠；至少一条数据扇出线的第一端与所述引出线连接，第二端向着远离引线区的方向延伸后与所述数据线连接。
  2. 根据权利要求1所述的显示基板，其中，所述数据扇出线的数量和所述数据线的数量相同。
  3. 根据权利要求1所述的显示基板，其中，在平行于显示基板的平面内，所述显示基板具有第一中心线，所述第一中心线沿着第一方向延伸并平分所述显示区域的像素列，所述第一方向与所述数据线平行；在所述第一中心线一侧，所述多条数据线包括沿着第二方向或者第二方向的反方向依次设置的第一数据线、第二数据线、……、第N数据线，所述第二方向与第一方向交叉；所述多条数据扇出线包括沿着第二方向或者第二方向的反方向依次设置的第一数据扇出线、第二数据扇出线、……、第N数据扇出线；所述多条引出线包括沿着第二方向或者第二方向的反方向依次设置的第一引出线、第二引出线、……、第N引出线；任意一条数据扇出线在显示基板平面上的正投影与其它数据扇出线在显示基板平面上的正投影没有重叠区域；任意一条引出线在显示基板平面上的正投影与其它引出线在显示基板平面上的正投影没有重叠区域；N为所述显示区域内数据线的数量。
  4. 根据权利要求1所述的显示基板，其中，至少一条数据扇出线包括第一线段和第二线段；所述第一线段的第一端与所述引出线连接，所述第一线段的第二端沿着第二方向或者第二方向的反方向延伸后，与所述第二线段的第一端连接；所述第二线段的第二端向着远离引线区的方向延伸后，通过过孔与所述数据线连接；所述第二方向与第一方向交叉，所述第一方向与所述数据线平行。
  5. 根据权利要求4所述的显示基板，其中，所述第一线段包括引出段和第一延伸段；所述引出段的第一端与所述引出线连接，所述引出段的第二 端向着远离引线区的方向延伸后，与所述第一延伸段的第一端连接；所述第一延伸段的第二端沿着第二方向或者第二方向的反方向延伸后，与所述第二线段的第一端连接，相邻引出段之间的间距小于相邻数据线之间的间距。
  6. 根据权利要求5所述的显示基板，其中，所述引线区中多条引出线的宽度相同，相邻引出线之间的间距相同，相邻引出线之间的间距小于相邻数据线之间的间距。
  7. 根据权利要求5所述的显示基板，其中，所述第二线段包括第二延伸段和连接段；所述第二延伸段的第一端与所述第一线段的第二端连接，所述第二延伸段的第二端向着远离引线区的方向延伸后，与所述连接段的第一端连接；所述连接段的第二端沿着第二方向或者第二方向的反方向延伸后，通过过孔与所述数据线连接。
  8. 根据权利要求4所述的显示基板，其中，在平行于显示基板的平面内，所述显示基板具有第二中心线，所述第二中心线沿着所述第二方向延伸并平分所述显示区域的像素行；任意一条数据扇出线与所述数据线连接的过孔，与所述第二中心线具有距离L1，所述距离L1满足：
    L1≤0.2*显示区域内数据线的长度；
    其中，所述长度和距离为所述第一方向上的尺寸。
  9. 根据权利要求8所述的显示基板，其中，多个所述数据扇出线与所述数据线连接的过孔位于所述第二中心线上。
  10. 根据权利要求4所述的显示基板，其中，任意一条数据扇出线在所述显示区域内具有延伸长度L2，所述延伸长度L2满足：
    |L2i-L2j|/L2i≤0.2，或者|L2i-L2j|/L2j≤0.2；
    其中，L2i为所述显示区域内一条数据扇出线的延伸长度，L2j为所述显示区域内另一条数据扇出线的延伸长度，所述数据扇出线的延伸长度为所述第一线段的延伸长度和第二线段的延伸长度之和。
  11. 根据权利要求10所述的显示基板，其中，多个所述数据扇出线与所述数据线连接的过孔，与所述第二中心线的距离不同。
  12. 根据权利要求1至11任一项所述的显示基板，其中，在垂直于显示基板的平面内，所述显示基板包括第一导电层、第二导电层和第三导电层，所述第一导电层和所述第二导电层之间、所述第二导电层和所述第三导电层之间均设置有绝缘层；所述数据线和数据扇出线设置在不同的导电层中。
  13. 根据权利要求12所述的显示基板，其中，所述数据扇出线包括奇数数据扇出线和偶数数据扇出线，所述奇数数据扇出线与奇数列的数据线连接，所述偶数数据扇出线与偶数列的数据线连接；所述奇数数据扇出线和偶数数据扇出线设置在不同的导电层中。
  14. 根据权利要求13所述的显示基板，其中，所述引出线包括奇数引出线和偶数引出线，所述奇数引出线通过所述奇数数据扇出线与奇数列的数据线连接，所述偶数引出线通过所述偶数数据扇出线与偶数列的数据线连接；所述奇数引出线与所述奇数数据扇出线同层设置，且为相互连接的一体结构，所述偶数引出线与所述偶数数据扇出线同层设置，且为相互连接的一体结构。
  15. 根据权利要求13所述的显示基板，其中，所述奇数数据扇出线设置在所述第一导电层，所述偶数数据扇出线设置在所述第二导电层，所述数据线设置在所述第三导电层；或者，所述偶数数据扇出线设置在所述第一导电层，所述奇数数据扇出线设置在所述第二导电层，所述数据线设置在所述第三导电层；所述第一导电层的材料和所述第二导电层的材料相同。
  16. 根据权利要求1至11任一项所述的显示基板，其中，在平行于显示基板的平面内，所述显示基板包括多个像素岛，所述像素岛包括多个子像素；在垂直于显示基板的平面内，所述子像素包括设置在基底上的驱动电路层和设置在所述驱动电路层远离基底一侧的发光结构层，所述驱动电路层包括像素驱动电路，所述发光结构层包括与所述像素驱动电路连接的发光器件；
    至少一个像素岛包括电路子区和布线子区，所述电路子区设置所述像素岛中多个子像素的像素驱动电路，所述布线子区内设置所述数据扇出线。
  17. 根据权利要求16所述的显示基板，其中，所述像素岛中至少一个发光器件在显示基板平面上的正投影与所述数据扇出线在显示基板平面上的正投影存在重叠区域。
  18. 根据权利要求16所述的显示基板，其中，所述布线子区内还设置有虚拟扇出线。
  19. 一种显示装置，包括如权利要求1至18任一项所述的显示基板。
  20. 一种显示基板的制备方法，所述显示基板包括显示区域和位于所述显示区域一侧的绑定区域，所述绑定区域至少包括引线区；所述制备方法包括：
    在所述显示区域形成多条数据线和多条数据扇出线，在所述引线区形成多条引出线，多条数据线和多条数据扇出线在显示基板平面上的正投影至少部分重叠；至少一条数据扇出线的第一端与所述引出线连接，第二端向着远离引线区的方向延伸后与所述数据线连接。
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