WO2022152223A1 - 电极结构、显示面板及电子设备 - Google Patents

电极结构、显示面板及电子设备 Download PDF

Info

Publication number
WO2022152223A1
WO2022152223A1 PCT/CN2022/071870 CN2022071870W WO2022152223A1 WO 2022152223 A1 WO2022152223 A1 WO 2022152223A1 CN 2022071870 W CN2022071870 W CN 2022071870W WO 2022152223 A1 WO2022152223 A1 WO 2022152223A1
Authority
WO
WIPO (PCT)
Prior art keywords
electrode
strips
strip
connection
conductive connection
Prior art date
Application number
PCT/CN2022/071870
Other languages
English (en)
French (fr)
Other versions
WO2022152223A9 (zh
Inventor
陈晓晓
胡杨
陈创
郭远辉
江鹏
石侠
高玉杰
朱宁
李云
刘建涛
Original Assignee
京东方科技集团股份有限公司
武汉京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CN202110041652.XA external-priority patent/CN114764204A/zh
Priority claimed from PCT/CN2021/083044 external-priority patent/WO2022198578A1/zh
Priority claimed from PCT/CN2021/085622 external-priority patent/WO2022213256A1/zh
Application filed by 京东方科技集团股份有限公司, 武汉京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/764,734 priority Critical patent/US20230185141A1/en
Priority to KR1020237003286A priority patent/KR20230127198A/ko
Priority to EP22739099.4A priority patent/EP4145215A4/en
Priority to JP2022574146A priority patent/JP2024502220A/ja
Priority to CN202280000135.0A priority patent/CN115702380A/zh
Publication of WO2022152223A1 publication Critical patent/WO2022152223A1/zh
Publication of WO2022152223A9 publication Critical patent/WO2022152223A9/zh

Links

Images

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G02F1/13394—Gaskets; Spacers; Sealing of cells spacers regularly patterned on the cell subtrate, e.g. walls, pillars
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G02F1/133707—Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/50—Protective arrangements

Definitions

  • Embodiments of the present disclosure relate to the field of display technology, and in particular, to an electrode structure, a display panel, and an electronic device.
  • Embodiments of the present disclosure provide an electrode structure, a display panel, and an electronic device.
  • the first electrode portion and the second electrode portion of the electrode structure By designing the first electrode portion and the second electrode portion of the electrode structure to have semi-open first slits and second slits, respectively,
  • the liquid crystal molecules can also be deflected at the openings of the first slit and the second slit, and the first slit and the second slit are in a semi-open state, which can also improve the light efficiency around the electrode structure, and at least to a certain extent can overcome the problems caused by the related art. one or more problems caused by limitations and defects.
  • the display panel includes an array substrate and an opposite substrate arranged in a cell: the array substrate includes a first substrate and a pair of substrates formed on the first substrate close to the pair. Scan lines, data lines, first blocking walls and second blocking walls on one side of the substrate; the data lines extend in a first direction, the scan lines extend in a second direction, and the first direction and all The second direction intersects; the first blocking wall and the second blocking wall are respectively located on opposite sides of the scan line in the first direction, and the first blocking wall and the second blocking wall are Each of the walls includes a first barrier layer arranged on the same layer as the scan lines and spaced from each other, and a second barrier layer arranged on the same layer as the data lines and separated from each other, and the second barrier layer is on the first substrate.
  • the opposite substrate includes a second substrate and a The spacer on the side of the second substrate close to the array substrate, the surface of the spacer close to the first substrate is the top surface, and the top surface of the spacer is on the first substrate
  • the orthographic projection on the bottom is located within the orthographic projection of the scan line on the first substrate and between the orthographic projections of the first retaining wall and the second retaining wall on the first substrate ; and the size of the top surface of the spacer in the first direction is greater than the first spacing.
  • a ratio between a size of the top surface of the spacer in the first direction and the first spacing is greater than or equal to 2.
  • a distance between the second barrier layer and the spacer in the first direction is a third distance, and the third distance is a distance from the spacer
  • the ratio between the dimensions of the top surface of the pad in the first direction is greater than or equal to 0.5.
  • a ratio between the third distance and the size of the top surface of the spacer in the first direction is greater than or equal to 1.
  • the ratio between the third pitch and the size of the data line in the second direction is 2 to 4.
  • the orthographic projection of the second barrier layer on the first substrate is located at the orthographic projection of the first barrier layer on the first substrate inside, and the first direction is perpendicular to the second direction.
  • the array substrate further includes a first common line formed on the first substrate and extending in the second direction, the first common line and the scanning lines are arranged in the same layer and spaced apart from each other; and the first barrier layer of the second barrier wall is a part of the structure of the first common line.
  • the array substrate further includes a plurality of sub-pixel units, which are arrayed on the first substrate along the second direction and the first direction;
  • Each of the sub-pixel units includes a pixel electrode, a common electrode and a transistor: the transistor includes a gate, a first electrode and a second electrode, the gate is connected to the scan line, and the first electrode is connected to the The pixel electrode is connected, the second electrode is connected to the data line; the orthographic projection of the common electrode on the first substrate overlaps with the orthographic projection of the pixel electrode on the first substrate , and the common electrode is connected to the first common line.
  • the pixel electrode is located on a side of the common electrode away from the first substrate, and the pixel electrode includes: a first electrode part, which is included in the A first connection strip extending in a first direction and a plurality of first electrode strips arranged at intervals in the first direction, the first connection strip having opposite first sides and a second electrode in the second direction On two sides, the plurality of first electrode strips are located on the first side of the first connection strip and are connected to the first connection strip, and the adjacent first electrode strips are far from the first connection strip.
  • the second electrode part is spaced apart from the first electrode part in the first direction, and the second electrode part includes a second connection extending in the first direction strips and a plurality of second electrode strips spaced in the first direction, the second connection strips are located at a position away from the second side from the first side, and the second connection strips have the third side and the fourth side opposite in the second direction, the third side is located at the position of the fourth side close to the first side; the plurality of second electrode strips are located at the second connection strip
  • the third side of the electrode is connected to the second connection bar, and the ends of the adjacent second electrode bars away from the second connection bar are in an opening shape;
  • the conductive connection part is located at the first electrode between the second electrode part and the second electrode part, the two ends of the conductive connection part are respectively connected with the first connection bar and the second connection bar; and the area of the conductive connection part is larger than that of the first electrode the area of the strip and the area of the second electrode strip.
  • the conductive connecting portion includes first conductive connecting strips and second conductive connecting strips that are spaced apart in the second direction and both extend in the first direction.
  • the first electrode strips, the second electrode strips, and the third conductive connecting strips all extend in a third direction, and the first electrode strips , the first widths of the second electrode strips and the third conductive connection strips are equal; wherein, the first width is the dimension in the fourth direction, and the third direction is perpendicular to the fourth direction, And the third direction intersects the first direction and the second direction.
  • the array substrate further includes: a second common line disposed in the same layer as the data line and spaced apart from each other, and the second common line is in the first extending in the first direction, and two ends of the second common line are respectively connected to the common electrodes of the two adjacent sub-pixel units in the first direction through the first via structure.
  • the first via structure includes a first via portion, a second via portion, and a via connection portion, and the via connection portion is connected to the pixel.
  • the electrodes are arranged on the same layer and spaced apart from each other, the via connection portion is connected to the second common line through the first via portion, and the via connection portion is connected to the common electrode via the second via portion connect.
  • At least one embodiment of the present disclosure further provides an electronic device, which includes the display panel in any of the foregoing embodiments.
  • At least one embodiment of the present disclosure further provides an electrode structure, the electrode structure includes a first electrode part and a second electrode part spaced in a first direction, and the first electrode part and the second electrode are located in the first electrode part and the second electrode part.
  • connection bar has a first side and a second side opposite in the second direction, and the plurality of first electrode bars are located on the first side of the first connection bar and connected to the first connection bar and are adjacent to the first connection bar
  • the ends of the first electrode strips away from the first connecting strips are in the shape of openings;
  • the second electrode parts include a second connecting strip extending in the first direction and a second connecting strip extending in the first direction.
  • a plurality of second electrode strips are arranged at intervals in the direction, the second connection strips are located at a position away from the second side from the first side, and the second connection strips have opposite sides in the second direction.
  • the third side and the fourth side, the third side is located at the position of the fourth side close to the first side; the plurality of second electrode strips are located on the third side of the second connection strip and are connected with all the The second connection strips are connected, and the ends of the adjacent second electrode strips away from the second connection strips are in an opening shape; the two ends of the conductive connection parts are respectively connected to the first connection strips. connected to the second connecting bar.
  • the area of the conductive connection portion is larger than the area of the first electrode strip, and is larger than the area of the second electrode strip.
  • the area of the first electrode portion and the area of the second electrode portion are both larger than the area of the conductive connection portion.
  • the conductive connecting portion includes first conductive connecting strips and second conductive connecting strips that are spaced apart in the second direction and both extend in the first direction.
  • the first electrode strips, the second electrode strips, and the third conductive connecting strips all extend in a third direction, and the first electrode strips , the first widths of the second electrode strips and the third conductive connection strips in the fourth direction are equal; the third direction is perpendicular to the fourth direction, and the third direction and the first The direction intersects the second direction.
  • ends of the adjacent first electrode strips that are far away from the first connection strips are not connected to each other;
  • the ends of the second connecting bars are not connected to each other.
  • first gaps between adjacent first electrode strips there are first gaps between adjacent first electrode strips, the first electrode strips and the first gaps extend in the same direction, and the first electrode strips extend in the same direction.
  • the first slit is semi-open; there is a second slit between the adjacent second electrode strips, the second electrode strip and the second slit extend in the same direction, and the second slit is semi-open ;
  • the opening directions of the first slit and the second slit are opposite.
  • the first widths of the first electrode strips and the second electrode strips in the fourth direction are equal, and the first slits are in the fourth direction.
  • the first width in the fourth direction is equal to the first width of the second slit in the fourth direction.
  • the first width of the first slit in the fourth direction is a difference of the first width of the first electrode strip in the fourth direction. 1 to 4 times.
  • a first width of the first electrode strip in the fourth direction and a first width of the second electrode strip in the fourth direction Both are 1.8 ⁇ m to 3 ⁇ m; the first width of the first slit in the fourth direction and the first width of the second slit in the fourth direction are both 3 ⁇ m to 7 ⁇ m.
  • a third gap is formed between adjacent third conductive connecting strips, and the periphery of the third gap is closed.
  • the conductive connection portion includes a plurality of the third slits.
  • the first width of the third conductive connection strip in the fourth direction is the same as the first width of the first electrode strip in the fourth direction
  • the widths are equal, and the first widths of the third slit, the first slit and the second slit in the fourth direction are equal.
  • the electrode structure provided in at least one embodiment of the present disclosure, there is a fourth gap between the third conductive connection strip and the adjacent first electrode strip, the third conductive connection strip and the There is a fifth slit between the adjacent second electrode strips, and the first slit, the second slit, the third slit, the fourth slit and the fifth slit are in the first slit.
  • the first widths in the four directions are equal.
  • the first width of the first electrode strip in the fourth direction and the entire width of the second electrode strip in the fourth direction is smaller than the first width of the entire conductive connection portion in the fourth direction.
  • the second width of the first connection strip in the second direction is the same as the second width of the second connection strip in the second direction equal; the second width of the first connection strip and the second connection strip in the second direction is greater than or equal to the width of the first electrode strip and the second electrode strip in the fourth direction first width.
  • the length of the first conductive connection strip in the first direction and the length of the second conductive connection strip in the first direction are both less than
  • the length of the first connecting strip in the first direction is smaller than the length of the second connecting strip in the first direction.
  • the length of the first connection strip in the first direction is smaller than the length of the second connection strip in the first direction.
  • the ratio of the length of the first connection strip in the first direction to the length of the second connection strip in the first direction is 0.1 ⁇ 0.9.
  • the first connection bar, the conductive connection portion and the second connection bar are connected in a zigzag shape as a whole, and one end of the first connection bar is connected to the One end of the conductive connection portion is connected, the other end of the conductive connection portion is connected to one end of the second connection bar, and the first connection bar and the second connection bar are located in the second direction. different sides of the conductive connections.
  • the second width of the first conductive connection strip in the second direction is the same as the second width of the first connection strip in the second direction.
  • the widths are equal, and the second width of the second conductive connection strip in the second direction is equal to the second width of the second connection strip in the second direction.
  • the conductive connection portion includes a conductive connection strip, and the conductive connection strip extends in a third direction, and the third direction is related to the first direction and the other direction.
  • the second direction intersects.
  • the third direction is perpendicular to the fourth direction, and the first width of the conductive connecting strip in the fourth direction is the same as that of the first electrode.
  • the ratio of the first widths of the strips in the fourth direction is 1.5 to 5.5.
  • the first width of the conductive connecting strip in the fourth direction is 5 ⁇ m to 10 ⁇ m, and the first electrode strip is in the fourth direction.
  • the upward first width is 1.8 ⁇ m to 3 ⁇ m.
  • the second width of the first connection strip in the second direction is the same as the second width of the second connection strip in the second direction are 2.3 ⁇ m to 2.7 ⁇ m
  • the first width of the conductive connection strips in the fourth direction is 2.5 ⁇ m to 3.0 ⁇ m
  • the first electrode strips and the second electrode strips are in the fourth direction.
  • the upward first widths are each 1.8 ⁇ m to 2.6 ⁇ m.
  • the second electrode portion further includes a signal connection portion, and the signal connection portion is located at a portion of the plurality of second electrode strips that is away from the conductive connection portion. side and connected with the second connecting bar.
  • the first connection strip and the second electrode strip are arranged in a mirror image with respect to the second direction.
  • FIG. 1 is a schematic plan view of an electrode structure
  • FIG. 2 is a schematic plan view of an electrode structure according to an embodiment of the present disclosure
  • FIG. 3 is a schematic plan view of still another electrode structure according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic partial cross-sectional structural diagram of a display panel according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic plan view of a display panel according to an embodiment of the present disclosure.
  • Fig. 6 is the enlarged structural representation of A part shown in Fig. 5;
  • FIG. 7 is a schematic cross-sectional structure diagram along the C-C direction in FIG. 6.
  • FIG. 8 is an enlarged schematic structural diagram of the first via structure in FIG. 5 .
  • Opposing substrate 40, blocking layer; 41, second substrate; 42, spacer;
  • Thin Film Transistor-Liquid Crystal Display (TFT-LCD) technology is a technology that combines microelectronics technology and liquid crystal display technology ingeniously. Those skilled in the art use the technology of microelectronics fine processing on silicon substrate (Si), and then transplant it to large-area glass to process Thin Film Transistor (TFT) arrays to form array substrates, and reuse matured
  • the liquid crystal display (Liquid Crystal Display, LCD) technology is used to align the array substrate with another substrate with a color filter layer (ie: the opposite substrate) to form a liquid crystal cell, and then go through the subsequent processes, such as sticking The process of covering the polarizer, etc., finally forms a liquid crystal display panel.
  • the liquid crystal cell also includes a photo spacer (Photo Spacer, PS for short), and the main function of the spacer is to support the liquid crystal cell, so that the cell thickness of each area of the liquid crystal display panel is consistent, and the Uniformity of brightness.
  • a photo spacer Photo Spacer, PS for short
  • the main function of the spacer is to support the liquid crystal cell, so that the cell thickness of each area of the liquid crystal display panel is consistent, and the Uniformity of brightness.
  • ADS Advanced Super Dimension Switch
  • IPS In-Plane Switching
  • the spacer will move.
  • the spacer may scratch the alignment film (ie: PI film) on the slit electrode (electrode structure with a slit), which will cause the alignment of the liquid crystal in this area to fail, resulting in light leakage during the operation of the display panel. Irregular bright spots are formed on the macro level, which in turn affects the quality of the product.
  • FIG. 1 is a schematic plan view of an electrode structure.
  • the pattern of the electrode structure 10 of the liquid crystal display panel is designed to have a slit 11 opened inside, and the periphery of the slit 11 is closed.
  • the light efficiency around the slit electrode 10 is poor, so that the problem of poor display is likely to occur.
  • Embodiments of the present disclosure provide an electrode structure, in which the first electrode part and the second electrode part are designed to have semi-open first slits and second slits, respectively, so that the first slits and the second slits
  • the liquid crystal molecules can also be deflected at the opening of the electrode, and the first slit and the second slit are in a semi-open state, which can also improve the light efficiency around the electrode structure, and at least to a certain extent, can overcome the limitations and defects of the related technology.
  • the electrode structure can be used in a liquid crystal display panel, and can be used as a pixel electrode or a common electrode of the liquid crystal display panel.
  • the material of the electrode structure is indium tin oxide, that is, the electrode structure may be an ITO (indium tin oxide) electrode, and the electrode structure has the property of light transmission.
  • FIG. 2 is a schematic plan view of an electrode structure according to an embodiment of the disclosure.
  • the electrode structure includes a first electrode part 20 and a conductive connection part arranged in sequence in the first direction Y 22 and the second electrode part 21, the first electrode part 20 may include a first connection strip 201 extending in the first direction Y and a plurality of first electrode strips 202 arranged at intervals in the first direction Y, the first The connection bar 201 has a first side 201a and a second side 201b opposite in the second direction X, a plurality of first electrode bars 202 are located on the first side 201a of the first connection bar 201 and are connected to the first connection bar 201, and The ends of the adjacent first electrode strips 202 away from the first connection strips 201 are open-shaped, that is, the ends of the adjacent first electrode strips 202 away from the first connection strips 201 are not connected to each other.
  • first electrode strips 202 are arranged at intervals in the first direction Y, that is to say, there are first gaps S1 between adjacent first electrode strips 202, and the first gap S1 is semi-open.
  • the second electrode part 21 includes a second connection bar 211 extending in the first direction Y and a plurality of second electrode bars 212 arranged at intervals in the first direction Y, the second connection The strip 211 is located at a position where the first side 201a is far from the second side 201b, the second connecting strip 211 has a third side 211a and a fourth side 211b opposite in the second direction X, and the third side 211a is located on the fourth side 211b close to the second side 211b.
  • the position of one side 201a it should be noted that the second direction X and the first direction Y are perpendicular to each other; a plurality of second electrode strips 212 are located on the third side 211a of the second connecting strip 211 and are connected to the second connecting strip 211, And the ends of the adjacent second electrode bars 212 away from the second connection bars 211 are open-shaped, that is, the ends of the adjacent second electrode bars 212 away from the second connection bars 211 are open to each other. no connection.
  • the aforementioned plurality of second electrode strips 212 are arranged at intervals in the first direction Y, that is to say, there are second gaps S2 between adjacent second electrode strips 212, and the second gap S2 semi-open.
  • the conductive connection portion 22 is located between the first electrode portion 20 and the second electrode portion 21 , and two ends of the conductive connection portion 22 are respectively connected to the first connection bar 201 and the second connection bar 211 .
  • the first electrode part 20 and the second electrode part 21 of the electrode structure are designed to have the semi-open first slit S1 and the second slit S2, respectively, the first slit S1 Liquid crystal molecules can also be deflected at the opening of the second slit S2, so compared with the closed electrode structure around the slit shown in FIG. 1, the light efficiency around the electrode structure can be improved.
  • the opening direction of one of the first slit S1 of the first electrode part 20 and the second slit S2 of the second electrode part 21 is to the right, and the opening direction of the other is to the left, that is, the first
  • the openings of the first slit S1 of the electrode part 20 and the second slit S2 of the second electrode part 21 are in opposite directions, so that the light on both sides of the electrode structure in the second direction X (ie, the left and right sides in FIG. 2 ) can be balanced. Therefore, the light effect around the electrode structure is more balanced, so as to improve the display effect.
  • the orthographic projections of the first electrode portion 20 , the second electrode portion 21 and the conductive connecting portion 22 on the reference plane are coincident with each other, and the coincidence mentioned here refers to completely within the allowable error range
  • This design can reduce the design difficulty of the electrode structure, thereby facilitating the arrangement of a plurality of electrode structures in the array substrate, but the embodiments of the present disclosure are not limited to this, the first electrode part 20 and the second electrode part 21 are electrically connected to the The orthographic projections of the portion 22 on the reference plane may also not coincide, depending on the specific situation.
  • the reference plane mentioned in the embodiments of the present disclosure is a plane perpendicular to the first direction Y.
  • the aforementioned first electrode strips 202 and the second electrode strips 212 may be parallel to each other, that is, the extension directions of the first electrode strips 202 and the second electrode strips 212 are parallel to each other, so as to balance the first electrodes part 20 and the light effect at the second electrode part 21 .
  • both the first electrode strips 202 and the second electrode strips 212 extend in the third direction Q, which intersects the first direction Y and the second direction X, that is, the third direction Q does not intersect with the first direction Y and the second direction X.
  • the first direction Y and the second direction X are parallel or collinear, which can reduce color shift and improve the display effect of the display panel when the electrode structure is used in the display panel.
  • the acute angle between the third direction Q and the second direction X may be 5° to 15°, such as: 5°, 7°, 9°, 11°, 13°, 15°, etc. , which is not limited by the embodiments of the present disclosure.
  • the first width of the first electrode strip 202 may be equal to the first width of the second electrode strip 212 .
  • the first width of the first slit S1 may be equal to the first width of the second slit S2, so that the light efficiency at the first electrode part 20 and the second electrode part 21 can be further balanced, so as to improve the use of the electrode structure for The display effect of the display panel when in the display panel.
  • the first width mentioned in the embodiments of the present disclosure refers to the dimension in the fourth direction P, and the fourth direction P and the third direction Q are perpendicular to each other.
  • the first electrode strips 202 The first width in the fourth direction P, the first width of the first slit S1 in the fourth direction P, the first width of the second electrode strip 212 in the fourth direction P, and the first width of the second slit S2 in the fourth direction
  • the first width on P needs to meet certain requirements, that is, the ratio of the first width of the first slit S1 in the fourth direction P to the first width of the first electrode strip 202 in the fourth direction P may be 1 to 4 , for example: 1, 1.5, 2, 2.5, 3, 3.5, 4, etc., which are not limited in the embodiments of the present disclosure.
  • the first widths of the first electrode strips 202 and the second electrode strips 212 in the fourth direction P may be 1.8 ⁇ m to 3 ⁇ m, such as: 1.8 ⁇ m, 2 ⁇ m, 2.2 ⁇ m, 2.4 ⁇ m, 2.6 ⁇ m ⁇ m, 2.8 ⁇ m, 3 ⁇ m, etc.; the first width of the first slit S1 and the second slit S2 in the fourth direction P may be 3 ⁇ m to 7 ⁇ m, such as: 3 ⁇ m, 3.5 ⁇ m, 4 ⁇ m, 4.5 ⁇ m, 5 ⁇ m, 5.5 ⁇ m , 6 ⁇ m, 6.5 ⁇ m, 7 ⁇ m and so on.
  • the first connection bar 201 is in the second direction X
  • the second width of , and the second width of the second connection bar 211 in the second direction X may be set to be equal.
  • the second width of the first connection strip 201 and the second connection strip 211 in the second direction X may be equal to the first width of the first electrode strip 202 and the second electrode strip 212 in the fourth direction P, but The embodiment of the present disclosure is not limited thereto, and the second widths of the first connection strips 201 and the second connection strips 211 in the second direction X may also be slightly larger than the first electrode strips 202 and the second electrode strips 212 in the fourth direction
  • the first width in the P direction can improve the light efficiency and also improve the first connection bar 201 caused by the first width of the first connection bar 201 and the second connection bar 211 in the fourth direction P being too small. and the problem of easy disconnection of the second connection bar 211, thereby improving the yield rate of the finally formed display panel.
  • the second width mentioned in the embodiments of the present disclosure is the dimension in the second direction X.
  • the first electrode part 20 and the second electrode part 21 of the above-mentioned electrode structure are connected by the conductive connection part 22, in order to avoid the conductive connection part 22 being affected by the impurity particles (Partical) during the manufacturing process.
  • the problem is, in the embodiment of the present disclosure, the area of the conductive connection portion 22 is designed to be larger, so as to avoid the problem of being easily disconnected, which may cause the pixel to fail.
  • the area of the conductive connection portion 22 is larger than that of the first electrode strip 202 and larger than that of the second electrode strip 212 .
  • the entirety of the conductive connection portion 22 may also extend in the third direction Q, so as to reduce the difficulty of processing and design.
  • the orthographic projection of the conductive connection portion 22 on the reference plane coincides with the orthographic projection of the first electrode portion 20 and the second electrode portion 21 on the reference plane, in order to make the area of the conductive connection portion 22 larger than that of the first electrode
  • the areas of the strips 202 and the second electrode strips 212 in one example, can be such that the first width of the first electrode strips 202 in the fourth direction P and the first width of the second electrode strips 212 in the fourth direction P are smaller than The first width of the entire conductive connection portion 22 in the fourth direction P.
  • the conductive connection part 22 can be a conductive connection bar 22a extending in the third direction Q, wherein the conductive connection bar 22a is in the fourth direction
  • the ratio of the first width on P to the first width of the first electrode strips 202 in the fourth direction P may be 1.5 to 5.5, that is, the conductive connection portion 22 is wider than the first electrode strips 202 processing, so as to improve the situation that the conductive connection portion 22 is easily broken, so as to ensure the quality of the finally formed display panel.
  • the first width of the conductive connection bar 22a in the fourth direction P may be 5 ⁇ m to 10 ⁇ m, for example: 5 ⁇ m, 6 ⁇ m, 7 ⁇ m, 8 ⁇ m, 9 ⁇ m, 10 ⁇ m, etc.
  • the second width of the first connection bar 201 in the second direction X and the second width of the second connection bar 211 in the second direction X are both 2.3 ⁇ m to 2.7 ⁇ m
  • the first width of 22 a in the fourth direction P is 2.5 ⁇ m to 3.0 ⁇ m
  • the first widths of the first electrode strips 202 and the second electrode strips 212 in the fourth direction P are both 1.8 ⁇ m to 2.6 ⁇ m.
  • the first connection strips 201 and the second electrode strips 212 are arranged in a mirror image with respect to the second direction X, which can simplify the process of preparing the electrode structure.
  • FIG. 3 is a schematic plan view of yet another electrode structure according to an embodiment of the disclosure.
  • the conductive connection portion 22 may include a first conductive connection bar 221 , a second conductive connection bar 222 and at least Two third conductive connection bars 223, wherein the first conductive connection bars 221 and the second conductive connection bars 222 both extend in the first direction Y, and the first conductive connection bars 221 and the second conductive connection bars 222 are in the first direction Y.
  • the first conductive connection bar 221 is connected to the first connection bar 201
  • the second conductive connection bar 222 is connected to the second connection bar 211
  • at least two third conductive connection bars 223 are in the first direction
  • the Y is spaced apart and located between the first conductive connection bar 221 and the second conductive connection bar 222, and the two ends of each third conductive connection bar 223 (ie, the two ends in the extending direction) are respectively connected with the first conductive connection bar 221 and the second conductive connection bar 222.
  • a conductive connection bar 221 is connected to the second conductive connection bar 222 , that is, a third gap S3 is formed between adjacent third conductive connection bars 223 , and the periphery of the third gap S3 is closed.
  • the number of the third slits S3 included in the conductive connection portion 22 is not limited, and the conductive connection portion 22 may also include a plurality of third slits S3.
  • the loss of light efficiency above the conductive connection portion 22 can be reduced, thereby improving the overall electrode structure.
  • the first electrode part 20 and the second electrode part 21 can be connected through at least two wires (ie, the third conductive connecting bar 223), so that even if the impurity particles cause one of the wires to be disconnected , there are still other wires connected to conduct the first electrode part 20 and the second electrode part 21 , so that the occurrence rate of pixel failure can be greatly reduced, that is, the yield rate of subsequent formation of the display panel can be improved.
  • the third conductive connecting strips 223 are arranged in two pieces, and while ensuring stable connection between the first electrode part 20 and the second electrode part 21, the conductive connection part 22 can be appropriately reduced in the electrode
  • the proportion in the structure can provide more design space for the first electrode part 20 and the second electrode part 21 , in other words, the area of the first electrode part 20 and the second electrode part 21 can be larger than that of the conductive connection part 22 area, since the first slit S1 in the first electrode portion 20 and the second slit S2 in the second electrode portion 21 are both semi-open design, and the third slit S3 in the conductive connecting portion 22 is a closed design, therefore,
  • the light efficiency of the first electrode part 20 and the second electrode part 21 is better than that of the conductive connection part 22 , so that the area of the first electrode part 20 and the second electrode part 21 is larger than that of the conductive connection part 22 , the overall light efficiency of the electrode structure can be improved, so that the quality of the display panel when the electrode structure is used in the display panel can
  • the third slit S3 is opened in the conductive connection part 22, the situation that the impurity particles adhere to the conductive connection part 22 during the process of fabricating the electrode structure can also be alleviated, so that the resistance value of the conductive connection part 22 can be alleviated due to the impurity particles.
  • the number of the third conductive connection strips 223 is not limited to two, but may also be set to three or four, depending on the specific situation, which is not limited in the embodiments of the present disclosure.
  • the length of the first conductive connection bar 221 and the length of the second conductive connection bar 222 may both be smaller than the length of the first connection bar 201 and the length of the second connection bar Length of bar 211. It should be understood that the length mentioned here is the dimension in the first direction Y. FIG.
  • the length of the first connection bar 201 in the first direction Y is smaller than the length of the second connection bar 211 in the first direction Y.
  • the ratio of the length of the first connection bar 201 in the first direction Y to the length of the second connection bar 211 in the first direction Y is 0.1 ⁇ 0.9, for example, the ratio is 0.1, 0.2 , 0.3, 0.4, 0.5, 0.6, 0.7, 0.8 or 0.9.
  • the first connection bar 201 , the conductive connection portion 22 and the second connection bar 211 are connected in a zigzag shape as a whole, and one end of the first connection bar 201 is connected to one end of the conductive connection portion 22 , the other end of the conductive connection part 22 is connected to one end of the second connection bar 211 , and the first connection bar 201 and the second connection bar 211 are located on different sides of the conductive connection part 22 in the second direction X.
  • the second width of the first conductive connection bar 221 in the second direction X may be equal to the second width of the first connection bar 201 in the second direction X, and the second conductive connection bar 222 in the second direction X
  • the second width of , and the second width of the second connection bar 211 in the second direction X may be equal.
  • the third conductive connection bar 223 may also extend in the third direction Q.
  • the first width of the third conductive connection bar 223 in the fourth direction P may be equal to the first width of the first electrode bar 202 in the fourth direction P.
  • first width of the third slits S3 between the adjacent third conductive connection strips 223 in the fourth direction P may be the same as the first width of the first slits S1 between the adjacent first electrode strips 202 in the fourth direction P
  • the first width of the second gap S2 between the adjacent second electrode strips 212 in the fourth direction P is equal, so that the conductive connection portion 22 can be balanced with the first electrode portion 20 and the second electrode
  • the light effect at the portion 21 can be improved to improve the display effect of the display panel when the electrode structure is used in the display panel.
  • a fourth gap S4 between the third conductive connection bar 223 and the first electrode bar 202 adjacent thereto, and between the third conductive connection bar 223 and the second electrode bar 212 adjacent thereto
  • a fifth slit S5, the fourth slit S4, the fifth slit S5 and the first slit S1, the second slit S2, the third slit S3 mentioned above in the fourth direction (P) are equal to the first width
  • the second electrode part 21 may further include a signal connection part 213 , and the signal connection part 213 may be located away from the conductive connection part of the plurality of second electrode strips 212 22 and connected with the second connecting bar 211 .
  • the signal connection portion 213 can be connected to a common line in the array substrate, that is, the signal connection portion 213 can be used to receive a common signal,
  • the embodiments of the present disclosure are not limited thereto.
  • the signal connection part 213 can also be connected to the source and drain electrodes of the transistors in the array substrate, and the signal connection part 213 is used to receive the signal transmitted from the source and drain electrodes. , for example: data signals.
  • FIG. 2 and FIG. 3 have no practical significance, and are only for distinguishing the aforementioned structures, so as to facilitate understanding of the positional relationship between the aforementioned structures.
  • the shape of the signal connection portion 213 is not limited to the shape shown in FIG. 2 and FIG. 3 , and may also be other shapes, depending on the specific situation, which is not limited by the embodiments of the present disclosure. It should also be noted that the electrode structure mentioned in the embodiments of the present disclosure is an integral structure as a whole.
  • FIG. 4 is a schematic partial cross-sectional structural diagram of a display panel provided by an embodiment of the present disclosure.
  • the display panel may include an array substrate 3 and an opposite substrate 4 arranged in a cell, and may also include The liquid crystal molecules 5 are located between the opposite substrate 4 and the array substrate 3 .
  • the display panel according to the embodiment of the present disclosure will be described in detail below with reference to FIGS. 2 to 8 .
  • the array substrate 3 may include a first substrate 30 and a plurality of sub-pixel units, a plurality of rows of scan lines 31 , a plurality of rows of first common lines 32 , and a plurality of columns formed on the first substrate 30 . data line 33.
  • FIG. 5 is a schematic plan view of a display panel according to an embodiment of the present disclosure.
  • the first substrate 30 may have lines along a row direction X (second direction) and a column direction Y (first direction direction) a plurality of sub-pixel regions 301 arranged in an array, a first wiring region 302 located between two adjacent rows of sub-pixel regions 301, and a second wiring region 303 located between two adjacent columns, the first wiring region 302 There is an overlap with the second wiring region 303 .
  • each sub-pixel unit includes a pixel electrode 34 located at least partially in the sub-pixel area 301 , a common electrode 35 , and a pixel electrode 35 located at least partially in the first wiring area 302 .
  • transistor 36 located at least partially in the first wiring area 302 .
  • the sub-pixel unit may further include a storage capacitor (not shown in the figure).
  • FIG. 6 is an enlarged schematic view of the structure of part A shown in FIG. 5 , and as shown in FIG. 5 and FIG. 6 , the transistor 36 may include an active layer 360 , a gate electrode 361 , and a first electrode 362 and a second electrode disposed in the same layer.
  • an insulating layer can be provided between the gate electrode 361 and the active layer 360 to insulate the gate electrode 361 and the active layer 360 from each other.
  • the insulating layer can be made of inorganic materials, for example, Inorganic materials such as silicon oxide and silicon nitride.
  • the gate electrode 361 may be disposed in the same layer as the scan line 31 , and the gate electrode 361 may belong to a part of the aforementioned scan line 31 .
  • the transistor 36 may be a top-gate thin film transistor or a bottom-gate thin film transistor.
  • the transistor 36 is mainly a bottom-gate thin film transistor as an example for description.
  • the gate 361 is formed on the first substrate 30, and the material of the gate 361 may include metal materials or alloy materials, for example, including molybdenum, aluminum, titanium, etc., to ensure its Good electrical conductivity.
  • An insulating layer is formed on the first substrate 30 and covers the gate electrode 361.
  • the insulating layer can be made of inorganic materials, such as inorganic materials such as silicon oxide and silicon nitride.
  • the active layer 360 is formed on the side of the insulating layer away from the first substrate 30, the first electrode 362 and the second electrode 363 are respectively connected to the two doped regions of the active layer 360, the first electrode 362 and the second electrode 363
  • the material can include metal materials or alloy materials, for example, a metal single-layer or multi-layer structure formed by molybdenum, aluminum and titanium, for example, the multi-layer structure is a multi-metal laminate layer, such as titanium, aluminum, titanium three-layer metal Laminate (Al/Ti/Al) etc.
  • the number of transistors 36 in the sub-pixel unit may be set to multiple, and the transistors 36 are further classified into N-type transistors and P-type transistors.
  • the pixel electrode 34 may be connected to the first electrode 362 , wherein the first electrode 362 of the transistor 36 may be the drain electrode, and the second electrode 363 may be the source electrode.
  • the first electrode 362 of the transistor 36 may be the source electrode
  • the second electrode 363 may be the drain electrode, depending on the specific situation
  • the orthographic projection of the common electrode 35 on the first substrate 30 may be There is an overlap with the orthographic projection of the pixel electrode 34 on the first substrate 30 .
  • the pixel electrode 34 and the common electrode 35 is the electrode structure described in any of the foregoing embodiments, so that the light efficiency around the pixel can be improved, and the quality of the display panel when the electrode structure is used in a display panel can be improved.
  • the row direction X mentioned in the embodiments of the present disclosure may be the aforementioned second direction X
  • the column direction Y may be the aforementioned first direction Y.
  • FIG. 7 is a schematic cross-sectional view of FIG. 6 along the C-C direction.
  • the first substrate 30 may be a single-layer structure, and the first substrate 30 may be a glass substrate.
  • the first substrate 30 can also be a multi-layer structure, and the material of the first substrate 30 is not limited to glass, and can also be other materials, such as polyimide (PI) and other materials, depending on Depends on the specific situation.
  • PI polyimide
  • the pixel electrode 34 may be located on the side of the common electrode 35 away from the first substrate 30 , that is, the common electrode 35 may be fabricated on the first substrate 35 prior to the pixel electrode 34 . on the substrate 30.
  • the common electrode 35 can be a plate-shaped electrode, that is, the common electrode 35 is a whole piece without slits, and the pixel electrode 34 can be the electrode structure described in any of the foregoing embodiments.
  • the electric field generated between the electrode and the common electrode 35 causes all the liquid crystal molecules between the electrodes and directly above the electrodes to be deflected, so that the working efficiency of the liquid crystal can be improved, and the light transmission efficiency can be increased.
  • the positional relationship between the pixel electrode 34 and the common electrode 35 is not limited to the aforementioned relationship.
  • the pixel electrode 34 may also be located near the first substrate of the common electrode 35 .
  • One side of the bottom 30, and the common electrode 35 is the electrode structure described in any of the foregoing embodiments, and the pixel electrode 34 is a plate electrode.
  • the pixel electrode 34 may be made of indium tin oxide (ITO) material, but the embodiment of the present disclosure is not limited thereto, and indium zinc oxide (ITO) can also be used.
  • ITO indium tin oxide
  • IZO indium tin oxide
  • ZnO zinc oxide
  • other transparent materials that is to say, since the material used for the pixel electrode 34 is different from the material of the gate 361, the first electrode 362 and the second electrode 363 of the transistor 36, the The pixel electrode 34 and the gate electrode 361 , the first electrode 362 and the second electrode 363 of the transistor 36 can be fabricated by using different patterning processes.
  • the common electrode 35 may be located on the side of the first electrode 362 and the second electrode 363 of the transistor 36 close to the first substrate 30 , and the common electrode 35 may be formed before the gate electrode 361 of the transistor 36 is formed It is formed on the first substrate 30, that is to say, when fabricating the array substrate, a patterning process can be used to form the common electrode 35 on the first substrate 30, and then another patterning process can be used to form the common electrode 35 on the first substrate 30.
  • the gate 361 of the transistor 36 is formed thereon. It should be noted that although the common electrode 35 and the gate electrode 361 are both formed on the first substrate 30, the common electrode 35 and the gate electrode 361 are disconnected from each other (ie, not connected). It should be understood that the common electrode 35 can also be formed on the first substrate 30 after the gate electrode 361 of the transistor 36 is formed, and the common electrode 35 can also be located on the side of the gate electrode 361 away from the first substrate 30, As the case may be.
  • the pixel electrode 34 can also be made of transparent conductive materials such as ITO.
  • the pixel electrode 34 can pass through the second via structure H2 Connected to the first pole 362 of the transistor.
  • the pixel electrode 34 can be connected to the first electrode 362 of the transistor through the signal connection portion 213 through the second via structure H2. It should be understood that this The signal connection part 213 may be located in the first wiring area 302 .
  • the slit opening directions of the first electrode portion 20 in the two adjacent pixel electrodes 34 in the first direction Y and the second direction X are opposite, and The slit openings of the second electrode portion 21 are opposite to each other.
  • each electrode structure in the array substrate 3 may be slightly different, for example, some electrode structures need to be designed to avoid other structures in the array substrate 3, etc., but it should be understood that although The overall shapes of the electrode structures in the array substrate 3 may not be exactly the same, but the overall design concept should be the same, that is, the first electrode portion 20 and the second electrode portion 21 are both semi-slit designs, and the conductive connection portion 22 is entirely in the The first width in the fourth direction P is greater than the first width of the first electrode strip 202 in the fourth direction P and the first width of the second electrode strip 212 in the fourth direction P.
  • At least one row of scan lines 31 may be located in one first wiring area 302 , in other words, at least one row of scan lines 31 may be provided in each first wiring area 302 , it should be understood that this scan line
  • the entirety of 31 can be seen as extending in the row direction X.
  • the scan line 31 is connected to the gate 361 of the transistor 36 in the sub-pixel unit.
  • the scan line 31 and the gate 361 of the transistor 36 can be arranged in the same layer and have an integral structure.
  • the scan line 31 is configured to be connected to the sub-pixel.
  • the unit provides the scan signal.
  • first common lines 32 may be located in one first wiring area 302 , in other words, each first wiring area 302 may be provided with at least one row of first common lines 32 , it should be understood that , the whole of the first common line 32 can be regarded as extending in the row direction X, and the first common line 32 can be connected with the common electrode 35, which is configured to provide a common signal to the sub-pixel unit.
  • the first common line 32 can be disposed on the same layer as the scan line 31, wherein the aforementioned common electrode 35 can be disposed on the first substrate 30 before the scan line 31. Therefore, in order to make the first common electrode 35
  • the line 32 is connected to the common electrode 35 , and in the process of manufacturing the first common line 32 , the first common line 32 and the common electrode 35 can be overlapped together.
  • each first wiring area 302 may be provided with a row of scan lines 31 and a row of first common lines 32. It should be understood that the scan lines 31 and the first common lines 32 are disconnected from each other. On, that is, the orthographic projection of the scan line 31 on the first substrate 30 does not overlap with the orthographic projection of the first common line 32 on the first substrate 30 . It should be noted that, the first wiring area 302 is not limited to one row of scan lines 31 and one row of first common lines 32, but also two rows of scan lines 31, or no first common line 32, etc., depending on the specific situation. Certainly, the embodiments of the present disclosure do not limit this. The embodiments of the present disclosure are mainly described with a row of scan lines 31 and a row of first common lines 32 disposed in each of the first wiring regions 302 .
  • At least one column of data lines 33 may be located in one second wiring area 303 , in other words, at least one column of data lines 33 is disposed in each second wiring area 303 , it should be understood that the The whole can be regarded as extending in the column direction Y, and the orthographic projection of the data line 33 on the first substrate 30 overlaps with the orthographic projection of the scan line 31 and the first common line 32 on the first substrate 30 .
  • the data line 33 may be connected to the second pole 363 of the transistor 36 in the sub-pixel unit, which is configured to provide a data signal to the sub-pixel unit.
  • the data line 33 in the embodiment of the present disclosure can be disposed in the same layer as the first electrode 362 and the second electrode 363 of the transistor 36 in the sub-pixel unit, that is, it can be fabricated by the same patterning process, so as to reduce the mask
  • the embodiments of the present disclosure are not limited to this, and can also be fabricated by using different patterning processes, depending on the specific situation.
  • a column of data lines 33 may be arranged in each second wiring area 303 , and the data lines 33 may be connected to the second poles 363 of the sub-pixel units in the same column, that is, the data lines 33 Data signals may be provided for the same column of sub-pixel units.
  • each column of data lines 33 may be symmetrically arranged with respect to the central axis. It should be noted that the central axis mentioned here is a line passing through the center of the data line 33 and extending in the column direction Y.
  • the distance between the first pole 362 of each sub-pixel unit and the data line 33 connected thereto in the row direction X is equal to ensure that the transistors 36 and data lines 33 of each sub-pixel unit in each column are The coupling capacitance between them is close to the same, thereby ensuring the uniformity of light efficiency at each sub-pixel unit in each column.
  • the first pole 362 of the column overlaps with the gate 361 The area needs to be consistent with the other columns.
  • the array substrate may further include second common lines 37 , and the second common lines 37 and the data lines 33 may be disposed at the same layer and spaced apart from each other.
  • the second common line 37 extends in the first direction Y
  • the middle part of the orthographic projection of the second common line 37 on the first substrate 30 is located in the first wiring area 302
  • two of the second common line 37 The ends are respectively located in the sub-pixel regions 301 .
  • both ends of the second common line 37 are respectively connected to the common electrodes 35 of two sub-pixels adjacent to each other in the first direction Y through the first via structure H1.
  • FIG. 8 is an enlarged schematic structural diagram of the first via structure in FIG. 5 .
  • the first via structure H1 includes a first via portion H11 , a second via portion H12 and a via connection portion H13 , the via hole connecting portion H13 and the pixel electrode 34 are arranged in the same layer and spaced apart from each other, the via hole connecting portion H13 is connected to the second common line 37 through the first via hole portion H11, and the via hole connecting portion H13 is connected to the second common line 37 through the second via hole portion H12.
  • the common electrode 35 is connected.
  • the opposite substrate 4 may further include a second substrate 41 and spacers 42 located on the side of the second substrate 41 close to the array substrate 3 and located close to the spacers 42 .
  • the shielding layer 40 on the side of the second substrate 41 may be provided for the specific structure of the second substrate 41.
  • the orthographic projection of the shielding layer 40 on the first substrate 30 may completely cover the first wiring area 302, the second wiring area 303 and at least part of the sub-pixel area 30, and a plurality of spacers 42 may be provided.
  • the arrangement of the spacer 42 can improve the uniformity of the overall thickness of the display panel, and can improve the tolerance of the display panel to fluctuations of liquid crystal molecules, thereby improving the yield of the display panel.
  • the plurality of spacers 42 may include a main spacer and an auxiliary spacer.
  • the display panel When the display panel is not subjected to external pressure, one end of the main spacer away from the second substrate 41 and the array substrate 3 contact, it mainly plays a supporting role, and when the display panel is not subjected to external pressure, there is a certain distance between the end of the auxiliary spacer away from the second substrate 41 and the array substrate 1, that is, There is a level difference (height difference) between the main spacer and the auxiliary spacer, and the thickness of the display panel can be fine-tuned by adjusting the level difference between the main spacer and the auxiliary spacer.
  • the height of the main spacer is greater than the height of the auxiliary spacer.
  • the main spacer first bears all the pressure and is compressed.
  • the main spacer is compressed to the point where the main spacer and the auxiliary spacer are compressed.
  • the main and auxiliary pads jointly bear the external pressure.
  • the two main spacers and the auxiliary spacers may be arranged according to a certain period.
  • the size and height of different types of spacers need to be monitored during the manufacturing process. Because the size of the spacer is small, and there are generally fewer main spacers, it is difficult for the equipment to accurately identify the position of the main spacer depending on the size alone. : do not set any spacers) to facilitate faster and more accurate identification of the position of the main spacer and monitor it. For example, in the design, no spacer is set under the main spacer. When monitoring, you can First quickly determine the position where no spacer is to be provided, and then the above-mentioned design rules can make it clear that the spacer at the upper position without any spacer is the main spacer.
  • the surface of the spacer 42 close to the first substrate 30 may be the top surface, and the surface away from the first substrate 30 may be the bottom surface, wherein, as shown in FIG. 5 , the orthographic projection of the top surface of the spacer 42 on the first substrate 30 is located within the orthographic projection of the scan line 31 on the first substrate 30 , that is, the top surface of the spacer 42 is on the first substrate 30
  • the outer contour of the orthographic projection of the scan line 31 is located on the inner side of the outer contour of the orthographic projection of the scan line 31 on the first substrate 30, thereby ensuring the flatness of the support of the spacers 42 to ensure that the spacers 42 are stably supported on the array. on the substrate 3.
  • the orthographic projections of the spacers 42 on the first substrate 30 in the embodiments of the present disclosure do not overlap with the orthographic projections of the data lines 33 and the transistors on the first substrate 30 .
  • the orthographic projection of the top surface of the spacer 42 on the first substrate 30 in the embodiment of the present disclosure may be located within the orthographic projection of the bottom surface of the spacer 42 on the first substrate 30, That is to say, the whole of the spacer 42 may be similar to a cone, but the embodiment of the present disclosure is not limited thereto.
  • the top surface of the spacer 42 is on the first substrate 30
  • the projection may also coincide exactly with the orthographic projection of the bottom surface of the spacer 42 on the first substrate 30, as the case may be.
  • the orthographic projection of the bottom surface of the spacer 42 on the first substrate 30 may be located within the orthographic projection of the scan line 31 on the first substrate 30, but the embodiments of the present disclosure are not limited thereto , the contour of the spacer 42 in the column direction Y may also exceed the contour of the scan line 31 in the column direction Y.
  • a blocking wall may be provided around the spacer 42 .
  • the orthographic projection of the spacer 42 on the first substrate 30 is located within the orthographic projection of the scan line 31 on the first substrate 30, and the scan line 31 is covered by the blocking layer 40, therefore, the spacer 42 Even if the movement occurs in the row direction X, it is still within the range covered by the blocking layer 40 and will not affect the display effect. Reduce design difficulty.
  • transistors are disposed on opposite sides of the spacers 42 in the row direction X, and the overall height of the region where the transistors are located in the array substrate 3 is greater than the overall height of the region where the spacers 42 are located, that is to say , the transistor can be used as a blocking wall to prevent the spacer 42 from slipping in the row direction X.
  • the blocking wall 38a and the second blocking wall 38b are respectively located on opposite sides of the scan line 31 in the column direction Y, wherein the orthographic projection of the spacer 42 on the first substrate 30 can be located on the first blocking wall 38a and the second blocking wall 38a. Between the orthographic projections of the blocking walls 38b on the first substrate 30; in other words, the first blocking walls 38a and the second blocking walls 38b may be provided on opposite sides of the spacer 42 in the column direction Y.
  • first blocking wall 38 a and the second blocking wall 38 b may be located in the sub-pixel region 301 ; the first blocking wall 38 a and the second blocking wall 38 b may be blocked by the blocking layer 40 .
  • both the first blocking wall 38a and the second blocking wall 38b include a first blocking layer 381 disposed on the same layer as the scan lines 31 and spaced from each other, and a second blocking layer 382 disposed on the same layer as the data lines 33 and spaced from each other.
  • the orthographic projection of the second barrier layer 382 on the first substrate 30 overlaps with the orthographic projection of the first barrier layer 381 on the first substrate.
  • the distance between the first barrier layer 381 and the scan line 31 in the first direction Y is the first distance W1
  • the distance between the second barrier layer 382 and the scan line 31 in the first direction Y is the first distance W1.
  • the spacing is the second spacing W2, which is greater than the first spacing W1; that is, the first barrier layer 381 is protruded toward the spacer 42 compared to the second barrier layer 382, and this The protruding part can play a supporting role when the spacer is moved by force, so as to relieve the situation that the spacer 42 falls into the gap between the scan line 31 and the first barrier layer 381 and cannot be restored to its original state.
  • the distance between the second barrier layer 382 and the spacer 42 is larger than the distance between the first barrier layer 381 and the spacer 42, so compared to the distance between the second barrier layer 382 and the spacer 42
  • the space between the spacers 42 and the space between the first barrier layer 381 and the spacers 42 are designed to be equal, and when the spacers 42 are subjected to the same external stress, the spacers 42 can be tilted at an angle becomes smaller, so that when the external stress on the spacer 42 is the force in the horizontal direction (for example: the first direction Y), the resistance in the vertical direction (that is, in the thickness direction of the display panel) can be reduced, at this time , it is more difficult for the spacers 42 to cross the blocking wall to scratch the alignment film in the light-transmitting area (ie, the area not covered by the shielding layer 40 in the sub-pixel area 301 ), that is, the risk of scratching the alignment film is reduced.
  • the spacers 42 can cross the blocking wall to scratch the alignment film
  • the surface of the spacer 42 close to the first substrate 30 may be the top surface, and the dimension W4 of the top surface of the spacer 42 in the first direction Y may be larger than the first There is a distance W1 to relieve the situation that the spacer 42 falls into the gap between the scan line 31 and the first barrier layer 381 during the movement and cannot be restored to its original state.
  • the ratio between the dimension W4 of the top surface of the spacer 42 in the first direction Y and the first distance W1 is greater than or equal to 2, so as to further relieve the spacer 42 from falling into the scanning line 31 and the first spacer during the moving process. In the case where the space between the barrier layers 381 cannot be restored to the original state.
  • the distance between the second barrier layer 382 and the spacer 42 in the first direction Y is the third distance W3, and the ratio between the third distance W3 and the size of the top surface of the spacer 42 in the first direction Y greater than or equal to 0.5, this design can reduce the risk of the spacer 42 passing over the retaining wall, thereby reducing the risk of scratching the alignment film at the light-transmitting area; further, the third distance W3 and the top surface of the spacer 42 are in the first The ratio between the dimensions W4 in the direction Y may be greater than or equal to 1.
  • the ratio between the third spacing W3 and the size of the data line 33 in the second direction X is 2 to 4; wherein the size of the data line 33 in the second direction X may be 5 ⁇ m to 7 ⁇ m, such as: 5 ⁇ m, 5.5 ⁇ m, 6 ⁇ m, 6.5 ⁇ m, 7 ⁇ m, etc.
  • the third spacing W3 may be 10 ⁇ m to 28 ⁇ m, such as: 10 ⁇ m, 13 ⁇ m, 17 ⁇ m, 21 ⁇ m, 25 ⁇ m, 28 ⁇ m and so on.
  • the orthographic projection of the aforementioned second barrier layer 382 on the first substrate 30 is located within the orthographic projection of the first barrier layer 381 on the first substrate 30, so that the first barrier can be guaranteed.
  • the film layer ie: the second barrier layer 382 ) that mainly plays a blocking role in the wall 38a and the second blocking wall 38b has a sufficient width in the first direction Y to better block the spacer 42 in the first direction Swipe up on Y. That is to say, as shown in FIG. 7 , the longitudinal sections of the first retaining wall 38a and the second retaining wall 38b in the embodiment of the present disclosure may appear to be “L”-shaped as a whole, and the longitudinal section here refers to the distance between the display panel and the display panel. A plane in which the thickness direction and the first direction Y are parallel.
  • first barrier layer 381 of the second barrier wall 38b may be a partial structure of the first common line 32 .
  • first spacing W1, the second spacing W2 between the second blocking wall 38b and the scan line 31, the third spacing W3 between the second blocking wall 38b and the spacer 42 and the first blocking wall The first distance W1, the second distance W2 between the scan line 38a and the scan line 31, and the third distance W3 between the first blocking wall 38a and the spacer 42 may be equal or unequal, depending on the specific situation.
  • the above-mentioned blocking layer 40 may also cover part of the sub-pixel area 301, specifically, may cover part of the common electrode 35 and part of the pixels electrode 34 .
  • the edge of the pixel electrode 34 is close to the scan line 31 and the data line 33 and there is a coupling electric field.
  • the liquid crystal arrangement will be disordered, resulting in a failure area, resulting in light leakage from the edge of the dark state pixel. Therefore, the shielding layer 40 is required for this part of the failure area. to block.
  • the blocking layer 40 may Cover the edge of the pixel electrode 34 by at least 5 ⁇ m. It should be noted that when the color filter layer is located on the opposite substrate, considering the accuracy of the upper and lower substrates, it needs to be wider, but it should not exceed 10 ⁇ m to avoid excessive influence on the pixels. opening rate.
  • a coupling electric field also exists between the data line 33 and the edge of the pixel electrode 34 , that is, a portion of the pixel electrode 34 close to the data line 33 in the embodiment of the present disclosure has a failure area.
  • the shielding layer 40 can cover the edge of the pixel electrode 34 by about 1 ⁇ m to shield the shadow area near the data line 33; If the liquid crystal molecules 5 are positive liquid crystal molecules, the coupled electric field between the data lines 33 and the pixel electrodes 34 will not cause obvious dark light leakage, but will cause the liquid crystal molecules to cause aggravation of the crosstalk phenomenon.
  • the layer 40 may cover the edge of the pixel electrode 34 by at least 6 ⁇ m to block the coupled electric field region.
  • the color filter layer used in the liquid crystal display panel may be located on the opposite substrate 4 or on the array substrate 3, depending on the specific situation.
  • liquid crystal display panels in the embodiments of the present disclosure can be used in display products with 4K resolution or 8K resolution.
  • Embodiments of the present disclosure also provide an electronic device including the display panel described in any of the above embodiments.
  • the specific type of the electronic device is not particularly limited, and any type of electronic device commonly used in the art can be used, such as liquid crystal displays, mobile devices such as mobile phones and laptop computers, wearable devices such as watches, VR The device, etc., can be selected by those skilled in the art according to the specific use of the display device, which will not be repeated here.
  • the electronic device also includes other necessary components and components. Taking the display as an example, it may also include a backlight module, a casing, a main circuit board, a power cord, etc. The specific usage requirements of the electronic device are supplemented accordingly, and details are not repeated here.
  • on may mean that one layer is directly formed or disposed on another layer, or may mean that a layer is formed directly on or disposed on another layer.
  • a layer is formed or disposed indirectly on another layer, ie there are other layers in between.
  • the term “same layer arrangement” is used to mean that two layers, components, components, elements or sections may be formed by the same patterning process, and that the two layers, components, components , elements or parts are generally formed of the same material.
  • patterning process generally includes steps of photoresist coating, exposure, development, etching, and photoresist stripping.
  • one-shot patterning process means a process of forming patterned layers, features, members, etc. using one mask.

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Geometry (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)

Abstract

本公开的实施例涉及一种电极结构、显示面板以及电子设备。该电极结构包括：在第一方向(Y)上间隔排布的第一电极部(20)和第二电极部(21)，以及位于所述第一电极部(20)与所述第二电极部(21)之间的导电连接部(22)，其中，所述第一电极部(20)包括在所述第一方向(Y)上延伸的第一连接条(201)以及在所述第一方向(Y)上间隔排布的多个第一电极条(202)，所述第一连接条(201)具有在第二方向(X)上相对的第一侧(201a)和第二侧(201b)，所述多个第一电极条(202)位于所述第一连接条(201)的第一侧(201a)并与所述第一连接条(201)连接，且相邻的所述第一电极条(202)中远离所述第一连接条(201)的端部之间呈开口状；所述第二电极部(21)包括在所述第一方向(Y)上延伸的第二连接条(211)以及在所述第一方向(Y)上间隔排布的多个第二电极条(212)，所述第二连接条(211)位于所述第一侧(201a)远离所述第二侧(201b)的位置，所述第二连接条(211)具有在所述第二方向(X)上相对的第三侧(211a)和第四侧(211b)，所述第三侧(211a)位于所述第四侧(211b)靠近所述第一侧(201a)的位置；所述多个第二电极条(212)位于所述第二连接条(211)的第三侧(211a)并与所述第二连接条(211)连接，且相邻的所述第二电极条(212)的远离所述第二连接条(211)的端部之间呈开口状；所述导电连接部(22)的两端分别与所述第一连接条(201)和所述第二连接条(211)连接，该电极结构的设计可以提高电极结构周围的光效，进而可以提高该电极结构用于显示面板中时显示面板的质量。

Description

电极结构、显示面板及电子设备
本申请要求于2021年1月13日递交的中国专利申请第202110041652.X号的优先权、2021年3月25日递交的PCT国际申请第PCT/CN2021/083044号的优先权、2021年4月6日递交的PCT国际申请第PCT/CN2021/085622号的优先权，在此全文引用上述中国专利申请以及PCT国际申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及显示技术领域，具体而言，涉及一种电极结构、显示面板及电子设备。
背景技术
随着液晶显示面板的不断发展，高分辨率的产品被不断开发，但随着像素的增多，容易导致一系列的问题发生，例如：在对液晶显示面板进行某些压力测试或跌落测试时，容易出现亮点、雪花等亮度不均匀的问题。此外，液晶显示面板中的电极结构极易在制造过程中受到杂质颗粒(Partical)的影响，极易形成断线等不良情况，从而导致像素失效，进而降低了液晶显示面板的良率，并影响了液晶显示面板的信赖性和产品质量。
发明内容
本公开的实施例提供一种电极结构、显示面板以及电子设备，通过将电极结构的第一电极部和第二电极部分别设计成具有呈半开放式的第一缝隙和第二缝隙，使得第一缝隙和第二缝隙开口处也可以发生液晶分子偏转，并且第一缝隙和第二缝隙呈半开放式状态，还可以提高电极结构周围的光效，进而至少在一定程度上可以克服由于相关技术的限制和缺陷而导致的一个或者多个问题。
本公开至少一实施例提供一种显示面板，该显示面板包括对盒设置的阵列基板和对置基板：所述阵列基板包括第一衬底及形成在所述第一衬底的靠 近所述对置基板一侧的扫描线、数据线、第一挡墙及第二挡墙；所述数据线在第一方向上延伸，所述扫描线在第二方向上延伸，所述第一方向与所述第二方向相交；所述第一挡墙和所述第二挡墙分别位于所述扫描线在所述第一方向上的相对两侧，且所述第一挡墙和所述第二挡墙均包括与所述扫描线同层设置并相互间隔的第一阻挡层和与所述数据线同层设置并相互间隔的第二阻挡层，所述第二阻挡层在所述第一衬底上的正投影与所述第一阻挡层在所述第一衬底上的正投影存在交叠；所述第一阻挡层与所述扫描线在所述第一方向上的间距为第一间距，所述第二阻挡层与所述扫描线在所述第一方向上的间距为第二间距，所述第二间距大于所述第一间距；所述对置基板包括第二衬底和位于所述第二衬底靠近所述阵列基板一侧的隔垫物，所述隔垫物靠近所述第一衬底的表面为顶表面，所述隔垫物的顶表面在所述第一衬底上的正投影位于所述扫描线在所述第一衬底的正投影内，并位于所述第一挡墙和所述第二挡墙在所述第一衬底上的正投影之间；且所述隔垫物的顶表面在所述第一方向上的尺寸大于所述第一间距。
例如，在本公开至少一实施例提供的显示面板中，所述隔垫物的顶表面在所述第一方向上的尺寸与所述第一间距之间的比值大于等于2。
例如，在本公开至少一实施例提供的显示面板中，所述第二阻挡层与所述隔垫物在所述第一方向上的间距为第三间距，所述第三间距与所述隔垫物的顶表面在所述第一方向上的尺寸之间的比值大于等于0.5。
例如，在本公开至少一实施例提供的显示面板中，所述第三间距与所述隔垫物的顶表面在所述第一方向上的尺寸之间的比值大于等于1。
例如，在本公开至少一实施例提供的显示面板中，所述第三间距与所述数据线在所述第二方向上的尺寸之间的比值为2至4。
例如，在本公开至少一实施例提供的显示面板中，所述第二阻挡层在所述第一衬底上的正投影位于所述第一阻挡层在所述第一衬底上的正投影内，且所述第一方向与所述第二方向相垂直。
例如，在本公开至少一实施例提供的显示面板中，所述阵列基板还包括形成在所述第一衬底上并在所述第二方向延伸的第一公共线，所述第一公共线与所述扫描线同层设置并相互间隔；且所述第二挡墙的第一阻挡层为所述第一公共线的部分结构。
例如，在本公开至少一实施例提供的显示面板中，所述阵列基板还包括多个子像素单元，沿所述第二方向和所述第一方向阵列排布在所述第一衬底上；每个所述子像素单元包括像素电极、公共电极和晶体管：所述晶体管包括栅极、第一极和第二极，所述栅极与所述扫描线连接，所述第一极与所述像素电极连接，所述第二极与所述数据线连接；所述公共电极在所述第一衬底上的正投影与所述像素电极在所述第一衬底上的正投影存在交叠，且所述公共电极与所述第一公共线连接。
例如，在本公开至少一实施例提供的显示面板中，所述像素电极位于所述公共电极远离所述第一衬底的一侧，所述像素电极包括：第一电极部，包括在所述第一方向上延伸的第一连接条以及在所述第一方向上间隔排布的多个第一电极条，所述第一连接条具有在所述第二方向上相对的第一侧和第二侧，所述多个第一电极条位于所述第一连接条的第一侧并与所述第一连接条连接，且相邻所述第一电极条中远离所述第一连接条的端部之间呈开口状；第二电极部，与所述第一电极部在所述第一方向上间隔排布，所述第二电极部包括在所述第一方向上延伸的第二连接条以及在所述第一方向上间隔排布的多个第二电极条，所述第二连接条位于所述第一侧远离所述第二侧的位置，所述第二连接条具有在所述第二方向上相对的第三侧和第四侧，所述第三侧位于所述第四侧靠近所述第一侧的位置；所述多个第二电极条位于所述第二连接条的第三侧并与所述第二连接条连接，且相邻所述第二电极条的远离所述第二连接条的端部之间呈开口状；导电连接部，位于所述第一电极部与所述第二电极部之间，所述导电连接部的两端分别与所述第一连接条和所述第二连接条连接；且所述导电连接部的面积大于所述第一电极条的面积和所述第二电极条的面积。
例如，在本公开至少一实施例提供的显示面板中，所述导电连接部包括在所述第二方向上间隔排布且均在所述第一方向上延伸的第一导电连接条和第二导电连接条，以及位于所述第一导电连接条和所述第二导电连接条之间并在所述第一方向上间隔排布的至少两条第三导电连接条，各所述第三导电连接条的两端分别与所述第一导电连接条和所述第二导电连接条连接；其中，所述第一导电连接条与所述第一连接条连接，所述第二导电连接条与所述第二连接条连接。
例如，在本公开至少一实施例提供的显示面板中，所述第一电极条、所述第二电极条及所述第三导电连接条均在第三方向上延伸，且所述第一电极条、所述第二电极条及所述第三导电连接条的第一宽度相等；其中，所述第一宽度为在第四方向上的尺寸，所述第三方向与所述第四方向垂直，且所述第三方向与所述第一方向和所述第二方向相交。
例如，在本公开至少一实施例提供的显示面板中，所述阵列基板还包括：与所述数据线同层设置并相互间隔的第二公共线，所述第二公共线在所述第一方向上延伸，且所述第二公共线的两端分别通过第一过孔结构与在所述第一方向上相邻两所述子像素单元的公共电极连接。
例如，在本公开至少一实施例提供的显示面板中，所述第一过孔结构包括第一过孔部、第二过孔部及过孔连接部，所述过孔连接部与所述像素电极同层设置并相互间隔，所述过孔连接部通过所述第一过孔部与所述第二公共线连接，所述过孔连接部通过所述第二过孔部与所述公共电极连接。
本公开至少一实施例还提供一种电子设备，该电子设备包括上述任一实施例中的显示面板。
本公开至少一实施例还提供一种电极结构，该电极结构包括在第一方向上间隔排布的第一电极部和第二电极部，以及位于所述第一电极部与所述第二电极部之间的导电连接部：该第一电极部包括在所述第一方向上延伸的第一连接条以及在所述第一方向上间隔排布的多个第一电极条，所述第一连接条具有在第二方向上相对的第一侧和第二侧，所述多个第一电极条位于所述第一连接条的第一侧并与所述第一连接条连接，且相邻的所述第一电极条中远离所述第一连接条的端部之间呈开口状；所述第二电极部包括在所述第一方向上延伸的第二连接条以及在所述第一方向上间隔排布的多个第二电极条，所述第二连接条位于所述第一侧远离所述第二侧的位置，所述第二连接条具有在所述第二方向上相对的第三侧和第四侧，所述第三侧位于所述第四侧靠近所述第一侧的位置；所述多个第二电极条位于所述第二连接条的第三侧并与所述第二连接条连接，且相邻的所述第二电极条的远离所述第二连接条的端部之间呈开口状；所述导电连接部的两端分别与所述第一连接条和所述第二连接条连接。
例如，在本公开至少一实施例提供的电极结构中，所述导电连接部的面 积大于所述第一电极条的面积，且大于所述第二电极条的面积。
例如，在本公开至少一实施例提供的电极结构中，所述第一电极部的面积和所述第二电极部的面积均大于所述导电连接部的面积。
例如，在本公开至少一实施例提供的电极结构中，所述导电连接部包括在所述第二方向上间隔排布且均在所述第一方向上延伸的第一导电连接条和第二导电连接条，以及位于所述第一导电连接条和所述第二导电连接条之间并在所述第一方向上间隔排布的至少两条第三导电连接条，各个所述第三导电连接条的两端分别与所述第一导电连接条和所述第二导电连接条连接；所述第一导电连接条与所述第一连接条连接，以及所述第二导电连接条与所述第二连接条连接。
例如，在本公开至少一实施例提供的电极结构中，所述第一电极条、所述第二电极条以及所述第三导电连接条均在第三方向上延伸，且所述第一电极条、所述第二电极条以及所述第三导电连接条在第四方向上的第一宽度相等；所述第三方向与所述第四方向垂直，且所述第三方向与所述第一方向和所述第二方向相交。
例如，在本公开至少一实施例提供的电极结构中，相邻的所述第一电极条的远离所述第一连接条的端部彼此不连接；相邻的所述第二电极条的远离所述第二连接条的端部彼此不连接。
例如，在本公开至少一实施例提供的电极结构中，相邻的所述第一电极条之间具有第一缝隙，所述第一电极条和所述第一缝隙的延伸方向相同，所述第一缝隙呈半开放状；相邻的所述第二电极条之间具有第二缝隙，所述第二电极条与所述第二缝隙的延伸方向相同，所述第二缝隙呈半开放状；所述第一缝隙和所述第二缝隙的开口方向相反。
例如，在本公开至少一实施例提供的电极结构中，所述第一电极条和所述第二电极条在所述第四方向上的第一宽度相等，且所述第一缝隙在所述第四方向上的第一宽度和所述第二缝隙在所述第四方向上的第一宽度相等。
例如，在本公开至少一实施例提供的电极结构中，所述第一缝隙在所述第四方向上的第一宽度为所述第一电极条在所述第四方向上的第一宽度的1至4倍。
例如，在本公开至少一实施例提供的电极结构中，所述第一电极条在所 述第四方向上的第一宽度和所述第二电极条在所述第四方向上的第一宽度均为1.8μm至3μm；所述第一缝隙在所述第四方向上的第一宽度和所述第二缝隙在所述第四方向上的第一宽度均为3μm至7μm。
例如，在本公开至少一实施例提供的电极结构中，相邻的所述第三导电连接条之间具有第三缝隙，且所述第三缝隙的四周闭合。
例如，在本公开至少一实施例提供的电极结构中，所述导电连接部中包括多个所述第三缝隙。
例如，在本公开至少一实施例提供的电极结构中，所述第三导电连接条在所述第四方向上的第一宽度与所述第一电极条在所述第四方向上的第一宽度相等，且所述第三缝隙、所述第一缝隙和所述第二缝隙在所述第四方向上的第一宽度相等。
例如，在本公开至少一实施例提供的电极结构中，所述第三导电连接条和与之相邻的所述第一电极条之间具有第四缝隙、所述第三导电连接条和与之相邻的所述第二电极条之间具有第五缝隙，所述第一缝隙、所述第二缝隙、所述第三缝隙、所述第四缝隙和所述第五缝隙在所述第四方向上的第一宽度相等。
例如，在本公开至少一实施例提供的电极结构中，所述第一电极条在所述第四方向上的所述第一宽度和所述第二电极条在所述第四方向上的所述第一宽度小于所述导电连接部的整体在所述第四方向上的第一宽度。
例如，在本公开至少一实施例提供的电极结构中，所述第一连接条在所述第二方向上的第二宽度与所述第二连接条在所述第二方向上的第二宽度相等；所述第一连接条与所述第二连接条在所述第二方向上的第二宽度大于或者等于所述第一电极条和所述第二电极条在所述第四方向上的第一宽度。
例如，在本公开至少一实施例提供的电极结构中，所述第一导电连接条在所述第一方向上的长度、所述第二导电连接条在所述第一方向上的长度均小于所述第一连接条在所述第一方向上的长度，且小于所述第二连接条在所述第一方向上的长度。
例如，在本公开至少一实施例提供的电极结构中，所述第一连接条在所述第一方向上的长度小于所述第二连接条在所述第一方向上的长度。
例如，在本公开至少一实施例提供的电极结构中，所述第一连接条在所 述第一方向上的长度与所述第二连接条在所述第一方向上的长度的比值为0.1～0.9。
例如，在本公开至少一实施例提供的电极结构中，所述第一连接条、所述导电连接部和所述第二连接条连接的整体呈折线型，所述第一连接条的一端与所述导电连接部的一端连接，所述导电连接部的另一端与所述第二连接条的一端连接，且所述第一连接条和所述第二连接条在所述第二方向上位于所述导电连接部的不同侧。
例如，在本公开至少一实施例提供的电极结构中，所述第一导电连接条在所述第二方向上的第二宽度与所述第一连接条在所述第二方向上的第二宽度相等，且所述第二导电连接条在所述第二方向上的第二宽度与第二连接条在所述第二方向上的第二宽度相等。
例如，在本公开至少一实施例提供的电极结构中，所述导电连接部包括一条导电连接条，所述导电连接条在第三方向上延伸，所述第三方向与所述第一方向和所述第二方向相交。
例如，在本公开至少一实施例提供的电极结构中，所述第三方向与所述第四方向垂直，所述导电连接条在所述第四方向上的第一宽度与所述第一电极条在所述第四方向上的第一宽度的比值为1.5至5.5。
例如，在本公开至少一实施例提供的电极结构中，所述导电连接条在所述第四方向上的所述第一宽度为5μm至10μm，所述第一电极条在所述第四方向上的第一宽度为1.8μm至3μm。
例如，在本公开至少一实施例提供的电极结构中，所述第一连接条在所述第二方向上的第二宽度与所述第二连接条在所述第二方向上的第二宽度均为2.3μm至2.7μm，所述导电连接条在所述第四方向上的第一宽度为2.5μm至3.0μm，所述第一电极条和所述第二电极条在所述第四方向上的第一宽度均为1.8μm至2.6μm。
例如，在本公开至少一实施例提供的电极结构中，所述第二电极部还包括信号连接部，所述信号连接部位于多个所述第二电极条的远离所述导电连接部的一侧并与所述第二连接条连接。
例如，在本公开至少一实施例提供的电极结构中，所述第一连接条和所述第二电极条关于所述第二方向呈镜像设置。
本公开的其他特性和优点将通过下面的详细描述变得显然，或部分地通过本公开的实践而习得。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为一种电极结构的平面结构示意图；
图2为本公开一实施例提供的一种电极结构的平面结构示意图；
图3为本公开一实施例提供的再一种电极结构的平面结构示意图；
图4为本公开一实施例提供的一种显示面板的局部截面结构示意图；
图5为本公开一实施例提供的一种显示面板的平面结构示意图；
图6为图5中所示的A部分的放大结构示意图；
图7为图6中沿C-C方向的剖视结构示意图；以及
图8为图5中第一过孔结构的放大结构示意图。
图1中的附图标记：
10、狭缝电极；11、狭缝；
图2至图8中的附图标记：
20、第一电极部；201、第一连接条；201a、第一侧；201b、第二侧；202、第一电极条；21、第二电极部；211、第二连接条；211a、第三侧；211b、第四侧；212、第二电极条；213、信号连接部；22、导电连接部；221、第一导电连接条；222、第二导电连接条；223、第三导电连接条；
3、阵列基板；30、第一衬底；301、子像素区；302、第一布线区；303、第二布线区；31、扫描线；32、第一公共线；33、数据线；34、像素电极；35、公共电极；36、晶体管；360、有源层；361、栅极；362、第一极；363、第二极；37、第二公共线；38a、第一挡墙；38b、第二挡墙；381、第一阻挡层；382、第二阻挡层；
4、对置基板；40、遮挡层；41、第二衬底；42、隔垫物；
5、液晶分子。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其它实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。
薄膜晶体管液晶显示器(Thin Film Transistor-Liquid Crystal Display，TFT-LCD)技术是微电子技术与液晶显示器技术巧妙结合的一种技术。本领域技术人员利用在硅基板(Si)上进行微电子精细加工的技术，再移植到大面积玻璃上进行薄膜晶体管(Thin Film Transistor，TFT)阵列的加工，以形成阵列基板，再利用已成熟的液晶显示器(Liquid Crystal Display，LCD)技术将该阵列基板与另一个带彩膜层的基板(即：对置基板)进行对盒，以形成一个液晶盒，再经过后续的工序，例如，贴覆偏光片等过程，最后形成液晶显示面板。
应当理解的是，该液晶盒还包括隔垫物(Photo Spacer，简称：PS)，该隔垫物的主要作用为支撑液晶盒，使液晶显示面板各个区域的盒厚保持一致，保证显示面板的亮度的均一性。但对于高级超维场转换(Advanced Super Dimension Switch，ADS)或平面转换(In-Plane Switching，IPS)等水平电场偏转产品，当显示面板受到外部应力作用时，隔垫物会发生移动，若移动较大，隔垫物可能划伤狭缝电极(具有缝隙的电极结构)上的配向膜(即：PI膜)，使得该区域中液晶的配向失效，导致显示面板工作时发生漏光的现象，从而在宏观上形成不规则的亮斑，进而影响产品的品质。
例如，图1为一种电极结构的平面结构示意图，如图1所示，该液晶显示面板的电极结构10的图形设计为内部开设有狭缝11，且狭缝11四周闭合，但这种狭缝电极10周边的光效较差，从而容易出现显示不良的问题。
本公开的实施例提供一种电极结构，该电极结构通过将第一电极部和第二电极部分别设计成具有呈半开放式的第一缝隙和第二缝隙，使得第一缝隙和第二缝隙的开口处也可以发生液晶分子的偏转，并且第一缝隙和第二缝隙呈半开放式状态，还可以提高电极结构周围的光效，进而至少在一定程度上可以克服由于相关技术的限制和缺陷而导致的一个或者多个问题，该电极结构可用于液晶显示面板中，并可以作为液晶显示面板的像素电极或者公共电极使用。在一个示例中，该电极结构的材料为氧化铟锡，即该电极结构可以为ITO(氧化铟锡)电极，且该电极结构具有透光的性能。
例如，图2为本公开一实施例提供的一种电极结构的平面结构示意图，如图2所示，该电极结构包括在第一方向Y上依次排布的第一电极部20、导电连接部22以及第二电极部21，该第一电极部20可包括在第一方向Y上延伸的第一连接条201以及在第一方向Y上间隔排布的多个第一电极条202，第一连接条201具有在第二方向X上相对的第一侧201a和第二侧201b，多个第一电极条202位于第一连接条201的第一侧201a并与第一连接条201连接，且相邻第一电极条202中远离第一连接条201的端部之间呈开口状，也就是说，相邻第一电极条202中远离第一连接条201的端部之间彼此无连接。
需要说明的是，前述提到的多个第一电极条202在第一方向Y上间隔排布，也就说明，相邻的第一电极条202之间具有第一缝隙S1，该第一缝隙S1呈半开放状。
例如，如图2所示，该第二电极部21包括在第一方向Y上延伸的第二连接条211以及在第一方向Y上间隔排布的多个第二电极条212，第二连接条211位于第一侧201a远离第二侧201b的位置，第二连接条211具有在第二方向X上相对的第三侧211a和第四侧211b，第三侧211a位于第四侧211b靠近第一侧201a的位置，需要说明的是，第二方向X与第一方向Y相互垂直；多个第二电极条212位于第二连接条211的第三侧211a并与第二连接条211连接，且相邻的第二电极条212的远离第二连接条211的端部之间呈开 口状，也就是说，相邻的第二电极条212的远离第二连接条211的端部之间彼此无连接。
需要说明的是，前述提到的多个第二电极条212在第一方向Y上间隔排布，也就说明，相邻第二电极条212之间具有第二缝隙S2，该第二缝隙S2呈半开放状。
例如，如图2所示，该导电连接部22位于第一电极部20与第二电极部21之间，导电连接部22的两端分别与第一连接条201和第二连接条211连接。
例如，在本公开的实施例中，通过将电极结构的第一电极部20和第二电极部21分别设计成具有呈半开放式的第一缝隙S1和第二缝隙S2，使得第一缝隙S1和第二缝隙S2的开口处也可以发生液晶分子偏转，因此，相比于图1示出的缝隙周围呈闭合的电极结构，可以提高电极结构周围的光效。
此外，如图2所示，第一电极部20的第一缝隙S1和第二电极部21的第二缝隙S2中一者的开口方向朝右，另一者的开口方向朝左，即第一电极部20的第一缝隙S1和第二电极部21的第二缝隙S2的开口朝向相反，这样可以均衡电极结构在第二方向X的两侧(即：图2中的左右两侧)的光效，从而使得电极结构周边的光效更加均衡，以提高显示效果。
例如，在一个示例中，该第一电极部20、第二电极部21与导电连接部22在参考平面上的正投影相互重合，此处提到的重合指的是在误差允许的范围内完全重合，这样设计可以降低电极结构的设计难度，从而利于阵列基板中多个电极结构的排布，但本公开的实施例不限于此，该第一电极部20、第二电极部21与导电连接部22在参考平面上的正投影也可以不重合，视具体情况而定。
需要说明的是，本公开的实施例中提到的参考平面为与第一方向Y相垂直的平面。
例如，在一个示例中，前述提到的第一电极条202和第二电极条212可以相互平行，即：第一电极条202和第二电极条212的延伸方向相互平行，以均衡第一电极部20和第二电极部21处的光效。具体地，第一电极条202和第二电极条212均在第三方向Q上延伸，该第三方向Q与第一方向Y和第二方向X相交，也就是说，第三方向Q不与第一方向Y和第二方向X平 行或者共线，这样设计可以减小色偏，以提高该电极结构用于显示面板中时显示面板的显示效果。
例如，在一个示例中，该第三方向Q与第二方向X之间的锐角可以为5°至15°，比如：5°、7°、9°、11°、13°、15°等等，本公开的实施例对此不作限制。
例如，在一个示例中，该第一电极条202的第一宽度可以与第二电极条212的第一宽度相等。此外，该第一缝隙S1的第一宽度可以与第二缝隙S2的第一宽度相等，这样可以进一步均衡第一电极部20和第二电极部21处的光效，以提高该电极结构用于显示面板中时显示面板的显示效果。
需要说明的是，本公开的实施例中提到的第一宽度指的是在第四方向P上的尺寸，此第四方向P与第三方向Q相互垂直。
例如，在一个示例中，为了保证第一电极部20和第二电极部21处的液晶分子偏转良好，以提高第一电极部20和第二电极部21处的光效，第一电极条202在第四方向P上的第一宽度、第一缝隙S1在第四方向P上的第一宽度、第二电极条212在第四方向P上的第一宽度以及第二缝隙S2在第四方向P上的第一宽度需要满足一定的要求，即第一缝隙S1在第四方向P上的第一宽度与第一电极条202在第四方向P上的第一宽度之比可以为1至4，比如：1、1.5、2、2.5、3、3.5、4等等，本公开的实施例对此不作限定。
例如，在一个示例中，该第一电极条202和第二电极条212在第四方向P上的第一宽度可以为1.8μm至3μm，比如：1.8μm、2μm、2.2μm、2.4μm、2.6μm、2.8μm、3μm等等；第一缝隙S1和第二缝隙S2在第四方向P上的第一宽度可以为3μm至7μm，比如：3μm、3.5μm、4μm、4.5μm、5μm、5.5μm、6μm、6.5μm、7μm等等。
此外，为了进一步均衡第一电极部20和第二电极部21处的光效，以提高该电极结构用于显示面板中时显示面板的显示效果，该第一连接条201在第二方向X上的第二宽度与第二连接条211在第二方向X上的第二宽度可以设置成相等。例如，该第一连接条201与第二连接条211在第二方向X上的第二宽度可以与第一电极条202和第二电极条212在第四方向P上的第一宽度相等，但本公开的实施例不限于此，该第一连接条201与第二连接条211在第二方向X上的第二宽度也可以略大于第一电极条202和第二电极条212 在第四方向P上的第一宽度，以在提高光效的同时，还可以改善由于第一连接条201和第二连接条211在第四方向P上的第一宽度过小而导致的第一连接条201和第二连接条211容易断线的问题，从而提高了最终形成的显示面板的良率。
需要说明的是，本公开实施例提到的第二宽度为在第二方向X上的尺寸。
例如，前述提到的电极结构的第一电极部20和第二电极部21通过导电连接部22连接，为了避免在制造过程中导电连接部22受到杂质颗粒(Partical)的影响而发生断线的问题，本公开的实施例中将导电连接部22的面积设计的较大，以避免其极易出现断线的问题而导致像素失效的情况。例如，在一个示例中，该导电连接部22的面积大于第一电极条202的面积，且大于第二电极条212的面积。
应当理解的是，此导电连接部22整体也可在第三方向Q上延伸，以降低加工设计的难度。举例而言，当导电连接部22在参考平面上的正投影与第一电极部20和第二电极部21在参考平面上的正投影重合时，为了使得导电连接部22的面积大于第一电极条202和第二电极条212的面积，在一个示例中，可以使得第一电极条202在第四方向P上的第一宽度和第二电极条212在第四方向P上的第一宽度小于导电连接部22的整体在第四方向P上的第一宽度。
例如，在一个示例中，如图2所示，该导电连接部22可为一条导电连接条22a，该导电连接条22a在第三方向Q上延伸，其中，该导电连接条22a在第四方向P上的第一宽度与第一电极条202在第四方向P上的第一宽度之比可以为1.5至5.5，也就是说，导电连接部22相比于第一电极条202进行了加宽处理，以改善导电连接部22容易断线的情况，从而保证最终形成的显示面板的质量。
例如，在一个示例中，在导电连接部22仅为一条导电连接条22a时，该导电连接条22a在第四方向P上的第一宽度可以为5μm至10μm，例如：5μm、6μm、7μm、8μm、9μm、10μm等等。
例如，在一个示例中，该第一连接条201在第二方向X上的第二宽度与第二连接条211在第二方向X上的第二宽度均为2.3μm至2.7μm，导电连接条22a在第四方向P上的第一宽度为2.5μm至3.0μm，第一电极条202和 第二电极条212在第四方向P上的第一宽度均为1.8μm至2.6μm。
例如，在一个示例中，该第一连接条201和第二电极条212关于第二方向X呈镜像设置，这样可以使得制备电极结构的过程变得简单。
例如，图3为本公开一实施例提供的再一种电极结构的平面结构示意图，如图3所示，该导电连接部22可以包括第一导电连接条221、第二导电连接条222以及至少两条第三导电连接条223，其中，该第一导电连接条221和第二导电连接条222均在第一方向Y上延伸，且第一导电连接条221和第二导电连接条222在第二方向X上间隔排布，此第一导电连接条221与第一连接条201连接，第二导电连接条222与第二连接条211连接；至少两条第三导电连接条223在第一方向Y上间隔排布，并位于第一导电连接条221和第二导电连接条222之间，且各个第三导电连接条223的两端(即：在其延伸方向上的两端)分别与第一导电连接条221和第二导电连接条222连接，也就是说，相邻的第三导电连接条223之间具有第三缝隙S3，且此第三缝隙S3的四周闭合。例如，该导电连接部22中包括的第三缝隙S3的个数不作限定，该导电连接部22中还可以包括多个第三缝隙S3。
例如，如图3所示，通过在导电连接部22的内部进行开缝(即：第三缝隙S3)设计，一方面可以减小导电连接部22上方的光效损失，从而可以提高电极结构整体的光效，另一方面，可以使得第一电极部20和第二电极部21通过至少两条导线(即：第三导电连接条223)连接导通，这样即使杂质颗粒导致其中一条导线断开，仍有其他导线连接以导通第一电极部20和第二电极部21，从而可以大大降低像素失效的发生率，即可以提高后续形成显示面板的良率。
例如，在一个示例中，该第三导电连接条223设置成两条，在保证第一电极部20和第二电极部21连接导通稳定的同时，还可以适当减小导电连接部22在电极结构中的占比，即可以为第一电极部20和第二电极部21提供更多的设计空间，换言之，第一电极部20和第二电极部21的面积可以均大于导电连接部22的面积，由于第一电极部20中的第一缝隙S1和第二电极部21中的第二缝隙S2均呈半开放设计，而导电连接部22中的第三缝隙S3为封闭式设计，因此，该第一电极部20和第二电极部21处的光效优于导电连接部22处的光效，这样通过使第一电极部20和第二电极部21的面积大于导 电连接部22的面积，可以提高电极结构整体的光效，从而可以提高该电极结构用于显示面板中时显示面板的质量。此外，由于在导电连接部22中开设第三缝隙S3，还可以缓解在制作电极结构的过程中杂质颗粒附着在导电连接部22上的情况，从而可以缓解导电连接部22的阻值因杂质颗粒的附着而增加的情况，继而缓解对像素的驱动产生的影响。
但应当理解的是，第三导电连接条223不限于设置成两条，也可设置为三条或者四条等，视具体情况而定，本公开的实施例对此不作限定。
例如，为了进一步减小导电连接部22在电极结构中的占比，第一导电连接条221的长度和第二导电连接条222的长度均可以小于第一连接条201的长度以及小于第二连接条211的长度。应当理解的是，此处提到的长度为在第一方向Y上的尺寸。
例如，在一个示例中，该第一连接条201在第一方向Y上的长度小于第二连接条211在第一方向Y上的长度。
例如，在一个示例中，该第一连接条201在第一方向Y上的长度与第二连接条211在第一方向Y上的长度的比值为0.1～0.9，例如，该比值为0.1、0.2、0.3、0.4、0.5、0.6、0.7、0.8或者0.9。
例如，如图2和图3所示，该第一连接条201、导电连接部22和第二连接条211连接的整体呈折线型，第一连接条201的一端与导电连接部22的一端连接，导电连接部22的另一端与第二连接条211的一端连接，且第一连接条201和第二连接条211在第二方向X上位于导电连接部22的不同侧。
例如，该第一导电连接条221在第二方向X上的第二宽度与第一连接条201在第二方向X上的第二宽度可以相等，第二导电连接条222在第二方向X上的第二宽度与第二连接条211在第二方向X上的第二宽度可以相等。
例如，如图3所示，该第三导电连接条223也可以在第三方向Q上延伸。该第三导电连接条223在第四方向P上的第一宽度可以与第一电极条202在第四方向P上的第一宽度相等。此外，相邻的第三导电连接条223之间的第三缝隙S3在第四方向P上的第一宽度可以与相邻的第一电极条202之间的第一缝隙S1在第四方向P上的第一宽度、相邻的第二电极条212之间的第二缝隙S2在第四方向P上的第一宽度相等，这样可以均衡导电连接部22与第一电极部20和第二电极部21处的光效，以提高该电极结构用于显示面板 中时显示面板的显示效果。
进一步地，该第三导电连接条223和与之相邻的第一电极条202之间具有第四缝隙S4，该第三导电连接条223和与之相邻的与第二电极条212之间具有第五缝隙S5，该第四缝隙S4、第五缝隙S5与前述提到的第一缝隙S1、第二缝隙S2、第三缝隙S3在第四方向(P)上的第一宽度均相等，以均衡导电连接部22、第一电极部20、第二电极部21处以及三者之间处的光效，从而可以提高该电极结构用于显示面板中时显示面板的显示效果。
在本公开的一个实施例中，如图2和图3所示，第二电极部21还可以包括信号连接部213，该信号连接部213可以位于多个第二电极条212的远离导电连接部22的一侧并与第二连接条211连接。举例而言，在本公开的实施例中的电极结构为公共电极时，此信号连接部213可与阵列基板中的公共线连接，也就是说，此信号连接部213处可用于接收公共信号，但本公开的实施例不限于此。在本公开的实施例中的电极结构为像素电极时，此信号连接部213还可与阵列基板中的晶体管的源漏电极连接，该信号连接部213用于接收来自源漏电极传递过来的信号，例如：数据信号。
需要说明的是，图2和图3中虚线不具有实际意义，仅仅是为了将前述提到的各结构进行区分，以方便理解前述提到的各结构之间的位置关系。
此外，还应当理解的是，信号连接部213的形状不限于图2和图3所示的形状，也可以为其他形状，视具体情况而定，本公开的实施例对此不作限定。还需说明的是，本公开的实施例提到的电极结构的整体为一体式结构。
本公开实施例还提供了一种显示面板，该显示面板可以为液晶显示面板。例如，图4为本公开一实施例提供的一种显示面板的局部截面结构示意图，如图4所示，该显示面板可以包括对盒设置的阵列基板3和对置基板4，以及还可以包括位于对置基板4与阵列基板3之间的液晶分子5。
下面结合附图2至图8对本公开实施例在本公开实施例的显示面板进行详细说明。
结合图5至图7所示，阵列基板3可以包括第一衬底30以及形成在第一衬底30上的多个子像素单元、多行扫描线31、多行第一公共线32、多列数据线33。
例如，图5为本公开一实施例提供的一种显示面板的平面结构示意图， 如图5所示，第一衬底30可具有沿行方向X(第二方向)和列方向Y(第一方向)呈阵列排布的多个子像素区301、位于相邻两行子像素区301之间的第一布线区302以及位于相邻两列之间的第二布线区303，第一布线区302与第二布线区303之间存在交叠。
如图5所示，多个子像素单元形成在第一衬底30上，每个子像素单元包括至少部分位于子像素区301内的像素电极34、公共电极35以及至少部分位于第一布线区302的晶体管36。此外，子像素单元中还可包括存储电容(图中未示出)。
例如，图6为图5中所示的A部分的放大结构示意图，结合图5和图6所示，晶体管36可以包括有源层360、栅极361及同层设置的第一极362和第二极363，其中，栅极361与有源层360之间还可以设置绝缘层，以使栅极361与有源层360之间相互绝缘，该绝缘层可以采用无机材料制作而成，例如，氧化硅、氮化硅等无机材料。需要说明的是，栅极361可与扫描线31同层设置，栅极361可属于前述提到的扫描线31的一部分。
例如，该晶体管36可以为顶栅型薄膜晶体管，也可以为底栅型薄膜晶体管。在本公开的实施例中，主要以晶体管36为底栅型薄膜晶体管为例进行说明。在晶体管36为底栅型薄膜晶体管时，栅极361形成在第一衬底30上，该栅极361的材料可以包括金属材料或者合金材料，例如，包括钼、铝及钛等，以保证其良好的导电性能。绝缘层形成在第一衬底30上并覆盖栅极361，该绝缘层可以采用无机材料制作而成，例如：氧化硅、氮化硅等无机材料。有源层360形成在绝缘层的背离第一衬底30的一侧，第一极362和第二极363分别与有源层360的两掺杂区连接，第一极362和第二极363的材料可以包括金属材料或者合金材料，例如，由钼、铝及钛等形成的金属单层或多层结构，例如，该多层结构为多金属层叠层，例如钛、铝、钛三层金属叠层(Al/Ti/Al)等。
应当理解的是，子像素单元中晶体管36的数量可以设置为多个，该晶体管36还分为N型晶体管和P型晶体管等。
例如，结合图5和图6所示，该像素电极34可以与第一极362连接，其中，晶体管36的第一极362可以为漏电极，该第二极363可以为源电极，但本公开的实施例不限于此，也可以是晶体管36的第一极362为源电极，第二 极363为漏电极，视具体情况而定，而公共电极35在第一衬底30上的正投影可以与像素电极34在第一衬底30上的正投影存在交叠。
例如，像素电极34和公共电极35中的至少一者为前述任一实施例所描述的电极结构，从而可以提高像素周边的光效，提高该电极结构用于显示面板中时显示面板的质量。需要说明的是，本公开的实施例中提到的行方向X可为前述提到的第二方向X，而列方向Y可为前述提到的第一方向Y。
例如，图7为图6中沿C-C方向的剖视结构示意图，如图7所示，该第一衬底30可以为单层结构，该第一衬底30可为玻璃基板，但本公开的实施例不限于此，该第一衬底30还可以为多层结构，且第一衬底30的材料不限于玻璃，也可以为其他材料，例如：聚酰亚胺(PI)等材料，视具体情况而定。
在本公开的实施例中，如图7所示，像素电极34可以位于公共电极35的远离第一衬底30的一侧，也就是说，公共电极35可先于像素电极34制作在第一衬底30上。举例而言，此公共电极35可为板状电极，即公共电极35为一整块并未开设狭缝，而像素电极34可为前述任一实施例所描述的电极结构，通过在像素电极34和公共电极35之间产生的电场，使得在电极之间和电极正上方的所有液晶分子发生偏转，从而可以提高液晶的工作效率，且增加了透光效率。
应当理解的是，在本公开的实施例中，像素电极34和公共电极35之间的位置关系不限于前述提到的关系，例如：也可以是像素电极34位于公共电极35的靠近第一衬底30的一侧，且此公共电极35为前述任一实施例所描述的电极结构，而像素电极34为板状电极。
在本公开的实施例中，为了保证阵列基板的透光率，像素电极34可以采用氧化铟锡(ITO)材料制作而成，但本公开的实施例不限于此，也可采用氧化铟锌(IZO)、氧化锌(ZnO)等透明材料制作而成，也就是说，由于像素电极34采用的材料与晶体管36的栅极361、第一极362和第二极363的材料不同，因此，该像素电极34与晶体管36的栅极361、第一极362和第二极363可以采用不同构图工艺制作而成。
例如，如图7所示，公共电极35可以位于晶体管36的第一极362和第二极363的靠近第一衬底30的一侧，该公共电极35可以在形成晶体管36 的栅极361之前形成在第一衬底30上，也就是说，在制作阵列基板时，可以先采用一构图工艺在第一衬底30上形成公共电极35，然后再采用另一构图工艺在第一衬底30上形成晶体管36的栅极361。需要说明的是，公共电极35与栅极361虽然都形成在第一衬底30上，但公共电极35与栅极361之间是相互断开的(即：无连接)。应当理解的是，公共电极35还可以在形成晶体管36的栅极361之后形成在第一衬底30上，且此公共电极35还可以位于栅极361的远离第一衬底30的一侧，视具体情况而定。
同理，为了保证阵列基板的透光率，像素电极34也可采用ITO等透明导电材料制作而成，该像素电极34可以形成在晶体管36的第一极362和第二极363的远离第一衬底30的一侧，应当理解的是，该像素电极34和晶体管36的第一极362和第二极363之间还具有一层绝缘层，该像素电极34可以通过第二过孔结构H2与晶体管的第一极362连接。具体地，在像素电极34为前述实施例提到的电极结构时，该像素电极34可通过信号连接部213经第二过孔结构H2与晶体管的第一极362连接，应当理解的是，此信号连接部213可位于第一布线区302内。
例如，在像素电极34为前述实施例提到的电极结构时，在第一方向Y、第二方向X上相邻的两个像素电极34中第一电极部20的狭缝开口方向相反，且第二电极部21的狭缝开口相反。此外，还需说明的是，阵列基板3中各电极结构的整体形状可稍有不同，例如：部分电极结构需要为阵列基板3中的其他结构做避让设计等等，但应当理解的是，虽然阵列基板3中各电极结构的整体形状可不完全相同，但整体设计构思应是相同的，即：第一电极部20、第二电极部21均为半开缝设计，且导电连接部22整体在第四方向P上的第一宽度大于第一电极条202在第四方向P上的第一宽度和第二电极条212在第四方向P上的第一宽度。
例如，如图5所示，至少一行扫描线31可以位于一个第一布线区302内，换言之，每一个第一布线区302内可设置有至少一行扫描线31，应当理解的是，此扫描线31的整体可以看作是在行方向X上延伸。该扫描线31与子像素单元中晶体管36的栅极361连接，前述提到扫描线31可与晶体管36的栅极361同层设置且为一体式结构，此扫描线31被配置为向子像素单元提供扫描信号。
例如，如图5所示，至少一行第一公共线32可位于一个第一布线区302内，换言之，每一个第一布线区302内可设置有至少一行第一公共线32，应当理解的是，该第一公共线32的整体可以看作在行方向X上延伸，该第一公共线32可以与公共电极35连接，其被配置为向子像素单元提供公共信号。
举例而言，该第一公共线32可以与扫描线31同层设置，其中，前述提到的公共电极35可以先于扫描线31设置在第一衬底30上，因此，为了使得第一公共线32与公共电极35连接，在制作第一公共线32的过程中，可以使第一公共线32与公共电极35搭接在一起。
例如，如图5所示，每一个第一布线区302内可以设置有一行扫描线31和一行第一公共线32，应当理解的是，该扫描线31与第一公共线32之间相互断开，即：扫描线31在第一衬底30上的正投影与第一公共线32在第一衬底30上的正投影不交叠。需要说明的是，第一布线区302内不限于设置一行扫描线31和一行第一公共线32，也可设置两行扫描线31，或不设置第一公共线32等等，视具体情况而定，本公开的实施例对此不作限定。本公开实施例主要以每一第一布线区302内设置有一行扫描线31和一行第一公共线32进行说明。
例如，如图5所示，至少一列数据线33可位于一个第二布线区303内，换言之，每一个第二布线区303内设置至少一列数据线33，应当理解的是，该数据线33的整体可以看作在列方向Y上延伸，该数据线33在第一衬底30上的正投影与扫描线31和第一公共线32在第一衬底30上的正投影存在交叠。例如，该数据线33可以与子像素单元中晶体管36的第二极363连接，其被配置为向子像素单元提供数据信号。
举例而言，本公开的实施例中的数据线33可以与子像素单元中晶体管36的第一极362和第二极363同层设置，即可以采用同一构图工艺制作而成，以降低掩膜成本；但本公开的实施例不限于此，也可以采用不同的构图工艺制作而成，视具体情况而定。
例如，如图5所示，每一个第二布线区303内可设置一列数据线33，此数据线33可与同一列中各子像素单元的第二极363连接，也就是说，数据线33可以为同一列子像素单元提供数据信号。
在本公开的实施例中，每列数据线33可以关于其中轴线呈对称设置，需 要说明的是，此处提到的中轴线为经过数据线33的中心并在列方向Y上延伸的线。
例如，在一列子像素单元中，各个子像素单元的第一极362和与其相连的数据线33在行方向X上的间距相等，以保证每列中各个子像素单元的晶体管36和数据线33之间的耦合电容接近一致，进而保证每列中各个子像素单元处的光效均一性。需要说明的是，在一列子像素单元中各子像素单元的第一极362和与其相连的数据线33在行方向X上的间距相等的同时，该列第一极362与栅极361交叠面积需要与其他列保持一致。
例如，如图5所示，阵列基板还可以包括第二公共线37，该第二公共线37可以与数据线33同层设置并相互间隔。其中，该第二公共线37在第一方向Y上延伸，此第二公共线37在第一衬底30上的正投影的中间部分位于第一布线区302，该第二公共线37的两端分别位于子像素区301内。在本公开的实施例中，第二公共线37的两端分别通过第一过孔结构H1与在第一方向Y上相邻的两个子像素的公共电极35连接。
例如，图8为图5中第一过孔结构的放大结构示意图，如图8所示，第一过孔结构H1包括第一过孔部H11、第二过孔部H12以及过孔连接部H13，过孔连接部H13与像素电极34同层设置并相互间隔，过孔连接部H13通过第一过孔部H11与第二公共线37连接，过孔连接部H13通过第二过孔部H12与公共电极35连接。
例如，如图5至图7所示，对置基板4还可以包括第二衬底41和位于第二衬底41的靠近阵列基板3一侧的隔垫物42以及位于隔垫物42的靠近第二衬底41一侧的遮挡层40。该第二衬底41的具体结构可以参考第一衬底30的描述，在此不再重复赘述。该遮挡层40在第一衬底30上的正投影可以完全覆盖第一布线区302、第二布线区303和覆盖至少部分子像素区30，而隔垫物42可以设置有多个，该隔垫物42的设置可以提高显示面板整体厚度的均一性，并可以提高显示面板对液晶分子波动的容忍度，进而提高显示面板的良率。
举例而言，多个隔垫物42中可以包括主隔垫物和辅隔垫物，该主隔垫物在显示面板未受到外界压力时，其远离第二衬底41的一端与阵列基板3接触，其主要起到支撑作用，而辅隔垫物在显示面板未受到外界压力时，辅隔垫物 远离第二衬底41的一端与阵列基板1之间具有一定的间距，也就是说，主隔垫物与辅隔垫物之间存在段差(高度差)，通过调节主隔垫物与辅隔垫物之间的段差可以对显示面板的厚度进行微调。
示例性地，主隔垫物的高度大于辅隔垫物的高度，当显示面板受到外界压力时，主隔垫物先承受所有压力并压缩，当主隔垫物压缩至主隔垫物与辅隔垫物之间的段差降为0时，主隔垫物和辅隔垫物共同承受外界压力。
需要说明的是，主隔垫物和辅隔垫物这两种可以按照一定的周期排布。工艺制作过程中需要对不同种类隔垫物的尺寸高度进行监控。因隔垫物尺寸较小，且主隔垫物一般较少，单独依靠尺寸，设备很难准确识别主隔垫物的位置，通常将主隔垫物周围某个位置空缺隔垫物设计(即：不设置任何隔垫物)，以方便更快更准确的识别主隔垫物位置对其进行监控，例如：在设计时将主隔垫物下方不设置任何隔垫物，在监控时，可先快速确定不设置任何隔垫物的位置，然后前述提到的设计规则，可明确不设置任何隔垫物的上方位置处的隔垫物即为主隔垫物。
需要说明的是，本公开的实施例中的隔垫物42的靠近第一衬底30的表面可以为顶表面，其远离第一衬底30的表面为底表面，其中，如图5所示，隔垫物42的顶表面在第一衬底30上的正投影位于扫描线31在第一衬底30的正投影内，也就是说，隔垫物42的顶表面在第一衬底30上的正投影的外轮廓位于扫描线31在第一衬底30的正投影的外轮廓的内侧，从而确保了隔垫物42支撑处的平坦度，以保证隔垫物42稳定地支撑在阵列基板3上。需要说明的是，本公开的实施例中的隔垫物42在第一衬底30上的正投影不与数据线33和晶体管在第一衬底30上的正投影重叠。
应当理解的是，本公开的实施例中的隔垫物42的顶表面在第一衬底30上的正投影可以位于隔垫物42的底表面在第一衬底30上的正投影内，也就是说，此隔垫物42的整体可以类似为锥形，但本公开的实施例不限于此，本公开的实施例中的隔垫物42的顶表面在第一衬底30上的正投影也可以与隔垫物42的底表面在第一衬底30上的正投影完全重合，视具体情况而定。
此外，还需说明的是，隔垫物42的底表面在第一衬底30上的正投影可位于扫描线31在第一衬底30的正投影内，但本公开的实施例不限于此，隔垫物42在列方向Y上的轮廓也可超出扫描线31在列方向Y上的轮廓。
例如，为了防止隔垫物42受外力作用移动后划伤配向膜而导致红斑产生的情况，可以在隔垫物42的周围设置挡墙。具体地，由于隔垫物42在第一衬底30上的正投影位于扫描线31在第一衬底30的正投影内，且扫描线31处被遮挡层40遮盖，因此，隔垫物42即使在行方向X上发生移动，仍然位于遮挡层40遮盖的范围内，基本不会影响显示效果；基于此，可不需要在隔垫物42的行方向X上的相对两侧设置挡墙，以降低设计难度。
此外，如图5所示，在隔垫物42的行方向X上的相对两侧设置有晶体管，阵列基板3中晶体管所在区域的整体高度大于隔垫物42所在区域的整体高度，也就是说，此晶体管处可作为挡墙阻挡隔垫物42在行方向X上滑移。
而为了防止隔垫物42受外力作用在列方向Y上过度滑移，结合图5和图6所示，可在阵列基板3上设置第一挡墙38a和第二挡墙38b，此第一挡墙38a和第二挡墙38b分别位于扫描线31在列方向Y上的相对两侧，其中，隔垫物42在第一衬底30上的正投影可位于第一挡墙38a和第二挡墙38b在第一衬底30上的正投影之间；换言之，隔垫物42在列方向Y上的相对两侧可设置第一挡墙38a和第二挡墙38b。
需要说明的是，此第一挡墙38a和第二挡墙38b的至少部分可位于子像素区301；此第一挡墙38a和第二挡墙38b可被遮挡层40遮挡住。
例如，第一挡墙38a和第二挡墙38b均包括与扫描线31同层设置并相互间隔的第一阻挡层381和与数据线33同层设置并相互间隔的第二阻挡层382，此第二阻挡层382在第一衬底30上的正投影与第一阻挡层381在第一衬底上的正投影存在交叠。例如，如图5至图7所示，第一阻挡层381与扫描线31在第一方向Y上的间距为第一间距W1，第二阻挡层382与扫描线31在第一方向Y上的间距为第二间距W2，此第二间距W2大于所述第一间距W1；也就是说，第一阻挡层381相比于第二阻挡层382向靠近隔垫物42的方向凸出设置，此凸出的部分可在隔垫物受力移动时起到支撑作用，以缓解隔垫物42掉入扫描线31与第一阻挡层381之间的空隙而无法恢复原状的情况，同时，本公开的实施例中的第二阻挡层382与隔垫物42之间的间距相比于第一阻挡层381与隔垫物42之间的间距较大，这样相比于将第二阻挡层382与隔垫物42之间的间距和第一阻挡层381与隔垫物42之间的间距设计为相等的方案，当隔垫物42受到的外应力相同时，可使隔垫物42翘起角度 变小，这样在隔垫物42受到的外应力为水平方向(例如：第一方向Y)上的力时，竖直方向上(即：显示面板的厚度方向上)阻力可减小，此时，隔垫物42更难以越过挡墙而划伤透光区(即：子像素区301中未被遮挡层40覆盖的区域)处的配向膜，即：划伤配向膜的风险降低。此外，显示面板竖向形变量降低，T-DNU(Touch-Dark Non-uniformity，触摸后面板暗态不均)也得到改善。
需要说明的是，本公开的实施例中的隔垫物42的靠近第一衬底30的表面可以为顶表面，此隔垫物42的顶表面在第一方向Y上的尺寸W4可大于第一间距W1，以缓解隔垫物42在移动过程中掉入扫描线31与第一阻挡层381之间的空隙而无法恢复原状的情况。
例如，隔垫物42的顶表面在第一方向Y上的尺寸W4与第一间距W1之间的比值大于等于2，以进一步缓解隔垫物42在移动过程中掉入扫描线31与第一阻挡层381之间的空隙而无法恢复原状的情况。
例如，第二阻挡层382与隔垫物42在第一方向Y上的间距为第三间距W3，第三间距W3与隔垫物42的顶表面在第一方向Y上的尺寸之间的比值大于等于0.5，这样设计可降低隔垫物42越过挡墙的风险，从而可降低划伤透光区处配向膜的风险；进一步地，第三间距W3与隔垫物42的顶表面在第一方向Y上的尺寸W4之间的比值可大于等于1。
举例而言，第三间距W3与数据线33在第二方向X上的尺寸之间的比值为2至4；其中，数据线33在第二方向X上的尺寸可为5μm至7μm，比如：5μm、5.5μm、6μm、6.5μm、7μm等等，此时，第三间距W3可为10μm至28μm，比如：10μm、13μm、17μm、21μm、25μm、28μm等等。
应当理解的是，前述提到的第二阻挡层382在第一衬底30上的正投影位于所述第一阻挡层381在第一衬底30上的正投影内，这样可以保证第一挡墙38a和第二挡墙38b中主要起到阻挡作用的膜层(即：第二阻挡层382)在第一方向Y上具有足够的宽度，以更好地阻挡隔垫物42在第一方向Y上滑动。也就是说，如图7所示，本公开实施例的第一挡墙38a和第二挡墙38b的纵截面整体可看似为“L”型，此处纵截面指的是与显示面板的厚度方向和第一方向Y相平行的面。
需要说明的是，前述提到的第二挡墙38b的第一阻挡层381可为第一公 共线32的部分结构。还需说明的是，第二挡墙38b与扫描线31之间的第一间距W1、第二间距W2、第二挡墙38b与隔垫物42之间的第三间距W3与第一挡墙38a与扫描线31之间的第一间距W1、第二间距W2、第一挡墙38a与隔垫物42之间的第三间距W3可相等，也可不相等，视具体情况而定。
在本公开的实施例中，前述提到遮挡层40除了完全覆盖第一布线区302、第二布线区303之外，还可覆盖部分子像素区301，具体可覆盖部分公共电极35和部分像素电极34。其中，像素电极34边缘靠近扫描线31、数据线33区域存在耦合电场，显示过程中会导致液晶排布紊乱，产生失效区，导致暗态像素边缘漏光，因此需要遮挡层40对这部分失效区进行遮挡。
举例而言，像素电极34与扫描线31存在耦合电场，也就是说，像素电极34靠近扫描线31的部分存在失效区，为了对此失效区进行遮挡，在列方向Y上，遮挡层40可覆盖像素电极34的边缘至少5μm，需要说明的是，在彩膜层位于对置基板上时，考虑上下基板对盒精度，需加宽更多，但也不得超过10μm，以避免过多影响像素开口率。
此外，数据线33与像素电极34边缘同样存在耦合电场，也就是说，本公开的实施例中的像素电极34的靠近数据线33的部分存在失效区。例如，在液晶分子5为负性液晶分子时，该电场不会导致液晶旋转，此遮挡层40可以覆盖像素电极34的边缘大约为1μm，以遮挡数据线33附近的阴暗(Shadow)区；而若在液晶分子5为正性液晶分子时，数据线33与像素电极34之间的耦合电场不会导致明显的暗态漏光，但是会导致液晶分子造成串扰(Crosstalk)现象加重，此时，遮挡层40可覆盖像素电极34的边缘至少6μm，以遮挡耦合电场区域。
需要说明的是，液晶显示面板中用到的彩膜层可位于对置基板4上，也可位于阵列基板3上，视具体情况而定。
基于上述内容，本公开的实施例中的液晶显示面板可以用于4K分辨率或8K分辨率的显示产品中。
本公开的实施例还提供了一种电子设备，其包括上述任一实施例所描述的显示面板。
根据本公开的实施例，该电子设备的具体类型不受特别的限制，本领域常用的电子设备类型均可，具体例如液晶显示屏、手机、笔记本电脑等移动 装置、手表等可穿戴设备、VR装置等等，本领域技术人员可根据该显示设备的具体用途进行相应地选择，在此不再赘述。
需要说明的是，该电子设备除了显示面板以外，还包括其他必要的部件和组成，以显示器为例，还可包括背光模组、外壳、主电路板、电源线，等等，本领域可根据该电子设备的具体使用要求进行相应地补充，在此不再赘述。
需要说明的是，本文中所述的“在……上”、“在……上形成”和“设置在……上”可以表示一层直接形成或设置在另一层上，也可以表示一层间接形成或设置在另一层上，即两层之间还存在其它的层。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。
在本公开中，除非另有说明，所采用的术语“同层设置”指的是两个层、部件、构件、元件或部分可以通过同一构图工艺形成，并且，这两个层、部件、构件、元件或部分一般由相同的材料形成。
在本公开中，除非另有说明，表述“构图工艺”一般包括光刻胶的涂布、曝光、显影、刻蚀、光刻胶的剥离等步骤。表述“一次构图工艺”意指使用一块掩模板形成图案化的层、部件、构件等的工艺。
有以下几点需要说明：
(1)本公开的实施例附图中，只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开的同一实施例及不同实施例中的特征可以相互组合。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (41)

  1. 一种显示面板，包括对盒设置的阵列基板(3)和对置基板(4)，其中，
    所述阵列基板(3)包括第一衬底(30)及形成在所述第一衬底(30)的靠近所述对置基板(4)一侧的扫描线(31)、数据线(33)、第一挡墙(38a)及第二挡墙(38b)；所述数据线(33)在第一方向(Y)上延伸，所述扫描线(31)在第二方向(X)上延伸，所述第一方向(Y)与所述第二方向(X)相交；所述第一挡墙(38a)和所述第二挡墙(38b)分别位于所述扫描线(31)在所述第一方向(Y)上的相对两侧，且所述第一挡墙(38a)和所述第二挡墙(38b)均包括与所述扫描线(31)同层设置并相互间隔的第一阻挡层(381)和与所述数据线(33)同层设置并相互间隔的第二阻挡层(382)，所述第二阻挡层(382)在所述第一衬底(30)上的正投影与所述第一阻挡层(381)在所述第一衬底(30)上的正投影存在交叠；所述第一阻挡层(381)与所述扫描线(31)在所述第一方向(Y)上的间距为第一间距(W1)，所述第二阻挡层(382)与所述扫描线(31)在所述第一方向(Y)上的间距为第二间距(W2)，所述第二间距(W2)大于所述第一间距(W1)；
    所述对置基板(4)包括第二衬底(41)和位于所述第二衬底(41)靠近所述阵列基板(3)一侧的隔垫物(42)，所述隔垫物(42)靠近所述第一衬底(30)的表面为顶表面，所述隔垫物(42)的顶表面在所述第一衬底(30)上的正投影位于所述扫描线(31)在所述第一衬底(30)的正投影内，并位于所述第一挡墙(38a)和所述第二挡墙(38b)在所述第一衬底(30)上的正投影之间；且所述隔垫物(42)的顶表面在所述第一方向(Y)上的尺寸(W4)大于所述第一间距(W1)。
  2. 根据权利要求1所述的显示面板，其中，所述隔垫物(42)的顶表面在所述第一方向(Y)上的尺寸(W4)与所述第一间距(W1)之间的比值大于等于2。
  3. 根据权利要求2所述的显示面板，其中，所述第二阻挡层(382)与所述隔垫物(42)在所述第一方向(Y)上的间距为第三间距(W3)，所述第三间距(W3)与所述隔垫物(42)的顶表面在所述第一方向(Y)上的尺 寸(W4)之间的比值大于等于0.5。
  4. 根据权利要求3所述的显示面板，其中，所述第三间距(W3)与所述隔垫物(42)的顶表面在所述第一方向(Y)上的尺寸(W4)之间的比值大于等于1。
  5. 根据权利要求3所述的显示面板，其中，所述第三间距(W3)与所述数据线(33)在所述第二方向(X)上的尺寸之间的比值为2至4。
  6. 根据权利要求1至5中任一项所述的显示面板，其中，所述第二阻挡层(382)在所述第一衬底(30)上的正投影位于所述第一阻挡层(381)在所述第一衬底(30)上的正投影内，且所述第一方向(Y)与所述第二方向(X)相垂直。
  7. 根据权利要求6所述的显示面板，其中，所述阵列基板(3)还包括形成在所述第一衬底(30)上并在所述第二方向(X)延伸的第一公共线(32)，所述第一公共线(32)与所述扫描线(31)同层设置并相互间隔；且所述第二挡墙(38b)的第一阻挡层(381)为所述第一公共线(32)的部分结构。
  8. 根据权利要求7所述的显示面板，其中，所述阵列基板(3)还包括多个子像素单元，沿所述第二方向(X)和所述第一方向(Y)阵列排布在所述第一衬底(30)上；
    每个所述子像素单元包括像素电极(34)、公共电极(35)和晶体管(36)：所述晶体管(36)包括栅极(361)、第一极(362)和第二极(363)，所述栅极(361)与所述扫描线(31)连接，所述第一极(362)与所述像素电极(34)连接，所述第二极(363)与所述数据线(33)连接；
    所述公共电极(35)在所述第一衬底(30)上的正投影与所述像素电极(34)在所述第一衬底(30)上的正投影存在交叠，且所述公共电极(35)与所述第一公共线(32)连接。
  9. 根据权利要求8所述的显示面板，其中，所述像素电极(34)位于所述公共电极(35)远离所述第一衬底(30)的一侧，所述像素电极(34)包括：
    第一电极部(20)，包括在所述第一方向(Y)上延伸的第一连接条(201)以及在所述第一方向(Y)上间隔排布的多个第一电极条(202)，所述第一连接条(201)具有在所述第二方向(X)上相对的第一侧(201a)和第二侧 (201b)，所述多个第一电极条(202)位于所述第一连接条(201)的第一侧(201a)并与所述第一连接条(201)连接，且相邻所述第一电极条(202)中远离所述第一连接条(201)的端部之间呈开口状；
    第二电极部(21)，与所述第一电极部(20)在所述第一方向(Y)上间隔排布，所述第二电极部(21)包括在所述第一方向(Y)上延伸的第二连接条(211)以及在所述第一方向(Y)上间隔排布的多个第二电极条(212)，所述第二连接条(211)位于所述第一侧(201a)远离所述第二侧(201b)的位置，所述第二连接条(211)具有在所述第二方向(X)上相对的第三侧(211a)和第四侧(211b)，所述第三侧(211a)位于所述第四侧(211b)靠近所述第一侧(201a)的位置；所述多个第二电极条(212)位于所述第二连接条(211)的第三侧(211a)并与所述第二连接条(211)连接，且相邻所述第二电极条(212)的远离所述第二连接条(211)的端部之间呈开口状；
    导电连接部(22)，位于所述第一电极部(20)与所述第二电极部(21)之间，所述导电连接部(22)的两端分别与所述第一连接条(201)和所述第二连接条(211)连接；且所述导电连接部(22)的面积大于所述第一电极条(202)的面积和所述第二电极条(212)的面积。
  10. 根据权利要求9所述的显示面板，其中，所述导电连接部(22)包括在所述第二方向(X)上间隔排布且均在所述第一方向(Y)上延伸的第一导电连接条(221)和第二导电连接条(222)，以及位于所述第一导电连接条(221)和所述第二导电连接条(222)之间并在所述第一方向(Y)上间隔排布的至少两条第三导电连接条(223)，各所述第三导电连接条(223)的两端分别与所述第一导电连接条(221)和所述第二导电连接条(222)连接；
    其中，所述第一导电连接条(221)与所述第一连接条(201)连接，所述第二导电连接条(222)与所述第二连接条(211)连接。
  11. 根据权利要求10所述的显示面板，其中，所述第一电极条(202)、所述第二电极条(212)及所述第三导电连接条(223)均在第三方向(Q)上延伸，且所述第一电极条(202)、所述第二电极条(212)及所述第三导电连接条(223)的第一宽度相等；
    其中，所述第一宽度为在第四方向(P)上的尺寸，所述第三方向(Q) 与所述第四方向(P)垂直，且所述第三方向(Q)与所述第一方向(Y)和所述第二方向(X)相交。
  12. 根据权利要求9所述的显示面板，其中，所述阵列基板(3)还包括：与所述数据线(33)同层设置并相互间隔的第二公共线(37)，所述第二公共线(37)在所述第一方向(Y)上延伸，且所述第二公共线(37)的两端分别通过第一过孔结构(H1)与在所述第一方向(Y)上相邻两所述子像素单元的公共电极(35)连接。
  13. 根据权利要求12所述的显示面板，其中，所述第一过孔结构(H1)包括第一过孔部(H11)、第二过孔部(H12)及过孔连接部(H13)，所述过孔连接部(H13)与所述像素电极(34)同层设置并相互间隔，所述过孔连接部(H13)通过所述第一过孔部(H11)与所述第二公共线(37)连接，所述过孔连接部(H13)通过所述第二过孔部(H12)与所述公共电极(35)连接。
  14. 一种电子设备，包括权利要求1至13中任一项所述的显示面板。
  15. 一种电极结构，包括：在第一方向(Y)上间隔排布的第一电极部(20)和第二电极部(21)，以及位于所述第一电极部(20)与所述第二电极部(21)之间的导电连接部(22)，其中，
    所述第一电极部(20)包括在所述第一方向(Y)上延伸的第一连接条(201)以及在所述第一方向(Y)上间隔排布的多个第一电极条(202)，所述第一连接条(201)具有在第二方向(X)上相对的第一侧(201a)和第二侧(201b)，所述多个第一电极条(202)位于所述第一连接条(201)的第一侧(201a)并与所述第一连接条(201)连接，且相邻的所述第一电极条(202)中远离所述第一连接条(201)的端部之间呈开口状；
    所述第二电极部(21)包括在所述第一方向(Y)上延伸的第二连接条(211)以及在所述第一方向(Y)上间隔排布的多个第二电极条(212)，所述第二连接条(211)位于所述第一侧(201a)远离所述第二侧(201b)的位置，所述第二连接条(211)具有在所述第二方向(X)上相对的第三侧(211a)和第四侧(211b)，所述第三侧(211a)位于所述第四侧(211b)靠近所述第一侧(201a)的位置；所述多个第二电极条(212)位于所述第二连接条(211)的第三侧(211a)并与所述第二连接条(211)连接，且相邻的所述第二电极 条(212)的远离所述第二连接条(211)的端部之间呈开口状；
    所述导电连接部(22)的两端分别与所述第一连接条(201)和所述第二连接条(211)连接。
  16. 根据权利要求15所述的电极结构，其中，所述导电连接部(22)的面积大于所述第一电极条(202)的面积，且大于所述第二电极条(212)的面积。
  17. 根据权利要求15所述的电极结构，其中，所述第一电极部(20)的面积和所述第二电极部(21)的面积均大于所述导电连接部(22)的面积。
  18. 根据权利要求15～17中任一项所述的电极结构，其中，所述导电连接部(22)包括在所述第二方向(X)上间隔排布且均在所述第一方向(Y)上延伸的第一导电连接条(221)和第二导电连接条(222)，以及位于所述第一导电连接条(221)和所述第二导电连接条(222)之间并在所述第一方向(Y)上间隔排布的至少两条第三导电连接条(223)，各个所述第三导电连接条(223)的两端分别与所述第一导电连接条(221)和所述第二导电连接条(222)连接；
    所述第一导电连接条(221)与所述第一连接条(201)连接，以及所述第二导电连接条(222)与所述第二连接条(211)连接。
  19. 根据权利要求18所述的电极结构，其中，所述第一电极条(202)、所述第二电极条(212)以及所述第三导电连接条(223)均在第三方向(Q)上延伸，且所述第一电极条(202)、所述第二电极条(212)以及所述第三导电连接条(223)在第四方向(P)上的第一宽度相等；
    所述第三方向(Q)与所述第四方向(P)垂直，且所述第三方向(Q)与所述第一方向(Y)和所述第二方向(X)相交。
  20. 根据权利要求18所述的电极结构，其中，相邻的所述第一电极条(202)的远离所述第一连接条(201)的端部彼此不连接；相邻的所述第二电极条(212)的远离所述第二连接条(211)的端部彼此不连接。
  21. 根据权利要求20所述的电极结构，其中，相邻的所述第一电极条(202)之间具有第一缝隙(S1)，所述第一电极条(202)和所述第一缝隙(S1)的延伸方向相同，所述第一缝隙(S1)呈半开放状；相邻的所述第二电极条(212)之间具有第二缝隙(S2)，所述第二电极条(212)与所述第 二缝隙(S2)的延伸方向相同，所述第二缝隙(S2)呈半开放状；所述第一缝隙(S1)和所述第二缝隙(S2)的开口方向相反。
  22. 根据权利要求21所述的电极结构，其中，所述第一电极条(202)和所述第二电极条(212)在所述第四方向(P)上的第一宽度相等，且所述第一缝隙(S1)在所述第四方向(P)上的第一宽度和所述第二缝隙(S2)在所述第四方向(P)上的第一宽度相等。
  23. 根据权利要求22所述的电极结构，其中，所述第一缝隙(S1)在所述第四方向(P)上的第一宽度为所述第一电极条(202)在所述第四方向(P)上的第一宽度的1至4倍。
  24. 根据权利要求23所述的电极结构，其中，所述第一电极条(202)在所述第四方向(P)上的第一宽度和所述第二电极条(212)在所述第四方向(P)上的第一宽度均为1.8μm至3μm；所述第一缝隙(S1)在所述第四方向(P)上的第一宽度和所述第二缝隙(S2)在所述第四方向(P)上的第一宽度均为3μm至7μm。
  25. 根据权利要求21所述的电极结构，其中，相邻的所述第三导电连接条(223)之间具有第三缝隙(S3)，且所述第三缝隙(S3)的四周闭合。
  26. 根据权利要求25所述的电极结构，其中，所述导电连接部(22)中包括多个所述第三缝隙(S3)。
  27. 根据权利要求25所述的电极结构，其中，所述第三导电连接条(223)在所述第四方向(P)上的第一宽度与所述第一电极条(202)在所述第四方向(P)上的第一宽度相等，且所述第三缝隙(S3)、所述第一缝隙(S1)和所述第二缝隙(S2)在所述第四方向(P)上的第一宽度相等。
  28. 根据权利要求27所述的电极结构，其中，所述第三导电连接条(223)和与之相邻的所述第一电极条(202)之间具有第四缝隙(S4)、所述第三导电连接条(223)和与之相邻的所述第二电极条(212)之间具有第五缝隙(S5)，所述第一缝隙(S1)、所述第二缝隙(S2)、所述第三缝隙(S3)、所述第四缝隙(S4)和所述第五缝隙(S5)在所述第四方向(P)上的第一宽度相等。
  29. 根据权利要求18所述的电极结构，其中，所述第一电极条(202)在所述第四方向(P)上的所述第一宽度和所述第二电极条(212)在所述第 四方向(P)上的所述第一宽度小于所述导电连接部(22)的整体在所述第四方向(P)上的第一宽度。
  30. 根据权利要求15所述的电极结构，其中，所述第一连接条(201)在所述第二方向(X)上的第二宽度与所述第二连接条(211)在所述第二方向(X)上的第二宽度相等；所述第一连接条(201)与所述第二连接条(211)在所述第二方向(X)上的第二宽度大于或者等于所述第一电极条(202)和所述第二电极条(212)在所述第四方向(P)上的第一宽度。
  31. 根据权利要求18所述的电极结构，其中，所述第一导电连接条(221)在所述第一方向(Y)上的长度、所述第二导电连接条(222)在所述第一方向(Y)上的长度均小于所述第一连接条(201)在所述第一方向(Y)上的长度，且小于所述第二连接条(211)在所述第一方向(Y)上的长度。
  32. 根据权利要求31所述的电极结构，其中，所述第一连接条(201)在所述第一方向(Y)上的长度小于所述第二连接条(211)在所述第一方向(Y)上的长度。
  33. 根据权利要求32所述的电极结构，其中，所述第一连接条(201)在所述第一方向(Y)上的长度与所述第二连接条(211)在所述第一方向(Y)上的长度的比值为0.1～0.9。
  34. 根据权利要求15所述的电极结构，其中，所述第一连接条(201)、所述导电连接部(22)和所述第二连接条(211)连接的整体呈折线型，所述第一连接条(201)的一端与所述导电连接部(22)的一端连接，所述导电连接部(22)的另一端与所述第二连接条(211)的一端连接，且所述第一连接条(201)和所述第二连接条(211)在所述第二方向(X)上位于所述导电连接部(22)的不同侧。
  35. 根据权利要求15所述的电极结构，其中，所述第一导电连接条(221)在所述第二方向(X)上的第二宽度与所述第一连接条(201)在所述第二方向(X)上的第二宽度相等，且所述第二导电连接条(222)在所述第二方向(X)上的第二宽度与第二连接条(211)在所述第二方向(X)上的第二宽度相等。
  36. 根据权利要求15～17中任一项所述的电极结构，其中，所述导电连接部(22)包括一条导电连接条(22a)，所述导电连接条(22a)在第三方 向(Q)上延伸，所述第三方向(Q)与所述第一方向(Y)和所述第二方向(X)相交。
  37. 根据权利要求36所述的电极结构，其中，所述第三方向(Q)与所述第四方向(P)垂直，所述导电连接条(22a)在所述第四方向(P)上的第一宽度与所述第一电极条(202)在所述第四方向(P)上的第一宽度的比值为1.5至5.5。
  38. 根据权利要求37所述的电极结构，其中，所述导电连接条(22a)在所述第四方向(P)上的所述第一宽度为5μm至10μm，所述第一电极条(202)在所述第四方向(P)上的第一宽度为1.8μm至3μm。
  39. 根据权利要求37所述的电极结构，其中，所述第一连接条(201)在所述第二方向(X)上的第二宽度与所述第二连接条(211)在所述第二方向(X)上的第二宽度均为2.3μm至2.7μm，所述导电连接条(22a)在所述第四方向(P)上的第一宽度为2.5μm至3.0μm，所述第一电极条(202)和所述第二电极条(212)在所述第四方向(P)上的第一宽度均为1.8μm至2.6μm。
  40. 根据权利要求15所述的电极结构，其中，所述第二电极部(21)还包括信号连接部(213)，所述信号连接部(213)位于多个所述第二电极条(212)的远离所述导电连接部(22)的一侧并与所述第二连接条(211)连接。
  41. 根据权利要求15所述的电极结构，其中，所述第一连接条(201)和所述第二电极条(212)关于所述第二方向(X)呈镜像设置。
PCT/CN2022/071870 2021-01-13 2022-01-13 电极结构、显示面板及电子设备 WO2022152223A1 (zh)

Priority Applications (5)

Application Number Priority Date Filing Date Title
US17/764,734 US20230185141A1 (en) 2021-01-13 2022-01-13 Electrode structure, display panel, and electronic device
KR1020237003286A KR20230127198A (ko) 2021-01-13 2022-01-13 전극 구조, 디스플레이 패널 및 전자 기기
EP22739099.4A EP4145215A4 (en) 2021-01-13 2022-01-13 ELECTRODE STRUCTURE, DISPLAY BOARD AND ELECTRONIC DEVICE
JP2022574146A JP2024502220A (ja) 2021-01-13 2022-01-13 電極構造、表示パネル及び電子機器
CN202280000135.0A CN115702380A (zh) 2021-01-13 2022-01-13 电极结构、显示面板及电子设备

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
CN202110041652.X 2021-01-13
CN202110041652.XA CN114764204A (zh) 2021-01-13 2021-01-13 显示面板及电子设备
CNPCT/CN2021/083044 2021-03-25
PCT/CN2021/083044 WO2022198578A1 (zh) 2021-03-25 2021-03-25 像素单元、阵列基板和显示面板
PCT/CN2021/085622 WO2022213256A1 (zh) 2021-04-06 2021-04-06 像素电极、阵列基板及显示装置
CNPCT/CN2021/085622 2021-04-06

Publications (2)

Publication Number Publication Date
WO2022152223A1 true WO2022152223A1 (zh) 2022-07-21
WO2022152223A9 WO2022152223A9 (zh) 2022-11-24

Family

ID=82447999

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/071870 WO2022152223A1 (zh) 2021-01-13 2022-01-13 电极结构、显示面板及电子设备

Country Status (6)

Country Link
US (1) US20230185141A1 (zh)
EP (1) EP4145215A4 (zh)
JP (1) JP2024502220A (zh)
KR (1) KR20230127198A (zh)
CN (1) CN115702380A (zh)
WO (1) WO2022152223A1 (zh)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN202141876U (zh) * 2011-07-05 2012-02-08 北京京东方光电科技有限公司 一种薄膜晶体管阵列基板与液晶显示面板及液晶显示器
CN105572983A (zh) * 2016-03-11 2016-05-11 深圳市华星光电技术有限公司 一种像素电极结构及液晶显示面板
CN106444171A (zh) * 2016-08-03 2017-02-22 厦门天马微电子有限公司 一种液晶显示面板及液晶显示装置
CN107255879A (zh) * 2017-08-01 2017-10-17 京东方科技集团股份有限公司 一种阵列基板、显示面板及显示装置
CN111505870A (zh) * 2020-05-19 2020-08-07 武汉京东方光电科技有限公司 像素电极、像素结构、显示面板及显示装置
WO2021168683A1 (zh) * 2020-02-26 2021-09-02 京东方科技集团股份有限公司 液晶显示面板及液晶显示装置
CN214375724U (zh) * 2021-01-13 2021-10-08 京东方科技集团股份有限公司 显示面板及电子设备

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4829501B2 (ja) * 2005-01-06 2011-12-07 シャープ株式会社 液晶表示装置
JP5425485B2 (ja) * 2009-02-09 2014-02-26 株式会社ジャパンディスプレイ 液晶表示装置
JP6116220B2 (ja) * 2012-12-12 2017-04-19 三菱電機株式会社 液晶表示パネル
KR102069821B1 (ko) * 2013-07-03 2020-01-28 삼성디스플레이 주식회사 액정 표시 장치
KR20150026586A (ko) * 2013-09-03 2015-03-11 엘지디스플레이 주식회사 컬럼스페이서를 구비한 액정표시소자
CN103488002B (zh) * 2013-09-18 2015-03-11 京东方科技集团股份有限公司 像素电极、阵列基板和显示装置
CN105629591B (zh) * 2016-01-11 2018-10-30 京东方科技集团股份有限公司 一种阵列基板、其制备方法及液晶显示面板
CN107272271A (zh) * 2017-08-16 2017-10-20 京东方科技集团股份有限公司 一种显示面板及其制作方法、显示装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN202141876U (zh) * 2011-07-05 2012-02-08 北京京东方光电科技有限公司 一种薄膜晶体管阵列基板与液晶显示面板及液晶显示器
CN105572983A (zh) * 2016-03-11 2016-05-11 深圳市华星光电技术有限公司 一种像素电极结构及液晶显示面板
CN106444171A (zh) * 2016-08-03 2017-02-22 厦门天马微电子有限公司 一种液晶显示面板及液晶显示装置
CN107255879A (zh) * 2017-08-01 2017-10-17 京东方科技集团股份有限公司 一种阵列基板、显示面板及显示装置
WO2021168683A1 (zh) * 2020-02-26 2021-09-02 京东方科技集团股份有限公司 液晶显示面板及液晶显示装置
CN111505870A (zh) * 2020-05-19 2020-08-07 武汉京东方光电科技有限公司 像素电极、像素结构、显示面板及显示装置
CN214375724U (zh) * 2021-01-13 2021-10-08 京东方科技集团股份有限公司 显示面板及电子设备

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4145215A4

Also Published As

Publication number Publication date
JP2024502220A (ja) 2024-01-18
EP4145215A1 (en) 2023-03-08
WO2022152223A9 (zh) 2022-11-24
KR20230127198A (ko) 2023-08-31
CN115702380A (zh) 2023-02-14
EP4145215A4 (en) 2024-04-17
US20230185141A1 (en) 2023-06-15

Similar Documents

Publication Publication Date Title
CN111090202B (zh) 显示面板及显示装置
US11860492B2 (en) Liquid crystal display device
WO2021208643A1 (zh) 显示面板及显示装置
CN214375724U (zh) 显示面板及电子设备
CN101950101B (zh) 液晶显示面板
WO2020124896A1 (zh) 液晶显示面板
WO2015180302A1 (zh) 阵列基板及其制备方法、显示装置
US11294245B2 (en) Display panel, manufacturing method therefor, and display device
TWI647524B (zh) 陣列基板及液晶顯示面板
WO2019062320A1 (zh) 阵列基板及其制备方法、显示装置
WO2022152223A1 (zh) 电极结构、显示面板及电子设备
KR20070080475A (ko) 박막 트랜지스터 기판 및 액정 표시 장치
US20200004073A1 (en) Liquid crystal display device
US20230152635A1 (en) Display panel and display device
WO2022151836A1 (zh) 显示面板及电子设备
WO2022088102A1 (zh) 电极结构、显示面板及显示装置
TW201917475A (zh) 顯示面板
US20230161206A1 (en) Liquid crystal display panel
CN114967254A (zh) 阵列基板及液晶显示装置
US20230110276A1 (en) Array substrate and display device
KR20060128564A (ko) 액정 표시 장치, 박막 트랜지스터 기판 및 그 제조 방법
WO2023184426A1 (zh) 阵列基板、显示面板及显示装置
WO2023060547A1 (zh) 阵列基板及其制备方法、显示装置
KR20130064262A (ko) 박막트랜지스터 기판 및 그 제조 방법
CN115327823A (zh) 显示面板及其制备方法、显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22739099

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 2022574146

Country of ref document: JP

ENP Entry into the national phase

Ref document number: 2022739099

Country of ref document: EP

Effective date: 20221128

NENP Non-entry into the national phase

Ref country code: DE