WO2022213256A1 - 像素电极、阵列基板及显示装置 - Google Patents

像素电极、阵列基板及显示装置 Download PDF

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Publication number
WO2022213256A1
WO2022213256A1 PCT/CN2021/085622 CN2021085622W WO2022213256A1 WO 2022213256 A1 WO2022213256 A1 WO 2022213256A1 CN 2021085622 W CN2021085622 W CN 2021085622W WO 2022213256 A1 WO2022213256 A1 WO 2022213256A1
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WIPO (PCT)
Prior art keywords
electrode
sub
group
strip
slit
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PCT/CN2021/085622
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English (en)
French (fr)
Inventor
陈晓晓
江鹏
郭远辉
朱宁
李云
石侠
刘建涛
Original Assignee
京东方科技集团股份有限公司
武汉京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 武汉京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP21935493.3A priority Critical patent/EP4209835A4/en
Priority to CN202180000716.XA priority patent/CN115812175A/zh
Priority to PCT/CN2021/085622 priority patent/WO2022213256A1/zh
Priority to JP2023525089A priority patent/JP2024512846A/ja
Priority to US17/639,030 priority patent/US20240036426A1/en
Priority to US17/764,734 priority patent/US20230185141A1/en
Priority to KR1020237003286A priority patent/KR20230127198A/ko
Priority to PCT/CN2022/071870 priority patent/WO2022152223A1/zh
Priority to EP22739099.4A priority patent/EP4145215A4/en
Priority to JP2022574146A priority patent/JP2024502220A/ja
Priority to CN202280000135.0A priority patent/CN115702380A/zh
Publication of WO2022213256A1 publication Critical patent/WO2022213256A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G02F1/133707—Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a pixel electrode, an array substrate and a display device.
  • the purpose of the present disclosure is to provide a pixel electrode, an array substrate and a display device, thereby at least to a certain extent overcoming one or more problems caused by limitations and defects of the related art.
  • a first aspect of the present disclosure provides a pixel electrode, comprising: a first edge conductive part and a second edge conductive part spaced in a first direction, and at least partially located on the first edge conductive part and the second edge conductive part the main conductive part between the second edge conductive parts, the main conductive part is respectively connected with the first edge conductive part and the second edge conductive part, the main conductive part includes at least one first group of sub-conductive parts part and at least one second group of sub-conducting parts, the first group of sub-conducting parts and the second group of sub-conducting parts are alternately arranged in the first direction;
  • the first group of sub-conducting parts includes a first connection bar, the first connection bar extends in the first direction and has a first surface and a second surface opposite in the second direction; the The first group of sub-conducting parts has a first slit located on the side of the first surface away from the second surface, and one end of the first slit away from the first connecting bar is an open end;
  • the second group of sub-conductive parts includes a second connection bar located on a side of the first gap away from the first connection bar and connected to the first group of sub-conductive parts, the second connection bar extending in the first direction and having a third face and a fourth face opposite in the second direction, the third face being located on a side of the fourth face close to the first face; and the The second group of sub-conducting parts has a second slit located on the side of the third surface away from the fourth surface, and one end of the second slit away from the second connecting bar is an open end;
  • the pixel electrode in the second direction, is configured such that the first connection bar is closer to the transistor than the second connection bar; and the first edge conductive portion or the second An end of the edge conductive portion away from the second connection bar is configured to be connected with the transistor;
  • the sum of the lengths of the first connecting bars in the at least one first group of sub-conducting portions is less than the sum of the lengths of the second connecting bars in the at least one second group of sub-conducting portions;
  • the first direction intersects with the second direction.
  • the first group of sub-conducting parts further includes a plurality of first electrode strips arranged at intervals in the first direction, and the plurality of first electrode strips are located at positions of the first surface away from the second surface and connected with the first surface; the first gap is provided between two adjacent first electrode strips;
  • the second group of sub-conducting parts further includes a plurality of second electrode strips arranged at intervals in the first direction, and the plurality of second electrode strips are located at positions of the third surface away from the fourth surface and connected with the third surface; the second gap is arranged between two adjacent second electrode strips;
  • the third surface of the second connecting bar is connected to the end of the first electrode bar that is closest to the second group of sub-conducting parts and is far away from the first connecting bar.
  • the length of the first connecting bar is smaller than the length of the second connecting bar.
  • the main conductive portion includes one of the first group of sub-conductive portions and one of the second group of sub-conductive portions,
  • the first edge conductive part is located on the side of the plurality of first electrode strips away from the second group of sub-conductive parts, and is located on the first surface of the first connecting strip away from the second surface. position; the first edge conductive portion is connected to the first surface, and has a third gap with the first electrode strip adjacent to it, and the end of the third gap away from the first connecting strip is open end;
  • the second edge conductive portion is located on the side of the plurality of second electrode strips away from the first group of sub-conductive parts, and is located on the third surface of the second connection strip away from the fourth surface. position; the second edge conductive portion is connected to the third surface, and has a fourth gap with the second electrode bar adjacent to it, and the end of the fourth gap away from the second connection bar is open end.
  • extending directions of the first electrode strips, the first slits and the third slits are the same and intersect with the first direction and the second direction; and
  • the extending directions of the second electrode strips, the second slits and the fourth slits are the same and intersect with the first direction and the second direction.
  • the first electrode strips, the second electrode strips, the first slits, the second slits, the third slits, and the fourth slits Equal width.
  • the extension directions of the first electrode strips and the second electrode strips are the same, and there is a certain distance between the adjacent first electrode strips and the second electrode strips. the second gap.
  • the extending directions of the first electrode strips and the extending directions of the second electrode strips are arranged in a mirror image with respect to the second direction.
  • the second group of sub-conducting parts further includes an adjustment part, and the adjustment part is located on a side of the plurality of second electrode strips close to the first group of sub-conducting parts , and is located at the position where the third surface of the second connecting bar is far away from the fourth surface, and the adjusting portion is connected with the third surface of the second connecting bar;
  • a fifth gap is formed between the adjustment part and the first electrode strip adjacent to it, and a sixth gap is formed between the adjustment part and the second electrode strip adjacent to it;
  • the ends of the fifth slot and the sixth slot away from the second connecting bar are both open ends;
  • the fifth slit and the first slit extend in the same direction and have the same width
  • the sixth slit and the second slit extend in the same direction and have the same width
  • the adjustment part includes a first adjustment bar and a second adjustment bar, and the fifth gap is formed between the first adjustment bar and the first electrode bar, so The sixth gap is formed between the second adjustment strip and the second electrode strip;
  • the extension direction of the first adjustment strip is the same as the extension direction of the first electrode strip and the width is the same, and the extension direction of the second adjustment strip is the same as the extension direction of the second electrode strip and the width is the same;
  • One end of the first adjusting bar and the second adjusting bar in the extending direction is connected with the third surface of the second connecting bar, and the other ends are connected with each other.
  • the sum of the lengths of the first connection bars in the at least one first group of sub-conducting parts and the second connection in the at least one second group of sub-conducting parts is 0.1 to 0.9.
  • a second aspect of the present disclosure provides an array substrate, which includes a first substrate and sub-pixels located on the first substrate and arranged in an array along a first direction and a second direction, wherein the sub-pixels include the transistor and the pixel electrode according to any one of the above, wherein the end of the first edge conductive part or the second edge conductive part of the pixel electrode that is far away from the second connection bar is connected to the transistor;
  • the transistor In the second direction, the transistor is disposed closer to the first connection bar than the second connection bar of the pixel electrode.
  • the orthographic projection of the transistor on the first substrate and the orthographic projection of the first connection bar of the pixel electrode on the first substrate are on the first substrate. Relatively arranged in the first direction.
  • two adjacent pixel electrodes in the second direction are two adjacent pixel electrodes in the second direction:
  • An end of the first edge conductive portion of one that is far away from the second connection bar is connected to the transistor, and is closer to the transistor connected thereto than the second edge conductive portion thereof;
  • the end of the second edge conductive portion of the other is connected to the transistor, and is closer to the transistor connected thereto than the first edge conductive portion thereof.
  • the array substrate further includes a plurality of data lines formed on the first substrate, the data lines extending in the first direction, and the data lines are connected to the first substrate.
  • the sub-pixels are alternately arranged in the second direction;
  • the distance between the first connection strip and the data line closest to it is the first distance
  • the second connection strip and the data line closest to it are the first distance.
  • the spacing between the data lines is a second spacing, and the first spacing and the second spacing are equal.
  • each of the data lines is connected to a transistor of each of the sub-pixels adjacent to it on the same side in the second direction;
  • the first pole and the second pole of the transistor are arranged in the same layer as the data line, and are located on the side of the pixel electrode close to the first substrate; the first pole of the transistor is connected to the data line.
  • the second electrode of the transistor is connected to the second edge conductive part or the first edge conductive part of the pixel electrode through a transfer via hole.
  • the first electrode and the second electrode of the transistor are arranged at intervals in the first direction, and the first electrode and the second electrode are in the first direction.
  • the spacing in the direction is the third spacing;
  • the ratio of the sum of the lengths of the first connecting bars in the at least one first group of sub-conducting portions to the third spacing is 2 to 20.
  • the sub-pixel further includes a common electrode, which is located on a side of the pixel electrode close to the first substrate and is insulated from the pixel electrode;
  • the orthographic projection of the common electrode on the first substrate overlaps with the orthographic projection of the pixel electrode on the first substrate, and does not overlap with the data line on the first substrate There is an overlap of the orthographic projections on .
  • the array substrate further includes a plurality of scan lines and a plurality of common lines formed on the first substrate and extending in the second direction, the scan lines The lines and the common lines are alternately arranged in the first direction, and the orthographic projection of the scanning line on the first substrate is not the same as the orthographic projection of the common line on the first substrate there is overlap;
  • the scan line and the common line are arranged in the same layer, and the scan line and the common line are located on the side of the data line close to the first substrate and are insulated from the data line set up;
  • one side of the sub-pixel in the first direction is adjacent to the common line, and the other side is adjacent to the scan line;
  • each of the scan lines is connected to the gates of the transistors of the sub-pixels that are located on the same side in the first direction and adjacent to it;
  • each of the common lines is connected to the common electrodes of the sub-pixels located on the same side in the first direction and adjacent thereto.
  • a portion of the scan line constitutes a gate of the transistor, and the common electrode is in contact with the common line.
  • a third aspect of the present disclosure provides a display device, which includes the array substrate described in any one of the above and a counter substrate arranged in a cell-to-cell manner with the array substrate.
  • FIG. 1 shows a schematic structural diagram of a pixel electrode according to an embodiment of the present disclosure
  • FIG. 2 shows a schematic structural diagram of a pixel electrode according to another embodiment of the present disclosure
  • FIG. 3 shows a schematic structural diagram of the pixel electrode described in the related art
  • FIG. 4 shows a schematic structural diagram of a minimum repeating unit of an array substrate according to an embodiment of the present disclosure
  • FIG. 5 is a schematic structural diagram of a minimum repeating unit of an array substrate according to another embodiment of the present disclosure.
  • FIG. 6 shows a schematic cross-sectional structure diagram of an array substrate according to an embodiment of the present disclosure.
  • an embodiment of the present disclosure provides a pixel electrode 10 , which can be applied to a liquid crystal display product, but is not limited thereto.
  • the pixel electrode 10 may include a first edge conductive portion 101 and a second edge conductive portion 102 arranged at intervals in the first direction Y, and at least partially located in the first edge conductive portion 101 and the second edge conductive portion 102 between the main conductors.
  • the main conductive part is connected to the first edge conductive part 101 and the second edge conductive part 102 respectively, and the main conductive part may include at least one first group of sub-conductive parts and at least one second group of sub-conductive parts, the first group of sub-conductive parts The conductive parts and the second group of sub-conductive parts are alternately arranged in the first direction Y.
  • the aforementioned first group of sub-conducting parts may include first connecting strips 103 and a plurality of first electrode strips 104 arranged at intervals in the first direction Y.
  • the first connecting bar 103 extends in the first direction Y (ie, the length direction of the first connecting bar 103 is the first direction Y).
  • the first connecting bar 103 may have a first surface 103a and a second surface 103b opposite to each other in the second direction X. It should be noted that the first direction Y may intersect the second direction X.
  • the first The direction Y and the second direction X may be perpendicular to each other; and the plurality of first electrode strips 104 may be located on the first surface 103a away from the second surface 103b and connected to the first surface 103a.
  • a gap is formed between two adjacent first electrode strips 104, which can be defined as a first gap S1, and the ends of the two adjacent first electrode strips 104 away from the first connecting strip 103 are in a state of being disconnected from each other, that is, :
  • One end of the first slit S1 away from the first connecting bar 103 is open, wherein, for the convenience of description, the end of the first slit S1 away from the first connecting bar 103 may be defined as an open end.
  • the aforementioned second group of sub-conducting parts includes second connection bars 105 and a plurality of second electrode bars 106 spaced in the first direction Y.
  • the second connection bars 105 are in the first direction Y. It extends in the first direction Y (that is, the length direction of the second connecting bar 105 is the first direction Y).
  • the second connection bar 105 may have a third surface 105a and a fourth surface 105b opposite in the second direction X, and in the second direction X, the third surface 105a of the second connection bar 105 may be located at the fourth surface of the second connection bar 105
  • the surface 105b is close to one side of the first surface 103a of the first connecting bar 103 .
  • the third surface 105a of the second connection bar 105 can be connected to the first electrode bar 104 close to the second group of sub-conducting parts, specifically connected to the end of the first electrode bar 104 away from the first connection bar 103.
  • the first electrode strips 104 close to the second group of sub-conducting parts mentioned here refer to the first electrode strips 104 closest to the second group of sub-conducting parts in the first group of sub-conducting parts.
  • the plurality of second electrode strips 106 are located at positions where the third surface 105 a of the second connecting strip 105 is far from the fourth surface 105 b and are connected to the third surface 105 a of the second connecting strip 105 .
  • a gap is formed between two adjacent second electrode strips 106, which can be defined as a second gap S2.
  • the ends of the two adjacent second electrode strips 106 away from the second connecting strip 105 are in a state of being disconnected from each other, that is, :
  • One end of the second slit S2 away from the second connection bar 105 is open, wherein, for the convenience of description, the end of the second slot S2 away from the second connection bar 105 may be defined as an open end.
  • the pixel electrode 10 may be connected to the transistor 20 (as shown in FIG. 4 and FIG. 5 ) through the aforementioned first edge conductive part 101 or the second edge conductive part 102 .
  • the end of the edge conductive portion 101 or the second edge conductive portion 102 away from the second connection bar 105 may be configured to be connected to the transistor 20; and in the second direction X, the pixel electrode 10 is configured to be in phase with the first connection bar 103 thereof. Closer to the transistor 20 than the second connection bar 105, it should be understood that the transistor 20 may be connected to the data line 40 adjacent thereto (as shown in FIG. 4 and FIG. 5).
  • the peripheries of the first slit S1 and the second slit S2 of the pixel electrode 10 are not completely closed, that is, the end of the first slit S1 close to the second connection bar 105 is an open end , and the end of the second slit S2 close to the first connecting bar 103 is an open end.
  • the open end of the first slit S1 and the second slit The open ends of S2 may be adjacent to the data lines 40 on both sides of the pixel electrode 10 (as shown in FIG. 4 and FIG. 5 ), respectively.
  • This design is compared with the pixel in the related art shown in FIG.
  • the electrode 1 is applied to a liquid crystal display product, the range of the dark field region of the liquid crystal display product can be effectively reduced, thereby improving the transmittance of the liquid crystal display product.
  • a lateral capacitance exists between the first pole 201 and the second pole 202 of the transistor 20 , and in the second direction X, the transistor 20 is compared with the second connecting bar 105 is closer to the first connecting bar 103; that is, when driving the display product, the side where the first connecting bar 103 of the pixel electrode 10 is located is closer than the side where the second connecting bar 105 is located (as shown in FIGS. 4 and 5 ).
  • the side capacitance generated between the first electrode 201 and the second electrode 202 of the transistor 20 will be added to the right side of the shown pixel electrode); that is, the pixel electrode 10 shown in FIG. 4 and FIG.
  • the generated capacitance may include the lateral capacitance generated between the first connection bar 103 and the data line 40 and the lateral capacitance generated between the first pole 201 and the second pole 202 of the transistor 20, and the capacitance generated on the right side thereof may include
  • the lateral capacitance generated by the second connecting bar 105 and the data line 40 shows that the left side of the pixel electrode 10 as shown in FIG. 4 and FIG. 5 has more first poles 201 and second poles of the transistor 20 than the right side.
  • the lateral capacitance generated between 202 may include the lateral capacitance generated between the first connection bar 103 and the data line 40 and the lateral capacitance generated between the first pole 201 and the second pole 202 of the transistor 20, and the capacitance generated on the right side thereof may include
  • the lateral capacitance generated by the second connecting bar 105 and the data line 40 shows that the left side of the pixel electrode 10 as shown in FIG. 4 and FIG. 5 has more first poles 201 and second poles of the transistor 20 than the
  • the sum of the lengths of the first connecting strips 103 of each first group of sub-conducting parts in the pixel electrode 10 is designed to be greater than or equal to the sum of the lengths of the second connecting strips 105 of each second group of sub-conducting parts, that is: the pixel electrode
  • the sum of the capacitances generated between each first connecting strip 103 of 10 and its adjacent data lines 40 is greater than or equal to the sum of the capacitances generated between each second connecting strip 105 and its adjacent data lines 40;
  • the side where the first connection bar 103 of the electrode 10 is located is more than the side where the second connection bar 105 is located, the lateral capacitance generated between the first electrode 201 and the second electrode 202 of the transistor 20 is larger.
  • the sum of the lengths of the first connecting strips 103 of the first group of sub-conducting parts in the pixel electrode 10 can be designed to be smaller than each The sum of the lengths of the second connecting bars 105 of the two groups of sub-conducting portions; it should be noted that the length mentioned here refers to the length in the extending direction thereof.
  • the ratio of the sum of the lengths of the first connecting strips 103 of the first group of sub-conducting parts to the sum of the lengths of the second connecting strips 105 of each second group of the sub-conducting parts in the pixel electrode 10 may be 0.1 to 0.9 , such as: 0.1, 0.3, 0.5, 0.7, 0.9, etc., but not limited to this; is 30 ⁇ m to 90 ⁇ m, such as: 30 ⁇ m, 40 ⁇ m, 50 ⁇ m, 60 ⁇ m, 70 ⁇ m, 80 ⁇ m, 90 ⁇ m, etc., but not limited to this;
  • the value range may be 60 ⁇ m to 120 ⁇ m, such as: 60 ⁇ m, 70 ⁇ m, 80 ⁇ m, 90 ⁇ m, 100 ⁇ m, 110 ⁇ m, 110 ⁇ m, etc., but not limited thereto.
  • the sum of the lengths of the first connecting bars 103 of the first group of sub-conducting parts and the sum of the lengths of the second connecting bars 105 of each second group of the sub-conducting parts The value range of the ratio, the sum of the lengths of the first connecting strips 103 of each first group of sub-conducting parts in the pixel electrode 10 and the sum of the lengths of the second connecting strips 105 of each first group of sub-conducting parts in the pixel electrode 10 It is not limited to the numerical range mentioned above, which can be determined according to the size of the transistor 20; that is, when designing a product, the size of the transistor 20 in the product can be determined first, so that the first pole 201 of the transistor 20 and the The lateral capacitance generated between the second electrodes 202, and then the length of the first connecting bar 103 and the length of the second connecting bar 105 of the pixel electrode 10 are designed and adjusted so that the first connecting bar 103 of the
  • the number of the first group of sub-conductive portions and the second group of sub-conductive portions in the main conductive portion of the pixel electrode 10 in the embodiment of the present disclosure may be the same, for example: one, two, etc.; but Not limited to this, the numbers of the first group of sub-conductive portions and the second group of sub-conductive portions in the main conductive portion of the pixel electrode 10 may also be different, that is, the number of the first group of sub-conductive portions in the main conductive portion of the pixel electrode 10 is greater than or less than the number of the second group of sub-conducting parts, and so on.
  • the sum of the lengths of the first connecting strips 103 of the first group of sub-conductive parts in the pixel electrode 10 mentioned above It is designed to be smaller than the sum of the lengths of the second connecting strips 105 of the second group of sub-conducting parts, which can be understood as: the length of the first connecting strips 103 of the first group of sub-conducting parts in the pixel electrode 10 is smaller than that of the second group of sub-conducting parts. the length of the second connecting strip 105.
  • the main conductive portion of the pixel electrode 10 in the embodiment of the present disclosure may include a first group of sub-conductive portions and a second group of sub-conductive portions.
  • the first edge of the pixel electrode 10 is conductive.
  • the portion 101 is located on the side of the plurality of first electrode strips 104 away from the second group of sub-conducting portions, and is located at a position where the first surface 103a of the first connecting strip 103 is away from the second surface 103b; and the first edge conductive portion 101 can be It is connected to the first surface 103 a and has a third gap S3 between the adjacent first electrode strip 104 , and the adjacent first edge conductive portion 101 and the first electrode strip 104 are far away from the first connection strip 103
  • the ends are disconnected from each other, that is, one end of the third slit S3 away from the first connecting bar 103 is open, wherein, for the convenience of description, the end of the third slit S3 away from the first connecting bar 103 can be defined as an open end;
  • the second edge conductive portion 102 is located on the side of the plurality of second electrode strips 106 away from the first group of sub-conductive parts, and is located at a position where the third surface 105a of the second connecting strip 105 is
  • the ends are disconnected from each other, that is, the end of the fourth slot S4 away from the first connecting bar 103 is open, wherein, for the convenience of description, the end of the fourth slot S4 away from the second connecting bar 105 can be defined as the open end .
  • the extension directions of the first electrode strips 104, the first slits S1 and the third slits S3 are the same to ensure the display uniformity at the first group of sub-conducting parts of the pixel electrode 10; and the first electrode strips 104, the third The extending directions of the first slit S1 and the third slit S3 both intersect with the aforementioned first direction Y and second direction X, so as to reduce color shift.
  • the extending directions of the second electrode strips 106 , the second slits S2 and the fourth slits S4 are the same to ensure the display uniformity at the second group of sub-conducting parts of the pixel electrode 10 ; and the second electrode strips 106 , the second The extending directions of the slits S2 and the fourth slits S4 both intersect with the aforementioned first direction Y and second direction X, so as to reduce color shift.
  • the widths of the first electrode strips 104, the second electrode strips 106, the first slits S1, the second slits S2, the third slits S3 and the fourth slits S4 are equal to better ensure the uniformity of product display; it needs to be explained Rather, the width mentioned here is the dimension in the direction perpendicular to the direction in which it extends.
  • the aforementioned extension directions of the first electrode strips 104 and the second electrode strips 106 may be the same, that is, the first electrode strips 104 and the second electrode strips 106 may extend in the same direction, that is, the pixel electrode 10 of the present disclosure may have a monodomain structure, which can reduce the difficulty of design. It should be noted that, in this embodiment, the gap between the adjacent first electrode strips 104 and the second electrode strips 106 may be the aforementioned second gap S2.
  • the extending direction of the first electrode strips 104 and the extending direction of the second electrode strips 106 may be arranged in a mirror image with respect to the second direction X, that is, the present
  • the disclosed pixel electrode 10 may have a dual-domain structure, which can expand the viewing angle of the product; it should be noted that, in the embodiment of the present disclosure, the extension direction of the first electrode strip 104 and the extension direction of the second electrode strip 106 are between The included angle can be an acute angle.
  • the second group of sub-conducting parts of the pixel electrode 10 may further include an adjustment part 107 , and the adjustment part 107 may be located in the plurality of second electrode strips 106 close to the second group of conductive parts 107 .
  • One side of a group of sub-conducting portions is located at a position where the third surface 105a of the second connecting bar 105 is far from the fourth surface 105b , and the adjusting portion 107 can be connected to the third surface 105a of the second connecting bar 105 .
  • a fifth slit S5 is formed between the adjustment part 107 and the first electrode strip 104 adjacent to it, and a sixth gap S5 is formed between the adjustment part 107 and the second electrode strip 106 adjacent to it.
  • this design can ensure that the electric field at the junction of the first group of sub-conducting parts and the second group of sub-conducting parts in the pixel electrode 10 is closer to the electric field in other parts of the pixel electrode 10, thereby ensuring display uniformity.
  • the adjusting portion 107 may include a first adjusting bar 107a and a second adjusting bar 107b, and the aforementioned fifth slit S5 is formed between the first adjusting bar 107a and the first electrode bar 104,
  • the above-mentioned sixth slit S6 is formed between the second adjustment strip 107b and the second electrode strip 106; wherein, the extension direction of the first adjustment strip 107a and the extension direction of the first electrode strip 104 can be the same and the width is equal, and the second The extension direction of the adjustment bar 107b can be the same as the extension direction of the second electrode bar 106 and the width is the same, so as to further ensure the uniformity of the electric field and thus ensure the uniformity of the display.
  • first adjusting bar 107a and the second adjusting bar 107b in the extending direction thereof is connected to the third surface 105a of the second connecting bar 105, and the other end may be connected to each other. It should be understood that the present disclosure In the embodiment, a slit pattern is formed between the first adjustment bar 107a and the second adjustment bar 107b, which can reduce the dark field area.
  • a spacer (Not shown in the figure), so as to divide the slit pattern into a slit with the same and equal extension direction as the first slit S1, and another slit with the same and equal extension direction as the second slit S2;
  • the spacer may not be provided.
  • the adjustment portion 107 can be a monolithic structure without a slit pattern, as the case may be.
  • the pixel electrode 10 of the embodiment of the present disclosure may have a one-piece structure.
  • the pixel electrode 10 of the embodiment of the present disclosure can be a transparent electrode, and the material thereof can be ITO (indium tin oxide) material, but not limited thereto, indium zinc oxide (IZO), zinc oxide (ZnO), etc. can also be used Made of transparent material.
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • ZnO zinc oxide
  • the present disclosure also provides an array substrate, which can be used in a liquid crystal display device, but is not limited thereto. 1 , 2 and 4 to 6 , the array substrate of the present disclosure may further include a first substrate 30 , on the first substrate 30 and arranged in an array along the first direction Y and the second direction X sub-pixels, a plurality of data lines 40 formed on the first substrate 30, a plurality of scan lines 60 and a plurality of common lines 70 formed on the first substrate 30; it should be noted that the present disclosure implements
  • the first direction Y mentioned in the example may be referred to as the column direction
  • the second direction X may be referred to as the row direction.
  • the first substrate 30 may have a single-layer structure, but is not limited thereto, and the first substrate 30 may also include a multi-layer structure.
  • the material of the first substrate 30 can be glass, but not limited thereto, the material of the first substrate 30 can also be other materials, such as polyimide (PI) and other materials, depending on the specific situation .
  • PI polyimide
  • the data lines 40 may extend in the first direction Y (ie, the column direction), and the data lines 40 and the sub-pixels may be alternately arranged in the second direction X (ie, the row direction).
  • each data line 40 is connected to the sub-pixels located on the same side in the second direction X and adjacent to it, that is, each column of data lines 40 is connected to the adjacent and adjacent sub-pixels.
  • the sub-pixels in the same column are connected to provide data signals for the sub-pixels in the same column.
  • the data line 40 may include a metal material or an alloy material, such as a metal single-layer or multi-layer structure formed of molybdenum, aluminum, titanium, etc. Titanium three-layer metal stack (Ti/Al/Ti), etc.
  • the scan lines 60 and the common lines 70 may extend in the second direction X, and the scan lines 60 and the common lines 70 are alternately arranged in the first direction Y. It should be understood that the scan lines The orthographic projection of 60 on the first substrate 30 does not overlap with the orthographic projection of the common line 70 on the first substrate 30 .
  • the scan lines 60 and the common lines 70 are arranged in the same layer.
  • “same layer arrangement” refers to a layer structure formed by using the same film forming process to form a film layer for forming a specific pattern, and then using the same mask to form a layer structure through one patterning process. That is, one patterning process corresponds to one mask (mask, also called photomask).
  • a patterning process may include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights Or have different thicknesses.
  • the production process is simplified, the production cost is saved, and the production efficiency is improved.
  • the scan line 60 and the common line 70 may be located on the side of the data line 40 close to the first substrate 30 and insulated from the data line 40, that is: the scan line 60 and the common line 70
  • a gate insulating layer 80 is provided between the lines 70 and the data lines 40 , and it should be understood that the gate insulating layer 80 is provided as a whole layer.
  • the adjacent row of scan lines 60 and the row of common lines 70 may be a group, and are set corresponding to one row of sub-pixels, that is, each row of sub-pixels is in the first row
  • One side in the direction Y is adjacent to a row of common lines 70, and the other side is adjacent to a row of scan lines 60; wherein, each scan line 60 is located on the same side and adjacent to it in the first direction Y
  • Each sub-pixel is connected, that is: each row of scan lines 60 can be connected to the sub-pixels adjacent to it and located in the same row to provide scan signals for the same row of sub-pixels; and each common line 70 is located in the first direction.
  • the same side on Y is connected to the adjacent sub-pixels, that is, each row of common lines 70 can be connected to the sub-pixels adjacent to it and located in the same row, so as to provide common signals for the sub-pixels in the same row.
  • the scan lines 60 and the common lines 70 may include metal materials or alloy materials, such as metal single-layer or multi-layer structures formed of molybdenum, aluminum, and titanium.
  • the sub-pixel may include a pixel electrode 10, a transistor 20 and a common electrode 50; wherein:
  • the structure of the pixel electrode 10 may refer to the content described in any of the foregoing embodiments, and the specific structure may be referred to as shown in FIG. 1 and FIG. 2 , which will not be repeated here.
  • the distance between the first connecting bar 103 and the data line 40 closest to it is the first distance h1
  • the second connecting bar 105 and the closest data line 40 are the first distance h1.
  • the spacing between the data lines 40 is the second spacing h2, and the first spacing h1 can be equal to the second spacing h2, which facilitates the subsequent design of the size of the first connecting bar 103 and the second connecting bar 105 and reduces the difficulty of manufacturing, but It should be understood that the first distance h1 may also be different from the second distance h2, depending on the specific situation.
  • the transistor 20 may include an active layer 203, a gate, and a first electrode 201 and a second electrode 202 disposed in the same layer.
  • the first electrode 201 and the second electrode 202 may be It is arranged on the same layer as the aforementioned data line 102 .
  • a gate insulating layer 80 can also be provided between the gate electrode of the transistor 20 and the active layer 203 to insulate the gate electrode and the active layer 203 from each other.
  • the gate insulating layer 80 can be made of inorganic materials, such as , silicon oxide, silicon nitride and other inorganic materials.
  • the gate can be disposed in the same layer as the aforementioned scan line 60 , and the gate can be a part of the aforementioned scan line 60 , that is, a part of the scan line 60 can be used as the transistor 20
  • the gate of the active layer 203 is connected to the transistor 20 to realize the connection between the scan line 60 and the transistor 20; and the first electrode 201 and the second electrode 202 can be respectively connected to the two doped regions of the active layer 203 (ie, the source doped region and the drain doped region) , and the first electrode 201 can also be connected to the data line 40 to realize the connection between the data line 40 and the transistor 20, and the second electrode 202 can be connected to the pixel electrode 10.
  • the first edge conductive portion 101 of the pixel electrode 10 or The end of the second edge conductive portion 102 away from the second connecting bar 105 can be connected to the second electrode 202 of the transistor 20 , so as to realize the connection between the transistor 20 and the pixel electrode 10 .
  • the transistor 20 of each sub-pixel is disposed closer to the first connection bar 103 than the second connection bar 105 of the pixel electrode 10 thereof, which can make the pixel
  • the total capacitance on the side where the first connecting bar 103 of the electrode 10 is located is equal to or substantially equal to the total capacitance on the side where the second connecting bar 105 is located, thereby improving the gray-scale V-Crosstalk phenomenon of the product.
  • the orthographic projection of the transistor 20 on the first substrate 30 is disposed opposite to the orthographic projection of the first connection bar 103 of the pixel electrode 10 on the first substrate 30 in the first direction Y.
  • two adjacent sub-pixels in the second direction X are taken as the minimum repeating unit, wherein, in the two adjacent pixel electrodes 10 in the second direction X: one of the first The end of the edge conductive portion 101 away from the second connection bar 105 is connected to the transistor 20 and is closer to the transistor 20 connected to it than the second edge conductive portion 102 thereof; the second edge conductive portion 102 of the other is far away from the second edge conductive portion 102 The ends of the connection bars 105 are connected to the transistors 20 and are closer to the transistors 20 connected to them than the first edge conducting portions 101 thereof; that is, as shown in FIG.
  • the second connection bars 105 of one and the other One of the first connection bars 103 is adjacent to the data line 40 between the two, and both the first connection bar 103 of the one and the second connection bar 105 of the other are far away from the data line 40 therebetween,
  • one of the two adjacent pixel electrodes 10 in the second direction X can be obtained by vertically flipping the other (ie: mirroring with respect to the second direction X), so that the design can reduce and balance the dark field area at the same time , the product viewing angle can also be enlarged, but not limited to this; the connection relationship between the two adjacent pixel electrodes 10 and the transistor 20 in the second direction X can also be the same, depending on the specific situation.
  • first edge conductive portion 101 or the second edge conductive portion 102 of one of the two adjacent pixel electrodes 10 in the second direction X may be conductive with the first edge conductive portion 101 or the second edge of the other one
  • the structure of the portion 102 can be designed to be exactly the same, but it is not limited to this, and can also be slightly adjusted according to the actual situation, as long as the total capacitance on the side where the first connecting bar 103 of the pixel electrode 10 is located and the total capacitance on the side where the second connecting bar 105 is located can be ensured.
  • the total capacitance should be equal or substantially equal, so as to improve the gray-scale V-Crosstalk phenomenon of the product.
  • the transistor 20 of the embodiment of the present disclosure may be a bottom-gate type, that is, a gate may be formed on the first substrate 30 first, and the gate may include a metal material or an alloy material, such as molybdenum, aluminum and Titanium, etc., to ensure its good electrical conductivity; then, a gate insulating layer 80 is formed on the first substrate 30, as shown in FIG. 6, the gate insulating layer 80 can cover the gate;
  • the active layer 203 is formed on one side of the first substrate 30 , that is, the active layer 203 is located on the side of the gate away from the first substrate 30 , and the active layer 203 is connected to the positive electrode of the gate on the first substrate 30 .
  • the orthographic projection of the active layer 203 on the first substrate 30 may be located within the orthographic projection of the gate on the first substrate; the first pole 201 and the second pole 202 may be formed on the The active layer 203 is then formed, wherein a portion of the first electrode 201 may be located on the side of the active layer 203 away from the first substrate 30 and in contact with the source doped region of the active layer 203, and a portion of the second electrode 202 may be located The side of the active layer 203 away from the first substrate 30 is in contact with the drain doped region of the active layer 203 .
  • the contact mentioned in the embodiments of the present disclosure refers to the fact that there is no other film layer between the two components and they are directly attached together, that is, the two components do not need to pass through other structures (eg, transfer vias) connect.
  • the transistors in the embodiments of the present disclosure are not limited to the bottom-gate type mentioned above, and may also be a top-gate type.
  • the first electrode 201 and the second electrode 202 of the transistor 20 may be arranged at intervals in the first direction Y, and the first electrode 201 and the second electrode 202
  • the spacing in the first direction Y may be the third spacing h3; wherein, the length design of the first connecting strip 103 and the second connecting strip 105 in the pixel electrode 10 mentioned above is related to the size selection of the transistor 20, specifically, the pixel
  • the ratio of the sum of the lengths of the first connecting strips 103 of each first group of sub-conducting parts in the electrode 10 to the third distance h3 may be 2 to 20, for example: 2, 5, 8, 11, 14, 17, 20, etc. etc.
  • the third spacing h3 may be 2 ⁇ m, 3 ⁇ m, 4 ⁇ m, 5 ⁇ m, 6 ⁇ m, etc., but not limited thereto, and may also be other values.
  • the sum of the lengths of the first connecting strips 103 of each first group of sub-conducting parts in the pixel electrode 10 is not only related to the aforementioned third spacing S3, but also related to the distance between the first pole 201 and the second pole 202. Thickness and length are related, wherein the thickness, length and third distance h3 of the first electrode 201 and the second electrode 202 are the keys to determine the lateral capacitance generated between the first electrode 201 and the second electrode 202 in the transistor 20 That is, the length design of the first connecting bar 103 and the second connecting bar 105 in the pixel electrode 10 mainly depends on the lateral capacitance generated between the first electrode 201 and the second electrode 202 in the transistor 20 .
  • the thicknesses of the first electrode 201 and the second electrode 202 in the transistor 20 may be to for example: etc., but not limited to this, other values are also possible; and the length of the first electrode 201 and the second electrode 202 in the transistor 20 may be 5 ⁇ m to 50 ⁇ m, such as: 5 ⁇ m, 15 ⁇ m, 25 ⁇ m, 35 ⁇ m, 45 ⁇ m, 50 ⁇ m, etc. etc., but not limited to this, other values can also be used.
  • first electrode 201 and the second electrode 202 of the transistor 20 are not limited to be arranged at intervals in the first direction Y, but may also be arranged at intervals in the second direction X. It should be noted that, in the transistor 20 When the first pole 201 and the second pole 202 are arranged at intervals in the second direction X, the aforementioned third distance h3 can be understood as the distance between the first pole 201 and the second pole 202 in the second direction X.
  • the length of the first electrode 201 and the second electrode 202 in the transistor 20 refers to the dimension in the direction perpendicular to the arrangement direction of the first electrode 201 and the second electrode 202 .
  • the first electrode 201 and the second electrode 202 of the transistor 20 may be located on the side of the pixel electrode 10 close to the first substrate 30 , that is, when the array substrate is fabricated In this case, the first electrode 201 and the second electrode 202 of the transistor 20 may be fabricated first, and then the pixel electrode 10 may be fabricated.
  • a passivation layer 90 may be further provided between the first electrode 201 and the second electrode 202 of the transistor 20 and the pixel electrode 10 , and the passivation layer 90 may be an inorganic film layer such as silicon nitride. But not limited to this, it can also be an organic film layer. It should be noted that, at this time, the aforementioned first edge conductive portion 101 or the second edge conductive portion 202 of the pixel electrode 10 can be connected to the second electrode 202 of the transistor 20 through the transfer via P.
  • the common electrode 50 may be located on the side of the pixel electrode 10 close to the first substrate 30 and be insulated from the pixel electrode 10 .
  • the common electrode 50 can be specifically formed on the first substrate 30 before the edge layer 203 is fabricated, that is, the gate insulating layer 80 and passivation can be provided between the common electrode 50 and the pixel electrode 10 through a stack.
  • Layer 90 provides insulation.
  • the orthographic projection of the common electrode 50 on the first substrate 30 may overlap with the orthographic projection of the common line 70 on the first substrate 30 , wherein the common electrode 50 may overlap with the aforementioned
  • the mentioned common line 70 contacts specifically, the common electrode 50 may be formed on the first substrate 30 prior to the common line 70 , but not limited thereto, and may also be formed on the first substrate 30 after the common line 70 is formed. on the first substrate 30 .
  • the orthographic projection of the common electrode 50 on the first substrate 30 overlaps with the orthographic projection of the pixel electrode 10 on the first substrate 30 , and does not overlap with the orthographic projection of the data line 40 on the first substrate 30 The orthographic projections overlap.
  • the material of the common electrode 50 can be the same as the material of the pixel electrode 10 , the common electrode 50 can be a transparent electrode, and the material of the common electrode 50 can be ITO (Indium Tin Oxide) material, but not limited to this, indium zinc oxide can also be used (IZO), zinc oxide (ZnO) and other transparent materials.
  • ITO Indium Tin Oxide
  • IZO Indium Tin Oxide
  • ZnO zinc oxide
  • the common electrode 50 may be a plate-shaped electrode, that is, the common electrode 50 is not provided with a slit, but is not limited thereto, and a slit may also be provided, depending on the specific situation.
  • An embodiment of the present disclosure also provides a display device, which may be a liquid crystal display device, but is not limited thereto. Moreover, the display device of the embodiment of the present disclosure may include the array substrate described in any of the foregoing embodiments, which will not be repeated here.
  • the display device may further include an opposite substrate (not shown in the figure) arranged in a cell-to-cell manner with the array substrate, and a liquid crystal layer (not shown in the figure) located between the array substrate and the opposite substrate.
  • the molecules may be negative liquid crystals to improve transmittance, but not limited thereto, and may also be positive liquid crystals.
  • the display device may further include spacers, and the spacers may be integrated on the opposite substrate, but not limited thereto, and may also be integrated on the array substrate, depending on the specific situation.
  • the opposite substrate of the present disclosure may include a second substrate (not shown in the figure) and a black matrix layer (not shown in the figure) located on the side of the second substrate close to the array substrate, and the black matrix layer may have
  • the blocking area and the light-transmitting area, the orthographic projection of the blocking area on the first substrate 30 can completely cover the aforementioned data lines 40, scan lines 60, common lines 70, sub-pixel transistors 20 and spacers, etc. , and the blocking area can also cover the edges of the common electrode 50 and the pixel electrode 10 ; and the orthographic projection of the light-transmitting area on the first substrate 30 can be located in the orthographic projection of the common electrode 50 and the pixel electrode 10 on the first substrate 30 Inside.
  • the opposite substrate of the present disclosure may further include a color filter layer, and the color filter layer may include a red filter block, a green filter block, a blue filter block, and the like.
  • the color filter layer is not limited to be integrated in the opposite substrate, but can also be integrated in the array substrate, depending on the specific situation.
  • the specific type of the display device is not particularly limited, and any type of display device commonly used in the art can be used, such as a TV, a vehicle display, etc., and those skilled in the art can use the display device according to the specific use. Make corresponding selections, which will not be repeated here.
  • the display device also includes other necessary components and components. Taking the display as an example, it may also include a backlight module, a housing, and a main circuit board. , power cord, etc., those skilled in the art can make corresponding supplements according to the specific usage requirements of the display device, which will not be repeated here.

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Abstract

一种像素电极(10)、阵列基板及显示装置，像素电极(10)包括：在第一方向(Y)上间隔排布的第一边缘导电部(101)和第二边缘导电部(102)、及主导电部，主导电部包括至少一个第一组子导电部和至少一个第二组子导电部，第一组子导电部包括第一连接条(103)和第一缝隙(S1)，第一缝隙(S1)远离第一连接条(103)的一端为开口端；第二组子导电部包括位于第一缝隙(S1)远离第一连接条(103)的一侧并与第一组子导电部连接的第二连接条(105)，且第二组子导电部具有第二缝隙(S2)，第二缝隙(S2)远离第二连接条(105)的一端为开口端；各第一组子导电部中第一连接条(103)的长度之和小于各第二组子导电部中第二连接条(105)的长度之和。

Description

像素电极、阵列基板及显示装置 技术领域
本公开涉及显示技术领域，具体而言，涉及一种像素电极、阵列基板及显示装置。
背景技术
随着液晶面板的不断发展，高分辨率的产品被不断开发；但对于8K等高分辨率像素而言，像素间距(即：Dot pitch)较小，存储电容(即：Cst)较小，因此，像素电压更容易受到数据电压的拉动，这样容易出现像素两侧的拉动不对称，从而使得灰阶V-Crosstalk(即：V型串扰)更加严重的现象，影响显示效果。
公开内容
本公开的目的在于提供一种像素电极、阵列基板及显示装置，进而至少在一定程度上克服由于相关技术的限制和缺陷而导致的一个或者多个问题。
本公开第一方面提供了一种像素电极，其中，包括：在第一方向上间隔排布的第一边缘导电部和第二边缘导电部、及至少部分位于所述第一边缘导电部和所述第二边缘导电部之间的主导电部，所述主导电部分别与所述第一边缘导电部和所述第二边缘导电部连接，所述主导电部包括至少一个第一组子导电部和至少一个第二组子导电部，所述第一组子导电部和所述第二组子导电部在所述第一方向上交替排布；
其中，所述第一组子导电部包括第一连接条，所述第一连接条在所述第一方向上延伸且其具有在第二方向上相对的第一面和第二面；所述第一组子导电部具有位于所述第一面远离所述第二面一侧的第一缝隙，所述第一缝隙远离所述第一连接条的一端为开口端；
其中，所述第二组子导电部包括位于所述第一缝隙远离所述第一连接条的一侧并与所述第一组子导电部连接的第二连接条，所述第二连接条在所述第一方向上延伸且其具有在第二方向上相对的第三面和第四面，所述第三面位于所述第四面靠近所述第一面的一侧；且所述第二组子导电部具有位于所述第三面远离所述第四面一侧的第二缝隙，所述第二缝隙远离所述第二连接条的一端为开口端；
其中，在所述第二方向上，所述像素电极被配置为其所述第一连接条相比于所述第二连接条更靠近晶体管；且所述第一边缘导电部或所述第二边缘导电部远离所述第二连接条的端部被配置为与所述晶体管连接；
其中，所述至少一个第一组子导电部中所述第一连接条的长度之和小于所述至少一个第二组子导电部中所述第二连接条的长度之和；
其中，所述第一方向与所述第二方向相交。
在本公开的一种示例性实施例中，
所述第一组子导电部还包括在所述第一方向上间隔排布的多个第一电极条，所述多个第一电极条位于所述第一面远离所述第二面的位置并与所述第一面连接；相邻两所述第一电极条之间具有所述第一缝隙；
所述第二组子导电部还包括在所述第一方向上间隔排布的多个第二电极条，所述多个第二电极条位于所述第三面远离所述第四面的位置并与所述第三面连接；相邻两所述第二电极条之间具有所述第二缝隙；
其中，所述第二连接条的第三面与最靠近所述第二组子导电部的所述第一电极条远离所述第一连接条的端部连接。
在本公开的一种示例性实施例中，所述第一连接条的长度小于所述第二连接条的长度。
在本公开的一种示例性实施例中，所述主导电部包括一个所述第一组子导电部和一个所述第二组子导电部，
所述第一边缘导电部位于所述多个第一电极条远离所述第二组子导电部的一侧，并位于所述第一连接条的所述第一面远离所述第二面的位置；所述第一边缘导电部与所述第一面连接，并和与之相邻的所述第一电极条具有第三缝隙，所述第三缝隙远离所述第一连接条的一端为开口端；
所述第二边缘导电部位于所述多个第二电极条远离所述第一组子导电部的一侧，并位于所述第二连接条的所述第三面远离所述第四面的位置；所述第二边缘导电部与所述第三面连接，并和与之相邻的所述第二电极条具有第四缝隙，所述第四缝隙远离所述第二连接条的一端为开口端。
在本公开的一种示例性实施例中，所述第一电极条、所述第一缝隙和所述第三缝隙的延伸方向相同并与所述第一方向和所述第二方向相交；且所述第二电极条、所述第二缝隙和所述第四缝隙的延伸方向相同并与所述第一方向和所述第二方向相交。
在本公开的一种示例性实施例中，所述第一电极条、所述第二电极条、所述第一缝隙、所述第二缝隙、所述第三缝隙和所述第四缝隙的宽度相等。
在本公开的一种示例性实施例中，所述第一电极条和所述第二电极条的延伸方向相同，且相邻所述第一电极条与所述第二电极条之间具有所述第二缝隙。
在本公开的一种示例性实施例中，所述第一电极条的延伸方向与所述第二电极条的延伸方向关于所述第二方向呈镜像设置。
在本公开的一种示例性实施例中，所述第二组子导电部还包括调整部，所述调整部位于所述多个第二电极条靠近所述第一组子导电部的一侧，并位于所述第二连接条的所述第三面远离所述第四面的位置，所述调整部与所述第二连接条的所述第三面连接；其中，
所述调整部和与之相邻的所述第一电极条之间形成有第五缝隙，并和与之相邻的所述第二电极条之间形成有第六缝隙；
所述第五缝隙和所述第六缝隙远离所述第二连接条的一端均为开口端；
所述第五缝隙与所述第一缝隙的延伸方向相同且宽度相等，所述第六缝隙与所述第二缝隙的延伸方向相同且宽度相等。
在本公开的一种示例性实施例中，所述调整部包括第一调整条和第二调整条，所述第一调整条与所述第一电极条之间形成所述第五缝隙，所述第二调整条与所述第二电极条之间形成所述第六缝隙；其中，
所述第一调整条的延伸方向与所述第一电极条的延伸方向相同且宽度相等，所述第二调整条的延伸方向与所述第二电极条的延伸方向相同且宽度相等；
所述第一调整条和所述第二调整条在其延伸方向上的一端与所述第二连接条的第三面连接，另一端彼此相连。
在本公开的一种示例性实施例中，所述至少一个第一组子导电部中所述第一连接条的长度之和与所述至少一个第二组子导电部中所述第二连接条的长度之和之比为0.1至0.9。
本公开第二方面提供了一种阵列基板，其包括第一衬底和位于所述第一衬底上并沿第一方向和第二方向阵列排布的子像素，其中，所述子像素包括晶体管和上述任一项所述的像素电极，所述像素电极的第一边缘导电部或第二边缘导电部远离第二连接条的端部与所述晶体管连接；
在所述第二方向上，所述晶体管相比于所述像素电极的所述第二连接条更靠近所述第一连接条设置。
在本公开的一种示例性实施例中，所述晶体管在所述第一衬底上的正投影与所述像素电极的第一连接条在所述第一衬底上的正投影在所述第一方向上相对设置。
在本公开的一种示例性实施例中，在所述第二方向相邻两所述像素电极中：
一者的所述第一边缘导电部远离所述第二连接条的端部与所述晶体管连接，并相比于与其所述第二边缘导电部更靠近与其连接的所述晶体管；
另一者的所述第二边缘导电部远离所述第二连接条的端部与所述晶体管连接，并相比于其所述第一边缘导电部更靠近与其连接的所述晶体管。
在本公开的一种示例性实施例中，阵列基板还包括多条形成在所述第一衬底上的数据线，所述数据线在所述第一方向上延伸，且所述数据线与所述子像素在所述第二方向上交替排布；
其中，在所述子像素的所述像素电极中，所述第一连接条和最靠近其的所述数据线之间的间距为第一间距，所述第二连接条和最靠近其的所述数据线之间的间距为第二间距，所述第一间距和所述第二间距相等。
在本公开的一种示例性实施例中，每条所述数据线和位于其在所述第二方向上 的同一侧并和与之相邻的各所述子像素的晶体管连接；
其中，所述晶体管的第一极和第二极与所述数据线同层设置，并位于所述像素电极靠近所述第一衬底的一侧；所述晶体管的第一极与所述数据线连接，所述晶体管的第二极通过转接过孔与所述像素电极的所述第二边缘导电部或所述第一边缘导电部连接。
在本公开的一种示例性实施例中，所述晶体管的第一极和第二极在所述第一方向上间隔排布，所述第一极和所述第二极在所述第一方向上的间距为第三间距；
其中，所述至少一个第一组子导电部中所述第一连接条的长度之和与所述第三间距的比值为2至20。
在本公开的一种示例性实施例中，所述子像素还包括公共电极，位于所述像素电极靠近所述第一衬底的一侧并与所述像素电极之间呈绝缘设置；
且所述公共电极在所述第一衬底上的正投影与所述像素电极在所述第一衬底上的正投影存在交叠，且不与所述数据线在所述第一衬底上的正投影存在交叠。
在本公开的一种示例性实施例中，所述阵列基板还包括形成在所述第一衬底上并在所述第二方向上延伸的多条扫描线和多条公共线，所述扫描线与所述公共线在所述第一方向上交替排布，且所述扫描线在所述第一衬底上的正投影不与所述公共线在所述第一衬底上的正投影存在交叠；
其中，所述扫描线与所述公共线同层设置，且所述扫描线与所述公共线位于所述数据线靠近所述第一衬底的一侧并与所述数据线之间呈绝缘设置；
其中，所述子像素在所述第一方向上的一侧与所述公共线相邻，另一侧与所述扫描线相邻；
其中，每条所述扫描线和位于其在所述第一方向上的同一侧并和与之相邻的各所述子像素的晶体管的栅极连接；
其中，每条所述公共线和位于其在所述第一方向上的同一侧并和与之相邻的各所述子像素的公共电极连接。
在本公开的一种示例性实施例中，所述扫描线的部分构成所述晶体管的栅极，且所述公共电极与所述公共线接触。
本公开第三方面提供了一种显示装置，其中，包括上述任一项所述的阵列基板及与所述阵列基板对盒设置的对置基板。
本公开的其他特性和优点将通过下面的详细描述变得显然，或部分地通过本公开的实践而习得。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1示出了本公开一实施例所述的像素电极的结构示意图；
图2示出了本公开另一实施例所述的像素电极的结构示意图；
图3示出了相关技术所述的像素电极的结构示意图；
图4示出了本公开一实施例所述的阵列基板的最小重复单元的结构示意图；
图5示出了本公开另一实施例所述的阵列基板的最小重复单元的结构示意图；
图6示出了本公开一实施例所述的阵列基板的截面结构示意图。
具体实施方式
下面通过实施例，并结合附图，对本公开的技术方案作进一步具体的说明。在说明书中，相同或相似的附图标号指示相同或相似的部件。下述参照附图对本公开实施方式的说明旨在对本公开的总体发明构思进行解释，而不应当理解为对本公开的一种限制。
另外，在下面的详细描述中，为便于解释，阐述了许多具体的细节以提供对本披露实施例的全面理解。然而明显地，一个或多个实施例在没有这些具体细节的情况下也可以被实施。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。
需要说明的是，虽然术语“第一”、“第二”等可以在此用于描述各种区域、层和/或部分，但是这些区域、层和/或部分不应受到这些术语限制。而是，这些术语用于将一个区域、层和/或部分与另一个相区分。
如图1和图2所示，本公开一实施例提供了一种像素电极10，其可应用于液晶显示产品中，但不限于此。具体地，此像素电极10可包括在第一方向Y上间隔排布的第一边缘导电部101和第二边缘导电部102、及至少部分位于第一边缘导电部101和第二边缘导电部102之间的主导电部。此主导电部分别与第一边缘导电部101和第二边缘导电部102连接，且主导电部可包括至少一个第一组子导电部和至少一个第二组子导电部，此第一组子导电部和第二组子导电部在第一方向Y上交替排布。
如图1和图2所示，前述提到的第一组子导电部可包括第一连接条103和在第一方向Y上间隔排布的多个第一电极条104。此第一连接条103在第一方向Y上延伸(即：第一连接条103的长度方向为第一方向Y)。其中，第一连接条103可具有在第二方向X上相对的第一面103a和第二面103b，需要说明的是，此第一方向Y 可与第二方向X相交，优选地，第一方向Y可与第二方向X相互垂直；而多个第一电极条104可位于第一面103a远离第二面103b的位置并与第一面103a连接。其中，相邻两第一电极条104之间形成有缝隙，其可定义为第一缝隙S1，此相邻两第一电极条104远离第一连接条103的一端呈彼此断开的状态，即：第一缝隙S1远离第一连接条103的一端呈开口状，其中，为了方便描述可将第一缝隙S1远离第一连接条103的一端定义为开口端。
如图1和图2所示，前述提到第二组子导电部包括第二连接条105和在第一方向Y上间隔排布的多个第二电极条106，此第二连接条105在第一方向Y上延伸(即：第二连接条105的长度方向为第一方向Y)。其中，第二连接条105可具有在第二方向X上相对的第三面105a和第四面105b，在第二方向X上，此第二连接条105的第三面105a可位于其第四面105b靠近第一连接条103的第一面103a的一侧。第二连接条105的第三面105a可与靠近第二组子导电部的第一电极条104连接，具体与第一电极条104远离第一连接条103的端部连接，应当理解的是，此处提到的靠近第二组子导电部的第一电极条104指的是第一组子导电部中离第二组子导电部最近的第一电极条104。而多个第二电极条106位于第二连接条105的第三面105a远离第四面105b的位置并与第二连接条105的第三面105a连接。其中，相邻两第二电极条106之间形成有缝隙，其可定义为第二缝隙S2，此相邻两第二电极条106远离第二连接条105的一端呈彼此断开的状态，即：第二缝隙S2远离第二连接条105的一端呈开口状，其中，为了方便描述可将第二缝隙S2远离第二连接条105的一端定义为开口端。
在本公开的实施例中，像素电极10可通过前述提到的第一边缘导电部101或第二边缘导电部102与晶体管20(如图4和图5所示)连接，具体地，第一边缘导电部101或第二边缘导电部102远离第二连接条105的端部可被配置为与晶体管20连接；且在第二方向X上，像素电极10被配置为其第一连接条103相比于第二连接条105更靠近晶体管20，应当理解的是，此晶体管20可和与其邻近的数据线40(如图4和图5所示)连接。
综上可知，在本公开的实施例中，像素电极10的第一缝隙S1和第二缝隙S2的四周并未全部封闭，即：此第一缝隙S1靠近第二连接条105的一端为开口端，且第二缝隙S2靠近第一连接条103的一端为开口端，应当理解的是，本公开实施例的像素电极10应用于显示产品中时，其第一缝隙S1的开口端和第二缝隙S2的开口端可分别与像素电极10两侧的数据线40(如图4和图5所示)相邻，这样设计相比于图3中所示的相关技术中缝隙1a四周全闭合的像素电极1，在其应用于液晶显示产品中时，可有效降低液晶显示产品暗场区的范围，从而可提升液晶显示产品透过率。
应当理解的是，如图4和图5所示，晶体管20的第一极201和第二极202之间 会存在侧向电容，在第二方向X上，晶体管20相比于第二连接条105更靠近第一连接条103；也就是说，在驱动显示产品时，像素电极10的第一连接条103所在的一侧比其第二连接条105所在的一侧(如图4和图5所示的像素电极的右侧)会多出晶体管20的第一极201和第二极202之间产生的侧向电容；即：如图4和图5所示的像素电极10，其左侧产生的电容可包括第一连接条103与数据线40之间产生的侧向电容以及晶体管20的第一极201和第二极202之间产生的侧向电容，其右侧产生的电容可包括第二连接条105和数据线40产生的侧向电容，因此可知，如图4和图5所示的像素电极10的左侧比起右侧多出晶体管20的第一极201和第二极202之间产生的侧向电容。
若将像素电极10中各第一组子导电部的第一连接条103的长度之和设计为大于或等于各第二组子导电部的第二连接条105的长度之和，即：像素电极10的各第一连接条103和与其相邻的数据线40之间产生的电容之和大于或等于各第二连接条105和与其相邻的数据线40之间产生的电容之和；由于像素电极10的第一连接条103所在侧比其第二连接条105所在侧会多出晶体管20的第一极201和第二极202之间产生的侧向电容，因此，像素电极10的第一连接条103所在侧的总电容会比其第二连接条105所在侧的总电容大，这样使得像素电极10两侧受到数据电压的拉动不同，使得显示产品出现灰阶V-Crosstalk更加严重的现象；基于此，为改善产品灰阶V-Crosstalk现象，在本公开的实施例中，可将像素电极10中各第一组子导电部的第一连接条103的长度之和设计为小于各第二组子导电部的第二连接条105的长度之和；需要说明的是，此处提到的长度指的是在其延伸方向上的长度。
可选地，像素电极10中各第一组子导电部的第一连接条103的长度之和与各第二组子导电部的第二连接条105的长度之和之比可为0.1至0.9，比如：0.1、0.3、0.5、0.7、0.9等等，但不限于此；举例而言，像素电极10中各第一组子导电部的第一连接条103的长度之和的取值范围可为30μm至90μm，比如：30μm、40μm、50μm、60μm、70μm、80μm、90μm等等，但不限于此；像素电极10中各第一组子导电部的第二连接条105的长度之和的取值范围可为60μm至120μm，比如：60μm、70μm、80μm、90μm、100μm、110μm、110μm等等，但不限于此。
需要说明的是，本公开实施例的像素电极10中各第一组子导电部的第一连接条103的长度之和与各第二组子导电部的第二连接条105的长度之和之比、像素电极10中各第一组子导电部的第一连接条103的长度之和、以及像素电极10中各第一组子导电部的第二连接条105的长度之和的取值范围不限于前述提到的数值区间，其具体可根据晶体管20的尺寸而定；即：在设计产品时，可先确定产品中晶体管20的尺寸，这样就可以先确定晶体管20的第一极201和第二极202之间产生的侧向电容，然后再对像素电极10的第一连接条103的长度和第二连接条105的长度进行设计调整，以使得像素电极10的第一连接条103所在侧的总电容与其第二连接条 105所在侧的总电容相等或基本相等(即：不超过误差范围)，从而改善产品灰阶V-Crosstalk现象。
此外，应当理解的是，本公开实施例的像素电极10的主导电部中第一组子导电部和第二组子导电部的数量可相同，例如：均为一个、两个等等；但不限于此，像素电极10的主导电部中第一组子导电部和第二组子导电部的数量也可不相同，即：像素电极10的主导电部中第一组子导电部的数量大于或小于第二组子导电部的数量等等。
其中，在像素电极10中第一组子导电部和第二组子导电部的数量相同时，前述提到的像素电极10中各第一组子导电部的第一连接条103的长度之和设计为小于各第二组子导电部的第二连接条105的长度之和，可理解为：像素电极10中第一组子导电部的第一连接条103的长度小于第二组子导电部的第二连接条105的长度。
如图1和图2所示，本公开实施例的像素电极10的主导电部可包括一个第一组子导电部和一个第二组子导电部，此时，像素电极10的第一边缘导电部101位于多个第一电极条104远离第二组子导电部的一侧，并位于第一连接条103的第一面103a远离第二面103b的位置；且其第一边缘导电部101可与第一面103a连接，并和与之相邻的第一电极条104之间具有第三缝隙S3，此相邻的第一边缘导电部101与第一电极条104远离第一连接条103的端部彼此呈断开状态，即：第三缝隙S3远离第一连接条103的一端呈开口状，其中，为了方便描述可将第三缝隙S3远离第一连接条103的一端定义为开口端；而第二边缘导电部102位于多个第二电极条106远离第一组子导电部的一侧，并位于第二连接条105的第三面105a远离第四面105b的位置；第二边缘导电部102与第三面105a连接，并和与之相邻的第二电极条106具有第四缝隙S4，此相邻的第二边缘导电部102与第二电极条106远离第二连接条105的端部彼此呈断开状态，即：第四缝隙S4远离第一连接条103的一端呈开口状，其中，为了方便描述可将此第四缝隙S4远离第二连接条105的一端定义为开口端。
可选地，第一电极条104、第一缝隙S1和第三缝隙S3的延伸方向相同，以保证像素电极10的第一组子导电部处的显示均一性；且第一电极条104、第一缝隙S1和第三缝隙S3的延伸方向均与前述提到的第一方向Y和第二方向X相交，以减小色偏。同理，第二电极条106、第二缝隙S2和第四缝隙S4的延伸方向相同，以保证像素电极10的第二组子导电部处的显示均一性；且第二电极条106、第二缝隙S2和第四缝隙S4的延伸方向均与前述提到的第一方向Y和第二方向X相交，以减小色偏。
进一步地，第一电极条104、第二电极条106、第一缝隙S1、第二缝隙S2、第三缝隙S3和第四缝隙S4的宽度相等，以更好地保证产品显示均一性；需要说明的是，此处提到的宽度为在与其延伸方向相垂直的方向上的尺寸。
在本公开的一可选实施例中，如图1所示，前述提到的第一电极条104和第二 电极条106的延伸方向可相同，即：第一电极条104和第二电极条106可在同一方向上延伸，也就是说，本公开的像素电极10可为单畴结构，这样可降低设计难度。需要说明的是，在此实施例中，相邻第一电极条104与第二电极条106之间的缝隙可为前述提到的第二缝隙S2。
在本公开的另一可选实施例中，如图2所示，第一电极条104的延伸方向可与第二电极条106的延伸方向关于第二方向X呈镜像设置，也就是说，本公开的像素电极10可为双畴结构，这样可扩大产品的可视角度；需要说明的是，本公开实施例中，第一电极条104的延伸方向与第二电极条106的延伸方向之间的夹角可为锐角。
其中，在像素电极10为双畴结构时，如图2所示，像素电极10的第二组子导电部还可包括调整部107，此调整部107可位于多个第二电极条106靠近第一组子导电部的一侧，并位于第二连接条105的第三面105a远离第四面105b的位置，此调整部107可与第二连接条105的第三面105a连接。
具体地，如图2所示，调整部107和与之相邻的第一电极条104之间形成有第五缝隙S5，并和与之相邻的第二电极条106之间形成有第六缝隙S6；此相邻调整部107与第一电极条104远离第二连接条105的端部彼此呈断开状态，且相邻调整部107与第二电极条106远离第二连接条105的端部彼此呈断开状态，即：第五缝隙S5和第六缝隙S6远离所述第二连接条105的一端呈开口状，其中，为了方便描述可将第五缝隙S5和第六缝隙S6远离所述第二连接条105的一端均定义为开口端；其中，第五缝隙S5可与前述提到的第一缝隙S1的延伸方向相同且宽度相等，第六缝隙S6与第二缝隙S2的延伸方向相同且宽度相等；这样设计可保证像素电极10中第一组子导电部和第二组子导电部相接处的电场与像素电极10其他处的电场更接近，从而保证显示均一性。
举例而言，如图2所示，调整部107可包括第一调整条107a和第二调整条107b，第一调整条107a与第一电极条104之间形成前述提到的第五缝隙S5，第二调整条107b与第二电极条106之间形成前述提到的第六缝隙S6；其中，第一调整条107a的延伸方向可与第一电极条104的延伸方向相同且宽度相等，第二调整条107b的延伸方向可与第二电极条106的延伸方向相同且宽度相等，以进一步保证电场均一性，从而保证显示均一性。
需要说明的是，第一调整条107a和第二调整条107b在其延伸方向上的一端与第二连接条105的第三面105a连接，而另一端可彼此相连，应当理解的是，本公开实施例的第一调整条107a与第二调整条107b之间形成有缝隙图案，这样设计可减小暗场区。
其中，若第一调整条107a与第二调整条107b之间形成的缝隙图案宽度较大时，还可在此缝隙图案中在设置与第二连接条105的第三面105a连接的间隔部(图中未示出)，以将此缝隙图案分割成与前述第一缝隙S1的延伸方向相同且相等的一缝隙， 及与第二缝隙S2的延伸方向相同且相等的另一缝隙；若第一调整条107a与第二调整条107b之间形成的缝隙图案宽度较小时，也可不设置间隔部。
此外，应当理解的是，在本公开实施例的调整部107的面积较小时，也不设置前述提到的第一调整条107a、第二调整条107b和缝隙图案，也就是说，调整部107可为整块结构，其不具有缝隙图案，视具体情况而定。
综上，本公开实施例的像素电极10可为一体式结构。举例而言，本公开实施例的像素电极10可为透明电极，其材料可为ITO(氧化铟锡)材料，但不限于此，也可采用氧化铟锌(IZO)、氧化锌(ZnO)等透明材料制作而成。
本公开还提供了一种阵列基板，可用于液晶显示装置中，但不限于此。结合图1、图2及图4至图6所示，本公开的阵列基板还可包括第一衬底30、位于第一衬底30上并沿第一方向Y和第二方向X阵列排布的子像素、多条形成在第一衬底30上的数据线40、多条形成在第一衬底30上的多条扫描线60和多条公共线70；需要说明的是，本公开实施例提到的第一方向Y可称为列方向，第二方向X可称为行方向。
下面结合附图对本公开实施例的阵列基板进行详细说明。
如图6所示，第一衬底30可为单层结构，但不限于此，此第一衬底30还可包括多层结构。举例而言，第一衬底30的材料可为玻璃，但不限于此，第一衬底30的材料也可为其他材料，例如：聚酰亚胺(PI)等材料，视具体情况而定。
如图4和图5所示，数据线40可在第一方向Y(即：列方向)上延伸，且数据线40可与子像素在第二方向X(即：行方向)交替排布。在本公开的实施例中，每条数据线40和位于其在第二方向X上的同一侧并和与之相邻的各子像素连接，即：每列数据线40和与之相邻且位于同一列的各子像素连接，以为同一列子像素提供数据信号。
举例而言，数据线40可包括金属材料或者合金材料，例如由钼、铝及钛等形成的金属单层或多层结构，例如，该多层结构为多金属层叠层，例如钛、铝、钛三层金属叠层(Ti/Al/Ti)等。
如图4和图5所示，扫描线60和公共线70可在第二方向X上延伸，且扫描线60和公共线70在第一方向Y上交替排布，应当理解的是，扫描线60在第一衬底30上的正投影不与公共线70在第一衬底30上的正投影存在交叠。
举例而言，扫描线60与公共线70同层设置。在本公开中，“同层设置”指的是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺形成的层结构。即一次构图工艺对应一道掩模板(mask，也称光罩)。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的，这些特定图形还可能处于不同的高度或者具有不同的厚度。从而简化制作工艺，节省制作成本，提高生产效率。
其中，结合图4至图6所示，扫描线60与公共线70可位于数据线40靠近第一衬底30的一侧并与数据线40之间呈绝缘设置，即：扫描线60和公共线70均与数据线40之间设置有栅绝缘层80，应当理解的是栅绝缘层80整层设置。
在本公开的实施例中，如图4和图5所示，相邻一行扫描线60和一行公共线70可为一组，并与一行子像素对应设置，即：每行子像素在第一方向Y上的一侧与一行公共线70相邻，另一侧与一行扫描线60相邻；其中，每条扫描线60和位于其在第一方向Y上的同一侧并和与之相邻的各子像素连接，即：每行扫描线60可和与之相邻且位于同一行的子像素连接，以为同一行子像素提供扫描信号；而每条公共线70和位于其在第一方向Y上的同一侧并和与之相邻的各子像素连接，即：每行公共线70可和与之相邻且位于同一行的子像素连接，以为同一行子像素提供公共信号。
举例而言，扫描线60和公共线70可包括金属材料或者合金材料，例如由钼、铝及钛等形成的金属单层或多层结构。
在本公开的实施中，如图4和图5所示，子像素可包括像素电极10、晶体管20及公共电极50；其中：
像素电极10的结构可参考前述任一实施例所描述的内容，且具体结构可参考图1和图2所示，在此不再重复赘述。
如图4和图5所示，在子像素的像素电极10中，第一连接条103和最靠近其的数据线40之间的间距为第一间距h1，第二连接条105和最靠近其的数据线40之间的间距为第二间距h2，此第一间距h1可与第二间距h2相等，这样便于后续设计第一连接条103和第二连接条105的尺寸，降低制作难度，但应当理解的是，第一间距h1也可与第二间距h2不等，视具体情况而定。
结合图4至图6所示，晶体管20可包括有源层203、栅极及同层设置的第一极201和第二极202，举例而言，此第一极201和第二极202可与前述提到的数据线102同层设置。其中，晶体管20的栅极与有源层203之间还可设置栅绝缘层80，以使栅极与有源层203之间相互绝缘，此栅绝缘层80可采用无机材料制作而成，例如，氧化硅、氮化硅等无机材料。
需要说明的是，栅极可与前述提到的扫描线60同层设置，此栅极可为前述提到的扫描线60的一部分，也就是说，可利用扫描线60的部分结构作为晶体管20的栅极，以实现扫描线60与晶体管20连接；而第一极201和第二极202可分别与有源层203的两掺杂区(即：源掺杂区和漏掺杂区)连接，且第一极201还可与数据线40连接，以实现数据线40与晶体管20连接，而第二极202可与像素电极10连接，具体地，像素电极10的第一边缘导电部101或第二边缘导电部102远离第二连接条105的端部可与晶体管20的第二极202连接，以实现晶体管20与像素电极10连接。
其中，如图4和图5所示，在第二方向X上，每个子像素的晶体管20相比于 其像素电极10的第二连接条105更靠近第一连接条103设置，这样可以使得像素电极10的第一连接条103所在侧的总电容与其第二连接条105所在侧的总电容相等或基本相等，从而改善产品灰阶V-Crosstalk现象。
进一步地，晶体管20在第一衬底30上的正投影与像素电极10的第一连接条103在第一衬底30上的正投影在第一方向Y上相对设置。
可选地，如图4和图5所示，以在第二方向X上相邻两子像素为最小重复单元，其中，在第二方向X相邻两像素电极10中：一者的第一边缘导电部101远离第二连接条105的端部与晶体管20连接，并相比于与其第二边缘导电部102更靠近与其连接的晶体管20；另一者的第二边缘导电部102远离第二连接条105的端部与晶体管20连接，并相比于其第一边缘导电部101更靠近与其连接的晶体管20；也就是说，如图5所示，一者的第二连接条105和另一者的第一连接条103均与两者之间的数据线40邻近，且一者的第一连接条103和另一者的第二连接条105均远离两者之间的数据线40，简而言之，在第二方向X相邻两像素电极10中一者可由另一者垂直翻转(即：关于第二方向X镜像)得到，这样设计可在减小和平衡暗场区的同时，还可扩大产品视角，但不限于此；也可使在第二方向X上相邻两像素电极10与晶体管20的连接关系相同，视具体情况而定。
需要说明的是，在第二方向X相邻两像素电极10中一者的第一边缘导电部101或第二边缘导电部102可与另一者的第一边缘导电部101或第二边缘导电部102的结构可设计为完全相同，但不限于此，也可根据实际情况进行稍微调整，只要能够保证像素电极10的第一连接条103所在侧的总电容与其第二连接条105所在侧的总电容相等或基本相等，从而能够改善产品灰阶V-Crosstalk现象即可。
举例而言，本公开的实施例的晶体管20可为底栅型，即：栅极可先形成在第一衬底30上，此栅极可包括金属材料或者合金材料，例如包括钼、铝及钛等，以保证其良好的导电性能；然后，再在第一衬底30上形成栅绝缘层80，如图6所示，此栅绝缘层80可覆盖栅极；之后在栅绝缘层80背离第一衬底30的一侧形成有源层203，即：有源层203位于栅极远离第一衬底30的一侧，此有源层203与栅极在第一衬底30上的正投影存在交叠，示例的，有源层203在第一衬底30上的正投影可位于栅极在第一衬底上的正投影内；第一极201和第二极202可在形成有源层203之后形成，其中，第一极201的部分可位于有源层203远离第一衬底30的一侧并与有源层203的源掺杂区接触，第二极202的部分可位于有源层203远离第一衬底30的一侧并与有源层203的漏掺杂区接触。
需要说明的是，本公开实施例提到的接触指的是两个部件之间无其他膜层并直接贴合在一起，即：两个部件不需要通过其他结构(例如：转接过孔)连接。此外，还需要说明的是，本公开实施例的晶体管不限于前述提到的底栅型，还可为顶栅型。
在本公开的实施例中，如图4和图5所示，晶体管20的第一极201和第二极 202可在第一方向Y上间隔排布，此第一极201和第二极202在第一方向Y上的间距可为第三间距h3；其中，前述提到像素电极10中第一连接条103和第二连接条105的长度设计与晶体管20的尺寸选择有关，具体地，像素电极10中各第一组子导电部的第一连接条103的长度之和与此第三间距h3的比值可为2至20，比如：2、5、8、11、14、17、20等等，举例而言，第三间距h3可为2μm、3μm、4μm、5μm、6μm等等，但不限于此，也可为其他取值。
需要说明的是，像素电极10中各第一组子导电部的第一连接条103的长度之和不仅与前述提到的第三间距S3相关，还与第一极201和第二极202的厚度和长度相关，其中，第一极201和第二极202的厚度、长度及第三间距h3均是决定晶体管20中第一极201和第二极202之间产生的侧向电容大小的关键，也就是说，像素电极10中第一连接条103和第二连接条105的长度设计主要取决于晶体管20中第一极201和第二极202之间产生的侧向电容。
举例而言，晶体管20中第一极201和第二极202的厚度可为
Figure PCTCN2021085622-appb-000001
至
Figure PCTCN2021085622-appb-000002
比如：
Figure PCTCN2021085622-appb-000003
等等，但不限于此，也可为其他取值；且晶体管20中第一极201和第二极202的长度可为5μm至50μm，比如：5μm、15μm、25μm、35μm、45μm、50μm等等，但不限于此，也可为其他取值。
应当理解的是，晶体管20的第一极201和第二极202不限于在第一方向Y上间隔排布，也可在第二方向X上间隔排布，需要说明的是，在晶体管20的第一极201和第二极202在第二方向X上间隔排布时，前述提到的第三间距h3则可理解为第一极201和第二极202在第二方向X上的间距。
此外，需要说明的是，晶体管20中第一极201和第二极202的长度指的是在与第一极201和第二极202的排布方向相垂直的方向上的尺寸。
在本公开的实施例中，如图6所示，晶体管20的第一极201和第二极202可位于像素电极10靠近第一衬底30的一侧，也就是说，在制作此阵列基板时，可先制作晶体管20的第一极201和第二极202，然后再制作像素电极10。
其中，如图6所示，晶体管20的第一极201和第二极202与像素电极10之间还可设置有钝化层90，此钝化层90可为氮化硅等无机膜层，但不限于此，也可为有机膜层。需要说明的是，在此时，前述提到的像素电极10的第一边缘导电部101或第二边缘导电部202可通过转接过孔P与晶体管20的第二极202连接。
在本公开的实施例中，如图6所示，公共电极50可位于像素电极10靠近第一衬底30的一侧并与像素电极10之间呈绝缘设置。举例而言，公共电极50具体可在制作有缘层203之前形成在第一衬底30上，也就是说，公共电极50与像素电极10之间可通过叠层设置的栅绝缘层80和钝化层90进行绝缘。
其中，如图4和图6所示，公共电极50在第一衬底30上的正投影可与公共线 70在第一衬底30上的正投影存在重叠，其中，公共电极50可与前述提到的公共线70接触，具体地，公共电极50可先于公共线70形成在第一衬底30上，但不限于此，也可在公共线70形成在第一衬底30之后形成在第一衬底30上。
应当理解的是，公共电极50在第一衬底30上的正投影与像素电极10在第一衬底30上的正投影存在交叠，且不与数据线40在第一衬底30上的正投影存在交叠。
举例而言，公共电极50的材料可与像素电极10的材料相同，此公共电极50可为透明电极，其材料可为ITO(氧化铟锡)材料，但不限于此，也可采用氧化铟锌(IZO)、氧化锌(ZnO)等透明材料制作而成。
在本公开实施例中，公共电极50可为板状电极，即：公共电极50上未开设缝隙，但不限于此，也可开设狭缝，视具体情况而定。
本公开实施例还提供了一种显示装置，此显示装置可为液晶显示装置，但不限于此。且本公开实施例的显示装置可包括前述任一实施例所描述的阵列基板，在此不做重复赘述。
且此显示装置还可包括与阵列基板对盒设置的对置基板(图中未示出)及位于阵列基板与对置基板之间的液晶层(图中未示出)，此液晶层的液晶分子可为负性液晶，以提高透过率，但不限于此，也可为正性液晶。
在本公开的实施例中，显示装置还可包括隔垫物，此隔垫物可集成在对置基板上，但不限于此，也可集成在阵列基板上，视具体情况而定。
其中，本公开的对置基板可包括第二衬底(图中未示出)和位于第二衬底靠近阵列基板一侧的黑矩阵层(图中未示出)，此黑矩阵层可具有遮挡区和透光区，此遮挡区在第一衬底30上的正投影可完全覆盖前述提到的数据线40、扫描线60、公共线70、子像素的晶体管20及隔垫物等等，且遮挡区还可覆盖公共电极50和像素电极10的边缘；而透光区在第一衬底30上的正投影可位于公共电极50和像素电极10在第一衬底30上的正投影内。
此外，本公开的对置基板还可包括彩膜层，此彩膜层可包括红色滤光块、绿色滤光块和蓝色滤光块等等。
需要说明的是，此彩膜层不限于集成在对置基板中，也可集成在阵列基板中，视具体情况而定。
根据本公开的实施例，该显示装置的具体类型不受特别的限制，本领域常用的显示装置类型均可，具体例如电视、车载显示等等，本领域技术人员可根据该显示设备的具体用途进行相应地选择，在此不再赘述。
需要说明的是，该显示装置除了前述提到的阵列基板、对置基板及液晶层以外，还包括其他必要的部件和组成，以显示器为例，还可包括背光模组、外壳、主电路板、电源线，等等，本领域技术人员可根据该显示装置的具体使用要求进行相应地补充，在此不再赘述。
本领域技术人员在考虑说明书及实践这里公开的内容后，将容易想到本公开的其它实施方案。本公开旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (21)

  1. 一种像素电极(10)，其中，包括：在第一方向(Y)上间隔排布的第一边缘导电部(101)和第二边缘导电部(102)、及至少部分位于所述第一边缘导电部(101)和所述第二边缘导电部(102)之间的主导电部，所述主导电部分别与所述第一边缘导电部(101)和所述第二边缘导电部(102)连接，所述主导电部包括至少一个第一组子导电部和至少一个第二组子导电部，所述第一组子导电部和所述第二组子导电部在所述第一方向(Y)上交替排布；
    其中，所述第一组子导电部包括第一连接条(103)，所述第一连接条(103)在所述第一方向(Y)上延伸且其具有在第二方向(X)上相对的第一面(103a)和第二面(103b)；所述第一组子导电部具有位于所述第一面(103a)远离所述第二面(103b)一侧的第一缝隙(S1)，所述第一缝隙(S1)远离所述第一连接条(103)的一端为开口端；
    其中，所述第二组子导电部包括位于所述第一缝隙(S1)远离所述第一连接条(103)的一侧并与所述第一组子导电部连接的第二连接条(105)，所述第二连接条(105)在所述第一方向(Y)上延伸且其具有在第二方向(X)上相对的第三面(105a)和第四面(105b)，所述第三面(105a)位于所述第四面(105b)靠近所述第一面(103a)的一侧；且所述第二组子导电部具有位于所述第三面(105a)远离所述第四面(105b)一侧的第二缝隙(S2)，所述第二缝隙(S2)远离所述第二连接条(105)的一端为开口端；
    其中，在所述第二方向(X)上，所述像素电极(10)被配置为其所述第一连接条(103)相比于所述第二连接条(105)更靠近晶体管(20)；且所述第一边缘导电部(101)或所述第二边缘导电部(102)远离所述第二连接条(105)的端部被配置为与所述晶体管(20)连接；
    其中，所述至少一个第一组子导电部中所述第一连接条(103)的长度之和小于所述至少一个第二组子导电部中所述第二连接条(105)的长度之和；
    其中，所述第一方向(Y)与所述第二方向(X)相交。
  2. 根据权利要求1所述的阵列基板，其中，
    所述第一组子导电部还包括在所述第一方向(Y)上间隔排布的多个第一电极条(104)，所述多个第一电极条(104)位于所述第一面(103a)远离所述第二面(103b)的位置并与所述第一面(103a)连接；相邻两所述第一电极条(104)之间具有所述第一缝隙(S1)；
    所述第二组子导电部还包括在所述第一方向(Y)上间隔排布的多个第二电极条(106)，所述多个第二电极条(106)位于所述第三面(105a)远离所述第四面(105b)的位置并与所述第三面(105a)连接；相邻两所述第二电极条(106)之间具有所述第二缝隙(S2)；
    其中，所述第二连接条(105)的第三面(105a)与最靠近所述第二组子导电部的所述第一电极条(104)远离所述第一连接条(103)的端部连接。
  3. 根据权利要求2所述的像素电极(10)，其中，所述第一连接条(103)的长度小于所述第二连接条(105)的长度。
  4. 根据权利要求3所述的像素电极(10)，其中，所述主导电部包括一个所述第一组子导电部和一个所述第二组子导电部，
    所述第一边缘导电部(101)位于所述多个第一电极条(104)远离所述第二组子导电部的一侧，并位于所述第一连接条(103)的所述第一面(103a)远离所述第二面(103b)的位置；所述第一边缘导电部(101)与所述第一面(103a)连接，并和与之相邻的所述第一电极条(104)具有第三缝隙(S3)，所述第三缝隙(S3)远离所述第一连接条(103)的一端为开口端；
    所述第二边缘导电部(102)位于所述多个第二电极条(106)远离所述第一组子导电部的一侧，并位于所述第二连接条(105)的所述第三面(105a)远离所述第四面(105b)的位置；所述第二边缘导电部(102)与所述第三面(105a)连接，并和与之相邻的所述第二电极条(106)具有第四缝隙(S4)，所述第四缝隙(S4)远离所述第二连接条(105)的一端为开口端。
  5. 根据权利要求4所述的像素电极(10)，其中，所述第一电极条(104)、所述第一缝隙(S1)和所述第三缝隙(S3)的延伸方向相同并与所述第一方向(Y)和所述第二方向(X)相交；且所述第二电极条(106)、所述第二缝隙(S2)和所述第四缝隙(S4)的延伸方向相同并与所述第一方向(Y)和所述第二方向(X)相交。
  6. 根据权利要求5所述的像素电极(10)，其中，所述第一电极条(104)、所述第二电极条(106)、所述第一缝隙(S1)、所述第二缝隙(S2)、所述第三缝隙(S3)和所述第四缝隙(S4)的宽度相等。
  7. 根据权利要求6所述的像素电极(10)，其中，所述第一电极条(104)和所述第二电极条(106)的延伸方向相同，且相邻所述第一电极条(104)与所述第二电极条(106)之间具有所述第二缝隙(S2)。
  8. 根据权利要求6所述的像素电极(10)，其中，所述第一电极条(104)的延伸方向与所述第二电极条(106)的延伸方向关于所述第二方向(X)呈镜像设置。
  9. 根据权利要求8所述的像素电极(10)，其中，所述第二组子导电部还包括调整部(107)，所述调整部(107)位于所述多个第二电极条(106)靠近所述第一组子导电部的一侧，并位于所述第二连接条(105)的所述第三面(105a)远离所述第四面(105b)的位置，所述调整部(107)与所述第二连接条(105)的所述第三面(105a)连接；其中，
    所述调整部(107)和与之相邻的所述第一电极条(104)之间形成有第五缝隙 (S5)，并和与之相邻的所述第二电极条(106)之间形成有第六缝隙(S6)；
    所述第五缝隙(S5)和所述第六缝隙(S6)远离所述第二连接条(105)的一端均为开口端；
    所述第五缝隙(S5)与所述第一缝隙(S1)的延伸方向相同且宽度相等，所述第六缝隙(S6)与所述第二缝隙(S2)的延伸方向相同且宽度相等。
  10. 根据权利要求9所述的像素电极(10)，其中，
    所述调整部(107)包括第一调整条(107a)和第二调整条(107b)，所述第一调整条(107a)与所述第一电极条(104)之间形成所述第五缝隙(S5)，所述第二调整条(107b)与所述第二电极条(106)之间形成所述第六缝隙(S6)；其中，
    所述第一调整条(107a)的延伸方向与所述第一电极条(104)的延伸方向相同且宽度相等，所述第二调整条(107b)的延伸方向与所述第二电极条(106)的延伸方向相同且宽度相等；
    所述第一调整条(107a)和所述第二调整条(107b)在其延伸方向上的一端与所述第二连接条(105)的第三面(105a)连接，另一端彼此相连。
  11. 根据权利要求1至10中任一项所述的像素电极(10)，其中，所述至少一个第一组子导电部中所述第一连接条(103)的长度之和与所述至少一个第二组子导电部中所述第二连接条(105)的长度之和之比为0.1至0.9。
  12. 一种阵列基板，其包括第一衬底(30)和位于所述第一衬底(30)上并沿第一方向(Y)和第二方向(X)阵列排布的子像素，其中，所述子像素包括晶体管(20)和权利要求1至11中任一项所述的像素电极(10)，所述像素电极(10)的第一边缘导电部(101)或第二边缘导电部(102)远离第二连接条(105)的端部与所述晶体管(20)连接；
    在所述第二方向(X)上，所述晶体管(20)相比于所述像素电极(10)的所述第二连接条(105)更靠近所述第一连接条(103)设置。
  13. 根据权利要求12所述的阵列基板，其中，所述晶体管(20)在所述第一衬底(30)上的正投影与所述像素电极(10)的第一连接条(103)在所述第一衬底(30)上的正投影在所述第一方向(Y)上相对设置。
  14. 根据权利要求13所述的阵列基板，其中，在所述第二方向(X)相邻两所述像素电极(10)中：
    一者的所述第一边缘导电部(101)远离所述第二连接条(105)的端部与所述晶体管(20)连接，并相比于与其所述第二边缘导电部(102)更靠近与其连接的所述晶体管(20)；
    另一者的所述第二边缘导电部(102)远离所述第二连接条(105)的端部与所述晶体管(20)连接，并相比于其所述第一边缘导电部(101)更靠近与其连接的所述晶体管(20)。
  15. 根据权利要求14所述的阵列基板，其中，还包括多条形成在所述第一衬底(30)上的数据线(40)，所述数据线(40)在所述第一方向(Y)上延伸，且所述数据线(40)与所述子像素在所述第二方向(X)上交替排布；
    其中，在所述子像素的所述像素电极(10)中，所述第一连接条(103)和最靠近其的所述数据线(40)之间的间距为第一间距(h1)，所述第二连接条(105)和最靠近其的所述数据线(40)之间的间距为第二间距(h2)，所述第一间距(h1)和所述第二间距(h2)相等。
  16. 根据权利要求15所述的阵列基板，其中，每条所述数据线(40)和位于其在所述第二方向(X)上的同一侧并和与之相邻的各所述子像素的晶体管(20)连接；
    其中，所述晶体管(20)的第一极(201)和第二极(202)与所述数据线(40)同层设置，并位于所述像素电极(10)靠近所述第一衬底(30)的一侧；所述晶体管(20)的第一极(201)与所述数据线(40)连接，所述晶体管(20)的第二极(202)通过转接过孔(P)与所述像素电极(10)的所述第二边缘导电部(102)或所述第一边缘导电部(101)连接。
  17. 根据权利要求16所述的阵列基板，其中，所述晶体管(20)的第一极(201)和第二极(202)在所述第一方向(Y)上间隔排布，所述第一极(201)和所述第二极(202)在所述第一方向(Y)上的间距为第三间距(h3)；
    其中，所述至少一个第一组子导电部中所述第一连接条(103)的长度之和与所述第三间距(h3)的比值为2至20。
  18. 根据权利要求16所述的阵列基板，其中，
    所述子像素还包括公共电极(50)，位于所述像素电极(10)靠近所述第一衬底(30)的一侧并与所述像素电极(10)之间呈绝缘设置；
    且所述公共电极(50)在所述第一衬底(30)上的正投影与所述像素电极(10)在所述第一衬底(30)上的正投影存在交叠，且不与所述数据线(40)在所述第一衬底(30)上的正投影存在交叠。
  19. 根据权利要求18所述的阵列基板，其中，
    所述阵列基板还包括形成在所述第一衬底(30)上并在所述第二方向(X)上延伸的多条扫描线(60)和多条公共线(70)，所述扫描线(60)与所述公共线(70)在所述第一方向(Y)上交替排布，且所述扫描线(60)在所述第一衬底(30)上的正投影不与所述公共线(70)在所述第一衬底(30)上的正投影存在交叠；
    其中，所述扫描线(60)与所述公共线(70)同层设置，且所述扫描线(60)与所述公共线(70)位于所述数据线(40)靠近所述第一衬底(30)的一侧并与所述数据线(40)之间呈绝缘设置；
    其中，所述子像素在所述第一方向(Y)上的一侧与所述公共线(70)相邻， 另一侧与所述扫描线(60)相邻；
    其中，每条所述扫描线(60)和位于其在所述第一方向(Y)上的同一侧并和与之相邻的各所述子像素的晶体管(20)的栅极连接；
    其中，每条所述公共线(70)和位于其在所述第一方向(Y)上的同一侧并和与之相邻的各所述子像素的公共电极(50)连接。
  20. 根据权利要求19所述的阵列基板，其中，所述扫描线(60)的部分构成所述晶体管(20)的栅极，且所述公共电极(50)与所述公共线(70)接触。
  21. 一种显示装置，其中，包括权利要求12至20中任一项所述的阵列基板及与所述阵列基板对盒设置的对置基板。
PCT/CN2021/085622 2021-01-13 2021-04-06 像素电极、阵列基板及显示装置 WO2022213256A1 (zh)

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