WO2022042253A1 - 铁电存储器及其制造方法 - Google Patents

铁电存储器及其制造方法 Download PDF

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WO2022042253A1
WO2022042253A1 PCT/CN2021/110870 CN2021110870W WO2022042253A1 WO 2022042253 A1 WO2022042253 A1 WO 2022042253A1 CN 2021110870 W CN2021110870 W CN 2021110870W WO 2022042253 A1 WO2022042253 A1 WO 2022042253A1
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electrode
ferroelectric
ferroelectric capacitor
capacitor
group
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PCT/CN2021/110870
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English (en)
French (fr)
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吕震宇
张暐
戴晓望
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无锡拍字节科技有限公司
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes

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  • the present invention relates to the technical field of ferroelectric memory, in particular to a ferroelectric capacitor of a ferroelectric memory.
  • Ferroelectric memories use layers of ferroelectric materials to achieve non-volatility.
  • a layer of ferroelectric material has a non-linear relationship between the applied electric field and the stored apparent charge, and thus can switch polarity under the electric field.
  • the advantages of ferroelectric memory include low power consumption, fast write performance, and high maximum read/write endurance.
  • the ferroelectric capacitor of the storage unit usually uses the structure of electrode-ferroelectric material layer-electrode.
  • the structure of the existing ferroelectric memory and the materials used will cause electrode oxidation during the manufacturing process. In this case, it is easy to cause the imprint of the ferroelectric material, which affects the performance of the ferroelectric memory.
  • the ferroelectric memory made of the electrode material used in the existing structure will have various problems such as low breakdown voltage and Q-Time limitation in the process.
  • the object of the present invention is to provide a ferroelectric memory and a manufacturing method thereof, which can improve the breakdown voltage of the ferroelectric capacitor of the ferroelectric memory, avoid the problem of uncontrolled electrode oxidation, and solve the Q-time problem of the manufacturing process .
  • the present invention provides a ferroelectric capacitor, which includes a first electrode, a second electrode and a ferroelectric material layer between the first electrode and the second electrode, and is characterized in that: in the ferroelectric capacitor At least one of the first electrode or the second electrode is doped with at least one of the fifth group metal elements.
  • the fifth group metal element includes vanadium, niobium, and tantalum.
  • the doped Group V metal element is a metal oxide of the Group V metal element.
  • the metal element of the fifth group is uniformly distributed in the first electrode or the second electrode.
  • the concentration of the fifth group metal element in a region of the first electrode or the second electrode close to the ferroelectric material layer is higher than that in other regions.
  • the ferroelectric capacitor is a planar capacitor.
  • the ferroelectric capacitor is a cylindrical three-dimensional capacitor whose inner layer is a first electrode, the middle layer is a ferroelectric material layer, and the outermost layer is a second electrode.
  • the materials of the first electrode and the second electrode may be one or more of the following materials: titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiNx), Titanium Aluminum Nitride (TiAlNx), Titanium Carbonitride (TiCNx), Tantalum Nitride (TaNx), Tantalum Silicon Nitride (TaSiNx), Tantalum Aluminum Nitride (TaAlNx), Tungsten Nitride (WNx), Tungsten Silicide (WSix) ), tungsten carbonitride (WCNx), ruthenium (Ru), ruthenium oxide (RuOx), iridium (Ir), doped polysilicon, transparent conductive oxide (TCO) or iridium oxide (IrOx) or a composite of these materials.
  • titanium titanium
  • TiN titanium nitride
  • TiSiNx titanium silicon nitride
  • TiAlNx Titanium Aluminum Nitride
  • the ferroelectric material includes a ferroelectric material composed of oxygen and one or more ferroelectric metals
  • the ferroelectric metals include zirconium (Zr), hafnium (Hf), titanium (Ti), aluminum (Al), nickel (Ni) and/or iron (Fe), and the ferroelectric material may be doped with Group II elements calcium (Ca), strontium (Sr) or barium (Ba); Or doped with Group III elements scandium (Sc), yttrium (Y), aluminum (Al), gallium (Ga) and indium (In)); or doped with lanthanide elements lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium
  • Zr zirconium
  • a ferroelectric memory includes several memory cells arranged in an array, each memory cell includes a transistor and a ferroelectric capacitor connected to the transistor, wherein the ferroelectric capacitor adopts the aforementioned ferroelectric capacitor.
  • the present invention provides a method for manufacturing a ferroelectric memory, comprising:
  • a transistor on a semiconductor substrate including a gate, a source and a drain;
  • a ferroelectric capacitor is formed over the transistor, one electrode of the ferroelectric capacitor is connected to the source or drain of the transistor through a metal interconnect, wherein at least one electrode is doped with at least one of the Group 5 metal elements when forming the electrode of the capacitor A sort of.
  • the electrode of the ferroelectric capacitor is doped with the fifth group metal element, which can effectively improve the breakdown voltage, avoid the problem of uncontrolled electrode oxidation, and solve the Q-Time problem of the manufacturing process.
  • FIG. 1 is a schematic diagram of a memory cell array structure circuit of a ferroelectric memory.
  • FIG. 2 is a schematic diagram of a physical structure of a ferroelectric memory cell according to an embodiment of the present invention, wherein the ferroelectric capacitor of the ferroelectric memory cell is a planar capacitor.
  • FIG. 3 is a schematic diagram of an embodiment of the electrode doping concentration distribution of the ferroelectric capacitor in the embodiment shown in FIG. 2 .
  • FIG. 4 is a schematic diagram of another embodiment of the electrode doping concentration distribution of the ferroelectric capacitor in the embodiment shown in FIG. 2 .
  • FIG. 5 is a schematic diagram of still another embodiment of the electrode doping concentration distribution of the ferroelectric capacitor in the embodiment shown in FIG. 2 .
  • FIG. 6 is a schematic structural diagram of a ferroelectric memory cell according to another embodiment of the present invention, wherein the ferroelectric capacitor of the ferroelectric memory cell is a cylindrical three-dimensional three-dimensional capacitor.
  • FIG. 7 is a schematic perspective view of the three-dimensional capacitor in the embodiment shown in FIG. 6 .
  • FIG. 8 is a schematic cross-sectional view of the three-dimensional capacitor shown in FIG. 7 .
  • FIG. 1 shows a schematic diagram of the circuit structure of the ferroelectric memory of the present invention.
  • the ferroelectric memory of the present invention includes several memory cells arranged in an array, and each memory cell includes a transistor T and a ferroelectric capacitor C connected to the transistor.
  • the transistor T is a CMOS transistor, which includes a gate electrode, a source electrode and a drain electrode.
  • the gate of the transistor of the ferroelectric memory cell is connected to the word line WL of the memory through a wire, and the word line WL is used to control the turn-on or turn-off of the transistor; the source or drain of the transistor T is connected to the ferroelectric One electrode of the capacitor C is connected, the drain or source of the transistor T is connected to the bit line BL of the memory, and the other electrode of the capacitor C is connected to the plate line PL of the memory.
  • the turn-on and turn-off of the transistor T is controlled by the word line WL, the data is written to the memory by applying different voltages to the ferroelectric capacitor through the bit line BL and the plate line PL, and the data is realized by detecting the stored data of the ferroelectric capacitor through the bit line BL. read.
  • the ferroelectric memory of the present invention can be a 2T2C structure in which each storage unit includes two transistors and two ferroelectric capacitors, and data reading is realized by comparing the two transistors of each unit with each other, or each storage unit includes The 1T1C structure of a transistor and a ferroelectric capacitor is used to compare the data with an additional reference cell.
  • FIG. 2 shows a schematic diagram of the physical structure of the memory cell of the ferroelectric memory of the present invention.
  • the memory cell of the ferroelectric memory of the present invention includes a transistor 1, a ferroelectric capacitor 2, and a metal interconnection 3 connecting the ferroelectric capacitor and the transistor.
  • the ferroelectric capacitor is a planar capacitor structure.
  • the transistor 1 of the ferroelectric memory includes a gate electrode 11, a source electrode 12 and a drain electrode 13 formed by doping on a semiconductor substrate.
  • the ferroelectric capacitor 2 includes an upper electrode 21 and a lower electrode 22 and a ferroelectric material layer 23 between the upper electrode 21 and the lower electrode 22 .
  • the material of the upper electrode 21 and the lower electrode 22 of the ferroelectric capacitor may be one or more of the following materials: titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiNx), Titanium Aluminum Nitride (TiAlNx), Titanium Carbonitride (TiCNx), Tantalum Nitride (TaNx), Tantalum Silicon Nitride (TaSiNx), Tantalum Aluminum Nitride (TaAlNx), Tungsten Nitride (WNx), Tungsten suicide (WSix), tungsten carbonitride (WCNx), ruthenium (Ru), ruthenium oxide (RuOx), iridium (Ir), doped polysilicon, transparent conductive oxide (TCO) or iridium oxide (IrOx) or these materials compound.
  • titanium titanium
  • TiN titanium nitride
  • TiSiNx titanium silicon nitride
  • TiAlNx Titanium Aluminum Nitride
  • the ferroelectric material layer 23 of the ferroelectric capacitor includes a ferroelectric material composed of oxygen and one or more ferroelectric metals
  • the ferroelectric metals include zirconium (Zr), hafnium ( Hf), titanium (Ti), aluminum (Al), nickel (Ni) and/or iron (Fe), and the ferroelectric material may be doped with group II elements calcium (Ca), strontium (Sr) or barium ( Ba); or doped with Group III elements scandium (Sc), yttrium (Y), aluminum (Al), gallium (Ga) and indium (In)); or doped with lanthanides lanthanum (La), cerium (Ce) ), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (
  • a metal element 24 of Group V in the periodic table is doped in the lower electrode of one of the electrodes of the ferroelectric capacitor, and the metal element includes vanadium, niobium, At least one of metals such as tantalum.
  • the region doped with the fifth group metal element is the region of the lower electrode close to the ferroelectric material layer or the surface of the lower electrode in contact with the ferroelectric material layer.
  • the doping of the fifth group metal elements is achieved by doping metal oxides of these metals, for example, the doping can be vanadium oxide (VO x ) or niobium oxide (Nb 2 O 5 ) or Tantalum oxide (Ta 2 O 5 ).
  • the doping can be vanadium oxide (VO x ) or niobium oxide (Nb 2 O 5 ) or Tantalum oxide (Ta 2 O 5 ).
  • both the upper electrode and the lower electrode of the ferroelectric capacitor are doped with Group V metal elements, such as vanadium, niobium, At least one of metals such as tantalum.
  • Group V metal elements such as vanadium, niobium, At least one of metals such as tantalum.
  • the same doping of the fifth group metal elements is achieved by doping the metal oxides of these metals, for example, the doping can be vanadium oxide (VO x ) or niobium oxide (Nb 2 O 5 ) or tantalum oxide ( Ta 2 O 5 ).
  • the doping concentration of the fifth group metal element in the upper electrode and the lower electrode is non-uniformly distributed, wherein the concentration of the doping group fifth metal element in the region of the electrode close to the ferroelectric material is higher than that of the electrode far from the ferroelectric material The doping concentration of the material layer region.
  • both the upper electrode and the lower electrode of the ferroelectric capacitor are doped with Group V metal elements, such as vanadium, niobium, At least one of metals such as tantalum.
  • the same doping of the fifth group metal elements is achieved by doping the metal oxides of these metals, for example, the doping can be vanadium oxide (VO x ) or niobium oxide (Nb 2 O 5 ) or tantalum oxide ( Ta 2 O 5 ).
  • the doping concentration of the fifth group metal element in the upper electrode and the lower electrode is uniformly distributed.
  • FIG. 6 shows a schematic diagram of the physical structure of another embodiment of the ferroelectric memory cell of the present invention.
  • a memory cell of a ferroelectric memory of one embodiment of the present invention includes a transistor 1 and a ferroelectric capacitor 5 connected to the transistor 1 through a conductive interconnect 4 .
  • the ferroelectric capacitor 5 is a capacitor with a three-dimensional cylindrical structure.
  • FIGS. 7 and 8 wherein FIG. 7 is a schematic three-dimensional view of the ferroelectric capacitor with a three-dimensional cylindrical structure in FIG. 6 , and FIG. 8 is a schematic cross-sectional view of the ferroelectric capacitor shown in FIG. 7 , as shown in FIGS.
  • the ferroelectric capacitor includes a first electrode 51 (upper electrode) in an inner layer, a second electrode 52 (lower electrode) in an outer layer, and a ferroelectric material layer 53 between the first electrode 51 and the second electrode 52 .
  • the material of the electrode of the capacitor can be one or more of the following materials: titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiNx), titanium aluminum nitride (TiAlNx), carbon nitride Titanium nitride (TiCNx), tantalum nitride (TaNx), tantalum silicon nitride (TaSiNx), tantalum aluminum nitride (TaAlNx), tungsten nitride (WNx), tungsten silicide (WSix), tungsten carbon nitride (WCNx), Ruthenium (Ru), ruthenium oxide (RuOx), iridium (Ir
  • the ferroelectric material layer of the ferroelectric capacitor of this embodiment includes a ferroelectric material composed of oxygen and one or more ferroelectric metals
  • the ferroelectric metals include zirconium (Zr), hafnium (Hf) , titanium (Ti), aluminum (Al), nickel (Ni) and/or iron (Fe), and the ferroelectric material may be doped with group II elements calcium (Ca), strontium (Sr) or barium (Ba) ; Or doped with Group III elements scandium (Sc), yttrium (Y), aluminum (Al), gallium (Ga) and indium (In)); or doped with lanthanides lanthanum (La), cerium (Ce), Praseodymium (Pr), Neodymium (Nd), Promethium (Pm), Samarium (Sm), Europium (Eu), Gadolinium (Gd), Terbium (Tb), Dysprosium (Dy), Holmium (Ho), Erbium (Er
  • the electrodes of the three-dimensional capacitor shown in FIG. 6 are doped with metal elements of Group V in the periodic table, such as at least one of metals such as vanadium, niobium, and tantalum.
  • the doping of the fifth group metal elements is achieved by doping the metal oxides of these metals, for example, the doping can be vanadium oxide (VO x ) or niobium oxide (Nb 2 O 5 ) or tantalum oxide (Ta 2 O 5 ).
  • the electrodes may be doped only in one of the electrodes, or both electrodes may be doped.
  • the doping concentration can be uniformly distributed in the electrode or non-uniformly distributed in the electrode.
  • the doping concentration of the electrode near the ferroelectric material area or the surface in contact with the ferroelectric material is higher than that of other areas of the electrode.
  • a method for manufacturing the ferroelectric memory which includes the following steps:
  • the step of forming a transistor on a semiconductor substrate wherein the transistor includes a gate, a source and a drain;
  • the step of forming a metal interconnection connected to the source or drain of the transistor on the semiconductor substrate may include depositing a dielectric layer over the transistor on the semiconductor substrate, then forming a through hole in the dielectric layer, and forming a through hole in the through hole metal interconnection.
  • a ferroelectric capacitor is formed over the transistor, one electrode of the ferroelectric capacitor is connected to the source or drain of the transistor through a metal interconnect, wherein at least one electrode is doped with at least one of the Group 5 metal elements when forming the electrode of the capacitor a step.
  • the method of forming a ferroelectric capacitor may specifically include, after forming a metal interconnection on a semiconductor substrate, depositing a lower electrode of a ferroelectric capacitor on a dielectric layer where the metal interconnection is formed, and then doping the lower electrode with a Group V metal element , then a ferroelectric material layer is formed on the lower electrode, and then an upper electrode is formed on the ferroelectric material layer. If necessary, the upper electrode is doped with Group V metal elements, and then formed by chemical mechanical grinding or mask etching. Individual ferroelectric capacitors separated from each other.
  • the method for forming a three-dimensional capacitance structure may specifically include, after forming a metal interconnection on a semiconductor substrate, depositing a dielectric layer on the dielectric layer forming the metal interconnection, then etching the dielectric layer to form a cylindrical deep hole structure, and then Referring to the structure shown in FIG. 8 , the lower electrode of the ferroelectric capacitor, the ferroelectric material layer and the upper electrode are sequentially deposited in the deep hole structure, wherein the electrodes are doped with Group V metal elements when forming the electrodes of the capacitor, and then pass through Separate individual ferroelectric capacitors are formed by chemical mechanical polishing or photomask etching.

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Abstract

本发明提供了一种铁电存储器及其制造方法，该铁电存储器包括存储单元阵列，每个存储单元包括晶体管和与晶体管连接的铁电电容，所述铁电电容包括第一电极、第二电极和位于第一电极和第二电极之间的铁电材料层，其中在第一电极或第二电极的至少一个中掺杂有第五族金属元素中的至少一种。通过在电极中掺杂第五族金属元素可以改善铁电存储器的产品性能。

Description

铁电存储器及其制造方法 技术领域
本发明涉及铁电存储器技术领域，特别涉及一种铁电存储器的铁电电容。
背景技术
铁电存储器使用铁电材料层来实现非易失性。铁电材料层具有所施加电场与所储存表观电荷之间的非线性关系，并且因此可以在电场下切换极性。铁电存储器的优点包括低功耗、快速写性能和高最大读/写耐久度。
现有的铁电存储器，其存储单元的铁电电容通常使用的是电极-铁电材料层-电极的结构，现有的铁电存储器的结构及使用的材料在制造过程中会发生电极氧化的情况，容易造成铁电材料印记，影响铁电存储器的性能。而且现有的结构使用的电极材料做成的铁电存储器会存在击穿电压低，工艺上Q-Time限制等多种问题。
发明内容
本发明的目的在于提供一种铁电存储器及其制造方法，可以改善铁电存储器的铁电电容的击穿电压，避免不受控制的电极氧化问题，并使得制造工艺的Q-time问题得到解决。
为解决上述技术问题，本发明提供了一种铁电电容器，其包括第一电极、第二电极和位于第一电极和第二电极之间的铁电材料层，其特征在于：在铁电电容器的第一电极或第二电极至少一个中掺杂有第五族金属元素中的至少一种。
根据本发明的一个实施例，其中所述第五族金属元素包括钒、铌、钽。
根据本发明的一个实施例，其中掺杂的第五族金属元素为第五族金属元素的金属氧化物。
根据本发明的一个实施例，其中所述第五族金属元素在第一电极或第二电极中为均匀分布。
根据本发明的一个实施例，其中所述第五族金属元素在第一电极或第二电极靠近铁电材料层的区域的浓度高于其他区域的浓度。
根据本发明的一个实施例，其中所述铁电电容器为平面电容器。
根据本发明的一个实施例，其中所述铁电电容器为内层为第一电极中间层为铁电材料层最外层为第二电极的柱体状三维立体电容器。
根据本发明的一个实施例，其中第一电极和第二电极的材料可以是以下材料中的一种或多种：钛(Ti)、氮化钛(TiN)、氮化钛硅(TiSiNx)、氮化钛铝(TiAlNx)、碳氮化钛(TiCNx)、氮化钽(TaNx)、氮化钽硅(TaSiNx)、氮化钽铝(TaAlNx)、氮化钨(WNx)、硅化钨(WSix)、碳氮化钨(WCNx)、钌(Ru)、氧化钌(RuOx)、铱(Ir)、掺杂多晶硅、透明导电氧化物(TCO)或氧化铱(IrOx)或这些材料的复合。
根据本发明的一个实施例，其中所述铁电材料包括氧和一种或多种铁电金属组成的具有铁电性的材料，所述铁电金属包括锆(Zr)、铪(Hf)、钛(Ti)、铝(Al)、镍(Ni)和/或铁(Fe)，并且所述铁电材料可以掺杂第II族元素钙(Ca)、锶(Sr)或钡(Ba)；或者掺杂第III族元素钪(Sc)、钇(Y)、铝(Al)、镓(Ga)以及铟(In))；或者掺杂镧系元素镧(La)、铈(Ce)、镨(Pr)、钕(Nd)、钷(Pm)、钐(Sm)、铕(Eu)、钆(Gd)、铽(Tb)、镝(Dy)、钬(Ho)、铒(Er)、铥(Tm)、镱(Yb)、镥(Lu)。
根据本发明的一个实施例的一种铁电存储器，其包括若干阵列排布的存储单元，每个存储单元包括晶体管和与晶体管连接的铁电电容器，其中所述铁电电容器采用前述的铁电电容器。
为达成前述目的，本发明一种制造铁电存储器的制造方法，其包括：
提供半导体衬底；
在半导体衬底上形成晶体管，其包括栅极、源极和漏极；
在半导体衬底上形成与晶体管的源极或漏极连接的金属互连；
在晶体管上方形成铁电电容器，铁电电容器的一个电极通过金属互连与晶体管的源极或漏极相连，其中在形成电容器的电极时在至少一个电极 中掺杂第五族金属元素中的至少一种。
本发明的铁电存储器其中在铁电电容的电极中掺杂第五族金属元素，可以有效改善击穿电压，避免不受控制的电极氧化问题，并且使得制造工艺的Q-Time问题得到解决。
附图说明
图1是铁电存储器的存储单元阵列结构电路示意图。
图2是本发明的一个实施例的铁电存储单元的物理结构示意图，其中铁电存储单元的铁电电容为平面电容。
图3是图2所示的实施例中铁电电容的电极掺杂浓度分布的一个实施例的示意图。
图4是图2所示的实施例中铁电电容的电极掺杂浓度分布的另一个实施例的示意图。
图5是图2所示的实施例中铁电电容的电极掺杂浓度分布的再一个实施例的示意图。
图6是本发明的另一个实施例的铁电存储单元的结构示意图，其中铁电存储单元的铁电电容为圆柱体三维立体电容。
图7是图6所示实施例中的三维立体电容器的立体示意图。
图8是图7所示三维立体电容器的剖面示意图。
具体实施方式
以下结合附图和具体实施例对本发明的内容做进一步详细说明。
请参阅图1所示，其显示本发明的铁电存储器的电路结构示意图。如图中所示，本发明的铁电存储器包括若干阵列排布的存储单元，每个存储单元包括晶体管T和与晶体管连接的铁电电容器C。其中在本发明的一个实施例中该晶体管T为CMOS晶体管，其包括栅极、源极和漏极。如图中所示，铁电存储单元的晶体管其栅极通过导线与存储器的字线WL相连，字线WL用于控制晶体管的导通或关断；晶体管T的源极或者漏极与铁电电容器C的一个电极相连，晶体管T的漏极或者源极与存储器的位线BL 相连，电容器C的另一个电极与存储器的板线PL相连。通过字线WL控制晶体管T的导通和关断，通过位线BL和板线PL向铁电电容施加不同的电压来向存储器写入数据，通过位线BL检测铁电电容的存储数据实现数据的读取。
本发明的铁电存储器可以是每个存储单元包括两个晶体管和两个铁电电容器的2T2C结构，通过每个单元的两个晶体管相互比较实现数据的读取，也可以是每个存储单元包括一个晶体管和一个铁电电容器的1T1C结构，通过额外设置的参考单元进行比较实现数据的读取。
请参阅图2所示，其显示本发明的铁电存储器的存储单元的物理结构示意图。如图中所示，本发明的铁电存储器的存储单元包括晶体管1、铁电电容2和连接铁电电容和晶体管的金属互连3。其中铁电电容为平面电容结构。
如图2所示本发明的实施例的铁电存储器的晶体管1包括栅极11，在半导体衬底上通过掺杂形成的源极12和漏极13。铁电电容器2包括上电极21和下电极22以及位于上电极21和下电极22之间的铁电材料层23。
在本发明的一个实施例中，铁电电容的上电极21和下电极22的材料可以是以下材料中的一种或多种：钛(Ti)、氮化钛(TiN)、氮化钛硅(TiSiNx)、氮化钛铝(TiAlNx)、碳氮化钛(TiCNx)、氮化钽(TaNx)、氮化钽硅(TaSiNx)、氮化钽铝(TaAlNx)、氮化钨(WNx)、硅化钨(WSix)、碳氮化钨(WCNx)、钌(Ru)、氧化钌(RuOx)、铱(Ir)、掺杂多晶硅、透明导电氧化物(TCO)或氧化铱(IrOx)或这些材料的复合。
在本发明的一个实施例，铁电电容的铁电材料层23包括氧和一种或多种铁电金属组成的具有铁电性的材料，所述铁电金属包括锆(Zr)、铪(Hf)、钛(Ti)、铝(Al)、镍(Ni)和/或铁(Fe)，并且所述铁电材料可以掺杂第II族元素钙(Ca)、锶(Sr)或钡(Ba)；或者掺杂第III族元素钪(Sc)、钇(Y)、铝(Al)、镓(Ga)以及铟(In))；或者掺杂镧系元素镧(La)、铈(Ce)、镨(Pr)、钕(Nd)、钷(Pm)、钐(Sm)、铕(Eu)、钆(Gd)、铽(Tb)、镝(Dy)、钬(Ho)、铒(Er)、铥(Tm)、镱(Yb)、镥(Lu)。
请参阅图3所示，在本发明的一个实施例中，在铁电电容的其中一个 电极下电极中掺杂有元素周期表中第五族的金属元素24，该金属元素包括钒、铌、钽等金属中的至少一种。
在该实施例中，第五族金属元素掺杂的区域为下电极靠近铁电材料层的区域或者是下电极与铁电材料层接触的表面。
在一个实施例中掺杂的第五族金属元素是通过掺杂这些金属的金属氧化物来实现掺杂，例如掺杂的可以是氧化钒(VO x)或者氧化铌(Nb 2O 5)或者氧化钽(Ta 2O 5)。
请参阅图4所示，其显示本发明的另一个实施例的示意图，在该实施例中在铁电电容的上电极和下电极中均掺杂有第五族金属元素，例如钒、铌、钽等金属中的至少一种。同样的掺杂的第五族金属元素是通过掺杂这些金属的金属氧化物来实现掺杂，例如掺杂的可以是氧化钒(VO x)或者氧化铌(Nb 2O 5)或者氧化钽(Ta 2O 5)。在该实施例中，第五族金属元素在上电极和下电极中的掺杂浓度为非均匀分布，其中电极靠近铁电材料区域的掺杂第五族金属元素的浓度高于电极远离铁电材料层区域的掺杂浓度。
请参阅图5所示，其显示本发明的再一个实施例的示意图，在该实施例中在铁电电容的上电极和下电极中均掺杂有第五族金属元素，例如钒、铌、钽等金属中的至少一种。同样的掺杂的第五族金属元素是通过掺杂这些金属的金属氧化物来实现掺杂，例如掺杂的可以是氧化钒(VO x)或者氧化铌(Nb 2O 5)或者氧化钽(Ta 2O 5)。在该实施例中，第五族金属元素在上电极和下电极中的掺杂浓度为均匀分布。
请参阅图6所示，其显示本发明的铁电存储单元的另一实施例的物理结构示意图。如图中所示，本发明的一个实施例的铁电存储器的存储单元包括晶体管1和与晶体管1通过导电互连4连接的铁电电容器5。在该实施例中该铁电电容器5为三维立体圆柱体结构的电容。请参考图7及图8所示，其中图7为图6中三维立体圆柱体结构铁电电容的立体示意图，图8为图7所示铁电电容的截面示意图，如图7及图8所示，该铁电电容器包括内层的第一电极51(上电极)和外层的第二电极52(下电极)以及位于第一电极51和第二电极52之间的铁电材料层53。同样的该电容的电极的材料可以是以下材料中的一种或多种：钛(Ti)、氮化钛(TiN)、氮化钛 硅(TiSiNx)、氮化钛铝(TiAlNx)、碳氮化钛(TiCNx)、氮化钽(TaNx)、氮化钽硅(TaSiNx)、氮化钽铝(TaAlNx)、氮化钨(WNx)、硅化钨(WSix)、碳氮化钨(WCNx)、钌(Ru)、氧化钌(RuOx)、铱(Ir)、掺杂多晶硅、透明导电氧化物(TCO)或氧化铱(IrOx)或这些材料的复合。
同样的，该实施例的铁电电容的铁电材料层包括氧和一种或多种铁电金属组成的具有铁电性的材料，所述铁电金属包括锆(Zr)、铪(Hf)、钛(Ti)、铝(Al)、镍(Ni)和/或铁(Fe)，并且所述铁电材料可以掺杂第II族元素钙(Ca)、锶(Sr)或钡(Ba)；或者掺杂第III族元素钪(Sc)、钇(Y)、铝(Al)、镓(Ga)以及铟(In))；或者掺杂镧系元素镧(La)、铈(Ce)、镨(Pr)、钕(Nd)、钷(Pm)、钐(Sm)、铕(Eu)、钆(Gd)、铽(Tb)、镝(Dy)、钬(Ho)、铒(Er)、铥(Tm)、镱(Yb)、镥(Lu)。
参考图3至图5的实施例，在图6所示的三维立体电容器的电极内掺杂有元素周期表中第五族金属元素，例如钒、铌、钽等金属中的至少一种。同样的，掺杂的第五族金属元素是通过掺杂这些金属的金属氧化物来实现掺杂，例如掺杂的可以是氧化钒(VO x)或者氧化铌(Nb 2O 5)或者氧化钽(Ta 2O 5)。而且电极可以是只在其中一个电极内掺杂，也可以是两个电极内都掺杂。而掺杂的浓度可以是在电极内均匀分布，也可以是在电极内非均匀分布，电极靠近铁电材料区域或者与铁电材料接触的表面的掺杂浓度高于电极的其他区域的浓度。
根据本发明的一个实施例，制造该铁电存储器的方法，其包括如下步骤：
提供半导体衬底的步骤；
在半导体衬底上形成晶体管的步骤，其中该晶体管包括栅极、源极和漏极；
在半导体衬底上形成与晶体管的源极或漏极连接的金属互连的步骤；具体可以包括在半导体衬底的晶体管上方沉积介质层，然后在介质层内形成通孔，在通孔内形成金属互连。
在晶体管上方形成铁电电容器，铁电电容器的一个电极通过金属互连与晶体管的源极或漏极相连，其中在形成电容器的电极时在至少一个电极 中掺杂第五族金属元素中的至少一种的步骤。
根据平面电容还是三维立体电容不同的电容结构，形成铁电电容的方法不同。形成平面电容的方法具体可以包括，在半导体衬底上形成金属互连后，在形成金属互连的介质层上沉积铁电电容的下电极，然后对下电极进行第五族金属元素的掺杂，然后在下电极上形成铁电材料层，然后在铁电材料层上形成上电极，需要的话对上电极进行第五族金属元素的掺杂，然后通过化学机械研磨或者光罩刻蚀的方式形成相互分离的单个铁电电容。
形成三维立体电容结构的方法具体可以包括，在半导体衬底上形成金属互连后，在形成金属互连的介质层上沉积介质层，然后在介质层内刻蚀形成圆柱形深孔结构，然后参考图8所示的结构在深孔结构内依次沉积铁电电容的下电极、铁电材料层和上电极，其中在形成电容的电极时对电极进行第五族金属元素的掺杂，然后通过化学机械研磨或者光罩刻蚀的方式形成相互分离的单个铁电电容。
上述描述仅是对本发明较佳实施例的描述，并非对本发明范围的任何限定，本发明领域的普通技术人员根据上述揭示内容做的任何变更、修饰，均属于本发明权利要求书的保护范围。

Claims (11)

  1. 一种铁电电容器，其包括第一电极、第二电极和位于第一电极和第二电极之间的铁电材料层，其特征在于：在铁电电容器的第一电极或第二电极至少一个中掺杂有第五族金属元素中的至少一种。
  2. 如权利要求1所述的铁电电容器，其中所述第五族金属元素包括钒、铌、钽。
  3. 如权利要求1所述的铁电电容器，其中掺杂的第五族金属元素为第五族金属元素的金属氧化物。
  4. 如权利要求1所述的铁电电容器，其中所述第五族金属元素在第一电极或第二电极中为均匀分布。
  5. 如权利要求1所述的铁电电容器，其中所述第五族金属元素在第一电极或第二电极靠近铁电材料层的区域的浓度高于其他区域的浓度。
  6. 如权利要求1所述的铁电电容器，其中所述铁电电容器为平面电容器。
  7. 如权利要求1所述的铁电电容器，其中所述铁电电容器为内层为第一电极，中间层为铁电材料层，最外层为第二电极的柱体状三维立体电容器。
  8. 如权利要求1所述的铁电电容器，其中第一电极和第二电极的材料可以是以下材料中的一种或多种：钛(Ti)、氮化钛(TiN)、氮化钛硅(TiSiNx)、氮化钛铝(TiAlNx)、碳氮化钛(TiCNx)、氮化钽(TaNx)、氮化钽硅(TaSiNx)、氮化钽铝(TaAlNx)、氮化钨(WNx)、硅化钨(WSix)、碳氮化钨(WCNx)、钌(Ru)、氧化钌(RuOx)、铱(Ir)、掺杂多晶硅、透明导电氧化物(TCO)或氧化铱(IrOx)或这些材料的复合。
  9. 如权利要求1所述的铁电电容器，其中所述铁电材料包括氧和一种或多种铁电金属组成的具有铁电性的材料，所述铁电金属包括锆(Zr)、铪(Hf)、钛(Ti)、铝(Al)、镍(Ni)和/或铁(Fe)，并且所述铁电材料可以掺杂第II族元素钙(Ca)、锶(Sr)或钡(Ba)；或者掺杂第III族元素钪(Sc)、钇(Y)、铝(Al)、镓(Ga)以及铟(In))；或者掺杂镧系元素镧(La)、铈(Ce)、镨(Pr)、钕(Nd)、钷(Pm)、钐(Sm)、铕(Eu)、 钆(Gd)、铽(Tb)、镝(Dy)、钬(Ho)、铒(Er)、铥(Tm)、镱(Yb)、镥(Lu)。
  10. 一种铁电存储器，其包括若干阵列排布的存储单元，每个存储单元包括晶体管和与晶体管连接的铁电电容器，其中所述铁电电容器采用前述权利要求1-9中的任意一项所述的铁电电容器。
  11. 一种制造权利要求10所述的铁电存储器的制造方法，其包括：
    提供半导体衬底；
    在半导体衬底上形成晶体管，其包括栅极、源极和漏极；
    在半导体衬底上形成与晶体管的源极或漏极连接的金属互连；
    在晶体管上方形成铁电电容器，铁电电容器的一个电极通过金属互连与晶体管的源极或漏极相连，其中在形成电容器的电极时在至少一个电极中掺杂第五族金属元素中的至少一种。
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