WO2021131620A1 - 接続構造体及び接続構造体の製造方法 - Google Patents

接続構造体及び接続構造体の製造方法 Download PDF

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Publication number
WO2021131620A1
WO2021131620A1 PCT/JP2020/045304 JP2020045304W WO2021131620A1 WO 2021131620 A1 WO2021131620 A1 WO 2021131620A1 JP 2020045304 W JP2020045304 W JP 2020045304W WO 2021131620 A1 WO2021131620 A1 WO 2021131620A1
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Prior art keywords
solder
electrode
particles
region
solder particles
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PCT/JP2020/045304
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English (en)
French (fr)
Inventor
邦彦 赤井
勝将 宮地
純一 畠
芳則 江尻
敏光 森谷
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昭和電工マテリアルズ株式会社
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Application filed by 昭和電工マテリアルズ株式会社 filed Critical 昭和電工マテリアルズ株式会社
Priority to US17/788,501 priority Critical patent/US20230060577A1/en
Priority to EP20906432.8A priority patent/EP4084020A4/en
Priority to JP2021567160A priority patent/JP7480789B2/ja
Priority to CN202080093197.1A priority patent/CN114982069A/zh
Priority to KR1020227023706A priority patent/KR20220123241A/ko
Publication of WO2021131620A1 publication Critical patent/WO2021131620A1/ja

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    • H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1189—Pressing leads, bumps or a die through an insulating layer
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    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof
    • H05K3/3463—Solder compositions in relation to features of the printed circuit board or the mounting process
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    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/36—Assembling printed circuits with other printed circuits
    • H05K3/368—Assembling printed circuits with other printed circuits parallel to each other

Definitions

  • the present invention relates to a connection structure and a method for manufacturing the connection structure.
  • a semiconductor chip mounted on an electronic device is mounted on a circuit board by wire bonding or ball grid array (BGA) connection using solder balls, and then sealed with an insulating resin material, which is a function called a semiconductor package. It is used as an aggregate.
  • BGA ball grid array
  • the BGA connection has contributed to the miniaturization of the semiconductor package because the pitch between the electrodes can be narrowed (Patent Document 1).
  • solder with silver or copper added to tin has been used since the 2000s, and it is mounted at a reflow temperature of around 260 ° C.
  • the problem is that stress is applied to the mounting part (solder part) due to the difference in the coefficient of thermal expansion of each material due to the thermal history due to the 260 ° C reflow, causing fracture. was there.
  • the alloying of the solder and the metal material of the electrode progresses and an alloy layer that promotes fracture is formed.
  • Patent Document 3 discloses a mounting method using low-temperature solder using tin and bismuth and having a melting point of 200 ° C. or lower.
  • tin-bismuth solder has a problem that the solder joint is easily broken by an external impact because the bismuth is brittle.
  • Patent Document 4 an attempt is made to improve the brittleness of a joint by adding a trace amount of metal to tin-bismuth solder.
  • anisotropic conductive materials such as anisotropic conductive films and anisotropic conductive pastes have been conventionally used as a method for electrically connecting a large number of electrodes at once.
  • the anisotropic conductive material is used for mounting a large number of wirings at once, such as mounting a control IC for a display and connecting / mounting tab wires, and in recent years, it has enabled narrow pitch connection of less than 30 ⁇ m.
  • solder particles has been conventionally studied as conductive particles to be blended in these anisotropic conductive materials.
  • Patent Document 5 describes a conductive paste containing a thermosetting component and a plurality of solder particles that have been subjected to a specific surface treatment.
  • connection temperature has been lowered in response to the diversification of circuit members, and the connection points have become smaller and thinner as the circuit members have become higher in definition, and the continuity reliability of the connection structure has been increased. It is difficult to secure.
  • the present invention has been made in view of the above circumstances, and an object of the present invention is to provide a connection structure having excellent conduction reliability and insulation reliability, and a method for manufacturing the same.
  • One aspect of the present invention is to electrically connect a first circuit member having a plurality of first electrodes, a second circuit member having a plurality of second electrodes, and a first electrode and a second electrode.
  • An intermediate layer having a plurality of joints to be formed is provided, and at least one of the first electrode and the second electrode connected at the joint is a gold electrode, and 90% or more of the plurality of joints are formed.
  • a connecting structure including a first region containing a tin-gold alloy connecting the first electrode and the second electrode, and a second region containing bismuth in contact with the first region.
  • the intermediate layer may further have an insulating resin layer that seals between the first circuit member and the second circuit member.
  • Another aspect of the present invention is a preparatory step for preparing a first circuit member having a plurality of first electrodes, a second circuit member having a plurality of second electrodes, and an anisotropic conductive film.
  • the surface of the first circuit member having the first electrode and the surface of the second circuit member having the second electrode are different from each other in the first circuit member, the second circuit member and the anisotropic conductive film.
  • the present invention relates to a method for manufacturing a connection structure, which comprises a connection step of electrically connecting a first electrode and the second electrode via a joint portion by heating in a state of being pressed in a direction.
  • at least one of the first electrode and the second electrode is a gold electrode
  • the anisotropic conductive film is an insulating film composed of an insulating resin composition and the insulating film.
  • the solder particles are arranged so as to be arranged in the horizontal direction in a state of being separated from the adjacent solder particles. Further, 90% or more of the plurality of joints formed in the connection step is a first region containing a tin-gold alloy connecting the first electrode and the second electrode, and the first region. Includes a second region containing bismuth, which is in contact with.
  • the solder particles include a solder fine particle preparation step of preparing a substrate having a plurality of recesses and solder fine particles containing a tin-bismuth alloy, and a storage step of accommodating at least a part of the solder fine particles in the recesses.
  • the C.I. V. The value may exceed 20.
  • the anisotropic conductive film is a first resin layer on which the solder particles are transferred by bringing the insulating resin composition into contact with the opening side of the recesses of the substrate having a plurality of recesses containing the solder particles.
  • An anisotropic conductive film is formed by forming a second resin layer composed of an insulating resin composition on the surface of the first resin layer on the side to which the solder particles are transferred. It may be an anisotropic conductive film produced by a method including a laminating step for obtaining the film.
  • connection structure having excellent conduction reliability and insulation reliability and a method for manufacturing the same are provided.
  • FIG. 1 is a cross-sectional view schematically showing a first embodiment of an anisotropic conductive film.
  • FIG. 2A is a schematic cross-sectional view taken along the line IIa-IIa shown in FIG. 1, and FIG. 2B is a cross-sectional view schematically showing a modified example of the first embodiment.
  • FIG. 3A is a plan view schematically showing an example of the substrate, and FIG. 3B is a cross-sectional view taken along the line Ib-Ib of FIG. 3A.
  • 4 (a) to 4 (h) are cross-sectional views schematically showing an example of the cross-sectional shape of the concave portion of the substrate.
  • FIG. 1 is a cross-sectional view schematically showing a first embodiment of an anisotropic conductive film.
  • FIG. 2A is a schematic cross-sectional view taken along the line IIa-IIa shown in FIG. 1
  • FIG. 2B is a cross-sectional view schematically showing a modified example of the first
  • FIG. 5 is a cross-sectional view schematically showing a state in which solder fine particles are contained in the recesses of the substrate.
  • FIG. 6 is a cross-sectional view schematically showing a state in which solder particles are formed in the recesses of the substrate.
  • FIG. 7A is a view of the solder particles viewed from the side opposite to the opening of the recess in FIG. 6, and
  • FIG. 7B is a quadrangle circumscribing the projected image of the solder particles created by two pairs of parallel lines. It is a figure which shows the distance X and Y (however, Y ⁇ X) between the opposite sides in the case.
  • FIG. 8 (a) to 8 (c) are cross-sectional views schematically showing an example of the manufacturing process of the anisotropic conductive film according to the first embodiment.
  • 9 (a) to 9 (c) are cross-sectional views schematically showing an example of the manufacturing process of the anisotropic conductive film according to the second embodiment.
  • 10 (a) and 10 (b) are cross-sectional views schematically showing another example of the manufacturing process of the anisotropic conductive film.
  • FIG. 11 is an enlarged view showing a part of the connection structure, and is a cross-sectional view schematically showing a state in which the first electrode and the second electrode are electrically connected by a joint portion.
  • 12 (a) and 12 (b) are cross-sectional views schematically showing a first example of the manufacturing process of the connection structure according to the present invention.
  • 13 (a) and 13 (b) are cross-sectional views schematically showing a second example of the manufacturing process of the connection structure according to the present invention.
  • 14 (a) and 14 (b) are cross-sectional views schematically showing a third example of the manufacturing process of the connection structure according to the present invention.
  • 15 (a), 15 (b), 15 (c) and 15 (d) are cross-sectional views schematically showing an example of a joint including a first region and a second region, respectively. is there.
  • 16 (a), 16 (b), 16 (c) and 16 (d) are cross-sectional views schematically showing an example of a joint including a first region and a second region, respectively. is there. 17 (a), 17 (b), 17 (c), 17 (d), 17 (e) and 17 (f) include a first region and a second region, respectively. It is a top view which shows an example of a joint portion schematically. 18 (a), 18 (b) and 18 (c) are cross-sectional views schematically showing an example of a joint portion not including the first region and the second region, respectively.
  • 19 (a), 19 (b), 19 (c) and 19 (d) are cross-sectional views schematically showing an example of a joint portion not including the first region and the second region, respectively.
  • FIG. 20 is a plan view schematically showing a first example of the relationship between the positions of the solder particles of the anisotropic conductive film before being pressed and heated and the positions of the bumps (electrodes).
  • FIG. 21 is a plan view schematically showing a second example of the relationship between the positions of the solder particles of the anisotropic conductive film before being pressed and heated and the positions of the bumps (electrodes).
  • FIG. 22 is a plan view schematically showing a third example of the relationship between the positions of the solder particles of the anisotropic conductive film before being pressed and heated and the positions of the bumps (electrodes).
  • FIG. 20 is a plan view schematically showing a first example of the relationship between the positions of the solder particles of the anisotropic conductive film before being pressed and heated and the positions of the bumps (electrodes).
  • FIG. 21 is a plan view schematically showing a second example of the relationship between the positions of the solder particles
  • FIG. 23 is a plan view schematically showing a fourth example of the relationship between the positions of the solder particles of the anisotropic conductive film before being pressed and heated and the bumps (electrodes).
  • FIG. 24 is a cross-sectional view schematically showing another example of the cross-sectional shape of the concave portion of the substrate.
  • FIG. 25 (a) is a cross-sectional image of the connected structure after being pressed and heated
  • FIG. 25 (b) is a diagram showing the EDX analysis result of the cross-sectional image.
  • each component in the composition means the total amount of the plurality of substances present in the composition when a plurality of substances corresponding to each component are present in the composition, unless otherwise specified.
  • the numerical range indicated by using "-" indicates a range including the numerical values before and after "-" as the minimum value and the maximum value, respectively.
  • the upper limit value or the lower limit value of the numerical range of one step may be replaced with the upper limit value or the lower limit value of the numerical range of another step.
  • the upper limit value or the lower limit value of the numerical range may be replaced with the value shown in the examples.
  • the connection structure includes a first circuit member having a plurality of first electrodes, a second circuit member having a plurality of second electrodes, a first electrode, and the second electrode. It includes an intermediate layer having a plurality of electrically connected joints. Further, at least one of the first electrode and the second electrode connected at the joint is a gold electrode, and 90% or more of the plurality of joints connects the first electrode and the second electrode. It includes a first region containing a tin-gold alloy and a second region containing bismuth in contact with the first region.
  • the connection structure according to the present embodiment includes a joint including a first region connecting the first electrode and the second electrode and a second region in contact with the first region.
  • the first region contains a tin-gold alloy and is integrated, and the second region functions as a reinforcing portion, so that cracks are unlikely to occur.
  • the first region of the joint contains a tin-gold alloy having a high melting point, remelting of the joint is sufficiently suppressed.
  • 90% or more of the joint portion of the connection structure according to the present embodiment includes such a first region and a second region, cracks in the joint portion and melting of the joint portion are sufficient. It is suppressed to excellent conduction reliability.
  • the connection structure according to the present embodiment is sufficiently suppressed from melting at the joint, it is easy to apply to secondary mounting and the like, and is also suitable for use in a high temperature environment.
  • the intermediate layer may further have an insulating resin layer that seals between the first circuit member and the second circuit member.
  • the insulating resin layer may be formed of an insulating film of an anisotropic conductive film described later.
  • the proportion of the joint portion including the first region and the second region in the joint portion in the connection structure is 80% or more, preferably 85% or more, more preferably. It is 90% or more, and may be 100%.
  • connection structure In order for most of the joints of the connection structure to include the first region and the second region, it is desirable that the solder particles used to form each joint are uniform. Further, in order to make most of the joints of the connecting structure include the first region and the second region, the insulating resin composition is arranged around the solder particles, and the solder particles are melted when they are melted. It is desirable that the solder is held between the first electrode and the second electrode for a sufficient time. From these viewpoints, the connection structure according to the present embodiment is preferably one in which the first circuit member and the second circuit member are joined by using the anisotropic conductive film shown below.
  • the anisotropic conductive film 10 according to the first embodiment shown in FIG. 1 is composed of an insulating film 2 made of an insulating resin composition and a plurality of solder particles 1 arranged in the insulating film 2. ing.
  • one solder particle 1 is arranged so as to be arranged in a horizontal direction (horizontal direction in FIG. 1) in a state of being separated from one adjacent solder particle 1.
  • the central region 10a in which a plurality of solder particles 1 are arranged in a horizontal direction and the surface side regions 10b and 10c in which the solder particles 1 are substantially not present are present. It is composed of and.
  • FIG. 2A is a schematic cross-sectional view taken along the line IIa-IIa shown in FIG.
  • the solder particles 1 are regularly arranged in the cross section of the anisotropic conductive film 10.
  • the solder particles 1 may be arranged at regular and substantially even intervals with respect to the entire region of the anisotropic conductive film 10, and is shown in FIG. 2 (b).
  • a region 10d in which a plurality of solder particles 1 are regularly arranged and a region 10e in which the solder particles 1 do not substantially exist are regular as in the modified example.
  • the solder particles 1 may be arranged so as to be formed in a uniform manner. For example, the position and number of the solder particles 1 may be set according to the shape, size, pattern, and the like of the electrodes to be connected.
  • solder particles The average particle size of the solder particles 1 is, for example, 30 ⁇ m or less, preferably 25 ⁇ m or less, more preferably 20 ⁇ m or less, and further preferably 15 ⁇ m or less.
  • the average particle size of the solder particles 1 is, for example, 1 ⁇ m or more, preferably 2 ⁇ m or more, more preferably 3 ⁇ m or more, and further preferably 5 ⁇ m or more.
  • the average particle size of the solder particles 1 can be measured by using various methods according to the size. For example, a dynamic light scattering method, a laser diffraction method, a centrifugal sedimentation method, an electrical detection band method, a resonance type mass measurement method, or the like can be used. Further, a method of measuring the particle size from an image obtained by an optical microscope, an electron microscope, or the like can be used. Specific devices include a flow-type particle image analyzer, a microtrack, a Coulter counter, and the like.
  • C. of solder particles 1 V The value is preferably 20% or less, more preferably 10% or less, still more preferably 7% or less, from the viewpoint of achieving more excellent conductivity reliability and insulation reliability.
  • the lower limit of the value is not particularly limited.
  • C.I. V. The value may be 1% or more, and may be 2% or more.
  • the solder particle 1 may have a flat surface portion 11 formed on a part of the surface thereof, and at this time, the surface other than the flat surface portion 11 is preferably spherical crown-shaped. That is, the solder particles 1 may have a flat surface portion 11 and a spherical crown-shaped curved surface portion.
  • the ratio (A / B) of the diameter A of the flat surface portion 11 to the diameter B of the solder particles 1 may be, for example, more than 0.01 and less than 1.0 (0.01 ⁇ A / B ⁇ 1.0), and is 0. It may be 1 to 0.9. Since the solder particles 1 have the flat surface portion 11, misalignment due to pressurization at the time of connection is less likely to occur, and more excellent conductivity reliability and insulation reliability can be realized.
  • solder particles 1 When a quadrangle circumscribing the projected image of the solder particle 1 is created by two pairs of parallel lines, and the distance between the opposing sides is X and Y (where Y ⁇ X), the ratio of Y to X (Y). / X) may be more than 0.8 and less than 1.0 (0.8 ⁇ Y / X ⁇ 1.0), and may be 0.9 or more and less than 1.0.
  • solder particles 1 can be said to be particles closer to a true sphere. According to the manufacturing method described later, such solder particles 1 can be easily obtained.
  • solder particles 1 are close to a true sphere, for example, when a plurality of opposing electrodes are electrically connected via the solder particles 1, the contact between the solder particles 1 and the electrodes is less likely to be uneven, and a stable connection is achieved. Tends to be obtained. Further, when a conductive film or resin in which the solder particles 1 are dispersed in a resin composition is produced, high dispersibility is obtained, and dispersion stability during production tends to be obtained. Further, when a film or paste in which the solder particles 1 are dispersed in the resin composition is used for the connection between the electrodes, even if the solder particles 1 rotate in the resin, if the solder particles 1 have a spherical shape, the projected image is obtained. When viewed, the projected areas of the solder particles 1 are close to each other. Therefore, when connecting the electrodes, it tends to be easy to obtain a stable electrical connection with little variation.
  • FIG. 7B is a diagram showing the distances X and Y (provided that Y ⁇ X) between the opposing sides when a quadrangle circumscribing the projected image of the solder particles is created by two pairs of parallel lines.
  • an arbitrary particle is observed with a scanning electron microscope to obtain a projected image.
  • Two pairs of parallel lines are drawn with respect to the obtained projected image, and the pair of parallel lines are arranged at the position where the distance between the parallel lines is the minimum, and the other pair of parallel lines are arranged at the position where the distance between the parallel lines is the maximum.
  • Find the Y / X of the particle This operation is performed on 300 solder particles, the average value is calculated, and the Y / X of the solder particles is obtained.
  • the solder particles 1 include a tin-bismuth alloy (Sn-Bi alloy).
  • tin-bismuth alloy include the following examples. -Sn-Bi (Sn43% by mass, Bi57% by mass, melting point 138 ° C.) -Sn-Bi (Sn72% by mass, Bi28% by mass, melting point 138 ° C.) -Sn-Bi-Ag (Sn42% by mass, Bi57% by mass, Ag1% by mass, melting point 139 ° C.)
  • the solder particles 1 may further contain metals other than Sn and Bi.
  • other metals include Ag, Cu, Ni, Bi, Zn, Pd, Pb, Au, P, B, Ga, As, Sb, Te, Ge, Si, Al and the like.
  • the content of the other metal of the solder particles 1 is, for example, 10% by mass or less, preferably 5% by mass or less, and more preferably 3% by mass or less.
  • the insulating resin composition constituting the insulating film 2 may contain a thermosetting compound.
  • the thermosetting compound include oxetane compounds, epoxy compounds, episulfide compounds, (meth) acrylic compounds, phenol compounds, amino compounds, unsaturated polyester compounds, polyurethane compounds, silicone compounds and polyimide compounds.
  • epoxy compounds are preferable from the viewpoint of further improving the curability and viscosity of the insulating resin and further enhancing the connection reliability.
  • the insulating resin composition may further contain a thermosetting agent.
  • the thermosetting agent include an imidazole curing agent, an amine curing agent, a phenol curing agent, a polythiol curing agent, an acid anhydride, a thermal cation initiator, a thermal radical generator and the like. These may be used alone or in combination of two or more.
  • an imidazole curing agent, a polythiol curing agent, or an amine curing agent is preferable because it can be cured quickly at a low temperature.
  • a latent curing agent is preferable because the storage stability becomes high when the thermosetting compound and the thermosetting agent are mixed.
  • the latent curing agent is preferably a latent imidazole curing agent, a latent polythiol curing agent, or a latent amine curing agent.
  • the thermosetting agent may be coated with a polymer substance such as a polyurethane resin or a polyester resin.
  • the imidazole curing agent is not particularly limited, and 2-methylimidazole, 2-ethyl-4-methylimidazole, 1-cyanoethyl-2-phenylimidazole, 1-cyanoethyl-2-phenylimidazolium trimerite, 2, 4-Diamino-6- [2'-methylimidazolyl- (1')]-ethyl-s-triazine and 2,4-diamino-6- [2'-methylimidazolyl- (1')]-ethyl-s- Examples thereof include triazine isocyanuric acid adduct.
  • the polythiol curing agent is not particularly limited, and examples thereof include trimethylolpropane tris-3-mercaptopropionate, pentaerythritol tetrakis-3-mercaptopropionate, and dipentaerythritol hexa-3-mercaptopropionate. ..
  • the solubility parameter of the polythiol curing agent is preferably 9.5 or more, preferably 12 or less.
  • the solubility parameter is calculated by the Fedors method. For example, the solubility parameter for trimethylolpropane tris-3-mercaptopropionate is 9.6 and the solubility parameter for dipentaerythritol hexa-3-mercaptopropionate is 11.4.
  • the amine curing agent is not particularly limited, and is hexamethylenediamine, octamethylenediamine, decamethylenediamine, 3,9-bis (3-aminopropyl) -2,4,8,10-tetraspiro [5.5].
  • examples thereof include undecane, bis (4-aminocyclohexyl) methane, metaphenylenediamine and diaminodiphenylsulfone.
  • thermal cation curing agent examples include an iodonium-based cation curing agent, an oxonium-based cation curing agent, and a sulfonium-based cation curing agent.
  • examples of the iodonium-based cationic curing agent include bis (4-tert-butylphenyl) iodonium hexafluorophosphate and the like.
  • Examples of the oxonium-based cationic curing agent examples include trimethyloxonium tetrafluoroborate.
  • the sulfonium-based cationic curing agent examples include try-p-tolylsulfonium hexafluorophosphate.
  • the thermal radical generator is not particularly limited, and examples thereof include azo compounds and organic peroxides.
  • examples of the azo compound include azobisisobutyronitrile (AIBN) and the like.
  • examples of the organic peroxide include di-tert-butyl peroxide and methyl ethyl ketone peroxide.
  • the anisotropic conductive film 10 preferably contains a flux. Specifically, it is preferable that the insulating resin composition constituting the anisotropic conductive film 10 contains a flux and the surface of the solder particles 1 is covered with the flux. The flux melts the oxide on the surface of the solder to improve the cohesiveness of the solder particles and the wettability of the solder to the electrodes.
  • a flux generally used for solder bonding or the like can be used.
  • Specific examples include zinc chloride, a mixture of zinc chloride and an inorganic halide, a mixture of zinc chloride and an inorganic acid, a molten salt, phosphoric acid, a derivative of phosphoric acid, an organic halide, hydrazine, an organic acid, and pine fat. Can be mentioned. These may be used alone or in combination of two or more.
  • Examples of the molten salt include ammonium chloride.
  • Examples of the organic acid include lactic acid, citric acid, stearic acid, glutamic acid and glutaric acid.
  • Examples of pine fat include activated pine fat and non-activated pine fat. Pine fat is a rosin whose main component is abietic acid.
  • the melting point of the flux is preferably 50 ° C. or higher, more preferably 70 ° C. or higher, and even more preferably 80 ° C. or higher.
  • the melting point of the flux is preferably 200 ° C. or lower, more preferably 160 ° C. or lower, still more preferably 150 ° C. or lower, and particularly preferably 140 ° C. or lower.
  • the melting point range of the flux is preferably 80 to 190 ° C, more preferably 80 to 140 ° C or less.
  • Fluxes having a melting point in the range of 80 to 190 ° C include succinic acid (melting point 186 ° C), glutaric acid (melting point 96 ° C), adipic acid (melting point 152 ° C), pimeric acid (melting point 104 ° C), and suberic acid (melting point 104 ° C).
  • Dicarboxylic acids such as 142 ° C., benzoic acid (melting point 122 ° C.), malic acid (melting point 130 ° C.) and the like can be mentioned.
  • the method for producing the anisotropic conductive film 10 includes a solder fine particle preparation step of preparing a substrate having a plurality of recesses and solder fine particles, a storage step of storing at least a part of the solder fine particles in the recess, and a method of storing the solder fine particles in the recess.
  • the solder particles are formed by fusing the solder fine particles to form the solder particles inside the recesses and by bringing the insulating resin composition into contact with the opening side of the recesses of the substrate in which the solder particles are housed in the recesses.
  • a transfer step of obtaining the transferred first resin layer, and forming a second resin layer composed of an insulating resin composition on the surface of the first resin layer on the side to which the solder particles are transferred. Includes a laminating step of obtaining an anisotropic conductive film.
  • FIG. 3A is a plan view schematically showing an example of the substrate 60
  • FIG. 3B is a cross-sectional view taken along the line Ib-Ib shown in FIG. 3A.
  • the substrate 60 shown in FIG. 3A has a plurality of recesses 62.
  • the plurality of recesses 62 may be regularly arranged in a predetermined pattern. In this case, the substrate 60 can be used as it is in the transfer step described later.
  • the recess 62 of the base 60 is preferably formed in a tapered shape in which the opening area expands from the bottom 62a side of the recess 62 toward the surface 60a side of the base 60. That is, as shown in FIGS. 3A and 3B, the width of the bottom 62a of the recess 62 (the width a in FIGS. 3A and 3B) is the opening at the surface 60a of the recess 62. Is preferably narrower than the width of (width b in FIGS. 3 (a) and 3 (b)).
  • the size of the recess 62 may be set according to the size of the target solder particles.
  • the shape of the recess 62 may be a shape other than the shapes shown in FIGS. 3 (a) and 3 (b).
  • the shape of the opening on the surface 60a of the recess 62 may be an ellipse, a triangle, a quadrangle, a polygon, or the like, in addition to the circular shape as shown in FIG. 3A.
  • the shape of the recess 62 in the cross section perpendicular to the surface 60a may be, for example, the shape shown in FIG. 4 (a) to 4 (h) are cross-sectional views schematically showing an example of the cross-sectional shape of the concave portion of the substrate.
  • the width (width b) of the opening on the surface 60a of the recess 62 is the maximum width in the cross-sectional shape.
  • the shape of the recess 62 in the cross section perpendicular to the surface 60a may be, for example, as shown in FIG. 24, even if the wall surface in the cross-sectional shape shown in FIGS. 4A to 4H is inclined. Good.
  • FIG. 24 can be said to have an inclined wall surface having the cross-sectional shape shown in FIG. 4 (b).
  • the material constituting the substrate 60 for example, an inorganic material such as a metal such as silicon, various ceramics, glass, and stainless steel, and an organic material such as various resins can be used.
  • the substrate 60 is preferably made of a heat-resistant material that does not deteriorate at the melting temperature of the solder fine particles.
  • the recess 62 of the substrate 60 can be formed by a known method such as a photolithography method, an imprint method, or an etching method.
  • the solder fine particles prepared in the solder fine particle preparation step may contain fine particles having a particle size smaller than the width (width b) of the opening on the surface 60a of the recess 62, and more fine particles having a particle size smaller than the width b may be included. It is preferable to include it.
  • the D10 particle size of the particle size distribution is preferably smaller than the width b
  • the D30 particle size of the particle size distribution is more preferably smaller than the width b
  • the D50 particle size of the particle size distribution is smaller than the width b. More preferred.
  • the particle size distribution of the solder fine particles can be measured using various methods according to the size. For example, a dynamic light scattering method, a laser diffraction method, a centrifugal sedimentation method, an electrical detection band method, a resonance type mass measurement method, or the like can be used. Further, a method of measuring the particle size from an image obtained by an optical microscope, an electron microscope, or the like can be used. Specific devices include a flow-type particle image analyzer, a microtrack, a Coulter counter, and the like.
  • the value is not particularly limited, but from the viewpoint of improving the filling property into the recess 62 by the combination of large and small fine particles, C.I. V.
  • the value is preferably high.
  • C.I. V. The value may exceed 20%, preferably 25% or more, more preferably 30% or more.
  • V. The value is calculated by dividing the standard deviation of the particle size measured by the above method by the average particle size (D50 particle size) and multiplying by 100.
  • the solder fine particles include a tin-bismuth alloy (Sn-Bi alloy).
  • tin-bismuth alloy include the following examples. -Sn-Bi (Sn43% by mass, Bi57% by mass, melting point 138 ° C.) -Sn-Bi (Sn72% by mass, Bi28% by mass, melting point 138 ° C.) -Sn-Bi-Ag (Sn42% by mass, Bi57% by mass, Ag1% by mass, melting point 139 ° C.)
  • the solder fine particles may further contain metals other than Sn and Bi.
  • metals include Ag, Cu, Ni, Bi, Zn, Pd, Pb, Au, P, B, Ga, As, Sb, Te, Ge, Si, Al and the like.
  • the content of other metals in the solder fine particles is, for example, 10% by mass or less, preferably 5% by mass or less, and more preferably 3% by mass or less.
  • the solder fine particles prepared in the solder fine particle preparation step are accommodated in each of the recesses 62 of the substrate 60.
  • the accommodating step may be a step of accommodating all the solder fine particles prepared in the solder fine particle preparation step into the recess 62, and a part of the solder fine particles prepared in the solder fine particle preparation step (for example, among the solder fine particles, the concave portion 62). It may be a step of accommodating (those smaller than the width b of the opening) in the recess 62.
  • FIG. 5 is a cross-sectional view schematically showing a state in which the solder fine particles 111 are housed in the recess 62 of the substrate 60. As shown in FIG. 5, a plurality of solder fine particles 111 are housed in each of the plurality of recesses 62.
  • the amount of the solder fine particles 111 contained in the recess 62 is, for example, preferably 20% or more, more preferably 30% or more, still more preferably 50% or more, based on the volume of the recess 62. , 60% or more is most preferable. As a result, the variation in the accommodating amount is suppressed, and it becomes easy to obtain solder particles having a smaller particle size distribution.
  • the method of accommodating the solder fine particles in the recess 62 is not particularly limited.
  • the accommodating method may be either dry or wet.
  • the solder fine particles prepared in the preparation step are placed on the substrate 60, and the surface 60a of the substrate 60 is rubbed with a squeegee to remove the excess solder fine particles while accommodating sufficient solder fine particles in the recess 62. can do.
  • the width b of the opening of the recess 62 is larger than the depth of the recess 62, solder fine particles may pop out from the opening of the recess 62.
  • a squeegee is used, the solder fine particles protruding from the opening of the recess 62 are removed.
  • Examples of the method of removing the excess solder fine particles include a method of blowing compressed air, a method of rubbing the surface 60a of the substrate 60 with a non-woven fabric or a bundle of fibers, and the like. Since these methods have a weaker physical force than the squeegee, they are preferable for handling easily deformable solder fine particles. Further, in these methods, the solder fine particles protruding from the opening of the recess 62 can be left in the recess.
  • the fusion step is a step of fusing the solder fine particles 111 contained in the recess 62 to form the solder particles 1 inside the recess 62.
  • FIG. 6 is a cross-sectional view schematically showing a state in which the solder particles 1 are formed in the recess 62 of the substrate 60.
  • the solder fine particles 111 housed in the recess 62 are united by melting and spheroidized by surface tension.
  • the molten solder follows the bottom portion 62a to form the flat surface portion 11.
  • the formed solder particles 1 have a shape having a flat surface portion 11 on a part of the surface.
  • FIG. 7A is a view of the solder particles 1 viewed from the side opposite to the opening of the recess 62 in FIG.
  • the solder particles 1 have a shape in which a flat surface portion 11 having a diameter A is formed on a part of the surface of a sphere having a diameter B.
  • the solder particles 1 shown in FIGS. 6 and 7A have a flat surface portion 11 because the bottom portion 62a of the recess 62 is flat, but when the bottom portion 62a of the recess 62 has a shape other than a flat surface, the bottom portion It will have surfaces with different shapes corresponding to the shape of 62a.
  • Examples of the method of melting the solder fine particles 111 contained in the recess 62 include a method of heating the solder fine particles 111 to a temperature equal to or higher than the melting point of the solder. Due to the influence of the oxide film, the solder fine particles 111 may not melt even when heated at a temperature equal to or higher than the melting point, may not spread when wet, or may not coalesce. Therefore, the solder fine particles 111 are exposed to a reducing atmosphere to remove the surface oxide film of the solder fine particles 111, and then heated to a temperature equal to or higher than the melting point of the solder fine particles 111 to melt the solder fine particles 111 and spread them wet. It can be unified.
  • the solder fine particles 111 are melted in a reducing atmosphere.
  • the oxide film on the surface of the solder fine particles 111 is reduced, and the solder fine particles 111 are efficiently melted, wetted and spread, and unified. It will be easier to proceed.
  • the method for creating a reducing atmosphere is not particularly limited as long as the above effects can be obtained, and for example, there is a method using hydrogen gas, hydrogen radical, formic acid gas, or the like.
  • a hydrogen reduction furnace, a hydrogen radical reduction furnace, a formic acid reduction furnace, or a conveyor furnace or a continuous furnace thereof the solder fine particles 111 can be melted in a reducing atmosphere.
  • These devices may be equipped with a heating device, a chamber filled with an inert gas (nitrogen, argon, etc.), a mechanism for evacuating the inside of the chamber, etc., which makes it easier to control the reducing gas. Become. Further, if the inside of the chamber can be evacuated, the voids can be removed by reducing the pressure after the solder fine particles 111 are melted and united, and the solder particles 1 having further excellent connection stability can be obtained.
  • Profiles such as reduction, melting conditions, temperature, and atmosphere adjustment in the furnace of the solder fine particles 111 may be appropriately set in consideration of the melting point, particle size, recess size, material of the substrate 60, and the like of the solder fine particles 111.
  • the substrate 60 in which the solder fine particles 111 are filled in the recesses is inserted into the furnace, vacuumed, and then the reducing gas is introduced to fill the inside of the furnace with the reducing gas, and the surface oxide film of the solder fine particles 111 is formed.
  • the reducing gas is removed by vacuuming, and then the gas is heated to a temperature equal to or higher than the melting point of the solder fine particles 111 to dissolve and coalesce the solder fine particles to form the solder particles in the recess 62. After filling with nitrogen gas, the temperature inside the furnace is returned to room temperature to obtain solder particles 1. Further, for example, the substrate 60 in which the solder fine particles 111 are filled in the recesses is inserted into the furnace, and after vacuuming, the reducing gas is introduced to fill the inside of the furnace with the reducing gas, and the in-core heater is used.
  • the solder fine particles 111 are heated to remove the surface oxide film of the solder fine particles 111, then the reducing gas is removed by vacuuming, and then the solder fine particles 111 are heated to the melting point or higher to dissolve and coalesce the solder fine particles. After forming the solder particles in the recess 62, the temperature inside the furnace is returned to room temperature after filling with nitrogen gas to obtain the solder particles 1.
  • the substrate 60 in which the solder fine particles 111 are filled in the recesses is inserted into the furnace, and after vacuuming, the reducing gas is introduced to fill the inside of the furnace with the reducing gas, and the in-core heater is used.
  • the substrate 60 is heated to a temperature equal to or higher than the melting point of the solder fine particles 111 to remove the surface oxide film of the solder fine particles 111 by reduction, and at the same time, the solder fine particles are melted and united to form solder particles in the recess 62 and evacuated.
  • the temperature in the furnace is returned to room temperature after filling with nitrogen gas to obtain the solder particles 1. In this case, since the temperature rise and fall in the furnace need only be adjusted once, there is an advantage that the processing can be performed in a short time.
  • the inside of the furnace may be made into a reducing atmosphere again to add a step of removing the surface oxide film that could not be completely removed. As a result, it is possible to reduce residues such as solder fine particles remaining unfused and a part of the oxide film remaining unfused.
  • the substrate 60 in which the solder fine particles 111 are filled in the recesses is placed on the conveyor and passed through a plurality of zones in succession to obtain the solder particles 1.
  • the substrate 60 in which the solder fine particles 111 are filled in the recesses is placed on a conveyor set at a constant speed and passed through a zone filled with an inert gas such as nitrogen or argon at a temperature lower than the melting point of the solder fine particles 111.
  • solder fine particles 111 is removed by passing through a zone in which a reducing gas such as formic acid gas having a temperature lower than the melting point of the solder fine particles 111 exists, and then nitrogen or nitrogen having a temperature higher than the melting point of the solder fine particles 111 is removed.
  • Solder particles 1 are obtained by passing through a zone filled with an inert gas such as argon to melt and coalesce the solder fine particles 111, and then passing through a cooling zone filled with an inert gas such as nitrogen or argon to obtain solder particles 1. be able to.
  • the substrate 60 in which the solder fine particles 111 are filled in the recesses is placed on a conveyor set at a constant speed and passed through a zone filled with an inert gas such as nitrogen or argon having a temperature equal to or higher than the melting point of the solder fine particles 111. Subsequently, it is passed through a zone in which a reducing gas such as formic acid gas having a temperature equal to or higher than the melting point of the solder fine particles 111 exists to remove the surface oxide film of the solder fine particles 111, melted and united, and then nitrogen, argon, etc.
  • the solder particles 1 can be obtained by passing through a cooling zone filled with the inert gas.
  • a film-like material can be continuously processed by roll-to-roll.
  • a continuous roll product of the substrate 60 in which the solder fine particles 111 are filled in the recesses is produced, a roll unwinder is installed on the inlet side of the conveyor furnace, and a roll winder is installed on the outlet side of the conveyor furnace to maintain a constant speed.
  • the solder fine particles 111 filled in the recesses can be fused.
  • solder fine particle preparation step to the fusion step it is possible to form the solder particles 1 having a uniform size regardless of the material and shape of the solder fine particles 111. Further, since the formed solder particles 1 can be handled in a state of being housed in the recess 62 of the substrate 60, the solder particles 1 can be transported and stored without being deformed. Further, since the formed solder particles 1 are simply housed in the recesses 62 of the substrate 60, they can be easily taken out, and the solder particles can be collected, surface-treated, etc. without being deformed.
  • solder fine particles 111 may have a large variation in particle size distribution or a distorted shape, and can be suitably used as a raw material if they can be accommodated in the recess 62.
  • the shape of the recess 62 of the substrate 60 can be freely designed by lithography, machining, imprinting, etching, or the like. Since the size of the solder particles 1 depends on the amount of the solder fine particles 111 accommodated in the recess 62, the size of the solder particles 1 can be freely designed by designing the recess 62.
  • the solder particles 1 formed in the fusion step may be used as they are in the transfer step, or may be used in the transfer step after the surface is coated with the flux component while being housed in the recess 62 of the substrate 60. It may be taken out from 62, the surface may be coated with a flux component, and the surface may be recontained in the recess 62 before use in the transfer step.
  • the base 60 used for forming the solder particles 1 is used as it is in the transfer step, but when the step of taking out the solder particles 1 from the recess 62 is included, the taken out solder particles 1 are referred to as the base 60. May be housed in different substrates and used in the transfer process.
  • the first solder particles 1 are transferred by bringing the insulating resin material 2a into contact with the substrate 60 in which the solder particles 1 are housed in the recess 62 from the opening side of the recess 62. This is a step of obtaining the resin layer 2b.
  • the substrate 60 shown in FIG. 8A is in a state in which one solder particle 1 is housed in each of the recesses 62.
  • the layered insulating resin composition 2a is opposed to the opening-side surface of the recess 62 of the substrate 60, and the substrate 60 and the layered insulating resin composition 2a are brought close to each other (arrows A in FIG. 8A).
  • the layered insulating resin composition 2a is formed on the surface of the support 65.
  • the support 65 may be a plastic film or a metal foil.
  • FIG. 8B shows the state after the transfer step, in which the opening-side surface of the recess 62 of the substrate 60 is brought into contact with the layered insulating resin composition 2a, so that the substrate 60 is accommodated in the recess 62 of the substrate 60. It shows a state in which the solder particles 1 have been transferred to the layered insulating resin composition 2a.
  • a first resin layer 2b in which a plurality of solder particles 1 are transferred to predetermined positions of the layered insulating resin composition 2a is obtained.
  • a plurality of solder particles 1 are exposed on the surface of the first resin layer 2b.
  • the plurality of solder particles 1 are all arranged in the anisotropic conductive film 10 with the flat surface portion 11 facing the second resin layer 2d side.
  • the laminating step is anisotropic by forming a second resin layer 2d composed of an insulating resin composition on the surface 2c of the first resin layer 2b on the side to which the solder particles 1 are transferred. This is a step of obtaining the conductive film 10.
  • FIG. 8C shows a state after the laminating step, in which the support 65 is formed after forming the second resin layer 2d on the surface 2c of the first resin layer 2b so as to cover the solder particles 1. Shows the removed state.
  • the second resin layer 2d may be formed by laminating an insulating film made of an insulating resin composition on the first resin layer 2b, and the first resin layer 2b is a varnish containing an insulating resin material. It may be formed by applying a curing treatment after coating the above.
  • the accommodating step and the fusion step are carried out in the same manner as in the first embodiment, the solder particles are penetrated into the recess 62 in the transfer step. 1 is embedded in the first resin layer 2b.
  • the substrate 60 shown in FIG. 9A is in a state in which one solder particle 1 is housed in each of the recesses 62.
  • the layered insulating resin composition 2a is opposed to the opening-side surface of the recess 62 of the substrate 60, and the substrate 60 and the layered insulating resin composition 2a are brought close to each other (arrows A and A in FIG. 9A). B).
  • FIG. 9B shows the state after the transfer step, in which the surface of the substrate 60 on the opening side of the recess 62 is brought into contact with the layered insulating resin composition 2a so that the substrate 60 is accommodated in the recess 62. It shows a state in which the solder particles 1 have been transferred to the layered insulating resin composition 2a.
  • a first resin layer 2b in which a plurality of solder particles 1 are arranged at predetermined positions can be obtained.
  • a plurality of convex portions 2e corresponding to the concave portions 62 are formed on the surface 2c side of the first resin layer 2b, and the solder particles 1 are embedded in these convex portions 2e.
  • the insulating resin material 2a is penetrated into the recess 62.
  • the layered insulating resin composition 2a is formed by pressurizing the substrate 60 and the layered insulating resin composition 2a in the laminating direction (directions of arrows A and B in FIG. 9A). It may be allowed to enter the inside of the recess 62. Further, when the transfer step is performed in a reduced pressure atmosphere, the layered insulating resin composition 2a easily enters the inside of the recess 62. Further, in FIG.
  • the transfer step is carried out using the layered insulating resin material 2a, but the insulating resin composition is applied to the inside of the recess 62 and the surface of the substrate 60 in the state of a varnish to be cured.
  • the first resin layer 2b can also be obtained.
  • FIG. 9C shows a state after the laminating step, in which the support 65 is removed after the second resin layer 2d is formed on the surface 2c of the first resin layer 2b.
  • the second resin layer 2d may be formed by laminating an insulating film made of an insulating resin composition on the first resin layer 2b, and the first resin layer is a varnish containing the insulating resin composition. It may be formed by coating 2b and then performing a curing treatment.
  • the plurality of solder particles 1 are all arranged in the anisotropic conductive film 10 with the flat surface portion 11 facing the second resin layer 2d side.
  • the solder particles 1 formed in the fusion step are taken out once, coated with a flux component, and then rearranged in the recesses 62, the plurality of solder particles 1 are formed on the flat surface portion 11.
  • the orientations of the may be different from each other.
  • FIG. 10A shows a state in which the solder particles 1 once taken out are rearranged in the recess 62.
  • FIG. 10B is a diagram showing a state in which a plurality of solder particles 1 are arranged on the anisotropic conductive film 10 in a state where the orientations of the flat surface portions 11 do not match.
  • FIG. 11 is an enlarged view showing a part of the connection structure, and is a cross-sectional view schematically showing a state in which the first electrode and the second electrode are electrically connected by a joint portion. .. That is, FIG. 11 shows a state in which the electrode 32 of the first circuit member 30 and the electrode 42 of the second circuit member 40 are electrically connected via a joint 70 formed by fusion of the solder particles 1. Is schematically shown. As described above, “fused” in the present specification means that at least a part of the electrode is bonded by the solder particles 1 melted by heat, and then the solder is bonded to the surface of the electrode through a step of solidifying the solder particles 1. Means the state of soldering.
  • the first circuit member 30 includes a first circuit board 31 and a first electrode 32 arranged on the surface 31a thereof.
  • the second circuit member 40 includes a second circuit board 41 and a second electrode 42 arranged on the surface 41a thereof.
  • the insulating resin layer 55 filled between the circuit members 30 and 40 maintains a state in which the first circuit member 30 and the second circuit member 40 are adhered to each other, and the first electrode 32 and the second electrode The 42 remains electrically connected.
  • circuit members 30 and 40 include chip components such as IC chips (semiconductor chips), resistor chips, capacitor chips, and driver ICs; rigid type package substrates. These circuit members are provided with circuit electrodes, and are generally provided with a large number of circuit electrodes. Specific examples of the other of the circuit members 30 and 40 include wiring boards such as flexible tape boards having metal wiring, flexible printed wiring boards, and glass boards on which indium tin oxide (ITO) is vapor-deposited.
  • ITO indium tin oxide
  • first electrode 32 or the second electrode 42 include copper, copper / nickel, copper / nickel / gold, copper / nickel / palladium, copper / nickel / palladium / gold, copper / nickel / gold, and copper.
  • / Palladium, copper / palladium / gold, copper / tin, copper / silver, indium tin oxide and other electrodes can be mentioned.
  • the first electrode 32 or the second electrode 42 can be formed by electroless plating or electroplating or sputtering or etching of a metal foil.
  • At least one of the first electrode 32 and the second electrode 42 is a gold electrode.
  • the joint 70 includes a first region 71 connecting the first electrode 32 and the second electrode 42, and a second region 72 in contact with the first region.
  • a part of the gold in the gold electrode forms an alloy (tin-gold alloy) with tin in the solder, and the first region 71 is formed.
  • the bismuth in the solder is extruded from the first region 71 along with this, and a second region 72 surrounding the periphery of the first region 71 is formed.
  • the first region 71 may be composed of a tin-gold alloy, and the second region 72 may be composed of bismuth.
  • the ratio V 2 / V 1 of the volume V 2 of the second region 72 to the volume V 1 of the first region 71 may be, for example, 0.05 to 2.0, preferably 0.1 to 1.5. , 0.18 to 1.0 is more preferable.
  • the ratio of the joint 70 including the first region 71 and the second region 72 is 90% or more, preferably 95% or more, more preferably. It is 99% or more, and may be 100%.
  • the joint portion that does not include the first region 71 and the second region 72 include a joint portion having a columnar portion made of a tin-bismuth alloy.
  • the first region 71 may have a columnar structure connecting the first electrode 32 and the second electrode 42, and the second region 71 may have a columnar structure.
  • 72 may have an annular structure surrounding the first region 71.
  • the cross section of the joint portion 70 shown in FIG. 15 (a) perpendicular to the stacking direction may have a structure as shown in FIG. 17 (a), for example.
  • the first region 71 may have a columnar structure connecting the first electrode 32 and the second electrode 42, and the second region 71 may have a columnar structure.
  • 72 may be a mass in contact with a part of the first region 71.
  • the cross section of the joint portion 70 shown in FIG. 15 (b) perpendicular to the stacking direction may have a structure as shown in FIG. 17 (b), for example.
  • the joint portion 70 may include a plurality of first regions 71 having a columnar structure connecting the first electrode 32 and the second electrode 42. Further, in the joint portion 70, the second region 72 may be arranged between the plurality of first regions 71 so as to connect the plurality of first regions 71 to each other.
  • the cross section of the joint portion 70 shown in FIG. 15 (c) perpendicular to the stacking direction may have a structure as shown in FIG. 17 (c), for example.
  • the first region 71 may have a columnar structure connecting the first electrode 32 and the second electrode 42. Further, the joint portion 70 may have a lump body further containing a tin-gold alloy in addition to the columnar structure. As shown in FIG. 15 (d), the massive body is integrated with the first region 71 to form a part of the first region 71 (that is, the first region 71 is a columnar portion and a massive portion). It may be present at a distance from the first region 71. In the former case, the second region 72 may be arranged so as to be in contact with the columnar portion or the massive portion of the first region 71, and in the latter case, the second region 72 is the first region 71 and the massive portion. It may be placed in contact with both bodies.
  • the cross section of the joint portion 70 shown in FIG. 15 (c) perpendicular to the stacking direction may have a structure as shown in FIG. 17 (c) or FIG. 17 (d), for example.
  • the first region 71 may have a columnar structure connecting the first electrode 32 and the second electrode 42, and the second region 71 may have a columnar structure.
  • 72 may have an annular structure surrounding the first region 71.
  • the joint portion 70 may have a lump body further containing bismuth, in addition to the annular structure.
  • the mass is integrated with the second region 72 to form a part of the second region 72 (that is, the second region 72 is in the form of an annular portion and a mass). It may have a portion) and may be in contact with the first region 71 as another second region 72, separated from the annular second region 72.
  • the cross section of the joint portion 70 shown in FIG. 16 (a) perpendicular to the stacking direction may have a structure as shown in FIG. 17 (d), for example.
  • the first region 71 may have a columnar structure connecting the first electrode 32 and the second electrode 42, and the second region 71 may have a columnar structure.
  • the 72 may have an annular structure surrounding a part of the first region 71. Further, the first region 71 may extend along the electrode surface of the first electrode 32 or the second electrode 42.
  • the joint portion 70 may be formed by unifying a plurality of solder particles 1 (or solder bumps). As shown in FIG. 16 (c), the joint portion 70 may include a first region 71 having a columnar structure formed by coalescence of a plurality of solder particles 1, and the first region 71 may be included. A second annular region 72 may be further included. Further, as shown in FIG. 16D, the joint portion 70 may have a plurality of first regions 71 from which each of the plurality of solder particles 1 (or solder bumps) are derived, and the second region 72 A plurality of first regions 71 may be connected by the solder. The cross section of the joint portion 70 shown in FIG.
  • FIG. 17 (e) perpendicular to the stacking direction may have a structure as shown in FIG. 17 (e), for example.
  • the cross section of the joint portion 70 shown in FIG. 16 (d) perpendicular to the stacking direction may have a structure as shown in FIG. 17 (f), for example.
  • FIGS. 18 (a), 18 (b) and 18 (c) are cross sections in the stacking direction schematically showing an example of a joint portion not including the first region and the second region, respectively. It is a figure.
  • the region 91 containing the tin-gold alloy is unevenly distributed on each of the first electrode 32 side and the second electrode 42 side, and the first electrode 32 and the region 91 are unevenly distributed.
  • the second electrode 42 cannot be connected.
  • a region 92 containing bismuth is formed between the region 91 on the side of the first electrode 32 and the region 91 on the side of the second electrode 42. Since the joint portion 90 shown in FIG. 18A does not have the first region, it does not correspond to the “joint portion including the first region and the second region”.
  • the cross section of the joint portion 90 shown in FIG. 18 (a) perpendicular to the stacking direction may have a structure as shown in FIGS. 19 (a), 19 (b) or 19 (c), for example.
  • the region 91 containing the tin-gold alloy is unevenly distributed on the side of the second electrode 42, and bismuth is formed between the region 91 and the first electrode 32.
  • the containing region 92 is formed.
  • the region 91 does not connect the first electrode 32 and the second electrode 42, and is a “joint portion including the first region and the second region”. Does not apply to.
  • the cross section of the joint portion 90 shown in FIG. 18 (a) perpendicular to the stacking direction may have a structure as shown in FIGS. 19 (a), 19 (b) or 19 (c), for example.
  • the region 91 containing the tin-gold alloy and the region 92 having the bismuth alloy are unevenly distributed on the side of the second electrode 42, and the first electrode 32 and the second electrode 32 are distributed.
  • the electrode 42 of the above is not electrically connected.
  • the alloying of gold and tin is insufficient, and a region 93 containing tin is formed in the region 92.
  • the region 91 does not connect the first electrode 32 and the second electrode 42, and is a “joint portion including the first region and the second region”. Does not apply to.
  • the cross section of the joint portion 90 shown in FIG. 18 (a) perpendicular to the stacking direction has, for example, a structure as shown in FIGS. 19 (a), 19 (b), 19 (c) or 19 (d). It may be there.
  • FIGS. 12 (a) and 12 (b) are cross-sectional views schematically showing an example of the process of forming the connection structure 50A shown in FIG.
  • the anisotropic conductive film 10 shown in FIG. 1 is prepared in advance and arranged so that the first circuit member 30 and the second circuit member 40 face each other (FIG. 12A).
  • the first electrode 32 of the first circuit member 30 and the second electrode 42 of the second circuit member 40 are installed so as to face each other.
  • pressure is applied in the thickness direction of the laminated body of these members (directions of arrows A and B shown in FIG. 12A).
  • the solder particles 1 By heating the whole to a temperature higher than the melting point of the solder particles 1 (for example, 130 to 260 ° C.) when pressurizing in the directions of the arrows A and B, the solder particles 1 are melted and the first electrode 32 and the first electrode 32 are formed.
  • the joint 70 is formed by gathering together between the second electrodes 42, and then by cooling, the joint 70 is fixed between the first electrode 32 and the second electrode 42, and the first electrode is formed.
  • the 32 and the second electrode 42 are electrically connected.
  • the insulating resin composition constituting the insulating film 2 contains, for example, a thermosetting resin
  • the insulating resin composition can be cured by heating the whole when pressurizing in the directions of arrows A and B. it can.
  • an insulating resin layer 55 made of a cured product of the insulating resin composition is formed between the circuit members 30 and 40.
  • 13 (a) and 13 (b) are cross-sectional views schematically showing a modified example of the manufacturing method of the connection structure 50A shown in FIGS. 12 (a) and 12 (b).
  • the manufacturing method according to this modification although a part of the solder particles 1 remains in the insulating resin layer 55 without contributing to the fusion of the electrodes 32 and 42, it is specific in the anisotropic conductive film 10. Only the solder particles 1 are arranged at the positions, that is, the density of the solder particles 1 is sufficiently low, so that the insulation reliability can be maintained high.
  • solder particles 1 become the joint portion 70, and the first electrode 32 of the first circuit member 30 and the second electrode 42 of the second circuit member 40 are formed. It is fused.
  • the arrangement of the solder particles 1 in the anisotropic conductive film 10 in advance it is possible to reduce the remaining solder particles 1 as much as possible without contributing to fusion. Thereby, the insulation reliability of the connection structure can be further improved.
  • connection structure of the present embodiment may be manufactured by a method that does not use the anisotropic conductive film. Good.
  • solder is applied to the surface of the first electrode 32 (or the second electrode 42 of the second circuit member 40) of the first circuit member 30.
  • a bump is formed, and the first electrode 32 (or the second electrode 42) and the second electrode 42 (or the first electrode 32) on which the solder bump is formed are arranged at opposite positions and heated and pressurized.
  • the first electrode 32 and the second electrode 42 may be connected to manufacture the joint portion 70.
  • solder bumps are not particularly limited, but for example, a substrate 60 in which the solder particles 1 are housed is prepared in each of the recesses 62, and the first circuit member is formed on the opening side surface of the recesses 62 of the substrate 60.
  • Solder bumps can be formed on the surface of the first electrode 32 by arranging the first electrodes 32 of 30 facing each other and heat-treating while pressurizing in the thickness direction of the substrate. Solder bumps can also be formed on the surface of the second electrode 42 in the same manner.
  • the heat treatment is preferably carried out in, for example, a deoxidizing atmosphere or a reducing atmosphere.
  • a deoxidizing atmosphere or a reducing atmosphere.
  • the deoxidizing atmosphere may be, for example, an inert gas atmosphere such as nitrogen or argon, a vacuum state, or the like.
  • a flux, a viscous substance, or the like may be used when forming the solder bumps. Further, since these may interfere with the connection between the first electrode 32 and the second electrode 42, or may oxidize or corrode the solder bumps or electrodes, there is a step of removing them after the bumps are formed. You may.
  • the connection between the first electrode 32 and the second electrode 42 is preferably carried out in, for example, a deoxidizing atmosphere or a reducing atmosphere.
  • a deoxidizing atmosphere or a reducing atmosphere.
  • the part 70 can be formed.
  • the deoxidizing atmosphere may be, for example, an inert gas atmosphere such as nitrogen or argon, a vacuum state, or the like.
  • a flux, a viscous substance, or the like may be used in forming the joint portion 70. Further, when they oxidize or corrode the joint portion or the electrode, they may adversely affect the formation of the insulating resin layer 55 described later. Therefore, there may be a step of removing these after the joint portion 70 is formed. ..
  • the insulating resin material is injected and cured between the first circuit member 30 and the second circuit member 40, and the insulating resin layer 55 is formed. May be formed.
  • the joint portion 70 when the joint portion 70 is formed, the first circuit member 30 having the first electrode 32 on which the solder bumps are formed and the second circuit having the second electrode 42 are formed.
  • the member 40 is arranged so that the first electrode 32 and the second electrode 42 face each other, and an insulating resin film is further arranged between the first circuit member 30 and the second circuit member 40.
  • FIG. 21, FIG. 22 and FIG. 23 are diagrams schematically showing the relationship between the position of the solder particles 1 of the anisotropic conductive film 10 and the position of the first electrode 32 before being pressed and heated. Is. 20, FIG. 21, FIG. 22 and FIG. 23 schematically show the relationship between the position of the solder particles 1 in the substrate 60 and the position of the first electrode 32 (or the second electrode 42) when the solder bumps are formed. It can also be said that it is a diagram showing the target.
  • connection structures include connections of semiconductor memories, semiconductor logic chips, etc., connection portions for primary and secondary mounting of semiconductor packages, CMOS image devices, laser devices, and the like.
  • Examples thereof include junctions such as LED light emitting elements and devices such as cameras, sensors, liquid crystal displays, personal computers, mobile phones, smartphones, and tablets using them.
  • Step a1 Classification of Solder Fine Particles 100 g of Sn-Bi solder fine particles (manufactured by 5N Plus, melting point 139 ° C., Type 8) are immersed in distilled water, ultrasonically dispersed, then allowed to stand, and the solder floats in the supernatant. Fine particles were collected. This operation was repeated to recover 10 g of solder fine particles. The average particle size of the obtained solder fine particles was 1.0 ⁇ m, and C.I. V. The value was 42%.
  • Step b1 Arrangement on the substrate As shown in Table 1, the opening diameter is 2.3 ⁇ m ⁇ , the bottom diameter is 2.0 ⁇ m ⁇ , and the depth is 2.0 ⁇ m (the bottom diameter of 2.0 ⁇ m ⁇ means that the opening diameter is 2.3 ⁇ m ⁇ when the opening is viewed from the top surface.
  • a substrate polyimide film, thickness 100 ⁇ m
  • the plurality of recesses were regularly arranged at intervals of 1.0 ⁇ m.
  • the solder fine particles average particle diameter 1.0 ⁇ m, CV value 42%) obtained in step a were placed in the recesses of the substrate.
  • Step c1 Formation of solder particles
  • the substrate in which the solder fine particles are arranged in the recesses in the step b1 is put into a hydrogen radical reduction furnace (plasma reflow device manufactured by Shinko Seiki Co., Ltd.), evacuated, and then hydrogen gas is discharged into the furnace. It was introduced into the inside and the inside of the furnace was filled with hydrogen gas. Then, the inside of the furnace was adjusted to 120 ° C. and irradiated with hydrogen radicals for 5 minutes.
  • a hydrogen radical reduction furnace plasma reflow device manufactured by Shinko Seiki Co., Ltd.
  • Step d1 Recovery of Solder Particles
  • Solder particles were recovered from the recesses by tapping the substrate that had undergone the step c1 from the back side of the recesses.
  • the obtained solder particles were evaluated by the following method. ⁇ Evaluation of solder particles> The obtained solder particles were placed on a conductive tape fixed to the surface of the SEM observation pedestal, and the SEM observation pedestal was tapped on a stainless plate having a thickness of 5 mm to spread the solder particles evenly on the conductive tape.
  • Step e1 Production of Flux Coated Solder Particles
  • Solder particles were produced by the same method as in Production Example 1. 20 g of the obtained solder particles, 4 g of adipic acid, and 7 g of acetone are weighed in a three-mouthed flask, and then dibutyltin oxide 0. 03 g was added and reacted at 60 ° C. for 4 hours. Then, the solder particles were filtered and recovered.
  • the recovered solder particles 5 g of adipic acid, 20 g of toluene, and 0.03 g of paratoluenesulfonic acid were weighed in a three-necked flask and reacted at 120 ° C. for 3 hours while vacuuming and refluxing. .. At this time, the reaction was carried out while removing the water produced by dehydration condensation using a Dean-Stark extraction device. Then, the solder particles were collected by filtration, washed with hexane, and dried. The dried solder particles were crushed by an air flow type crusher and passed through a mesh with a sonic sieve to obtain flux-coated solder particles.
  • Step f1 Arrangement of flux-coated solder particles Opening diameter 2.3 ⁇ m ⁇ , bottom diameter 2.0 ⁇ m ⁇ , depth 2.0 ⁇ m (bottom diameter 2.0 ⁇ m ⁇ is the center of the opening diameter 2.3 ⁇ m ⁇ when the opening is viewed from the top.
  • a transfer type polyimide film, thickness 100 ⁇ m
  • the plurality of recesses were regularly arranged at intervals of 1.0 ⁇ m.
  • the flux-coated solder particles obtained in step e1 were placed in the recesses of the transfer mold.
  • Step g1 Preparation of adhesive film 100 g of phenoxy resin (manufactured by Union Carbide, trade name "PKHC") and acrylic rubber (40 parts by mass of butyl acrylate, 30 parts by mass of ethyl acrylate, 30 parts by mass of acrylonitrile, 3 parts by mass of glycidyl methacrylate) 75 g of the copolymer, molecular weight: 850,000) was dissolved in 400 g of ethyl acetate to obtain a solution.
  • PKHC phenoxy resin
  • acrylic rubber 40 parts by mass of butyl acrylate, 30 parts by mass of ethyl acrylate, 30 parts by mass of acrylonitrile, 3 parts by mass of glycidyl methacrylate
  • Step h1 Transfer of Flux Coated Solder Particles
  • the adhesive film formed on the separator and the transfer mold on which the flux coated solder particles are arranged in step f1 are arranged facing each other, and the flux coated solder particles are transferred to the adhesive film.
  • Step i1 Preparation of Anisotropic Conductive Film
  • the adhesive film produced in the same manner as in step g1 is brought into contact with the transfer surface of the adhesive film obtained in step h1 at 50 ° C. and 0.1 MPa (1 kgf / cm 2).
  • An anisotropic conductive film in which flux-coated solder particles were arranged in layers was obtained in a cross-sectional view of the film.
  • 2 ⁇ m is superposed on a film having a thickness of 2 ⁇ m
  • 3 ⁇ m is superposed on 3 ⁇ m
  • 4 ⁇ m is superposed on 4 ⁇ m
  • 10 ⁇ m is superposed on 10 ⁇ m
  • 15 ⁇ m is superposed on 15 ⁇ m
  • 20 ⁇ m is superposed on 20 ⁇ m.
  • 6 ⁇ m, 8 ⁇ m, 20 ⁇ m, 30 ⁇ m and 40 ⁇ m thick anisotropic conductive films were prepared.
  • Step j1 Preparation of Connection Structure
  • Step j1 Preparation of Evaluation Chip Seven types of chips with gold bumps (3.0 ⁇ 3.0 mm, thickness: 0.5 mm) shown below were prepared.
  • -Chip C1 Area 100 ⁇ m ⁇ 100 ⁇ m, space 40 ⁇ m, height: 10 ⁇ m, number of bumps 362 -Chip C2: Area 75 ⁇ m ⁇ 75 ⁇ m, space 20 ⁇ m, height: 10 ⁇ m, number of bumps 362 -Chip C3: Area 40 ⁇ m ⁇ 40 ⁇ m, space 16 ⁇ m, height: 7 ⁇ m, number of bumps 362 -Chip C4: Area 30 ⁇ m ⁇ 30 ⁇ m, space 12 ⁇ m, height: 6 ⁇ m, number of bumps 362 -Chip C5: Area 20 ⁇ m ⁇ 20 ⁇ m, space 7 ⁇ m, height: 5 ⁇ m, number of bumps 362 -Chip C6: Area 10 ⁇
  • the gold bumps are also formed with lead-out wiring for resistance measurement.
  • Substrate D1 ... Area 100 ⁇ m ⁇ 100 ⁇ m, space 40 ⁇ m, height: 4 ⁇ m, number of bumps 362
  • Substrate D2 Area 75 ⁇ m ⁇ 75 ⁇ m, space 20 ⁇ m, height: 4 ⁇ m, number of bumps 362
  • Substrate D3 Area 40 ⁇ m ⁇ 40 ⁇ m, space 16 ⁇ m, height: 4 ⁇ m, number of bumps 362
  • Substrate D4 Area 30 ⁇ m ⁇ 30 ⁇ m, space 12 ⁇ m, height: 4 ⁇ m, number of bumps 362
  • Substrate D5 Area 20 ⁇ m ⁇ 20 ⁇ m, space 7 ⁇ m, height: 4 ⁇ m, number of bumps 362
  • Substrate D6 Area 10 ⁇ m ⁇ 10 ⁇ m, space 6 ⁇ m, height: 3 ⁇ m, number of bumps 362 (Ste
  • connection structure was obtained by following the procedure i) to iii) shown below. i) Peel off the single-sided separator (silicone-treated polyethylene terephthalate film, thickness 40 ⁇ m) of the anisotropic conductive film (3.5 ⁇ 19 mm), bring the anisotropic conductive film into contact with the evaluation substrate, and set the temperature at 80 ° C. It was attached at 98 MPa (10 kgf / cm 2). ii) The separator was peeled off, and the bumps on the evaluation chip and the bumps on the evaluation substrate were aligned. iii) The main connection was made by heating and pressurizing from above the chip under the conditions of 180 ° C., 40 gf / bump, and 10 seconds.
  • a total of seven types of connection structures according to (1) to (6) were produced by combining the following "chips / anisotropic conductive films / substrates" of (1) to (6).
  • An anisotropic conductive film / substrate D1 having a thickness of chip C 1/40 ⁇ m
  • Anisotropic conductive film / substrate D2 with a thickness of chip C2 / 30 ⁇ m
  • An anisotropic conductive film / substrate D5 having a thickness of chip C5 / 6 ⁇ m (6)
  • Anisotropic conductive film / substrate D6 with a thickness of chip C6 / 4 ⁇ m
  • connection structure A conduction resistance test and an insulation resistance test were performed on a part of the obtained connection structure as follows.
  • Conduction resistance test-moisture absorption and heat resistance test Regarding the conduction resistance between the chip with gold bump (bump) and the substrate with gold bump (bump), after the initial value of the conduction resistance and the moisture absorption and heat resistance test (leaving for 100, 500, 1000 hours under the conditions of temperature 85 ° C and humidity 85%). The value of was measured for 20 samples, and the average value thereof was calculated. From the obtained average value, the conduction resistance was evaluated according to the following criteria. The results are shown in Table 3.
  • the DC resistance values were measured at the solder joints (4 points) at the chip corners where the impact was greatest, and when the measured values increased 5 times or more from the initial resistance, it was considered that breakage had occurred and evaluation was performed. A total of 80 points were measured at 4 points for each sample. The results are shown in Table 4. When the criteria of A or B below were satisfied after 20 drops, the solder connection reliability was evaluated as good. A: There were no solder connections where the initial resistance increased by 5 times or more. B: The number of solder connection portions increased by 5 times or more from the initial resistance was 1 or more and 5 or less. C: The number of solder connection portions increased by 5 times or more from the initial resistance was 6 or more and 20 or less. D: There were 21 or more solder connection parts that increased by 5 times or more from the initial resistance.
  • the initial value of the insulation resistance and the value after the migration test (standing at temperature 60 ° C., humidity 90%, 20V application for 100, 500, 1000 hours) were measured for 20 samples, and all of them were measured. of 20 samples was calculated the ratio of the sample insulation resistance is 10 9 Omega more.
  • the insulation resistance was evaluated from the obtained ratio according to the following criteria. The results are shown in Table 5. If the following criteria A or B are satisfied after 1000 hours of the migration test, it can be said that the insulation resistance is good.
  • Examples 2 to 6 Except that the solder particles produced by the same method as in Production Examples 2 to 6 were used, and the transfer mold having the same shape as the substrate used for producing the solder particles in Production Examples 2 to 6 was used as the transfer mold. An anisotropic conductive film and a connecting structure were produced by the same method as in Example 1.
  • connection structure used for evaluation is hardened with epoxy casting resin, cut out with a refine saw, and polished with abrasive paper to the connection cross section where the gold bumps of the evaluation chip, solder particles, and gold bumps of the evaluation board can be seen. did. Then, a cryomilling device (IB-19520CCP, manufactured by JEOL) was used to flatten the connection cross section at ⁇ 120 ° C. or lower and 4.0 kV. A platinum layer of about 5 nm was formed on this cross-section processed portion by sputtering, and SEM observation and EDX analysis were performed.
  • IB-19520CCP manufactured by JEOL
  • Example 2 As a result, in (5) of Example 2, immediately after the connection structure was formed, the gold bumps of the evaluation chip and the gold bumps of the evaluation substrate kept a certain distance, and the gold and tin alloy layer was formed. It was confirmed that the connection was made via. In addition, a bismuth portion was present at a position in contact with the alloy layer.
  • the SEM image of the cross section is shown in FIG. 25 (a), and the EDX analysis result of the cross section is shown in FIG. 25 (b).
  • the cross-sectional structure after the evaluation test was almost the same as that before the test, although the gold-tin alloy layer spread on each gold bump side.
  • the insulating resin portion holds the solder particles and the gap between the gold bumps, and the alloying of the tin component of the solder with gold and the rearrangement of bismuth proceed with an appropriate heating time. , It is considered that a stable connection structure can be obtained.
  • Step m1 Preparation of substrate A liquid photosensitive resist (AH series manufactured by Showa Denko Materials Co., Ltd.) was applied to a thickness of 1.5 ⁇ m on a 6-inch silicon wafer by a spin coating method. The photosensitive resist on this silicon wafer is exposed and developed to have an opening diameter of 2.3 ⁇ m ⁇ , a bottom diameter of 2.0 ⁇ m ⁇ , and a depth of 1.5 ⁇ m (the bottom diameter of 2.0 ⁇ m ⁇ is an opening diameter of 2 when the opening is viewed from the top surface. A substrate 7 having a recess (located in the center of 3 ⁇ m ⁇ ) was obtained. These recesses were arranged at positions relative to the electrode arrangement pattern of the evaluation substrate 7. Further, on the surface of the substrate 7, three alignment marks were arranged at the same time as the concave portion was formed. The outline of the substrate 7 is shown in Table 6.
  • solder fine particles were obtained in the same manner as in step a1, and the solder fine particles were arranged in the recesses in the same manner as in step b1 except that the substrate 7 was used. Obtained.
  • Step j2 ⁇ Manufacturing of evaluation chips with solder bumps> (Step j2) Preparation of Evaluation Chip
  • Chip C7 Electrode size: 8 ⁇ m ⁇ 4 ⁇ m, Pitch: X direction 16 ⁇ m, Y direction 8 ⁇ m, Number of bumps: 180,000 Chip C8...
  • Electrode size 24 ⁇ m x 12 ⁇ m, pitch: X direction 48 ⁇ m, Y direction 24 ⁇ m, number of bumps: 15,000 chips C10 ...
  • Electrode size 140 ⁇ m x 70 ⁇ m, pitch: 280 ⁇ m in the X direction, Y direction 140 ⁇ m, number of bumps: 420 (process n1)
  • Solder bump formation A solder bump forming member 7 is placed on the stage of FC3000W (manufactured by Toray Engineering), the evaluation chip C8 is attached to the head and picked up, and the alignment marks of both are used. Then, the electrode alignment of the evaluation chip C8 with the solder particles arranged in the recess of the solder bump forming member 7 was performed, and the evaluation chip C7 was temporarily placed on the solder bump forming member 7.
  • Solder bumps were formed in the same manner as in step n1 except that the solder bump forming films 8 to 12 and the evaluation chips C8 to C12 were used. Further, the solder bumps of 300 electrodes were evaluated, and the transfer rate and the average height were calculated. The results are shown in Table 8.
  • Step k2 Preparation of Evaluation Substrate
  • the gold bumps are arranged at positions facing the gold electrodes of the evaluation chips C7 to C12 described above, and alignment marks are arranged. Further, a lead-out wiring for measuring resistance is also formed in a part of the gold bump.
  • ii) The pre-junction sample 7 obtained in i) was placed on the lower hot plate of a formic acid reflow furnace (batch type vacuum soldering device manufactured by Shinko Seiki Co., Ltd.).
  • a formic acid vacuum reflow furnace (batch type vacuum soldering device manufactured by Shinko Seiki Co., Ltd.).
  • the formic acid vacuum reflow furnace was operated, evacuated, filled with formic acid gas, the temperature of the lower hot plate was raised to 160 ° C., and the mixture was heated for 5 minutes. Then, after discharging formic acid gas by evacuation, nitrogen substitution was performed, the lower hot plate was returned to room temperature, and the inside of the furnace was opened to the atmosphere.
  • Chip C7 / Solder bump forming member 7 / Substrate D7 Chip C8 / Solder bump forming member 8 / Substrate D8 (9) Chip C9 / Solder bump forming member 9 / Substrate D9 (10) Chip C10 / Solder bump forming member 10 / Substrate D10 (11) Chip C11 / Solder bump forming member 11 / Substrate D11 (12) Chip C12 / Solder bump forming member 12 / Substrate D12
  • connection structure A part of the obtained connection structure was subjected to a conduction resistance test and an insulation resistance test in the same manner as described above. The results are shown in Table 9, Table 10 and Table 11.
  • connection structure ⁇ Manufacturing of connection structure> According to the procedures i) to iii) shown below, the evaluation chip with solder bumps produced in step n1 and the evaluation substrate with gold bumps prepared in step k2 were connected via the solder bumps.
  • the evaluation substrate with gold bumps was set on a spin coater, and a liquid flux (NS-334, manufactured by Nippon Superior Co., Ltd.) was coated on the gold bump surface side.
  • the evaluation board with gold bumps obtained in i) is placed on the stage of FC3000W (manufactured by Toray Engineering), the evaluation chip with solder bumps is picked up by the head, and the gold electrodes face each other using the alignment marks of both.
  • the evaluation chips with solder bumps were placed on the evaluation substrate with gold bumps to obtain samples 13 to 18 before joining.
  • the pre-junction sample was placed on the lower hot plate of a formic acid reflow furnace (manufactured by Shinko Seiki Co., Ltd., batch type vacuum soldering device).
  • the formic acid vacuum reflow furnace was operated, evacuated, filled with nitrogen gas, the temperature of the lower hot plate was raised to 160 ° C., and the mixture was heated for 3 minutes. Then, after evacuating, nitrogen substitution was performed, the lower hot plate was returned to room temperature, and the inside of the furnace was opened to the atmosphere.
  • the bonded sample was immersed in an isopropyl alcohol solution to wash away the flux residue.
  • connection structure of the evaluation board was prepared.
  • the combinations of the materials used to prepare the connection structure are as follows.
  • Chip C7 / Solder bump forming member 7 / Substrate D7 (14) Chip C8 / Solder bump forming member 8 / Substrate D8 (15) Chip C9 / Solder bump forming member 9 / Substrate D9 (16) Chip C10 / Solder bump forming member 10 / Substrate D10 (17) Chip C11 / Solder bump forming member 11 / Substrate D11 (18) Chip C12 / Solder bump forming member 12 / Substrate D12 ⁇ Evaluation of connection structure> A part of the obtained connection structure was subjected to a conduction resistance test and an insulation resistance test in the same manner as described above. The results are shown in Table 12, Table 13 and Table 14.
  • solder particles 1 ... solder particles, 2 ... insulating film, 2a ... insulating resin material, 2b ... first resin layer, 2c ... surface of first resin layer, 2d ... second resin layer, 10 ... anisotropic conductivity Film, 30 ... first circuit board, 31 ... first circuit board, 32 ... first electrode, 40 ... second circuit member, 41 ... second circuit board, 42 ... second electrode, 55 ... Insulating resin layer, 60 ... substrate, 62 ... recess, 70 ... joint, 71 ... first region, 72 ... second region, 80 ... intermediate layer, 111 ... solder fine particles.

Abstract

第一の電極を複数有する第一の回路部材と、第二の電極を複数有する第二の回路部材と、前記第一の電極と前記第二の電極とを電気的に接続する接合部を複数有する中間層と、を備え、前記接合部で接続される前記第一の電極及び前記第二の電極の少なくとも一方が金電極であり、複数の前記接合部のうち９０％以上が、前記第一の電極と前記第二の電極とを連結するスズ－金合金を含有する第一の領域と、前記第一の領域に接するビスマスを含する第二の領域と、を含む、接続構造体。

Description

接続構造体及び接続構造体の製造方法
　本発明は、接続構造体及び接続構造体の製造方法に関する。
　電子デバイスに搭載される半導体チップは、回路基板上にワイヤーボンディングやはんだボールを用いたボールグリッドアレイ（ＢＧＡ）接続などで実装された後、絶縁性樹脂材料で封止され、半導体パッケージと呼ばれる機能集積体として利用される。特に、ＢＧＡ接続は、電極間ピッチを狭く出来ることから、半導体パッケージの小型化に寄与してきた（特許文献１）。
　近年は、スマートフォンやタブレットといった小型で高機能な製品向けに、半導体パケージの低背、薄型、高機能化が進行し、接続する電極数の増大と、電極間ピッチの狭小化が進んでいる。半導体パッケージの１次接続側では、１００μｍ以下の狭ピッチ接続を実現するために、銅ピラーの先端にはんだを積層したはんだ付Ｃｕピラー構造が用いられている（特許文献２）。
　また、環境性能の観点から２０００年代からは、スズに銀や銅を添加した鉛フリーはんだが用いられており、２６０℃前後のリフロー温度により実装がなされている。しかしながら、金属やガラスや樹脂などの複合体である半導体パッケージでは、２６０℃リフローによる熱履歴により、各材料の熱膨張率の違いから、実装部（はんだ部分）へ応力が掛かり、破壊が起こる課題があった。また、２６０℃リフローでは、はんだと電極の金属材料との合金化が進行し、破壊を促進する合金層が生成してしまう課題もあった。また、スズ－銀系統のはんだは、２６０℃リフローを必要とするため、より安価な樹脂材料を適用出来ない課題があった。特許文献３では、スズとビスマスを用いた２００℃以下の融点を有する低温はんだを用いた実装方法が開示されている。しかしながら、スズ－ビスマスはんだは、ビスマスが脆いことから外部からの衝撃によりはんだ接合部が破壊しやすい課題があった。特許文献４では、スズ－ビスマスはんだに、微量金属を添加することで、接合部の脆さを改善する試みがなされている。
　一方で、多数の電極を一括で電気的な接続を取る方法として、従来から異方性導電フィルム、異方性導電ペースト等の異方性導電材料が用いられてきた。異方性導電材料は、ディスプレイのコントロールＩＣの実装やタブ線の接続・実装など多数の配線を一括で実装する用途に用いられ、近年では３０μｍを下回る狭ピッチ接続を可能としてきた。これら異方性導電材料に配合される導電性粒子として、従来からはんだ粒子の使用が検討されている。例えば、特許文献５には、熱硬化性成分と、特定の表面処理を施された複数のはんだ粒子と、を含む導電ペーストが記載されている。
特開２００３－７８９４公報 特開２０１５－１０６６５４公報 特開２０１４－８４３９５公報 ＷＯ２０１４０６１０８５公報 特開２０１６－７６４９４号公報
　このように、近年、回路部材の多様化に対応した接続温度の低温化、回路部材の高精細化に伴って接続箇所の微小化、薄型化が進行しており、接続構造体の導通信頼性の確保が難しくなっている。
　本発明は上記事情に鑑みてなされたものであり、導通信頼性及び絶縁信頼性に優れた接続構造体及びその製造方法を提供することを目的とする。
　本発明の一側面は、第一の電極を複数有する第一の回路部材と、第二の電極を複数有する第二の回路部材と、第一の電極と第二の電極とを電気的に接続する接合部を複数有する中間層と、を備え、接合部で接続される前記第一の電極及び前記第二の電極の少なくとも一方が金電極であり、複数の接合部のうち９０％以上が、第一の電極と第二の電極とを連結するスズ－金合金を含有する第一の領域と、前記第一の領域に接する、ビスマスを含有する第二の領域と、を含む、接続構造体に関する。
　一態様において、中間層は、第一の回路部材と第二の回路部材との間を封止する絶縁性樹脂層を更に有していてよい。
　本発明の他の一側面は、第一の電極を複数有する第一の回路部材と、第二の電極を複数有する第二の回路部材と、異方性導電フィルムと、を準備する準備工程と、第一の回路部材、第二の回路部材及び異方性導電フィルムを、第一の回路部材の第一の電極を有する面と第二の回路部材の第二の電極を有する面とが異方性導電フィルムを介して対向するように配置して、第一の回路部材、異方性導電フィルム及び第二の回路部材がこの順で積層した積層体を得る配置工程と、積層体を厚み方向に押圧した状態で加熱することにより、第一の電極と前記第二の電極とを接合部を介して電気的に接続する接続工程と、を含む、接続構造体の製造方法に関する。この製造方法において、第一の電極及び第二の電極のうち少なくとも一方は金電極であり、異方性導電フィルムは、絶縁性樹脂組成物から構成される絶縁性フィルムと、前記絶縁性フィルム中に配置されている複数のはんだ粒子とを含む。また、はんだ粒子は、スズ－ビスマス合金を含有し、はんだ粒子の平均粒子径は１μｍ～３０μｍであり、はんだ粒子のＣ．Ｖ．値は２０％以下である。また、異方性導電フィルムの縦断面において、はんだ粒子は、隣接するはんだ粒子と離隔した状態で横方向に並ぶように配置されている。また、接続工程で形成される複数の接合部のうち９０％以上は、第一の電極と第二の電極とを連結するスズ－金合金を含有する第一の領域と、前記第一の領域に接する、ビスマスを含有する第二の領域と、を含む。
　一態様において、はんだ粒子は、複数の凹部を有する基体と、スズ－ビスマス合金を含有するはんだ微粒子と、を準備するはんだ微粒子準備工程と、はんだ微粒子の少なくとも一部を凹部に収容する収容工程と、凹部に収容されたはんだ微粒子を融合させて、凹部の内部にはんだ粒子を形成する融合工程と、を含む方法により製造されたはんだ粒子であってよい。
　一態様において、はんだ微粒子準備工程で準備されるはんだ微粒子のＣ．Ｖ．値は２０を超えていてよい。
　一態様において、異方性導電フィルムは、はんだ粒子が収容された凹部を複数有する基体の、凹部の開口側に絶縁性樹脂組成物を接触させて、はんだ粒子が転写された第一の樹脂層を得る転写工程と、はんだ粒子が転写された側の第一の樹脂層の表面上に、絶縁性樹脂組成物から構成される第二の樹脂層を形成することにより、異方性導電フィルムを得る積層工程と、を含む方法により製造された異方性導電フィルムであってよい。
　本発明によれば、導通信頼性及び絶縁信頼性に優れた接続構造体及びその製造方法が提供される。
図１は異方性導電フィルムの第一実施形態を模式的に示す断面図である。 図２（ａ）は図１に示すＩＩａ－ＩＩａ線における模式的な横断面図であり、図２（ｂ）は第一実施形態の変形例を模式的に示す横断面図である。 図３（ａ）は基体の一例を模式的に示す平面図であり、図３（ｂ）は図３（ａ）のＩｂ－Ｉｂ線における断面図である。 図４（ａ）～（ｈ）は基体の凹部の断面形状の例を模式的に示す断面図である。 図５は基体の凹部にはんだ微粒子が収容された状態を模式的に示す断面図である。 図６は基体の凹部にはんだ粒子が形成された状態を模式的に示す断面図である。 図７（ａ）は図６における凹部の開口部と反対側からはんだ粒子を見た図であり、図７（ｂ）ははんだ粒子の投影像に外接する四角形を二対の平行線により作成した場合における、対向する辺間の距離Ｘ及びＹ（但しＹ≦Ｘ）を示す図である。 図８（ａ）～（ｃ）は第一実施形態に係る異方性導電フィルムの製造過程の一例を模式的に示す断面図である。 図９（ａ）～（ｃ）は第二実施形態に係る異方性導電フィルムの製造過程の一例を模式的に示す断面図である。 図１０（ａ）及び図１０（ｂ）は異方性導電フィルムの製造過程の他の一例を模式的に示す断面図である。 図１１は接続構造体の一部を拡大して示す図であって、第一の電極と第二の電極とが接合部によって電気的に接続された状態を模式的に示す断面図である。 図１２（ａ）及び図１２（ｂ）は、本発明に係る接続構造体の製造過程の第一の例を模式的に示す断面図である。 図１３（ａ）及び図１３（ｂ）は、本発明に係る接続構造体の製造過程の第二の例を模式的に示す断面図である。 図１４（ａ）及び図１４（ｂ）は、本発明に係る接続構造体の製造過程の第三の例を模式的に示す断面図である。 図１５（ａ）、図１５（ｂ）、図１５（ｃ）及び図１５（ｄ）は、それぞれ、第一の領域及び第二の領域を含む接合部の一例を模式的に示す断面図である。 図１６（ａ）、図１６（ｂ）、図１６（ｃ）及び図１６（ｄ）は、それぞれ、第一の領域及び第二の領域を含む接合部の一例を模式的に示す断面図である。 図１７（ａ）、図１７（ｂ）、図１７（ｃ）、図１７（ｄ）、図１７（ｅ）及び図１７（ｆ）は、それぞれ、第一の領域及び第二の領域を含む接合部の一例を模式的に示す平面図である。 図１８（ａ）、図１８（ｂ）及び図１８（ｃ）は、それぞれ、第一の領域及び第二の領域を含まない接合部の一例を模式的に示す断面図である。 図１９（ａ）、図１９（ｂ）、図１９（ｃ）及び図１９（ｄ）は、それぞれ、第一の領域及び第二の領域を含まない接合部の一例を模式的に示す断面図である。 図２０は、押圧及び加熱がなされる前の異方性導電フィルムのはんだ粒子の位置と、バンプ（電極）の位置との関係の第一の例を模式的に示す平面図である。 図２１は、押圧及び加熱がなされる前の異方性導電フィルムのはんだ粒子の位置と、バンプ（電極）の位置との関係の第二の例を模式的に示す平面図である。 図２２は、押圧及び加熱がなされる前の異方性導電フィルムのはんだ粒子の位置と、バンプ（電極）の位置との関係の第三の例を模式的に示す平面図である。 図２３は、押圧及び加熱がなされる前の異方性導電フィルムのはんだ粒子の位置と、バンプ（電極）との関係の第四の例を模式的に示す平面図である。 図２４は基体の凹部の断面形状の他の例を模式的に示す断面図である。 図２５（ａ）は、押圧及び加熱がなされた後の接続構造体の断面像であり、図２５（ｂ）は、当該断面像のＥＤＸ分析結果を示す図である。
　以下、本発明の実施形態について説明する。本発明は以下の実施形態に限定されるものではない。なお、以下で例示する材料は、特に断らない限り、一種単独で用いてもよく、二種以上を組み合わせて用いてもよい。組成物中の各成分の含有量は、組成物中に各成分に該当する物質が複数存在する場合、特に断らない限り、組成物中に存在する当該複数の物質の合計量を意味する。「～」を用いて示された数値範囲は、「～」の前後に記載される数値をそれぞれ最小値及び最大値として含む範囲を示す。本明細書中に段階的に記載されている数値範囲において、ある段階の数値範囲の上限値又は下限値は、他の段階の数値範囲の上限値又は下限値に置き換えてもよい。本明細書中に記載されている数値範囲において、その数値範囲の上限値又は下限値は、実施例に示されている値に置き換えてもよい。
　本実施形態に係る接続構造体は、第一の電極を複数有する第一の回路部材と、第二の電極を複数有する第二の回路部材と、第一の電極と前記第二の電極とを電気的に接続する接合部を複数有する中間層と、を備える。また、接合部で接続される第一の電極及び第二の電極の少なくとも一方が金電極であり、複数の接合部のうち９０％以上は、第一の電極と第二の電極とを連結するスズ－金合金を含有する第一の領域と、前記第一の領域に接する、ビスマスを含有する第二の領域と、を含むものとなっている。
　本実施形態に係る接続構造体は、第一の電極と第二の電極との間を連結する第一の領域と、前記第一の領域に接する第二の領域とを含む接合部を備えている。当該接合部は、第一の領域がスズ－金合金を含んで一体化され、更に第二の領域が補強部として機能するため、クラックが生じにくい。また、当該接合部は、第一の領域が融点の高いスズ－金合金を含むため、接合部の再溶融が十分に抑制されている。本実施形態に係る接続構造体は、接合部の９０％以上が、このような第一の領域及び第二の領域を含むものであることから、接合部へのクラックの発生及び接合部の溶融が十分に抑制され、導通信頼性に優れる。また、本実施形態に係る接続構造体は、接合部の溶融が十分に抑制されていることから、二次実装等への適用が容易であり、また、高温環境下での使用にも適する。
　中間層は、第一の回路部材と第二の回路部材との間を封止する絶縁性樹脂層を更に有していてもよい。絶縁性樹脂層は、後述の異方性導電フィルムの絶縁性フィルムにより形成されたものであってよい。
　本実施形態において、接続構造体中の接合部のうち、第一の領域及び第二の領域を含む上記接合部の割合は、８０％以上であり、好ましくは８５％以上であり、より好ましくは９０％以上であり、１００％であってもよい。
　接続構造体の接合部の大半を第一の領域及び第二の領域を含むものとするためには、各接合部の形成に供されるはんだ粒子が均一であることが望ましい。また、接続構造体の接合部の大半を第一の領域及び第二の領域を含むものとするためには、はんだ粒子の周囲に絶縁性樹脂組成物が配置されており、はんだ粒子の溶融時に、溶融したはんだが第一の電極及び第二の電極の間に十分な時間保持されることが望ましい。これらの観点から、本実施形態に係る接続構造体は、以下に示す異方性導電フィルムを用いて第一の回路部材と第二の回路部材とを接合したものであることが好ましい。
　以下、図面を参照しつつ、接続構造体の製造に有用な異方性導電フィルム及びその製造方法、並びに、接続構造体及びその製造方法の好適な形態について説明する。
＜異方性導電フィルム＞
　図１に示す第一実施形態に係る異方性導電フィルム１０は、絶縁性樹脂組成物からなる絶縁性フィルム２と、絶縁性フィルム２中に配置されている複数のはんだ粒子１とによって構成されている。異方性導電フィルム１０の所定の縦断面において、一個のはんだ粒子１は隣接する一個のはんだ粒子１と離隔した状態で横方向（図１における左右方向）に並ぶように配置されている。換言すると、異方性導電フィルム１０は、その縦断面において、複数のはんだ粒子１が横方向に列をなしている中央領域１０ａと、はんだ粒子１が実質的に存在しない表面側領域１０ｂ，１０ｃとによって構成されている。
　図２（ａ）は図１に示すＩＩａ－ＩＩａ線における模式的な横断面図である。図２に示されるとおり、異方性導電フィルム１０の横断面において、はんだ粒子１が規則的に配置されている。図２（ａ）に示されたとおり、はんだ粒子１は異方性導電フィルム１０の全体の領域に対して規則的且つほぼ均等の間隔で配置されていてもよく、図２（ｂ）に示された変形例のように、異方性導電フィルム１０の横断面において、複数のはんだ粒子１が規則的に配置されている領域１０ｄと、はんだ粒子１が実質的に存在しない領域１０ｅとが規則的に形成されるように、はんだ粒子１を配置してもよい。例えば、接続すべき電極の形状、サイズ及びパターン等に応じ、はんだ粒子１の位置及び個数等を設定すればよい。
（はんだ粒子）
　はんだ粒子１の平均粒子径は、例えば３０μｍ以下であり、好ましくは２５μｍ以下、より好ましくは２０μｍ以下、さらに好ましくは１５μｍ以下である。また、はんだ粒子１の平均粒子径は、例えば１μｍ以上であり、好ましくは２μｍ以上、より好ましくは３μｍ以上、さらに好ましくは５μｍ以上である。
　はんだ粒子１の平均粒子径は、サイズに合わせた各種方法を用いて測定することができる。例えば、動的光散乱法、レーザ回折法、遠心沈降法、電気的検知帯法、共振式質量測定法等の方法を利用できる。さらに、光学顕微鏡、電子顕微鏡等によって得られる画像から、粒子サイズを測定する方法を利用できる。具体的な装置としては、フロー式粒子像分析装置、マイクロトラック、コールターカウンター等が挙げられる。
　はんだ粒子１のＣ．Ｖ．値は、より優れた導電信頼性及び絶縁信頼性を実現できる観点から、好ましくは２０％以下、より好ましくは１０％以下、更に好ましくは７％以下である。また、はんだ粒子１のＣ．Ｖ．値の下限は特に限定されない。例えば、はんだ粒子１のＣ．Ｖ．値は１％以上であってよく、２％以上であってもよい。
　はんだ粒子１のＣ．Ｖ．値は、前述の方法によって測定された粒子径の標準偏差を平均粒子径で割った値に１００を掛けることで算出される。
　図７（ａ）に示すように、はんだ粒子１は、表面の一部に平面部１１が形成されていてよく、このとき当該平面部１１以外の表面は、球冠状であることが好ましい。すなわち、はんだ粒子１は、平面部１１と、球冠状の曲面部と、を有するものであってよい。はんだ粒子１の直径Ｂに対する平面部１１の直径Ａの比（Ａ／Ｂ）は、例えば０．０１超１．０未満（０．０１＜Ａ／Ｂ＜１．０）であってよく、０．１～０．９であってもよい。はんだ粒子１が平面部１１を有することで、接続時の加圧による位置ずれが生じ難くなり、より優れた導電信頼性及び絶縁信頼性を実現できる。
　はんだ粒子１の投影像に外接する四角形を二対の平行線により作成した場合において、対向する辺間の距離をＸ及びＹ（但しＹ＜Ｘ）としたときに、Ｘに対するＹの比（Ｙ／Ｘ）は、０．８超１．０未満（０．８＜Ｙ／Ｘ＜１．０）であってよく、０．９以上１．０未満であってもよい。このようなはんだ粒子１はより真球に近い粒子ということができる。後述の製造方法によれば、このようなはんだ粒子１を容易に得ることができる。はんだ粒子１が真球に近いことで、例えば、対向する複数の電極間をはんだ粒子１を介して電気的に接続させるときに、はんだ粒子１と電極間接触にムラが生じ難く、安定した接続が得られる傾向がある。また、はんだ粒子１を樹脂組成物中に分散した導電性フィルムや樹脂を作製したとき、高い分散性が得られ、製造時の分散安定性が得られる傾向がある。さらに、はんだ粒子１を樹脂組成物に分散したフィルムやペーストを、電極間の接続に用いる場合、樹脂中ではんだ粒子１が回転しても、はんだ粒子１が球体形状であれば、投影像で見たとき、はんだ粒子１同士の投影面積が近い。そのため、電極同士を接続する際にばらつきの少ない、安定した電気接続を得易い傾向がある。
　図７（ｂ）は、はんだ粒子の投影像に外接する四角形を二対の平行線により作成した場合における、対向する辺間の距離Ｘ及びＹ（但しＹ＜Ｘ）を示す図である。例えば、任意の粒子を走査型電子顕微鏡により観察して投影像を得る。得られた投影像に対し二対の平行線を描画し、一対の平行線は平行線の距離が最小となる位置に、もう一対の平行線は平行線の距離が最大となる位置に配し、その粒子のＹ／Ｘを求める。この作業を３００個のはんだ粒子に対して行って平均値を算出し、はんだ粒子のＹ／Ｘとする。
　はんだ粒子１は、スズ－ビスマス合金（Ｓｎ－Ｂｉ合金）を含む。スズ－ビスマス合金の具体例としては、下記の例が挙げられる。
・Ｓｎ－Ｂｉ（Ｓｎ４３質量％、Ｂｉ５７質量％ 融点１３８℃）
・Ｓｎ－Ｂｉ（Ｓｎ７２質量％、Ｂｉ２８質量％ 融点１３８℃）
・Ｓｎ－Ｂｉ－Ａｇ（Ｓｎ４２質量％、Ｂｉ５７質量％、Ａｇ１質量％　融点１３９℃）
　はんだ粒子１は、Ｓｎ及びＢｉ以外の他の金属を更に含んでいてもよい。他の金属としては、例えばＡｇ、Ｃｕ、Ｎｉ、Ｂｉ、Ｚｎ、Ｐｄ、Ｐｂ、Ａｕ、Ｐ、Ｂ、Ｇａ、Ａｓ、Ｓｂ、Ｔｅ、Ｇｅ、Ｓｉ、Ａｌ等が挙げられる。はんだ粒子１の他の金属の含有率は、例えば１０質量％以下であり、好ましくは５質量％以下、より好ましくは３質量％以下である。
（絶縁性フィルム）
絶縁性フィルム２を構成する絶縁性樹脂組成物は、熱硬化性化合物を含んでもよい。熱硬化性化合物としては、オキセタン化合物、エポキシ化合物、エピスルフィド化合物、（メタ）アクリル化合物、フェノール化合物、アミノ化合物、不飽和ポリエステル化合物、ポリウレタン化合物、シリコーン化合物及びポリイミド化合物等が挙げられる。なかでも、絶縁樹脂の硬化性及び粘度をより一層良好にし、接続信頼性をより一層高める観点から、エポキシ化合物が好ましい。
　絶縁性樹脂組成物は熱硬化剤をさらに含んでもよい。熱硬化剤としては、イミダゾール硬化剤、アミン硬化剤、フェノール硬化剤、ポリチオール硬化剤、酸無水物、熱カチオン開始剤及び熱ラジカル発生剤等が挙げられる。これらは一種を単独で用いてもよく、二種以上を併用してもよい。これらのうち、低温で速やかに硬化可能である点で、イミダゾール硬化剤、ポリチオール硬化剤又はアミン硬化剤が好ましい。また、熱硬化性化合物と熱硬化剤とを混合したときに保存安定性が高くなるので、潜在性の硬化剤が好ましい。潜在性の硬化剤は、潜在性イミダゾール硬化剤、潜在性ポリチオール硬化剤又は潜在性アミン硬化剤であることが好ましい。なお、上記熱硬化剤は、ポリウレタン樹脂又はポリエステル樹脂等の高分子物質で被覆されていてもよい。
　上記イミダゾール硬化剤としては、特に限定されず、２－メチルイミダゾール、２－エチル－４－メチルイミダゾール、１－シアノエチル－２－フェニルイミダゾール、１－シアノエチル－２－フェニルイミダゾリウムトリメリテート、２，４－ジアミノ－６－［２’－メチルイミダゾリル－（１’）］－エチル－ｓ－トリアジン及び２，４－ジアミノ－６－［２’－メチルイミダゾリル－（１’）］－エチル－ｓ－トリアジンイソシアヌル酸付加物等が挙げられる。
　上記ポリチオール硬化剤としては、特に限定されず、トリメチロールプロパントリス－３－メルカプトプロピオネート、ペンタエリスリトールテトラキス－３－メルカプトプロピオネート及びジペンタエリスリトールヘキサ－３－メルカプトプロピオネート等が挙げられる。ポリチオール硬化剤の溶解度パラメーターは、好ましくは９．５以上、好ましくは１２以下である。上記溶解度パラメーターは、Ｆｅｄｏｒｓ法にて計算される。例えば、トリメチロールプロパントリス－３－メルカプトプロピオネートの溶解度パラメーターは９．６、ジペンタエリスリトールヘキサ－３－メルカプトプロピオネートの溶解度パラメーターは１１．４である。
　上記アミン硬化剤としては、特に限定されず、ヘキサメチレンジアミン、オクタメチレンジアミン、デカメチレンジアミン、３，９－ビス（３－アミノプロピル）－２，４，８，１０－テトラスピロ［５．５］ウンデカン、ビス（４－アミノシクロヘキシル）メタン、メタフェニレンジアミン及びジアミノジフェニルスルホン等が挙げられる。
　上記熱カチオン硬化剤としては、ヨードニウム系カチオン硬化剤、オキソニウム系カチオン硬化剤及びスルホニウム系カチオン硬化剤等が挙げられる。上記ヨードニウム系カチオン硬化剤としては、ビス（４－ｔｅｒｔ－ブチルフェニル）ヨードニウムヘキサフルオロホスファート等が挙げられる。上記オキソニウム系カチオン硬化剤としては、トリメチルオキソニウムテトラフルオロボラート等が挙げられる。上記スルホニウム系カチオン硬化剤としては、トリ－ｐ－トリルスルホニウムヘキサフルオロホスファート等が挙げられる。
　上記熱ラジカル発生剤としては、特に限定されず、アゾ化合物及び有機過酸化物等が挙げられる。上記アゾ化合物としては、アゾビスイゾブチロニトリル（ＡＩＢＮ）等が挙げられる。上記有機過酸化物としては、ジ－ｔｅｒｔ－ブチルペルオキシド及びメチルエチルケトンペルオキシド等が挙げられる。
（フラックス）
　異方性導電フィルム１０は、フラックスを含むことが好ましい。具体的には、異方性導電フィルム１０を構成する絶縁性樹脂組成物がフラックスを含有するとともに、はんだ粒子１の表面をフラックスが覆っていることが好ましい。フラックスは、はんだ表面の酸化物を溶融して、はんだ粒子同士の融着性及び電極へのはんだの濡れ性を向上させる。
　フラックスとしては、はんだ接合等に一般的に用いられているものを使用できる。具体例としては、塩化亜鉛、塩化亜鉛と無機ハロゲン化物との混合物、塩化亜鉛と無機酸との混合物、溶融塩、リン酸、リン酸の誘導体、有機ハロゲン化物、ヒドラジン、有機酸及び松脂等が挙げられる。これらは一種を単独で用いてもよく、二種以上を併用してもよい。
　溶融塩としては、塩化アンモニウム等が挙げられる。有機酸としては、乳酸、クエン酸、ステアリン酸、グルタミン酸及びグルタル酸等が挙げられる。松脂としては、活性化松脂及び非活性化松脂等が挙げられる。松脂はアビエチン酸を主成分とするロジン類である。フラックスとして、カルボキシル基を二個以上有する有機酸又は松脂を使用することにより、電極間の導通信頼性がより一層高くなるという効果が奏される。
　フラックスの融点は、好ましくは５０℃以上であり、より好ましくは７０℃以上であり、さらに好ましくは８０℃以上である。フラックスの融点は、好ましくは２００℃以下であり、より好ましくは１６０℃以下であり、さらに好ましくは１５０℃以下であり、特に好ましくは１４０℃以下である。上記フラックスの融点が上記下限以上及び上記上限以下であると、フラックス効果がより一層効果的に発揮され、はんだ粒子が電極上により一層効率的に配置される。フラックスの融点の範囲は、８０～１９０℃であることが好ましく、８０～１４０℃以下であることがより好ましい。
　融点が８０～１９０℃の範囲にあるフラックスとしては、コハク酸（融点１８６℃）、グルタル酸（融点９６℃）、アジピン酸（融点１５２℃）、ピメリン酸（融点１０４℃）、スベリン酸（融点１４２℃）等のジカルボン酸、安息香酸（融点１２２℃）、リンゴ酸（融点１３０℃）等が挙げられる。
＜異方性導電フィルムの製造方法＞
　異方性導電フィルム１０の製造方法は、複数の凹部を有する基体とはんだ微粒子とを準備するはんだ微粒子準備工程と、はんだ微粒子の少なくとも一部を凹部に収容する収容工程と、凹部に収容されたはんだ微粒子を融合させて、凹部の内部にはんだ粒子を形成する融合工程と、はんだ粒子が凹部に収容されている基体の、凹部の開口側に絶縁性樹脂組成物を接触させて、はんだ粒子が転写された第一の樹脂層を得る転写工程と、はんだ粒子が転写された側の第一の樹脂層の表面上に、絶縁性樹脂組成物から構成される第二の樹脂層を形成することにより、異方性導電フィルムを得る積層工程と、を含む。
　図３～８を参照しながら、第一実施形態に係る異方性導電フィルム１０の製造方法について説明する。
　まず、はんだ微粒子と、はんだ微粒子を収容するための基体６０を準備する。図３（ａ）は基体６０の一例を模式的に示す平面図であり、図３（ｂ）は図３（ａ）に示すＩｂ－Ｉｂ線における断面図である。図３（ａ）に示す基体６０は、複数の凹部６２を有している。複数の凹部６２は所定のパターンで規則的に配置されていてよい。この場合、後述の転写工程に基体６０をそのまま用いることができる。
　基体６０の凹部６２は、凹部６２の底部６２ａ側から基体６０の表面６０ａ側に向けて開口面積が拡大するテーパ状に形成されていることが好ましい。すなわち、図３（ａ）及び図３（ｂ）に示すように、凹部６２の底部６２ａの幅（図３（ａ）及び図３（ｂ）における幅ａ）は、凹部６２の表面６０ａにおける開口の幅（図３（ａ）及び図３（ｂ）における幅ｂ）よりも狭いことが好ましい。そして、凹部６２のサイズ（幅ａ、幅ｂ、容積、テーパ角度及び深さ等）は、目的とするはんだ粒子のサイズに応じて設定すればよい。
　なお、凹部６２の形状は図３（ａ）及び図３（ｂ）に示す形状以外の形状であってもよい。例えば、凹部６２の表面６０ａにおける開口の形状は、図３（ａ）に示すような円形以外に、楕円形、三角形、四角形、多角形等であってよい。
　また、表面６０ａに対して垂直な断面における凹部６２の形状は、例えば、図４に示すような形状であってよい。図４（ａ）～（ｈ）は、基体が有する凹部の断面形状の例を模式的に示す断面図である。図４（ａ）～（ｈ）に示すいずれの断面形状も、凹部６２の表面６０ａにおける開口の幅（幅ｂ）が、断面形状における最大幅となっている。これにより、凹部６２内に形成されたはんだ粒子が取り出しやすくなり、作業性が向上する。また、表面６０ａに対して垂直な断面における凹部６２の形状は、例えば、図２４に示すように、図４（ａ）～（ｈ）に示す断面形状における壁面を傾斜させた形状であってもよい。図２４は、図４（ｂ）に示す断面形状の壁面を傾斜させた形状ということができる。
　基体６０を構成する材料としては、例えば、シリコン、各種セラミックス、ガラス、ステンレススチール等の金属等の無機材料、並びに、各種樹脂等の有機材料を使用することができる。これらのうち、基体６０は、はんだ微粒子の溶融温度で変質しない耐熱性を有する材質からなることが好ましい。また、基体６０の凹部６２は、フォトリソグラフ法、インプリント法、エッチング法等の公知の方法によって形成することができる。
　はんだ微粒子準備工程で準備されるはんだ微粒子は、凹部６２の表面６０ａにおける開口の幅（幅ｂ）より小さい粒子径の微粒子を含むものであればよく、幅ｂより小さい粒子径の微粒子をより多く含むことが好ましい。例えば、はんだ微粒子は、粒度分布のＤ１０粒子径が幅ｂより小さいことが好ましく、粒度分布のＤ３０粒子径が幅ｂより小さいことがより好ましく、粒度分布のＤ５０粒子径が幅ｂより小さいことが更に好ましい。
　はんだ微粒子の粒度分布は、サイズに合わせた各種方法を用いて測定することができる。例えば、動的光散乱法、レーザ回折法、遠心沈降法、電気的検知帯法、共振式質量測定法等の方法を利用できる。さらに、光学顕微鏡、電子顕微鏡等によって得られる画像から、粒子サイズを測定する方法を利用できる。具体的な装置としては、フロー式粒子像分析装置、マイクロトラック、コールターカウンター等が挙げられる。
　準備工程で準備されるはんだ微粒子のＣ．Ｖ．値は特に限定されないが、大小の微粒子の組み合わせによる凹部６２への充填性が向上する観点から、Ｃ．Ｖ．値は高いことが好ましい。例えば、はんだ微粒子のＣ．Ｖ．値は、２０％を超えていてよく、好ましくは２５％以上、より好ましくは３０％以上である。
　はんだ微粒子のＣ．Ｖ．値は、前述の方法によって測定された粒子径の標準偏差を平均粒子径（Ｄ５０粒子径）で割った値に１００を掛けることで算出される。
　はんだ微粒子は、スズ－ビスマス合金（Ｓｎ－Ｂｉ合金）を含む。スズ－ビスマス合金の具体例としては、下記の例が挙げられる。
・Ｓｎ－Ｂｉ（Ｓｎ４３質量％、Ｂｉ５７質量％ 融点１３８℃）
・Ｓｎ－Ｂｉ（Ｓｎ７２質量％、Ｂｉ２８質量％ 融点１３８℃）
・Ｓｎ－Ｂｉ－Ａｇ（Ｓｎ４２質量％、Ｂｉ５７質量％、Ａｇ１質量％　融点１３９℃）
　はんだ微粒子は、Ｓｎ及びＢｉ以外の他の金属を更に含んでいてもよい。他の金属としては、例えばＡｇ、Ｃｕ、Ｎｉ、Ｂｉ、Ｚｎ、Ｐｄ、Ｐｂ、Ａｕ、Ｐ、Ｂ、Ｇａ、Ａｓ、Ｓｂ、Ｔｅ、Ｇｅ、Ｓｉ、Ａｌ等が挙げられる。はんだ微粒子の他の金属の含有率は、例えば１０質量％以下であり、好ましくは５質量％以下、より好ましくは３質量％以下である。
　収容工程では、基体６０の凹部６２のそれぞれに、はんだ微粒子準備工程で準備したはんだ微粒子を収容する。収容工程では、はんだ微粒子準備工程で準備したはんだ微粒子の全部を凹部６２に収容する工程であってよく、はんだ微粒子準備工程で準備したはんだ微粒子の一部（例えば、はんだ微粒子のうち、凹部６２の開口の幅ｂより小さいもの）を凹部６２に収容する工程であってよい。
　図５は、基体６０の凹部６２にはんだ微粒子１１１が収容された状態を模式的に示す断面図である。図５に示すように、複数の凹部６２のそれぞれに、複数のはんだ微粒子１１１が収容される。
　凹部６２に収容されたはんだ微粒子１１１の量は、例えば、凹部６２の容積に対して２０％以上であることが好ましく、３０％以上であることがより好ましく、５０％以上であることが更に好ましく、６０％以上であることがもっとも好ましい。これにより、収容量のばらつきが抑えられ、粒度分布のより小さいはんだ粒子が得られやすくなる。
　はんだ微粒子を凹部６２に収容する方法は特に限定されない。収容方法は、乾式、湿式のいずれであってもよい。例えば、準備工程で準備したはんだ微粒子を基体６０上に配置し、スキージを用いて基体６０の表面６０ａを擦ることで、余分なはんだ微粒子を除去しつつ、凹部６２内に十分なはんだ微粒子を収容することができる。凹部６２の開口の幅ｂが凹部６２の深さより大きい場合、凹部６２の開口からはんだ微粒子が飛び出す場合がある。スキージを用いると、凹部６２の開口から飛び出ているはんだ微粒子は除去される。余分なはんだ微粒子を除去する方法として、圧縮空気を吹き付ける、不織布又は繊維の束で基体６０の表面６０ａを擦る、等の方法も挙げられる。これらの方法は、スキージと比べて物理的な力が弱いため、変形しやすいはんだ微粒子を扱う上で好ましい。また、これらの方法では、凹部６２の開口から飛び出ているはんだ微粒子を凹部内に残すこともできる。
　融合工程は、凹部６２に収容されたはんだ微粒子１１１を融合させて、凹部６２の内部にはんだ粒子１を形成する工程である。図６は、基体６０の凹部６２にはんだ粒子１が形成された状態を模式的に示す断面図である。凹部６２に収容されたはんだ微粒子１１１は、溶融することで合一化し、表面張力によって球状化する。このとき、凹部６２の底部６２ａとの接触部では、溶融したはんだが底部６２ａに追従して平面部１１を形成する。これにより、形成されるはんだ粒子１は、表面の一部に平面部１１を有する形状となる。
　図７（ａ）は、図６における凹部６２の開口部と反対側からはんだ粒子１を見た図である。はんだ粒子１は、直径Ｂを有する球の表面の一部に直径Ａの平面部１１が形成された形状を有している。なお、図６及び図７（ａ）に示すはんだ粒子１は、凹部６２の底部６２ａが平面であるため平面部１１を有するが、凹部６２の底部６２ａが平面以外の形状である場合は、底部６２ａの形状に対応した異なる形状の面を有するものとなる。
　凹部６２に収容されたはんだ微粒子１１１を溶融させる方法としては、はんだ微粒子１１１をはんだの融点以上に加熱する方法が挙げられる。はんだ微粒子１１１は、酸化被膜の影響で融点以上の温度で加熱しても溶融しない場合や、濡れ拡がらない場合や、合一化しない場合がある。このため、はんだ微粒子１１１を還元雰囲気下に晒し、はんだ微粒子１１１の表面酸化皮膜を除去した後に、はんだ微粒子１１１の融点以上の温度に加熱することで、はんだ微粒子１１１を溶融させ、濡れ拡がり、合一化させることができる。また、はんだ微粒子１１１の溶融は、還元雰囲気下で行うことが好ましい。はんだ微粒子１１１をはんだ微粒子１１１の融点以上に加熱し、かつ還元雰囲気とすることで、はんだ微粒子１１１の表面の酸化被膜が還元され、はんだ微粒子１１１の溶融、濡れ拡がり、合一化が効率的に進行しやすくなる。
　還元雰囲気にする方法は、上述の効果が得られる方法であれば特に限定されず、例えば水素ガス、水素ラジカル、ギ酸ガス等を用いる方法がある。例えば、水素還元炉、水素ラジカル還元炉、ギ酸還元炉、又はこれらのコンベアー炉若しくは連続炉を用いることで、還元雰囲気下にはんだ微粒子１１１を溶融させることができる。これらの装置は、炉内に、加熱装置、不活性ガス（窒素、アルゴン等）を充填するチャンバー、チャンバー内を真空にする機構等を備えていてよく、これにより還元ガスの制御がより容易となる。また、チャンバー内を真空にできると、はんだ微粒子１１１の溶融及び合一化の後に、減圧によってボイドの除去を行うことができ、接続安定性に一層優れるはんだ粒子１を得ることができる。
　はんだ微粒子１１１の還元、溶解条件、温度、炉内雰囲気調整などのプロファイルは、はんだ微粒子１１１の融点、粒度、凹部サイズ、基体６０の材質などを勘案して適宜設定されてよい。例えば、はんだ微粒子１１１が凹部に充填された基体６０を、炉内に挿入し、真空引きを行った後に、還元ガスを導入して、炉内を還元ガスで満たし、はんだ微粒子１１１の表面酸化被膜を除去した後、真空引きにて還元ガスを除去し、その後、はんだ微粒子１１１の融点以上に加熱して、はんだ微粒子を溶解及び合一化させて、凹部６２内にはんだ粒子を形成した後、窒素ガスを充填してから炉内温度を室温に戻し、はんだ粒子１を得ることができる。また、例えば、はんだ微粒子１１１が凹部に充填された基体６０を、炉内に挿入し、真空引きを行った後に、還元ガスを導入して、炉内を還元ガスで満たし、炉内加熱ヒーターによりはんだ微粒子１１１を加熱して、はんだ微粒子１１１の表面酸化被膜を除去した後、真空引きにて還元ガスを除去し、その後、はんだ微粒子１１１の融点以上に加熱して、はんだ微粒子を溶解及び合一化させて、凹部６２内にはんだ粒子を形成した後、窒素ガスを充填してから炉内温度を室温に戻し、はんだ粒子１を得ることができる。還元雰囲気下で、はんだ微粒子を加熱することで、還元力が増し、はんだ微粒子の表面酸化皮膜の除去が容易になる利点がある。
　さらに、例えば、はんだ微粒子１１１が凹部に充填された基体６０を、炉内に挿入し、真空引きを行った後に、還元ガスを導入して、炉内を還元ガスで満たし、炉内加熱ヒーターにより基体６０をはんだ微粒子１１１の融点以上に加熱して、はんだ微粒子１１１の表面酸化被膜を還元により除去すると同時にはんだ微粒子を溶解及び合一化させて、凹部６２内にはんだ粒子を形成し、真空引きにて還元ガスを除去し、さらにはんだ粒子内のボイドを減らした後、窒素ガスを充填してから炉内温度を室温に戻し、はんだ粒子１を得ることができる。この場合は、炉内温度の上昇、下降の調節がそれぞれ一回で良いため、短時間で処理出来る利点がある。
　上述の凹部６２内にはんだ粒子を形成した後に、もう一度炉内を還元雰囲気にして、除去し切れなかった表面酸化皮膜を除去する工程を加えてもよい。これにより、融合されずに残っていたはんだ微粒子や、融合されずに残っていた酸化皮膜の一部などの残渣を減らすことができる。
　大気圧のコンベアー炉を用いる場合は、はんだ微粒子１１１が凹部に充填された基体６０を搬送用コンベアーに載せ、複数のゾーンを連続して通過させてはんだ粒子１を得ることができる。例えば、はんだ微粒子１１１が凹部に充填された基体６０を、一定の速度に設定したコンベアーに載せ、はんだ微粒子１１１の融点より低い温度の窒素やアルゴンなどの不活性ガスが充満したゾーンを通過させ、続いてはんだ微粒子１１１の融点より低い温度のギ酸ガスなどの還元ガスが存在するゾーンを通過させて、はんだ微粒子１１１の表面酸化皮膜を除去し、続いてはんだ微粒子１１１の融点以上の温度の窒素やアルゴンなどの不活性ガスが充満したゾーンを通過させてはんだ微粒子１１１を溶融、合一化させ、続いて窒素やアルゴンなどの不活性ガスが充満した冷却ゾーンを通過させて、はんだ粒子１を得ることができる。例えば、はんだ微粒子１１１が凹部に充填された基体６０を、一定の速度に設定したコンベアーに載せ、はんだ微粒子１１１の融点以上の温度の窒素やアルゴンなどの不活性ガスが充満したゾーンを通過させ、続いてはんだ微粒子１１１の融点以上の温度のギ酸ガスなどの還元ガスが存在するゾーンを通過させて、はんだ微粒子１１１の表面酸化皮膜を除去し、溶融、合一化させ、続いて窒素やアルゴンなどの不活性ガスが充満した冷却ゾーンを通過させて、はんだ粒子１を得ることができる。前記のコンベアー炉は、大気圧での処理が可能であることから、フィルム状の材料をロールトゥロールで連続的に処理することもできる。例えば、はんだ微粒子１１１が凹部に充填された基体６０の連続ロール品を作製し、コンベアー炉の入り口側にロール巻きだし機、コンベアー炉の出口側にロール巻き取り機を設置して、一定の速度で基体６０を搬送し、コンベアー炉内の各ゾーンを通過させることで、凹部に充填されたはんだ微粒子１１１を融合させることができる。
　はんだ微粒子準備工程～融合工程によれば、はんだ微粒子１１１の材質及び形状によらず、均一なサイズのはんだ粒子１を形成することができる。また、形成されたはんだ粒子１は、基体６０の凹部６２に収容された状態で取り扱うことができるため、はんだ粒子１を変形させることなく運搬・保管等することができる。さらに、形成されたはんだ粒子１は、単に基体６０の凹部６２に収容された状態であるため、取り出しが容易であり、はんだ粒子を変形させることなく回収・表面処理等を行うことができる。
　また、はんだ微粒子１１１は、粒度分布にばらつきが大きくても、形状がいびつであってもよく、凹部６２内に収容することができれば原料として好適に用いることができる。
　また、上記方法において、基体６０は、リソグラフィー、機械加工、インプリント、エッチング等によって凹部６２の形状を自在に設計できる。はんだ粒子１のサイズは凹部６２に収容されるはんだ微粒子１１１の量に依存するため、凹部６２の設計によりはんだ粒子１のサイズを自在に設計できる。
　融合工程で形成されたはんだ粒子１は、そのまま転写工程に使用してよく、基体６０の凹部６２に収容された状態で表面をフラックス成分で被覆してから転写工程に使用してもよく、凹部６２から取り出し、表面をフラックス成分で被覆し、凹部６２に再度収容してから転写工程に使用してもよい。なお、ここでは、はんだ粒子１の形成に用いた基体６０をそのまま転写工程に利用しているが、凹部６２からはんだ粒子１と取り出すステップを含む場合は、取り出したはんだ粒子１を、基体６０とは異なる基体に収容して、転写工程に用いてもよい。
　転写工程は、はんだ粒子１が凹部６２に収容されている状態の基体６０に対して、凹部６２の開口側から絶縁性樹脂材料２ａを接触させることにより、はんだ粒子１が転写された第一の樹脂層２ｂを得る工程である。
　図８（ａ）に示す基体６０は、凹部６２のそれぞれに一個のはんだ粒子１が収容された状態である。この基体６０の凹部６２の開口側の面に、層状の絶縁性樹脂組成物２ａを対向させて、基体６０と層状の絶縁性樹脂組成物２ａとを近づける（図８（ａ）における矢印Ａ，Ｂ）。なお、層状の絶縁性樹脂組成物２ａは、支持体６５の表面上に形成されている。支持体６５は、プラスチックフィルムであってもよいし、金属箔であってもよい。
　図８（ｂ）は、転写工程後の状態であって、基体６０の凹部６２の開口側の面を層状の絶縁性樹脂組成物２ａに接触させたことにより、基体６０の凹部６２に収容されていたはんだ粒子１が層状の絶縁性樹脂組成物２ａに転写された状態を示している。転写工程を経ることで、層状の絶縁性樹脂組成物２ａの所定の位置に複数のはんだ粒子１が転写された第一の樹脂層２ｂが得られる。第一の樹脂層２ｂは、その表面に複数のはんだ粒子１が露出している。なお、上記製造方法において、複数のはんだ粒子１は、いずれも平面部１１が第二の樹脂層２ｄ側を向いた状態で、異方性導電フィルム１０中に配置されている。
　積層工程は、第一の樹脂層２ｂの、はんだ粒子１が転写された側の表面２ｃ上に、絶縁性樹脂組成物で構成される第二の樹脂層２ｄを形成することにより、異方性導電フィルム１０を得る工程である。
　図８（ｃ）は、積層工程後の状態であって、第一の樹脂層２ｂの表面２ｃ上に、はんだ粒子１を覆うように第二の樹脂層２ｄを形成した後、支持体６５を取り除いた状態を示している。第二の樹脂層２ｄは、絶縁性樹脂組成物からなる絶縁性フィルムを第一の樹脂層２ｂにラミネートすることによって形成してもよく、絶縁性樹脂材料を含むワニスで第一の樹脂層２ｂを被覆した後、硬化処理を施すことによって形成してもよい。
　次に、図９を参照しながら、第二実施形態に係る異方性導電フィルム１０の製造方法について説明する。
　第二実施形態では、準備工程、収容工程及び融合工程を第一実施形態と同様にして実施した後、転写工程において、凹部６２の内部にまで絶縁性樹脂組成物を侵入させることにより、はんだ粒子１を第一の樹脂層２ｂに埋設する。
　図９（ａ）に示す基体６０は、凹部６２のそれぞれに一個のはんだ粒子１が収容された状態である。この基体６０の凹部６２の開口側の面に、層状の絶縁性樹脂組成物２ａを対向させて、基体６０と層状の絶縁性樹脂組成物２ａとを近づける（図９（ａ）における矢印Ａ，Ｂ）。
　図９（ｂ）は、転写工程後の状態であって、基体６０の凹部６２の開口側の面を層状の絶縁性樹脂組成物２ａに接触させたことにより、基体６０の凹部６２に収容されていたはんだ粒子１が層状の絶縁性樹脂組成物２ａに転写された状態を示している。転写工程を経ることで、所定の位置に複数のはんだ粒子１が配置された第一の樹脂層２ｂが得られる。第一の樹脂層２ｂの表面２ｃ側には、凹部６２に応じた複数の凸部２ｅが形成されており、これら凸部２ｅにはんだ粒子１が埋設されている。このような第一の樹脂層２ｂを得るため、転写工程では、凹部６２の内部にまで絶縁性樹脂材料２ａを侵入させる。具体的には、基体６０と層状の絶縁性樹脂組成物２ａとを、積層方向（図９（ａ）における矢印Ａ，Ｂの方向）に加圧することで、層状の絶縁性樹脂組成物２ａを凹部６２の内部に侵入させてよい。また、転写工程を減圧雰囲気下で行うと、層状の絶縁性樹脂組成物２ａが凹部６２の内部に入りやすくなる。また、図９では層状の絶縁性樹脂材料２ａによって転写工程を実施しているが、絶縁性樹脂組成物をワニスの状態で凹部６２の内部及び基体６０の表面に塗布し、硬化処理を施すことによって、第一の樹脂層２ｂを得ることもできる。
　図９（ｃ）は、積層工程後の状態であって、第一の樹脂層２ｂの表面２ｃ上に、第二の樹脂層２ｄを形成した後、支持体６５を取り除いた状態を示している。第二の樹脂層２ｄは、絶縁性樹脂組成物からなる絶縁性フィルムを第一の樹脂層２ｂにラミネートすることによって形成してもよく、絶縁性樹脂組成物を含むワニスで第一の樹脂層２ｂを被覆した後、硬化処理を施すことによって形成してもよい。
　なお、上記製造方法において、複数のはんだ粒子１は、いずれも平面部１１が第二の樹脂層２ｄ側を向いた状態で、異方性導電フィルム１０中に配置されている。融合工程で形成されたはんだ粒子１を一度取り出し、フラックス成分での被覆等の処理を施した後、再度、凹部６２に再配置する方法を採用した場合、複数のはんだ粒子１は、平面部１１の向きが互いに異なっていてもよい。図１０（ａ）は、一度取り出したはんだ粒子１を凹部６２に再配置した状態を示している。このような状態で転写工程及び積層工程を行うことで、複数のはんだ粒子１は、平面部１１の向きが一致しない状態で異方性導電フィルム１０中に配置される。図１０（ｂ）は、複数のはんだ粒子１が、平面部１１の向きが一致しない状態で異方性導電フィルム１０に配置された状態を示す図である。
＜接続構造体＞
　図１１は、接続構造体の一部を拡大して示す図であって、第一の電極と第二の電極とが接合部によって電気的に接続された状態を模式的に示す断面図である。すなわち、図１１は、第一の回路部材３０の電極３２と第二の回路部材４０の電極４２が、はんだ粒子１の融着により形成された接合部７０を介して電気的に接続された状態を模式的に示したものである。本明細書において「融着」とは上記のとおり、電極の少なくとも一部が熱によって融解されたはんだ粒子１によって接合され、その後、これが固化する工程を経ることによって電極の表面にはんだが接合された状態を意味する。第一の回路部材３０は、第一の回路基板３１と、その表面３１ａ上に配置された第一の電極３２とを備える。第二の回路部材４０は、第二の回路基板４１と、その表面４１ａ上に配置された第二の電極４２とを備える。回路部材３０，４０の間に充填された絶縁樹脂層５５は、第一の回路部材３０と第二の回路部材４０が接着された状態を維持するとともに、第一の電極３２と第二の電極４２が電気的に接続された状態を維持する。
　回路部材３０，４０のうちの一方の具体例として、ＩＣチップ（半導体チップ）、抵抗体チップ、コンデンサチップ、ドライバーＩＣ等のチップ部品；リジット型のパッケージ基板が挙げられる。これらの回路部材は、回路電極を備えており、多数の回路電極を備えているものが一般的である。回路部材３０，４０のうちの他方の具体例としては、金属配線を有するフレキシブルテープ基板、フレキシブルプリント配線板、インジウムスズ酸化物（ＩＴＯ）が蒸着されたガラス基板等の配線基板が挙げられる。
　第一の電極３２又は第二の電極４２の具体例としては、銅、銅／ニッケル、銅／ニッケル／金、銅／ニッケル／パラジウム、銅／ニッケル／パラジウム／金、銅／ニッケル／金、銅／パラジウム、銅／パラジウム／金、銅／スズ、銅／銀、インジウムスズ酸化物等の電極が挙げられる。第一の電極３２または第二の電極４２は、無電解めっき又は電解めっき又はスパッタ又は金属箔のエッチングで形成することができる。
　本実施形態において、第一の電極３２及び第二の電極４２のうち少なくとも一方は金電極である。
　接合部７０は、第一の電極３２と第二の電極４２とを接続する第一の領域７１と、第一の領域と接する第二の領域７２とを含んでいる。本実施形態では、溶融したはんだと金電極との接触により、金電極中の金の一部がはんだ中のスズと合金（スズ－金合金）を形成し、第一の領域７１が形成されると考えられる。また、これに伴い、はんだ中のビスマスは第一の領域７１から押し出され、第一の領域７１の周囲を囲む第二の領域７２が形成されると考えられる。
　第一の領域７１は、スズ－金合金から構成されたものであってよく、第二の領域７２は、ビスマスから構成されたものであってよい。
　第一の領域７１の体積Ｖ１に対する第二の領域７２の体積Ｖ２の比Ｖ２／Ｖ１は、例えば０．０５～２．０であってよく、０．１～１．５が好ましく、０．１８～１．０がより好ましい。
　接続構造体中に複数存在する接合部のうち、第一の領域７１及び第二の領域７２を含む接合部７０の割合は、９０％以上であり、好ましくは９５％以上であり、より好ましくは９９％以上であり、１００％であってもよい。なお、第一の領域７１及び第二の領域７２を含まない接合部としては、例えば、スズ－ビスマス合金から構成された柱状部を有する接合部等が挙げられる。
　図１５（ａ）、図１５（ｂ）、図１５（ｃ）、図１５（ｄ）、図１６（ａ）、図１６（ｂ）、図１６（ｃ）及び図１６（ｄ）は、それぞれ、第一の領域７１及び第二の領域７２を含む接合部の一例を模式的に示す積層方向の断面図である。
　図１５（ａ）に示すように、接合部７０において、第一の領域７１は、第一の電極３２と第二の電極４２とを連結する柱状構造を有していてよく、第二の領域７２は、第一の領域７１を取り囲む円環状構造を有してよい。図１５（ａ）に示す接合部７０の積層方向に垂直な断面は、例えば、図１７（ａ）に示すような構造であってよい。
　図１５（ｂ）に示すように、接合部７０において、第一の領域７１は、第一の電極３２と第二の電極４２とを連結する柱状構造を有していてよく、第二の領域７２は、第一の領域７１の一部と接する塊状であってよい。図１５（ｂ）に示す接合部７０の積層方向に垂直な断面は、例えば、図１７（ｂ）に示すような構造であってよい。
　図１５（ｃ）に示すように、接合部７０は、第一の電極３２と第二の電極４２とを連結する柱状構造を有する第一の領域７１を複数含んでいてよい。また、この接合部７０において、第二の領域７２は、複数の第一の領域７１の間に、複数の第一の領域７１同士を接続するように配置されていてよい。図１５（ｃ）に示す接合部７０の積層方向に垂直な断面は、例えば，図１７（ｃ）に示すような構造であってよい。
　図１５（ｄ）に示すように、接合部７０において、第一の領域７１は、第一の電極３２と第二の電極４２とを連結する柱状構造を有していてよい。また、接合部７０は、柱状構造以外に更にスズ－金合金を含有する塊状体を有していてよい。当該塊状体は、図１５（ｄ）に示すように第一の領域７１と一体化して第一の領域７１の一部を構成して（すなわち、第一の領域７１が、柱状部と塊状部とを有して）いてよく、第一の領域７１と離間して存在していてもよい。前者の場合、第二の領域７２は、第一の領域７１の柱状部又は塊状部と接するように配置されていてよく、後者の場合、第二の領域７２が、第一の領域７１及び塊状体の両方に接するように配置されていてよい。図１５（ｃ）に示す接合部７０の積層方向に垂直な断面は、例えば、図１７（ｃ）又は図１７（ｄ）に示すような構造であってよい。
　図１６（ａ）に示すように、接合部７０において、第一の領域７１は、第一の電極３２と第二の電極４２とを連結する柱状構造を有していてよく、第二の領域７２は、第一の領域７１を取り囲む円環状構造を有していてよい。また、接合部７０は、円環状構造以外に、更にビスマスを含有する塊状体を有していてよい。当該塊状体は、図１６（ａ）に示すように第二の領域７２と一体化して第二の領域７２の一部を構成して（すなわち、第二の領域７２が、円環状部と塊状部とを有して）いてよく、円環状の第二の領域７２と離間して、もう一つの第二の領域７２として第一の領域７１と接していてもよい。図１６（ａ）に示す接合部７０の積層方向に垂直な断面は、例えば、図１７（ｄ）に示すような構造であってよい。
　図１６（ｂ）に示すように、接合部７０において、第一の領域７１は、第一の電極３２と第二の電極４２とを連結する柱状構造を有していてよく、第二の領域７２は、第一の領域７１の一部を取り囲む円環状構造を有していてよい。また、第一の領域７１は、第一の電極３２又は第二の電極４２の電極表面に沿って拡がっていてよい。
　図１６（ｃ）又は図１６（ｄ）に示すように、接合部７０は、複数のはんだ粒子１（又ははんだバンプ）が合一化して形成されたものであってよい。図１６（ｃ）に示すように、接合部７０は、複数のはんだ粒子１の合一化によって形成された、柱状構造を有する第一の領域７１を含んでいてよく、当該第一の領域７１を取り囲む円環状の第二の領域７２を更に含んでいてよい。また、図１６（ｄ）に示すように、接合部７０は、複数のはんだ粒子１（又ははんだバンプ）のそれぞれ由来する複数の第一の領域７１を有していてよく、第二の領域７２によって複数の第一の領域７１が接続されていてよい。図１６（ｃ）に示す接合部７０の積層方向に垂直な断面は、例えば、図１７（ｅ）に示すような構造であってよい。また、図１６（ｄ）に示す接合部７０の積層方向に垂直な断面は、例えば、図１７（ｆ）に示すような構造であってよい。
　次に、図１８（ａ）、図１８（ｂ）及び図１８（ｃ）、は、それぞれ、第一の領域及び第二の領域を含まない接合部の一例を模式的に示す積層方向の断面図である。
　図１８（ａ）に示す接合部９０では、スズ－金合金を含有する領域９１が、第一の電極３２側及び第二の電極４２側のそれぞれに偏在しており、第一の電極３２と第二の電極４２とを連結できていない。また、第一の電極３２側の領域９１と第二の電極４２側の領域９１との間に、ビスマスを含有する領域９２が形成されている。図１８（ａ）に示す接合部９０は、第一の領域を有しないため、「第一の領域と第二の領域とを含む接合部」には該当しない。図１８（ａ）に示す接合部９０の積層方向に垂直な断面は、例えば、図１９（ａ）、図１９（ｂ）又は図１９（ｃ）に示すような構造であってよい。
　図１８（ｂ）に示す接合部９０では、スズ－金合金を含有する領域９１が、第二の電極４２側に偏在しており、領域９１と第一の電極３２との間に、ビスマスを含有する領域９２が形成されている。図１８（ｂ）に示す接合部９０は、領域９１が第一の電極３２と第二の電極４２とを連結しておらず、「第一の領域と第二の領域とを含む接合部」には該当しない。図１８（ａ）に示す接合部９０の積層方向に垂直な断面は、例えば、図１９（ａ）、図１９（ｂ）又は図１９（ｃ）に示すような構造であってよい。
　図１８（ｃ）に示す接合部９０では、スズ－金合金を含有する領域９１とビスマス合金を有する領域９２とが第二の電極４２側に偏在しており、第一の電極３２と第二の電極４２とが電気的に接続されていない。また、図１８（ｃ）に示す接合部９０では、金とスズとの合金化が不十分で領域９２中に、スズを含む領域９３が形成されている。図１８（ｃ）に示す接合部９０は、領域９１が第一の電極３２と第二の電極４２とを連結しておらず、「第一の領域と第二の領域とを含む接合部」には該当しない。図１８（ａ）に示す接合部９０の積層方向に垂直な断面は、例えば、図１９（ａ）、図１９（ｂ）、図１９（ｃ）又は図１９（ｄ）に示すような構造であってよい。
＜接続構造体の製造方法＞
　図１２（ａ）及び図１２（ｂ）を参照しながら、接続構造体の製造方法について説明する。これらの図は、図１１に示す接続構造体５０Ａを形成する過程の一例を模式的に示す断面図である。まず、図１に示す異方性導電フィルム１０を予め準備し、これを第一の回路部材３０と第二の回路部材４０とが対面するように配置する（図１２（ａ））。このとき、第一の回路部材３０の第一の電極３２と第二の回路部材４０の第二の電極４２とが対向するように設置する。その後、これらの部材の積層体の厚さ方向（図１２（ａ）に示す矢印Ａ及び矢印Ｂの方向）に加圧する。矢印Ａ及び矢印Ｂの方向に加圧する際に全体をはんだ粒子１の融点よりも高い温度（例えば１３０～２６０℃）に少なくとも加熱することによって、はんだ粒子１が溶融し、第一の電極３２と第二の電極４２の間に寄り集まって、接合部７０が形成され、その後、冷却することで第一の電極３２と第二の電極４２の間に接合部７０が固着され、第一の電極３２と第二の電極４２が電気的に接続される。
　絶縁性フィルム２を構成する絶縁性樹脂組成物が例えば熱硬化性樹脂を含む場合、矢印Ａ及び矢印Ｂの方向に加圧する際に全体を加熱することによって絶縁性樹脂組成物を硬化させることができる。これにより、絶縁性樹脂組成物の硬化物からなる絶縁樹脂層５５が回路部材３０，４０の間に形成される。
　図１３（ａ）及び図１３（ｂ）は、図１２（ａ）及び図１２（ｂ）に示す接続構造体５０Ａの製造方法の変形例を模式的に示す断面図である。この変形例に係る製造方法においては、はんだ粒子１の一部が電極３２,４２の融着に寄与せずに絶縁樹脂層５５内に残存しているものの、異方性導電フィルム１０において特定の位置にはんだ粒子１が配置されているに過ぎず、つまり、はんだ粒子１の密度が十分に低いため、絶縁信頼性を高く維持することができる。
　図１４（ａ）及び図１４（ｂ）は、図１２（ａ）及び図１２（ｂ）に示す接続構造体５０Ａの製造方法の変形例を模式的に示す断面図である。この変形例に係る製造方法においては、実質的に全てのはんだ粒子１が接合部７０となり、第一の回路部材３０の第一の電極３２と第二の回路部材４０の第二の電極４２を融着している。異方性導電フィルム１０におけるはんだ粒子１の配置をあらかじめ設計することで、融着に寄与せずに残存するはんだ粒子１を極力低減することが可能である。これにより、接続構造体の絶縁信頼性をより一層向上することができる。
　以上、異方性導電フィルム１０を用いて本実施形態の接続構造体を製造する方法について説明したが、本実施形態の接続構造体は、異方性導電フィルムを使用しない方法によって製造してもよい。
　例えば、本実施形態の接続構造体の製造方法の他の一態様では、第一の回路部材３０の第一の電極３２（又は第二の回路部材４０の第二の電極４２）の表面にはんだバンプを形成し、当該はんだバンプを形成した第一の電極３２（又は第二の電極４２）と第二の電極４２（又は第一の電極３２）とを対向する位置に配置し、加熱加圧して第一の電極３２と第二の電極４２とを接続し、接合部７０を製造してもよい。
　はんだバンプを形成する方法は特に限定されないが、例えば、凹部６２のそれぞれにはんだ粒子１が収容された基体６０を準備し、この基体６０の凹部６２の開口側の面に、第一の回路部材３０の第一の電極３２を対向させて配置し、基体の厚み方向に加圧しながら加熱処理することで、第一の電極３２の表面にはんだバンプを形成することができる。同様の方法で、第二の電極４２の表面にはんだバンプを形成することもできる。
　加熱処理は、例えば、脱酸素雰囲気又は還元雰囲気で実施することが好ましい。これにより、はんだ粒子の酸化が抑制され、第一の電極３２（又は第二の電極４２）への濡れ拡がりが進みやすくなり、はんだバンプをより確実に第一の電極３２（又は第二の電極４２）の表面に配置することができる。脱酸素雰囲気は、例えば、窒素、アルゴン等の不活性ガス雰囲気、真空状態等であってよい。
　はんだバンプをより確実に第一の電極３２（又は第二の電極４２）の表面に配置する観点から、はんだバンプの形成に際し、フラックス、粘性物質等を使用してもよい。また、これらは第一の電極３２と第二の電極４２との接続を阻害する場合や、はんだバンプ又は電極を酸化又は腐食させる場合があるため、バンプの形成後に、これらを除去する工程があってもよい。
　第一の電極３２と第二の電極４２との接続は、例えば、脱酸素雰囲気又は還元雰囲気で実施することが好ましい。これにより、はんだ粒子の酸化が抑制され、第一の電極３２及び第二の電極４２への濡れ拡がりが進みやすくなり、より確実に第一の電極３２と第二の電極４２とを接続する接合部７０を形成することができる。脱酸素雰囲気は、例えば、窒素、アルゴン等の不活性ガス雰囲気、真空状態等であってよい。
　第一の電極３２と第二の電極４２とをより確実に製造する観点から、接合部７０の形成に際し、フラックス、粘性物質等を使用してもよい。また、これらは、接合部又は電極を酸化又は腐食させる場合、後述する絶縁樹脂層５５の形成に悪影響を与える場合があるため、接合部７０の形成後に、これらを除去する工程があってもよい。
　接続構造体の製造方法の上記態様では、接合部７０の形成後に、第一の回路部材３０及び第二の回路部材４０の間に絶縁性樹脂材料を注入及び硬化させて、絶縁性樹脂層５５を形成してよい。
　接続構造体の製造方法の上記態様では、接合部７０の形成に際し、はんだバンプが形成された第一の電極３２を有する第一の回路部材３０と、第二の電極４２を有する第二の回路部材４０とを、第一の電極３２と第二の電極４２とが対向するように配置し、更に第一の回路部材３０及び第二の回路部材４０の間に絶縁性樹脂フィルムを配置して、厚み方向に加圧しながら加熱処理することで、接合部７０の形成と絶縁樹脂層５５の形成とを同時に行うこともできる。
　図２０、図２１、図２２及び図２３は、押圧及び加熱がなされる前の異方性導電フィルム１０のはんだ粒子１の位置と第一の電極３２の位置との関係を模式的に示す図である。図２０、図２１、図２２及び図２３は、はんだバンプの形成時における、基体６０中のはんだ粒子１の位置と第一の電極３２（又は第二の電極４２）の位置との関係を模式的に示す図、ということもできる。
　上述の実施形態及びそれらの変形例に係る接続構造体の適用対象としては、半導体メモリー、半導体ロジックチップなどの接続、半導体パッケージの一次実装や二次実装の接続部、ＣＭＯＳ画像素子、レーザー素子、ＬＥＤ発光素子などの接合体や、それらを用いたカメラ、センサー、液晶ディスプレイ、パーソナルコンピュータ、携帯電話、スマートフォン、タブレット等のデバイスが挙げられる。
　以上、本発明の好適な実施形態について説明したが、本発明は上記実施形態に限定されるものではない。
　以下、実施例によって本発明を更に詳細に説明するが、本発明はこれらの実施例に限定されるものではない。
＜はんだ粒子の作製＞
（作製例１）
（工程ａ１）はんだ微粒子の分級
　Ｓｎ－Ｂｉはんだ微粒子（５Ｎ　Ｐｌｕｓ社製、融点１３９℃、Ｔｙｐｅ８）１００ｇを、蒸留水に浸漬し、超音波分散させた後、静置し、上澄みに浮遊するはんだ微粒子を回収した。この操作を繰り返して、１０ｇのはんだ微粒子を回収した。得られたはんだ微粒子の平均粒子径は１．０μｍ、Ｃ．Ｖ．値は４２％であった。
（工程ｂ１）基体への配置
　表１に示す、開口径２．３μｍφ、底部径２．０μｍφ、深さ２．０μｍ（底部径２．０μｍφは、開口を上面からみると、開口径２．３μｍφの中央に位置する）の凹部を複数有する基体（ポリイミドフィルム、厚さ１００μｍ）を準備した。複数の凹部は、１．０μｍの間隔で規則的に配列させた。工程ａで得られたはんだ微粒子（平均粒子径１．０μｍ、Ｃ．Ｖ．値４２％）を基体の凹部に配置した。なお、基体の凹部が形成された面側を微粘着ローラーでこすることで余分なはんだ微粒子を取り除き、凹部内のみにはんだ微粒子が配置された基体を得た。
（工程ｃ１）はんだ粒子の形成
　工程ｂ１で凹部にはんだ微粒子が配置された基体を、水素ラジカル還元炉（神港精機株式会社製、プラズマリフロー装置）に投入し、真空引き後、水素ガスを炉内に導入して、炉内を水素ガスで満たした。その後、炉内を１２０℃に調整し、５分間水素ラジカルを照射した。その後、真空引きにて炉内の水素ガスを除去し、１７０℃まで加熱した後、窒素を炉内に導入して大気圧に戻してから炉内の温度を室温まで下げることにより、はんだ粒子を形成した。
（工程ｄ１）はんだ粒子の回収
　工程ｃ１を経た基体を凹部裏側よりタップすることで、凹部よりはんだ粒子を回収した。得られたはんだ粒子を、下記の方法で評価した。
＜はんだ粒子の評価＞
　ＳＥＭ観察用台座表面に固定した導電テープ上に、得られたはんだ粒子を載せ、厚さ５ｍｍのステンレス板にＳＥＭ観察用台座をタップしてはんだ粒子を導電テープ上に万遍なく広げた。その後、導電テープ表面に圧縮窒素ガスを吹きかけ、はんだ粒子を導電テープ上に単層に固定した。ＳＥＭにてはんだ粒子の直径を３００個測定し、平均粒子径及びＣ．Ｖ．値を算出した。結果を表２に示す。
（作製例２～６）
　凹部のサイズを表１に記載のとおり変更したこと以外は、作製例１と同様にしてはんだ粒子を作製し、評価した。結果を表２に示す。
Figure JPOXMLDOC01-appb-T000001
Figure JPOXMLDOC01-appb-T000002
＜実施例１＞
（Ａ）異方性導電フィルムの作製
（工程ｅ１）フラックスコートはんだ粒子の製造
　作製例１と同じ方法ではんだ粒子を作製した。得られたはんだ粒子２０ｇと、アジピン酸４ｇと、アセトン７ｇとを３つ口フラスコに秤量し、次にはんだ粒子表面の水酸基とアジピン酸のカルボキシル基との脱水縮合反応を触媒するジブチルスズオキシド０．０３ｇを添加し、６０℃で４時間反応させた。その後、はんだ粒子を濾過して回収した。回収したはんだ粒子と、アジピン酸５ｇと、トルエン２０ｇと、パラトルエンスルホン酸０．０３ｇとを３つ口フラスコに秤量し、真空引き、及び還流を行いながら、１２０℃で、３時間反応させた。この際、ディーンスターク抽出装置を用いて、脱水縮合により生成した水を除去しながら反応させた。その後、濾過によりはんだ粒子を回収し、ヘキサンにて洗浄し、乾燥した。乾燥後のはんだ粒子を気流式解砕機で解砕し、音波篩によりメッシュを通すことで、フラックスコートはんだ粒子を得た。
（工程ｆ１）フラックスコートはんだ粒子の配置
　開口径２．３μｍφ、底部径２．０μｍφ、深さ２．０μｍ（底部径２．０μｍφは、開口部を上面からみると、開口径２．３μｍφの中央に位置する）の凹部を複数有する転写型（ポリイミドフィルム、厚さ１００μｍ）を準備した。なお、複数の凹部は、１．０μｍの間隔で規則的に配列させた。この転写型の凹部に、それぞれ工程ｅ１で得たフラックスコートはんだ粒子を配置した。
（工程ｇ１）接着フィルムの作製
　フェノキシ樹脂（ユニオンカーバイド社製、商品名「ＰＫＨＣ」）１００ｇと、アクリルゴム（ブチルアクリレート４０質量部、エチルアクリレート３０質量部、アクリロニトリル３０質量部、グリシジルメタクリレート３質量部の共重合体、分子量：８５万）７５ｇとを、酢酸エチル４００ｇに溶解し、溶液を得た。この溶液に、マイクロカプセル型潜在性硬化剤を含有する液状エポキシ樹脂（エポキシ当量１８５、旭化成エポキシ株式会社製、商品名「ノバキュアＨＸ－３９４１」）３００ｇを加え、撹拌して接着剤溶液を得た。得られた接着剤溶液を、セパレータ（シリコーン処理したポリエチレンテレフタレートフィルム、厚さ４０μｍ）にロールコータを用いて塗布し、９０℃で１０分間の加熱することにより乾燥して、厚さ２、３、４、１０，１５及び２０μｍの接着フィルム（絶縁樹脂フィルム）をセパレータ上に作製した。
（工程ｈ１）フラックスコートはんだ粒子の転写
　セパレータ上に形成された接着フィルムと、工程ｆ１でフラックスコートはんだ粒子が配置された転写型とを向かい合わせて配置し、接着フィルムにフラックスコートはんだ粒子を転写させた。
（工程ｉ１）異方性導電フィルムの作製
　工程ｈ１で得た接着フィルムの転写面に、工程ｇ１と同様の方法で作製された接着フィルムを接触させ、５０℃、０．１ＭＰａ（１ｋｇｆ／ｃｍ２）で加熱・加圧させることで、フィルムの断面視において、フラックスコートはんだ粒子が層状に配列された異方性導電フィルムを得た。なお、厚さ２μｍのフィルムに対しては２μｍを重ね合わせ、同様に、３μｍには３μｍ、４μｍには４μｍ、１０μｍには１０μｍ、１５μｍには１５μｍ、２０μｍには２０μｍを重ね合わることで、４μｍ、６μｍ、８μｍ、２０μｍ、３０μｍ及び４０μｍの厚みの異方性導電フィルムを作製した。
（Ｂ）接続構造体の作製
（工程ｊ１）評価チップの準備
　下記に示す、７種類の金バンプ付きチップ（３．０×３．０ｍｍ、厚さ：０．５ｍｍ）を準備した。
・チップＣ１…面積１００μｍ×１００μｍ、スペース４０μｍ、高さ：１０μｍ、バンプ数３６２
・チップＣ２…面積７５μｍ×７５μｍ、スペース２０μｍ、高さ：１０μｍ、バンプ数３６２
・チップＣ３…面積４０μｍ×４０μｍ、スペース１６μｍ、高さ：７μｍ、バンプ数３６２
・チップＣ４…面積３０μｍ×３０μｍ、スペース１２μｍ、高さ：６μｍ、バンプ数３６２
・チップＣ５…面積２０μｍ×２０μｍ、スペース７μｍ、高さ：５μｍ、バンプ数３６２
・チップＣ６…面積１０μｍ×１０μｍ、スペース６μｍ、高さ：３μｍ、バンプ数３６２
（工程ｋ１）評価基板の準備
　下記に示す、７種類の金バンプ付き基板（７０×２５ｍｍ、厚さ：０．５ｍｍ）を準備した。なお、これらの金バンプには抵抗測定用の引き出し配線も形成されている。
・基板Ｄ１…面積１００μｍ×１００μｍ、スペース４０μｍ、高さ：４μｍ、バンプ数３６２
・基板Ｄ２…面積７５μｍ×７５μｍ、スペース２０μｍ、高さ：４μｍ、バンプ数３６２
・基板Ｄ３…面積４０μｍ×４０μｍ、スペース１６μｍ、高さ：４μｍ、バンプ数３６２
・基板Ｄ４…面積３０μｍ×３０μｍ、スペース１２μｍ、高さ：４μｍ、バンプ数３６２
・基板Ｄ５…面積２０μｍ×２０μｍ、スペース７μｍ、高さ：４μｍ、バンプ数３６２
・基板Ｄ６…面積１０μｍ×１０μｍ、スペース６μｍ、高さ：３μｍ、バンプ数３６２
（工程ｌ１）
　次に、工程ｉ１作製した異方性導電フィルムを用いて、評価チップ（３．０×３．０ｍｍ、厚さ：０．５ｍｍ）と、評価基板（厚さ：０．５ｍｍ）との接続を、以下に示すｉ）～ｉｉｉ）の手順に従って行うことによって接続構造体を得た。
ｉ）異方性導電フィルム（３．５×１９ｍｍ）の片面のセパレータ（シリコーン処理したポリエチレンテレフタレートフィルム、厚さ４０μｍ）を剥がし、異方性導電フィルムと評価基板を接触させ、８０℃、０．９８ＭＰａ（１０ｋｇｆ／ｃｍ２）で貼り付けた。
ｉｉ）セパレータを剥離し、評価チップのバンプと評価基板のバンプの位置合わせを行った。
ｉｉｉ）１８０℃、４０ｇｆ／バンプ、１０秒の条件でチップ上方から加熱及び加圧を行い、本接続を行った。以下の（１）～（６）の「チップ／異方性導電フィルム／基板」の組み合わせで、（１）～（６）に係る計７種類の接続構造体をそれぞれ作製した。
（１）チップＣ１／４０μｍの厚みの異方性導電フィルム／基板Ｄ１
（２）チップＣ２／３０μｍの厚みの異方性導電フィルム／基板Ｄ２
（３）チップＣ３／２０μｍの厚みの異方性導電フィルム／基板Ｄ３
（４）チップＣ４／８μｍの厚みの異方性導電フィルム／基板Ｄ４
（５）チップＣ５／６μｍの厚みの異方性導電フィルム／基板Ｄ５
（６）チップＣ６／４μｍの厚みの異方性導電フィルム／基板Ｄ６
＜接続構造体の評価＞
　得られた接続構造体の一部について、導通抵抗試験及び絶縁抵抗試験を以下のように行った。
（導通抵抗試験－吸湿耐熱試験）
　金バンプ付きチップ（バンプ）／金バンプ付き基板（バンプ）間の導通抵抗に関して、導通抵抗の初期値と吸湿耐熱試験（温度８５℃、湿度８５％の条件で１００、５００、１０００時間放置）後の値を、２０サンプルについて測定し、それらの平均値を算出した。
得られた平均値から下記基準に従って導通抵抗を評価した。結果を表３に示す。なお、吸湿耐熱試験１０００時間後に、下記Ａ又はＢの基準を満たす場合は導通抵抗が良好といえる。
Ａ：導通抵抗の平均値が２Ω未満
Ｂ：導通抵抗の平均値が２Ω以上５Ω未満
Ｃ：導通抵抗の平均値が５Ω以上１０Ω未満
Ｄ：導通抵抗の平均値が１０Ω以上２０Ω未満
Ｅ：導通抵抗の平均値が２０Ω以上
（導通抵抗試験－高温放置試験）
　金バンプ付きチップ（バンプ）／金バンプ付き基板（バンプ）間の導通抵抗に関して、導通抵抗の初期値と高温放置試験（温度１００℃の条件で１００、５００、１０００時間放置）後の値を、２０サンプルについて測定した。なお、高温放置後は、落下衝撃を加え、落下衝撃後のサンプルの導通抵抗を測定した。落下衝撃は、接続構造体を、金属板にネジ止め固定し、高さ５０ｃｍから落下させることで生じさせた。落下後、最も衝撃の大きいチップコーナーのはんだ接合部（４箇所）において直流抵抗値を測定し、測定値が初期抵抗から５倍以上増加したときに破断が生じたとみなして、評価を行った。なお、各サンプルにつき４箇所で、合計８０箇所の測定を行った。結果を表４に示す。落下回数２０回後に下記Ａ又はＢの基準を満たす場合をはんだ接続信頼性が良好であると評価した。
Ａ：初期抵抗から５倍以上増加したはんだ接続部が、０箇所であった。
Ｂ：初期抵抗から５倍以上増加したはんだ接続部が、１箇所以上５箇所以下であった。
Ｃ：初期抵抗から５倍以上増加したはんだ接続部が、６箇所以上２０箇所以下であった。
Ｄ：初期抵抗から５倍以上増加したはんだ接続部が、２１箇所以上であった。
（絶縁抵抗試験）
　チップ電極間の絶縁抵抗に関し、絶縁抵抗の初期値とマイグレーション試験（温度６０℃、湿度９０％、２０Ｖ印加の条件で１００、５００、１０００時間放置）後の値を、２０サンプルについて測定し、全２０サンプル中、絶縁抵抗値が１０９Ω以上となるサンプルの割合を算出した。得られた割合から下記基準に従って絶縁抵抗を評価した。結果を表５に示す。なお、マイグレーション試験１０００時間後に、下記Ａ又はＢの基準を満たした場合は絶縁抵抗が良好といえる。
Ａ：絶縁抵抗値１０９Ω以上の割合が１００％
Ｂ：絶縁抵抗値１０９Ω以上の割合が９０％以上１００％未満
Ｃ：絶縁抵抗値１０９Ω以上の割合が８０％以上９０％未満
Ｄ：絶縁抵抗値１０９Ω以上の割合が５０％以上８０％未満
Ｅ：絶縁抵抗値１０９Ω以上の割合が５０％未満
＜実施例２～６＞
　作製例２～６と同じ方法で作製したはんだ粒子を用いたこと、及び、転写型として作製例２～６のはんだ粒子作製に用いた基体と同じ形状の転写型を用いたこと以外は、実施例１と同じ方法で異方導電性フィルム及び接続構造体の作製を行った。
Figure JPOXMLDOC01-appb-T000003
Figure JPOXMLDOC01-appb-T000004
Figure JPOXMLDOC01-appb-T000005
＜接続構造体の評価＞
　評価に用いた接続構造体を、エポキシ注型樹脂で固めた後、リファインソーで切り出し、研磨紙を用いて、評価チップの金バンプ、はんだ粒子、評価基板の金バンプが見える接続断面部まで研磨した。その後、クライオミリング装置（ＩＢ－１９５２０ＣＣＰ、ＪＥＯＬ製）にて、－１２０℃以下、４．０ｋＶで、接続断面を平坦に加工した。この断面加工部にスパッタによりプラチナ層を５ｎｍ程度形成して、ＳＥＭ観察及びＥＤＸ分析を行った。その結果、実施例２の（５）では、接続構造体を形成した直後は、評価チップの金バンプと評価基板の金バンプとが、一定の距離を保っており、金とスズの合金層を介して接続していることが確認された。また、この合金層に接する位置に、ビスマス部が存在した。断面のＳＥＭ画像を図２５（ａ）、断面のＥＤＸ分析結果を図２５（ｂ）に示す。評価試験後の断面構造は、金とスズの合金層が各金バンプ側に広がっていたものの、試験前と概ね変わらなかった。
　実施例１～６では、絶縁樹脂部によるはんだ粒子の保持、金バンプ間のギャップ保持があり、適度な加熱時間により、はんだのスズ成分と金との合金化及びビスマスの再配置が進行して、安定した接続構造体が得られるものと考えられる。
＜はんだバンプ形成部材の作製＞
（作製例７）
（工程ｍ１）基体の作製
　６インチのシリコンウエハ上に、液状感光性レジスト（昭和電工マテリアルズ株式会社製、ＡＨシリーズ）をスピンコート法にて１．５μｍの厚みに塗布した。このシリコンウエハ上の感光性レジストを露光・現像して、開口径２．３μｍφ、底部径２．０μｍφ、深さ１．５μｍ（底部径２．０μｍφは、開口を上面からみると、開口径２．３μｍφの中央に位置する）の凹部を有する基体７を得た。なお、これらの凹部は評価用基板７の電極配置パターンに相対した位置に配置した。また、基体７の表面には、凹部形成と同時に３箇所のアライメントマークを配置した。基体７の概要を表６に示す。
Figure JPOXMLDOC01-appb-T000006
　工程ａ１と同様にはんだ微粒子を得て、基体７を用いたこと以外は工程ｂ１と同様に凹部内にはんだ微粒子を配置し、工程ｃ１により凹部内にはんだ粒子を有したはんだバンプ形成部材７を得た。
＜はんだバンプ形成部材の評価＞
　はんだバンプ形成部材７の一部を、ＳＥＭ観察用台座表面に固定し、表面に白金スパッタを施した。ＳＥＭにて、はんだ粒子の直径を３００個測定し、平均粒子径及びＣ．Ｖ．値を算出した。結果を表７に示す。また、はんだバンプ形成部材７の一部の表面形状を、レーザー顕微鏡（オリンパス株式会社製、ＬＥＸＴ　ＯＬＳ５０００－ＳＡＦ）を用いて測定し、基体表面からのはんだ粒子の高さを測定し、３００個の平均値を算出した。結果を表７に示す。
Figure JPOXMLDOC01-appb-T000007
（作製例８～１２）
　感光性レジストの厚みを表６に示す深さの値に変更し、また凹部サイズも表６に記載のとおり変更し、凹部の配置位置は表６記載の評価用基板の電極配置パターンに相対した位置としたこと以外は、作製例７と同様にしてはんだバンプ形成部材を作製し、評価した。結果を表７に示す。
＜はんだバンプ付き評価チップの作製＞
（工程ｊ２）評価チップの準備
　下記に示す、６種類の金バンプ付きチップ（５×５ｍｍ、厚さ：０．５ｍｍ）を準備した。
チップＣ７…電極サイズ：８μｍ×４μｍ、ピッチ：Ｘ方向１６μｍ、Ｙ方向８μｍ、バンプ数：１８万個
チップＣ８…電極サイズ：１６μｍ×８μｍ、ピッチ：Ｘ方向３２μｍ、Ｙ方向１６μｍ、バンプ数：４．６万個
チップＣ９…電極サイズ：２４μｍ×１２μｍ、ピッチ：Ｘ方向４８μｍ、Ｙ方向２４μｍ、バンプ数：１．５万個
チップＣ１０…電極サイズ：７２μｍ×３６μｍ、ピッチ：Ｘ方向１４４μｍ、Ｙ方向７２μｍ、バンプ数：３４００個
チップＣ１１…電極サイズ：９６μｍ×４８μｍ、ピッチ：Ｘ方向１９２μｍ、Ｙ方向９６μｍ、バンプ数：８５０個
チップＣ１２…電極サイズ：１４０μｍ×７０μｍ、ピッチ：Ｘ方向２８０μｍ、Ｙ方向１４０μｍ、バンプ数：４２０個
（工程ｎ１）はんだバンプ形成
　ＦＣ３０００Ｗ（東レエンジニアリング製）のステージにはんだバンプ形成部材７を置き、評価チップＣ８をヘッドに装着してピックアップし、双方のアライメントマークを利用して、はんだバンプ形成部材７の凹部内に配置したはんだ粒子と評価チップＣ８の電極位置合わせを行い、はんだバンプ形成部材７の上に評価チップＣ７を仮置きした。その後、ギ酸リフロー炉（神港精機株式会社製、バッチ式真空半田付装置）の下部熱板上に置き、真空引きの後、ギ酸ガスを充填し、下部熱板を１４５℃に昇温し、１分加熱した。その後、真空引きにてギ酸ガスを排出後、窒素置換を行い、下部熱板を室温まで戻し、炉内を大気開放し、評価チップＣ７の電極上にはんだ粒子を転写し、はんだバンプを形成した。
＜はんだバンプの評価＞
　工程ｎ１を経て得た評価チップを、３００個の電極に対して、はんだ粒子が転写出来た数（はんだバンプ数）を数え、転写率を算出した。また、はんだバンプの高さをレーザー顕微鏡（オリンパス株式会社製、ＬＥＸＴ　ＯＬＳ５０００－ＳＡＦ）を用いて測定し、３００個の平均値を算出した。結果を表８に示す。
Figure JPOXMLDOC01-appb-T000008
　はんだバンプ形成フィルム８～１２と、評価チップＣ８～Ｃ１２を用いたこと以外は、工程ｎ１と同様にして、はんだバンプ形成を行った。更に、３００個の電極のはんだバンプを評価して、転写率と高さ平均値を算出した。結果を表８に示す。
＜接続構造体の作製＞
（工程ｋ２）評価基板の準備
　下記に示す、６種類の金バンプ付き評価基板（７０×２５ｍｍ、厚さ：０．５ｍｍ）を準備した。この金バンプは、前述の評価チップＣ７～Ｃ１２の金電極に対向した位置に配置されており、アライメントマークが配されている。また、金バンプの一部には抵抗測定用の引き出し配線も形成されている。
基板Ｄ７…面積８μｍ×４μｍ、ピッチ：Ｘ方向１６μｍ、Ｙ方向８μｍ、高さ：２μｍ、バンプ数：１８万個
基板Ｄ８…面積１６μｍ×８μｍ、ピッチ：Ｘ方向３２μｍ、Ｙ方向１６μｍ、高さ：３μｍ、バンプ数：４．６万個
基板Ｄ９…面積２４μｍ×１２μｍ、ピッチ：Ｘ方向４８μｍ、Ｙ方向２４μｍ、高さ：３μｍ、バンプ数：１．５万個
基板Ｄ１０…面積７２μｍ×３６μｍ、ピッチ：Ｘ方向１４４μｍ、Ｙ方向７２μｍ、高さ：３μｍ、バンプ数：３４００個
基板Ｄ１１…面積９６μｍ×４８μｍ、ピッチ：Ｘ方向１９２μｍ、Ｙ方向９６μｍ、高さ：３μｍ、バンプ数：８５０個
基板Ｄ１２…面積１４０μｍ×７０μｍ、ピッチ：Ｘ方向２８０μｍ、Ｙ方向１４０μｍ、高さ：３μｍ、バンプ数：４２０個
（工程及びｏ１）電極の接合
　以下に示すｉ）～ｉｉｉ）の手順に従い、工程ｎ１で作製したはんだバンプ付き評価チップと金バンプ付き評価基板とをはんだバンプを介して接続した。
ｉ）ＦＣ３０００Ｗ（東レエンジニアリング製）のステージに金バンプ付き評価基板Ｄ７を置き、はんだバンプ付き評価チップＣ７をヘッドでピックアップし、双方のアライメントマークを利用して金電極同士を対向させ、はんだバンプ付き評価チップＣ７を金バンプ付き評価基板Ｄ７上に配置し、接合前サンプル７を得た。
ｉｉ）ｉ）で得た接合前サンプル７を、ギ酸リフロー炉（神港精機株式会社製、バッチ式真空半田付装置）の下部熱板上に置いた。
ｉｉｉ）ギ酸真空リフロー炉を作動させ、真空引きの後、ギ酸ガスを充填し、下部熱板を１６０℃に昇温し、５分加熱した。その後、真空引きにてギ酸ガスを排出後、窒素置換を行い、下部熱板を室温まで戻し、炉内を大気開放した。評価チップと評価基板の間に粘度を調整したアンダーフィル材（昭和電工マテリアルズ株式会社製、ＣＥＬシリーズ）を適量入れ、真空引きにて充填後、１２５℃で３時間硬化させ、評価チップと評価基板の接続構造体を作製した。接続構造体の作製に用いた各材料の組合せは以下のとおりである。
（７）チップＣ７／はんだバンプ形成部材７／基板Ｄ７
（８）チップＣ８／はんだバンプ形成部材８／基板Ｄ８
（９）チップＣ９／はんだバンプ形成部材９／基板Ｄ９
（１０）チップＣ１０／はんだバンプ形成部材１０／基板Ｄ１０
（１１）チップＣ１１／はんだバンプ形成部材１１／基板Ｄ１１
（１２）チップＣ１２／はんだバンプ形成部材１２／基板Ｄ１２
＜接続構造体の評価＞
　得られた接続構造体の一部について、前述同様に導通抵抗試験及び絶縁抵抗試験を行った。結果を表９、表１０及び表１１に示す。
Figure JPOXMLDOC01-appb-T000009
Figure JPOXMLDOC01-appb-T000010
Figure JPOXMLDOC01-appb-T000011
＜作製例１３～１８＞
　工程ｍ１の基体の作製及び工程ｊ２の評価チップの準備、更に、工程ｎ１のはんだバンプ形成を経て、表８に示すはんだバンプ形成済みの評価チップＣ７～Ｃ１２を得た。
＜接続構造体の作製＞
　以下に示すｉ）～ｉｉｉ）の手順に従い、工程ｎ１で作製したはんだバンプ付き評価チップと工程ｋ２で準備した金バンプ付き評価基板とをはんだバンプを介して接続した。
ｉ）金バンプ付き評価基板をスピンコータにセットし、液状フラックス（ＮＳ－３３４、日本スペリア社製）を金バンプ面側にコートした。
ｉｉ）ｉ）で得た金バンプ付き評価基板をＦＣ３０００Ｗ（東レエンジニアリング製）のステージに置き、はんだバンプ付き評価チップをヘッドでピックアップし、双方のアライメントマークを利用して金電極同士を対向させ、はんだバンプ付き評価チップを金バンプ付き評価基板上に配置し、接合前サンプル１３～１８を得た。
ｉｉｉ）接合前サンプルを、ギ酸リフロー炉（神港精機株式会社製、バッチ式真空半田付装置）の下部熱板上に置いた。
ｉｖ）ギ酸真空リフロー炉を作動させ、真空引きの後、窒素ガスを充填し、下部熱板を１６０℃に昇温し、３分加熱した。その後、真空引きした後、窒素置換を行い、下部熱板を室温まで戻し、炉内を大気開放した。
ｖ）接合サンプルをイソプロピルアルコール液内に浸してフラックス残渣を洗い流した。
ｖｉ）評価チップと評価基板の間に粘度を調整したアンダーフィル材（昭和電工マテリアルズ株式会社製、ＣＥＬシリーズ）を適量入れ、真空引きにて充填後、１２５℃で３時間硬化させ、評価チップと評価基板の接続構造体を作製した。接続構造体の作製に用いた各材料の組合せは以下のとおりである。
（１３）チップＣ７／はんだバンプ形成部材７／基板Ｄ７
（１４）チップＣ８／はんだバンプ形成部材８／基板Ｄ８
（１５）チップＣ９／はんだバンプ形成部材９／基板Ｄ９
（１６）チップＣ１０／はんだバンプ形成部材１０／基板Ｄ１０
（１７）チップＣ１１／はんだバンプ形成部材１１／基板Ｄ１１
（１８）チップＣ１２／はんだバンプ形成部材１２／基板Ｄ１２
＜接続構造体の評価＞
　得られた接続構造体の一部について、前述同様に導通抵抗試験及び絶縁抵抗試験を行った。結果を表１２、表１３及び表１４に示す。
Figure JPOXMLDOC01-appb-T000012
Figure JPOXMLDOC01-appb-T000013
Figure JPOXMLDOC01-appb-T000014
　１…はんだ粒子、２…絶縁性フィルム、２ａ…絶縁性樹脂材料、２ｂ…第一の樹脂層、２ｃ…第一の樹脂層の表面、２ｄ…第二の樹脂層、１０…異方性導電フィルム、３０…第一の回路部材、３１…第一の回路基板、３２…第一の電極、４０…第二の回路部材、４１…第二の回路基板、４２…第二の電極、５５…絶縁樹脂層、６０…基体、６２…凹部、７０…接合部、７１…第一の領域、７２…第二の領域、８０…中間層、１１１…はんだ微粒子。

Claims (6)

  1. 　第一の電極を複数有する第一の回路部材と、
    　第二の電極を複数有する第二の回路部材と、
    　前記第一の電極と前記第二の電極とを電気的に接続する接合部を複数有する中間層と、
    を備え、
    　前記接合部で接続される前記第一の電極及び前記第二の電極の少なくとも一方が金電極であり、
    　複数の前記接合部のうち９０％以上が、前記第一の電極と前記第二の電極とを連結するスズ－金合金を含有する第一の領域と、前記第一の領域に接する、ビスマスを含有する第二の領域と、を含む、
    　接続構造体。
  2. 　前記中間層が、前記第一の回路部材と前記第二の回路部材との間を封止する絶縁性樹脂層を更に有する、請求項１に記載の接続構造体。
  3. 　第一の電極を複数有する第一の回路部材と、第二の電極を複数有する第二の回路部材と、異方性導電フィルムと、を準備する準備工程と、
    　前記第一の回路部材、前記第二の回路部材及び前記異方性導電フィルムを、前記第一の回路部材の前記第一の電極を有する面と前記第二の回路部材の前記第二の電極を有する面とが前記異方性導電フィルムを介して対向するように配置して、前記第一の回路部材、前記異方性導電フィルム及び前記第二の回路部材がこの順で積層した積層体を得る配置工程と、
    　前記積層体を厚み方向に押圧した状態で加熱することにより、前記第一の電極と前記第二の電極とを接合部を介して電気的に接続する接続工程と、
    を含み、
    　前記第一の電極及び前記第二の電極のうち少なくとも一方が金電極であり、
    　前記異方性導電フィルムが、絶縁性樹脂組成物から構成される絶縁性フィルムと、前記絶縁性フィルム中に配置されている複数のはんだ粒子とを含み、
    　前記はんだ粒子がスズ－ビスマス合金を含有し、前記はんだ粒子の平均粒子径が１μｍ～３０μｍであり、前記はんだ粒子のＣ．Ｖ．値が２０％以下であり、
    　前記異方性導電フィルムの縦断面において、前記はんだ粒子が隣接する前記はんだ粒子と離隔した状態で横方向に並ぶように配置されており、
    　前記接続工程で形成される複数の前記接合部のうち９０％以上が、前記第一の電極と前記第二の電極とを連結するスズ－金合金を含有する第一の領域と、前記第一の領域と接する、ビスマスを含有する第二の領域と、を含む、
    　接続構造体の製造方法。
  4. 　前記はんだ粒子が、
    　　複数の凹部を有する基体と、スズ－ビスマス合金を含有するはんだ微粒子と、を準備するはんだ微粒子準備工程と、
    　　前記はんだ微粒子の少なくとも一部を、前記凹部に収容する収容工程と、
    　　前記凹部に収容された前記はんだ微粒子を融合させて、前記凹部の内部にはんだ粒子を形成する融合工程と、
    を含む方法により製造されたはんだ粒子である、請求項３に記載の製造方法。
  5. 　前記はんだ微粒子準備工程で準備される前記はんだ微粒子のＣ．Ｖ．値が２０を超える、請求項４に記載の製造方法。
  6. 　前記異方性導電フィルムが、
    　　前記はんだ粒子が収容された凹部を複数有する基体の、前記凹部の開口側に絶縁性樹脂組成物を接触させて、前記はんだ粒子が転写された第一の樹脂層を得る転写工程と、
    　　前記はんだ粒子が転写された側の前記第一の樹脂層の表面上に、絶縁性樹脂組成物から構成される第二の樹脂層を形成することにより、異方性導電フィルムを得る積層工程と、
    を含む方法により製造された異方性導電フィルムである、請求項３～５のいずれか一項に記載の製造方法。
PCT/JP2020/045304 2019-12-27 2020-12-04 接続構造体及び接続構造体の製造方法 WO2021131620A1 (ja)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230060457A1 (en) * 2021-08-30 2023-03-02 Taiwan Semiconductor Manufacturing Company, Ltd. Chip package structure, chip structure and method for forming chip structure

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0523887A (ja) * 1991-07-19 1993-02-02 Matsushita Electric Ind Co Ltd 金属ボールの形成方法
JP2003007894A (ja) 2001-06-12 2003-01-10 Internatl Business Mach Corp <Ibm> ボール・グリッド・アレイ・モジュール及びその製造方法
JP2012142450A (ja) * 2010-12-29 2012-07-26 Panasonic Corp 多層配線基板、多層配線基板の製造方法
WO2014061085A1 (ja) 2012-10-15 2014-04-24 千住金属工業株式会社 低温ソルダペーストのはんだ付け方法
JP2014084395A (ja) 2012-10-23 2014-05-12 Hitachi Chemical Co Ltd 導電性接着剤組成物、導電性接着剤付金属導線、接続体及び太陽電池モジュールとその製造方法
JP2014225654A (ja) * 2013-04-26 2014-12-04 パナソニックＩｐマネジメント株式会社 配線板間接続構造、および配線板間接続方法
JP2015106654A (ja) 2013-11-29 2015-06-08 富士通株式会社 接合方法、半導体装置の製造方法、及び半導体装置
JP2016076494A (ja) 2014-02-24 2016-05-12 積水化学工業株式会社 導電ペースト、接続構造体及び接続構造体の製造方法
JP2017045832A (ja) * 2015-08-26 2017-03-02 日亜化学工業株式会社 発光装置及び発光装置の製造方法
JP2019029135A (ja) * 2017-07-27 2019-02-21 日立化成株式会社 異方性導電フィルム及びその製造方法、並びに接続構造体及びその製造方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180024029A (ko) * 2010-04-22 2018-03-07 세키스이가가쿠 고교가부시키가이샤 이방성 도전 재료 및 접속 구조체

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0523887A (ja) * 1991-07-19 1993-02-02 Matsushita Electric Ind Co Ltd 金属ボールの形成方法
JP2003007894A (ja) 2001-06-12 2003-01-10 Internatl Business Mach Corp <Ibm> ボール・グリッド・アレイ・モジュール及びその製造方法
JP2012142450A (ja) * 2010-12-29 2012-07-26 Panasonic Corp 多層配線基板、多層配線基板の製造方法
WO2014061085A1 (ja) 2012-10-15 2014-04-24 千住金属工業株式会社 低温ソルダペーストのはんだ付け方法
JP2014084395A (ja) 2012-10-23 2014-05-12 Hitachi Chemical Co Ltd 導電性接着剤組成物、導電性接着剤付金属導線、接続体及び太陽電池モジュールとその製造方法
JP2014225654A (ja) * 2013-04-26 2014-12-04 パナソニックＩｐマネジメント株式会社 配線板間接続構造、および配線板間接続方法
JP2015106654A (ja) 2013-11-29 2015-06-08 富士通株式会社 接合方法、半導体装置の製造方法、及び半導体装置
JP2016076494A (ja) 2014-02-24 2016-05-12 積水化学工業株式会社 導電ペースト、接続構造体及び接続構造体の製造方法
JP2017045832A (ja) * 2015-08-26 2017-03-02 日亜化学工業株式会社 発光装置及び発光装置の製造方法
JP2019029135A (ja) * 2017-07-27 2019-02-21 日立化成株式会社 異方性導電フィルム及びその製造方法、並びに接続構造体及びその製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230060457A1 (en) * 2021-08-30 2023-03-02 Taiwan Semiconductor Manufacturing Company, Ltd. Chip package structure, chip structure and method for forming chip structure
US11894331B2 (en) * 2021-08-30 2024-02-06 Taiwan Semiconductor Manufacturing Company, Ltd. Chip package structure, chip structure and method for forming chip structure

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