WO2021103014A1 - 阵列基板、显示面板、拼接显示面板及显示驱动方法 - Google Patents

阵列基板、显示面板、拼接显示面板及显示驱动方法 Download PDF

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Publication number
WO2021103014A1
WO2021103014A1 PCT/CN2019/122210 CN2019122210W WO2021103014A1 WO 2021103014 A1 WO2021103014 A1 WO 2021103014A1 CN 2019122210 W CN2019122210 W CN 2019122210W WO 2021103014 A1 WO2021103014 A1 WO 2021103014A1
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WIPO (PCT)
Prior art keywords
circuit
pixel
sub
group
shift register
Prior art date
Application number
PCT/CN2019/122210
Other languages
English (en)
French (fr)
Inventor
赵蛟
肖丽
玄明花
郑皓亮
刘冬妮
刘静
齐琪
张振宇
陈亮
陈昊
袁丽君
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN201980002696.2A priority Critical patent/CN113383382B/zh
Priority to JP2022523472A priority patent/JP7422869B2/ja
Priority to KR1020227000706A priority patent/KR20220106735A/ko
Priority to EP19945458.8A priority patent/EP4068258A4/en
Priority to US16/976,858 priority patent/US11373584B2/en
Priority to PCT/CN2019/122210 priority patent/WO2021103014A1/zh
Publication of WO2021103014A1 publication Critical patent/WO2021103014A1/zh
Priority to US17/744,965 priority patent/US11688336B2/en
Priority to US18/307,416 priority patent/US12033571B2/en
Priority to JP2024004286A priority patent/JP2024056691A/ja

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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
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    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
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Definitions

  • the present disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, a spliced display panel, and a display driving method.
  • the display needs to have a larger screen size and a narrower screen. Bezel and better display brightness uniformity.
  • an array substrate includes: a display area, at least one pixel group, and at least one pixel circuit group.
  • the at least one pixel group is located in the display area, and each of the at least one pixel group includes a plurality of pixels arranged in an array.
  • Each of the at least one pixel circuit group is located between two adjacent rows of pixels or two adjacent columns of pixels in the corresponding pixel group.
  • each of the plurality of pixels includes at least one sub-pixel.
  • the at least one pixel circuit group includes at least one pixel driving sub-circuit group.
  • Each of the at least one pixel driving sub-circuit group is electrically connected to two adjacent rows of sub-pixels or two adjacent columns of sub-pixels, and is configured to provide a pixel driving signal to each sub-pixel electrically connected to it.
  • the at least one pixel group is at least two pixel groups.
  • the at least two pixel groups are distributed along the row direction.
  • Each pixel driving sub-circuit group is located between two adjacent columns of sub-pixels in the corresponding pixel group.
  • the length of each pixel driving sub-circuit group along the column direction is smaller than the length of the pixel group along the column direction.
  • the at least one pixel circuit group further includes at least one functional sub-circuit located on at least one side of each pixel driving sub-circuit group along the column direction, and the functional sub-circuit includes a data strobe circuit, an electrostatic protection circuit or a signal routing circuit. Line collection area.
  • the at least one pixel group is at least two pixel groups.
  • the at least two pixel groups are distributed along the column direction.
  • Each pixel driving sub-circuit group is located between two adjacent rows of sub-pixels in the corresponding pixel group.
  • the length of each pixel driving sub-circuit group in the row direction is smaller than the length of the pixel group in the row direction.
  • the at least one pixel circuit group further includes at least one functional sub-circuit located on at least one side of each pixel driving sub-circuit group along the row direction, and the functional sub-circuit includes a data strobe circuit, an electrostatic protection circuit, or a signal routing circuit. Line collection area.
  • the array substrate further includes a shift register circuit.
  • the shift register circuit and the at least one pixel driving sub-circuit group are respectively located between two different rows of pixels or two columns of pixels.
  • the shift register circuit is electrically connected to the at least one pixel driving sub-circuit group, and is configured to provide a scan driving signal to the at least one pixel driving sub-circuit group.
  • the at least one pixel group is at least two pixel groups.
  • the at least two pixel groups are distributed along the row direction.
  • the shift register circuit is located between the two pixel groups or between two adjacent columns of sub-pixels in the corresponding pixel group.
  • the length of the shift register circuit in the column direction is smaller than the length of the pixel group in the column direction.
  • the at least one pixel circuit group further includes at least one functional sub-circuit located on at least one side of the shift register circuit along the column direction; the functional sub-circuit includes a data strobe circuit, an electrostatic protection circuit or a signal wiring assembly Area.
  • the at least one pixel group is at least two pixel groups.
  • the at least two pixel groups are distributed along the column direction.
  • the shift register circuit is located between two pixel groups or between two adjacent rows of sub-pixels in a corresponding pixel group.
  • the length of the shift register circuit in the row direction is smaller than the length of the pixel group in the row direction.
  • the at least one pixel circuit group further includes at least one functional sub-circuit located on at least one side of the shift register circuit along the row direction; the functional sub-circuit includes a data strobe circuit, an electrostatic protection circuit, or a signal wiring assembly line Area.
  • the at least one pixel driving sub-circuit group is a plurality of pixel driving sub-circuit groups.
  • the shift register circuit includes a first shift register circuit and a second shift register circuit. The first shift register circuit and the second shift register circuit are respectively electrically connected to the plurality of pixel driving sub-circuit groups.
  • the at least one pixel driving sub-circuit group is a plurality of pixel driving sub-circuit groups.
  • the shift register circuit includes a first shift register circuit and a second shift register circuit.
  • the first shift register circuit is electrically connected to a part of the pixel driving sub-circuit groups in the plurality of pixel driving sub-circuit groups
  • the second shift register circuit is electrically connected to another of the plurality of pixel driving sub-circuits.
  • a part of the pixel driving sub-circuit group is correspondingly electrically connected.
  • the first shift register circuit and the second shift register circuit are arranged adjacently along the row direction or the column direction.
  • the first shift register circuit and the second shift register circuit are located between two different rows of pixels or two columns of pixels, respectively.
  • the shift register circuit further includes a first backup circuit and a second backup circuit.
  • the first backup circuit is the backup of the first shift register circuit, and is configured to be electrically connected to the corresponding pixel driving sub-circuit group in the event of a failure of the first shift register circuit and to The pixel driving sub-circuit group provides scan driving signals.
  • the second backup circuit is the backup of the second shift register circuit, and is configured to be electrically connected to the corresponding pixel driving sub-circuit group and to the corresponding pixel driving sub-circuit group when the second shift register circuit fails.
  • the pixel driving sub-circuit group provides scan driving signals.
  • the first backup circuit and the first shift register circuit are located between the same two rows of pixels or two columns of pixels.
  • the second backup circuit and the second shift register circuit are located between the same two rows of pixels or two columns of pixels.
  • the array substrate further includes: a substrate, at least one fan-out structure, and at least one side structure.
  • the substrate includes a first surface and a second surface facing away from the first surface.
  • the at least one pixel group and the at least one pixel circuit group are located on the first surface.
  • the at least one fan-out structure is located on the second surface.
  • Each of the at least one fan-out structure includes a plurality of signal connection lines, and the plurality of signal connection lines extend from the edge of the second surface to the non-edge area of the second surface.
  • Each of the at least one side structure includes a plurality of side connection lines.
  • one end of each of the plurality of side connection lines is electrically connected to one signal connection line in the corresponding fan-out structure, and the other end is connected to the corresponding functional sub-circuit.
  • the array substrate includes a shift register circuit, and the shift register circuit is located on the first surface.
  • One end of each of the multiple side connection lines is electrically connected to a signal connection line in the corresponding fan-out structure, and the other end is connected to the corresponding functional sub-circuit or the shift register In the circuit.
  • the display panel includes the array substrate as described in some of the above embodiments.
  • the display panel further includes a control integrated circuit.
  • the control integrated circuit is located on the second surface of the substrate of the array substrate.
  • the control integrated circuit is electrically connected to a plurality of signal connection lines in the corresponding fan-out structure in the array substrate, and is configured to output control signals to the plurality of signal connection lines.
  • a spliced display panel in another aspect, includes: at least two display panels as described in some of the above embodiments spliced with each other.
  • a display driving method is provided.
  • the display driving method is applied to the display panel described in some of the above embodiments.
  • the display driving method includes: controlling each pixel driving sub-circuit group in the at least one pixel circuit group to provide pixel driving signals to two rows of sub-pixels or two columns of sub-pixels corresponding to and electrically connected to the at least one pixel circuit group.
  • the display driving method further includes: a control integrated circuit located on the second surface of the substrate of the array substrate, through at least one side structure, to the control integrated circuit located on the substrate of the array substrate.
  • the at least one pixel circuit group and/or shift register circuit on the first surface respectively transmit control signals.
  • FIG. 1 is a schematic diagram of wiring of an array substrate according to some embodiments
  • FIG. 2 is a schematic diagram of wiring of another array substrate according to some embodiments.
  • FIG. 3 is a schematic diagram of wiring of another array substrate according to some embodiments.
  • FIG. 4 is a schematic diagram of wiring of another array substrate according to some embodiments.
  • FIG. 5 is a schematic diagram of wiring of another array substrate according to some embodiments.
  • Fig. 6 is a structural diagram of a second surface of an array substrate according to some embodiments.
  • FIG. 7 is a cross-sectional view of an edge portion of an array substrate according to some embodiments.
  • FIG. 8 is a cross-sectional view of an edge portion of another array substrate according to some embodiments.
  • FIG. 9 is a structural diagram of a pixel driving sub-circuit according to some embodiments.
  • FIG. 10 is a structural diagram of a shift register according to some embodiments.
  • FIG. 11 is a structural diagram of a data strobe circuit according to some embodiments.
  • FIG. 12 is a cross-sectional view of an edge portion of another array substrate according to some embodiments.
  • FIG. 13 is a structural diagram of a display panel according to some embodiments.
  • FIG. 14 is a structural diagram of a spliced display panel according to some embodiments.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features.
  • plural means two or more.
  • a and/or B includes the following three combinations: A only, B only, and the combination of A and B.
  • the traditional spliced display panel is usually formed by splicing multiple display panels.
  • each display panel is a Liquid Crystal Display (LCD) display panel, but due to the presence of frame sealant and virtual pixels in the LCD display panel, a spliced display panel composed of spliced LCD display panels It is inevitable that there will be seams, so that perfect seamless splicing cannot be achieved.
  • LCD Liquid Crystal Display
  • each display panel is an Organic Light-Emitting Diode (OLED) display panel.
  • OLED Organic Light-Emitting Diode
  • the cathode of each OLED in an OLED display panel is generally formed by evaporation, and the OLED light-emitting device needs to be implemented to block water and oxygen in the air and ensure the life of the display panel, a spliced display composed of spliced OLED display panels The panels will inevitably have seams, which makes it impossible to achieve seamless splicing.
  • Mini-LED display panels and Micro-LED display panels For Mini Light-Emitting Diode (Mini-LED) display panels and Micro-Light-Emitting Diode (Micro-LED) display panels, due to the massive transfer technology in the current production process (Mass Transfer Technology) Due to the limitation of the development level, Mini-LED display panels and Micro-LED display panels have many obstacles in the direct realization of high resolution and large size. Seamless splicing technology can effectively make up for the shortcomings of the current massive transfer technology. It uses Mini-LED display panel or Micro-LED display panel to realize giant screen display.
  • the array substrate 101 includes a display area AA, at least one pixel group 1 and at least one pixel circuit group 2.
  • the at least one pixel group 1 is located in the display area AA, and each of the at least one pixel group 1 includes a plurality of pixels 10 arranged in an array.
  • Each of the at least one pixel circuit group 2 is located between two adjacent rows of pixels 10 or two adjacent columns of pixels 10 in the corresponding pixel group 1.
  • each pixel 10 includes at least one sub-pixel 11.
  • the at least one pixel circuit group 2 includes at least one pixel driving sub-circuit group 20.
  • Each pixel driving sub-circuit group 20 is electrically connected to two adjacent rows of sub-pixels 11 or two adjacent columns of sub-pixels 11, and is configured to provide pixel driving signals to each sub-pixel 11 electrically connected thereto.
  • each pixel 10 includes three sub-pixels 11, which are a red sub-pixel R, a green sub-pixel G and a blue sub-pixel B, respectively.
  • each pixel driving sub-circuit group 20 includes a plurality of independent pixel driving sub-circuits 21, wherein one pixel driving sub-circuit 21 is correspondingly connected to three sub-pixels of one pixel 10.
  • each pixel driving sub-circuit group 20 is placed between two adjacent rows of pixels 10 or two columns of pixels 10, and each pixel driving sub-circuit group 20 is used to direct the corresponding adjacent two pixels 10 respectively.
  • Each sub-pixel 11 in a row or two columns of pixels 10 provides a pixel driving signal, which can effectively realize the integration of the pixel driving sub-circuit 21, that is, the pixel driving sub-circuit 21 corresponding to each sub-pixel 11 on the array substrate 101 is arranged in a modular manner. Between the pixels 10 in some rows or columns, more space can be left in the display area AA of the array substrate, so as to use the space to modularly place other circuits required for the array substrate 101 to display, such as shift registers.
  • each pixel group 1 and the number of pixels 10 in each pixel group 1 can be selected and set according to actual requirements, for example, according to the resolution of the display panel where the array substrate is located.
  • each pixel group 1 includes 12 (2 ⁇ 6) pixels 10, where 2 is the number of columns and 6 is the number of rows.
  • each pixel driving sub-circuit group 20 described above can be located between two columns of pixels 10 in the corresponding pixel group 1.
  • the width of each pixel group 1 in the row direction or the column direction is limited to realize the distribution of the corresponding pixel driving sub-circuit group 20 therein. At least one of the intervals between two adjacent pixel groups 1 in the row direction or the column direction is greater than 70 ⁇ m.
  • each pixel 10 of the array substrate 101 is applied to a Micro-LED display panel or a Mini-LED display panel. Because Micro-LED or Mini-LED has a small size and high luminous intensity, each pixel 10 of the array substrate 101 can occupy only 10% of the area of the pixel 10 at the minimum. Therefore, there is enough space in each pixel 10 of the array substrate 101 or between the adjacent pixels 10 to dispose the electrical components of each circuit.
  • the number of pixel groups 1 is at least two.
  • the at least two pixel groups 1 are distributed along the row direction, that is, each pixel 10 on the array substrate 101 is divided into at least two groups along the row direction.
  • Each pixel driving sub-circuit group 20 is located between two adjacent columns of sub-pixels 11 in the corresponding pixel group 1.
  • the length of each pixel driving sub-circuit group 20 in the column direction is less than the length of the pixel group 1 in the column direction, that is, each pixel driving sub-circuit group 20 is centrally arranged between some pixels 10 in the corresponding two columns of pixels 10, As a result, space is left on at least one side of each pixel driving sub-circuit group 20 along the column direction.
  • the at least one pixel circuit group 2 further includes at least one functional sub-circuit 30 located on at least one side of each pixel driving sub-circuit group 20 along the column direction.
  • the functional sub-circuit 30 includes a data strobe (MUX) circuit, an electrostatic protection (ESD) circuit or a signal wiring collection area.
  • the signal wiring concentrating area refers to the concentrated lead-out ends of multiple signal lines in the display area AA, which are configured to bind each signal line to an external input circuit, such as a power supply voltage terminal, a common voltage terminal, and a clock signal terminal.
  • the pixel groups 1 are distributed along the row direction, for example, at equal intervals, so that at least one side of each pixel driving sub-circuit group 20 along the column direction appears to be located on at least one side of the array substrate 101 corresponding to the column direction.
  • One side (such as the top side, bottom side, or both sides of the top and bottom as shown in Figure 1). Therefore, the space utilization rate of the display area AA of the array substrate 101 can be effectively improved, so that other functional sub-circuits 30 required for the display of the array substrate 101 can be placed reasonably and easily, such as shift register circuits, data strobe (MUX) circuits or electrostatic protection. (Electro-Static discharge, ESD for short) circuit, etc.
  • MUX data strobe
  • the frame of the array substrate 101 can be effectively reduced or even eliminated, so as to facilitate seamless splicing of the display panels.
  • the pixel driving sub-circuit groups 20 and the functional sub-circuits 30 in the array substrate 101 are regularly distributed in the display area AA in a modular manner, which can also effectively reduce the risk of static electricity and additional capacitance.
  • the size of the aforementioned array substrate 101 is selected and set according to actual requirements, for example, set to a smaller size. In this way, by taking the display panel corresponding to each array substrate 101 as the smallest splicable unit, a large-size display panel of any size can be formed by splicing.
  • each pixel drive sub-circuit group 20 is centrally arranged between the pixels 10 of the corresponding two columns 10, the smaller the number of pixels 10, the more abundant space arrangement can be obtained.
  • the wire resistance between each pixel driving sub-circuit 21 in each pixel driving sub-circuit group 20 and the corresponding sub-pixel 11 needs to be equal or approximately equal.
  • the difference in wire resistance between any two pixel driving sub-circuits 21 in each pixel driving sub-circuit group 20 and the corresponding sub-pixel 11 is not greater than 100 ohms, so that any two pixel driving sub-circuits
  • the delay of the signal transmitted from 21 to the corresponding sub-pixel 11 does not exceed 0.01 ⁇ s at the maximum, which can meet the demand for display uniformity.
  • the number of pixel groups 1 is at least two.
  • the at least two pixel groups 1 are distributed along the column direction.
  • Each pixel driving sub-circuit group 20 is located between two adjacent rows of sub-pixels 11 in the corresponding pixel group 1.
  • the length of each pixel driving sub-circuit group 20 in the row direction is smaller than the length of the pixel group 1 in the row direction.
  • the at least one pixel circuit group 2 further includes at least one functional sub-circuit 30 located on at least one side of each pixel driving sub-circuit group 20 along the row direction.
  • the functional sub-circuit 30 includes a data strobe (MUX) circuit, an electrostatic Protection (ESD) circuit or signal trace collection area (Side wire pin bonding).
  • the pixel groups 1 are distributed along the column direction, for example, at equal intervals, so that at least one side of each pixel driving sub-circuit group 20 along the row direction appears to be located on the array substrate 101 corresponding to the row direction. At least one side (for example, the left side, the right side, or the left and right sides shown in Figure 2).
  • the beneficial effects that the array substrate 101 with the above structure can have can refer to the beneficial effects of the corresponding array substrate 101 when the pixel groups 1 are linearly distributed along the rows. I won't repeat them here.
  • each pixel driving sub-circuit 21 in each pixel driving sub-circuit group 20 of the array substrate 101 generally requires the shift control signal output by the shift register circuit to be turned on in sequence.
  • the array substrate 101 further includes a shift register circuit 4.
  • the shift register circuit 4 and the aforementioned at least one pixel driving sub-circuit group 20 are respectively located between two different rows of pixels 10 or two columns of pixels 10.
  • the shift register circuit 4 is located in the interval between two adjacent pixel groups 1 in the row direction or the column direction, or is located in two adjacent rows of sub-pixels 11 or two columns of sub-pixels in the corresponding pixel group 10 In the interval between 11, the interval is greater than 70 ⁇ m.
  • placing the shift register circuit 4 between the corresponding two rows of pixels 10 or two columns of pixels 10 can effectively reduce or even eliminate the frame of the array substrate 101 to facilitate seamless splicing of display panels.
  • the shift register circuit 4 adopts the above arrangement method, which not only can avoid splitting the shift register circuit 4 to reduce the signal transmission delay caused by this, but also helps simplify the design difficulty of the layout of the array substrate 101 (for example, : Realize the layout array of small-size layout units), thereby improving layout design efficiency and subsequent corresponding inspection efficiency.
  • the electronic components such as thin film transistors in the shift register circuit 4 do not need to be split and dispersed into each pixel 10, which can effectively reduce the wiring complexity of the array substrate 101, reduce additional parasitic capacitance, and avoid the array substrate 101 There are problems such as reduced aperture ratio and electrostatic interference.
  • the shift register circuit 4 is electrically connected to the at least one pixel driving sub-circuit group 20 correspondingly, and is configured to provide a scan driving signal to the at least one pixel driving sub-circuit group 20.
  • the pixel driving sub-circuits 21 corresponding to a plurality of pixels 10 in at least one row or at least one column are electrically connected to the same scanning signal line.
  • the shift register circuit 4 is electrically connected to the at least one pixel driving sub-circuit group 20 described above, and the shift register circuit 4 is electrically connected to the corresponding pixel driving sub-circuit 21 through each scanning signal line to drive each pixel.
  • the sub-circuit 21 provides a scan driving signal.
  • the scan signal line includes a gate scan signal line or a light-emitting scan signal line.
  • the number of pixel groups 1 is at least two.
  • the at least two pixel groups 1 are distributed along the row direction.
  • the shift register circuit 4 is located between two pixel groups 10 or between two adjacent columns of sub-pixels 11 in the corresponding pixel group 10.
  • the length of the shift register circuit 4 in the column direction is smaller than the length of the pixel group 1 in the column direction, that is, the shift register circuit 4 is centrally arranged between some of the pixels 10 in the two columns of pixels 10, so that the shift register circuit 4 There will be space on at least one side along the column direction.
  • the at least one pixel circuit group 2 further includes at least one functional sub-circuit 30 located on at least one side of the shift register circuit 4 along the column direction; the functional sub-circuit 30 includes a data strobe (MUX) circuit, electrostatic protection (ESD) Circuit or signal trace collection area.
  • MUX data strobe
  • ESD electrostatic protection
  • each pixel group 1 is linearly distributed along the row direction, so that at least one side of the shift register circuit 4 appears to be located on at least one side of the array substrate 101 corresponding to the column direction (for example, the top as shown in FIG. Side, bottom side or top and bottom sides). Therefore, the space utilization rate in the display area AA of the array substrate 101 can be further improved, so that other functional sub-circuits 30 required for the display of the array substrate 101 can be placed reasonably and easily. Furthermore, the frame of the array substrate 101 is effectively reduced or even eliminated, so as to facilitate seamless splicing of the display panels.
  • the shift register circuit 4 is centrally arranged between the few pixels 10 corresponding to the two columns of pixels 10, the more abundant space can be obtained.
  • the wire resistance between the shift register circuit 4 and each scanning signal line needs to be equal or approximately equal.
  • the difference between the wire resistance between the shift register circuit 4 and any two scanning signal lines in each scanning signal line is not more than 100 ohms, so that the shift register circuit 4 sends the signal to the any two scanning signal lines.
  • the maximum delay of the transmitted signal will not exceed 0.01 ⁇ s, which can meet the needs of display uniformity.
  • the number of pixel groups 1 is at least two.
  • the at least two pixel groups 1 are distributed along the column direction.
  • the shift register circuit 4 is located between two pixel groups 1 or between two adjacent rows of sub-pixels 11 in the corresponding pixel group 1.
  • the length of the shift register circuit 4 in the row direction is smaller than the length of the pixel group 1 in the row direction.
  • the at least one pixel circuit group 2 also includes at least one functional sub-circuit 3 located on at least one side of the shift register circuit 4 along the row direction; the functional sub-circuit 3 includes a data strobe (MUX) circuit, electrostatic protection (ESD ) Circuit or signal wiring concentrating area.
  • MUX data strobe
  • ESD electrostatic protection
  • each pixel group 1 is linearly distributed along the column direction, so that at least one side of the shift register circuit 4 appears to be located on at least one side of the array substrate 101 corresponding to the row direction (for example, the left side shown in FIG. 2 Side, right side or left and right sides).
  • the beneficial effects that the array substrate with the above structure can have can refer to the beneficial effects of the corresponding array substrate 101 when the pixel groups 1 are linearly distributed along the rows. I won't repeat them here.
  • the shift register circuit 4 includes a first shift register circuit 41 and a second shift register circuit 42, which facilitates the double-sided driving of the solid line scan signal, thereby effectively improving the array The display uniformity of the display panel where the substrate 101 is located.
  • the positions of the first shift register circuit 41 and the second shift register circuit 42 in the display area AA can be set according to actual requirements.
  • the first shift register circuit 41 and the second shift register circuit 42 are located in the middle area of the display area AA, that is, the first shift register circuit 41 and the second shift register circuit 42 are displayed from the display area respectively.
  • the middle area in the area AA transmits scan driving signals to both sides thereof.
  • the first shift register circuit 41 and the second shift register circuit 42 are respectively located in the inwardly extending part of the two sides of the display area AA, that is, the first shift register circuit 41 and the second shift register circuit 41
  • the bit register circuit 42 can respectively transmit scanning driving signals from both sides in the display area AA to the center, which is also allowed. Some embodiments of the present disclosure do not limit this.
  • the arrangement positions of the first shift register circuit 41 and the second shift register circuit 42 in the array substrate 101 are based on the size of the interval formed between two adjacent rows or columns of pixels 10 in the array substrate 101. determine.
  • the first shift register circuit 41 and the second shift register circuit 42 are arranged adjacently along the row direction or the column direction, which is convenient for wiring design and production.
  • the first shift register circuit 41 and the second shift register circuit 42 are respectively located between two different rows of pixels 10 or two columns of pixels 10, which is beneficial to improve display uniformity.
  • the array substrate includes a plurality of pixel drive sub-circuit groups 20, and the first shift register circuit 41 and the second shift register circuit 42 are electrically connected to the respective pixel drive sub-circuit groups 20, that is, the first shift register circuit
  • the bit register circuit 41 and the second shift register circuit 42 are electrically connected to the same pixel driving sub-circuit group 20, respectively.
  • the first shift register circuit 41 is electrically connected to a part of the pixel driving sub-circuit group 20 in each pixel driving sub-circuit group 20 correspondingly.
  • the second shift register circuit 42 is electrically connected to another part of the pixel driving sub-circuit group 20 in each pixel driving sub-circuit group 20 correspondingly. That is, the first shift register circuit 41 and the second shift register circuit 42 are electrically connected to different pixel driving sub-circuit groups 20, respectively.
  • the first shift register circuit 41 is electrically connected to the pixel driving sub-circuit group 20, which means that the first shift register circuit 41 is connected to each of the pixel driving sub-circuit groups 20 through a plurality of scanning signal lines.
  • the pixel driving sub-circuit is correspondingly electrically connected.
  • the second shift register circuit 42 is electrically connected to the pixel driving sub-circuit group 20 correspondingly, and the second shift register circuit 42 is correspondingly electrically connected to each pixel driving sub-circuit in the pixel driving sub-circuit group 20 through a plurality of scanning signal lines. .
  • the shift register circuit 4 further includes a first backup circuit 43 and a second backup circuit 44.
  • the first backup circuit 43 is a backup of the first shift register circuit 41, and is configured to be electrically connected to the corresponding pixel driving sub-circuit group 20 and drive to the corresponding pixel when the first shift register circuit 41 fails.
  • the sub-circuit group provides scan driving signals.
  • the second backup circuit 44 is the backup of the second shift register circuit 42, and is configured to be electrically connected to the corresponding pixel driving sub-circuit group 20 and drive to the corresponding pixel in the event that the second shift register circuit 42 fails
  • the sub-circuit group 20 provides scan driving signals.
  • the first backup circuit 43 is the backup of the first shift register circuit 41, which means that the electronic components included in the two and their connection modes and working principles are the same.
  • the first backup circuit 43 is usually vacantly placed in the array substrate 101 (that is, it is not electrically connected to other circuits and exists in the form of a redundant circuit). In this way, when the first shift register circuit 41 fails, the first backup circuit 43 is electrically connected to the corresponding pixel drive sub-circuit group 20 by means of laser repair, etc., so that the first backup circuit 43 can be used to replace the first backup circuit 43.
  • the shift register circuit 41 provides scan driving signals to the corresponding pixel driving sub-circuit group to ensure the normal use of the array substrate.
  • first backup circuit 43 and the first shift register circuit 41 may be located on different film layers. In this way, the first backup circuit 43 can also perform electrostatic protection on the first shift register circuit 41, thereby effectively improving the array The yield of the substrate and the corresponding display panel.
  • the relationship between the second backup circuit 44 and the second shift register circuit 42 can be correspondingly referred to the related expressions between the first backup circuit 43 and the first shift register circuit 41, which will not be described in detail here.
  • first backup circuit 43 and the first shift register circuit 41 are located between the same two rows of pixels 10 or two columns of pixels 10.
  • the second backup circuit 44 and the second shift register circuit 42 are located between the same two rows of pixels 10 or two columns of pixels 10.
  • the orthographic projections of the first backup circuit 43 and the first shift register circuit 41 on the substrate in the array substrate overlap or roughly overlap or do not overlap , Are allowed.
  • the orthographic projections of the second backup circuit 44 and the second shift register circuit 42 on the substrate in the array substrate overlap or substantially overlap or do not overlap, which are also allowed.
  • the substrate 100 of the array substrate 101 includes a first surface S1 and a second surface S2 facing away from the first surface S1.
  • Each pixel group 1, each pixel circuit group 2 and the shift register circuit 4 in some of the above embodiments are respectively located on the first surface S1 of the substrate 100.
  • the array substrate 101 further includes at least one fan-out structure 200 located on the second surface S2 of the substrate 100, and located on the first surface S1 and the second surface S1 of the substrate 100. At least one side structure 300 on the side surface between the two surfaces S2.
  • Each fan-out structure 200 includes a plurality of signal connection lines 201 extending from the edge of the second surface S2 of the substrate 100 to its non-edge area.
  • Each fan-out structure 200 further includes a signal binding end 202 electrically connected to the plurality of signal connection lines 201, and the signal binding end 202 is configured to be bound to an external input circuit.
  • External input circuits include control integrated circuits, flexible circuit boards, or printed circuit boards.
  • Each side structure 300 includes a plurality of side connection lines 301, wherein one end of each side connection line 301 is electrically connected to a signal connection line 201 in the corresponding fan-out structure 200, and the other end is connected to the corresponding function In the sub-circuit 3 or in the shift register circuit 4.
  • the fan-out structure 200 and the side structure 300 may have a one-to-one correspondence, or multiple side structures 300 may correspond to one fan-out structure 200.
  • the number and specific positions of the fan-out structure 200 and the side structure 300 can be selected and set according to actual requirements, so as to facilitate wiring and accurately realize the electrical connection of the corresponding line.
  • Each signal connection line 201 and each side connection line 301 are made of conductive material.
  • the conductive material is metal or conductive silver glue, where the metal includes at least one of silver or copper, which can ensure the signal connection
  • the wire 201 and each side connecting wire 301 have good conductivity.
  • the side structure 300 is located on the side surface between the first surface S1 and the second surface S2 of the substrate 100, and can be arranged in various ways.
  • the orthographic projection of the side structure 300 on the second surface S2 of the substrate 100 and the orthographic projection of the corresponding fan-out structure 200 on the second surface S2 have no overlap (as shown in FIG. 7) or partially overlap (as shown in FIG. Shown in Figure 8).
  • the fan-out structure 200 is provided on the second surface S2 of the substrate 100, and the side structure 300 is provided on the side surface of the substrate 100, which can route the signals originally located in the non-display area of the array substrate. It is arranged on the side surface of the substrate 100 and the second surface S2, so that the frame size of the array substrate can be further reduced or even eliminated, so as to facilitate seamless splicing.
  • the pixel groups 1, the pixel circuit groups 2 and the shift register circuit 4 and other circuit structures can be formed on the first surface S1 of the substrate 100 first, and then the substrate 100
  • the fan-out structures 200 are formed on the second surface S2 of the substrate 100; alternatively, the fan-out structures 200 may be formed on the second surface S2 of the substrate 100 first, and then the pixel groups are formed on the first surface S1 of the substrate 100 1.
  • each side structure 300 is formed on the side surface of the substrate 100 located between the first surface S1 and the second surface S2.
  • Each side structure 300 can be prepared by one of 3D printing, photocopying, sputtering, or etching.
  • the following description takes the array substrate in a Micro-LED display panel or a Mini-LED display panel as an example.
  • the LED binding end of each sub-pixel in each pixel 10 is located at The middle area of the pixel 10 and the size L of each LED binding end close to the edge of the display area AA from its corresponding edge is usually a fixed value, for example, between 150 ⁇ m and 200 ⁇ m.
  • functional sub-circuits 30 such as data strobe circuits, electrostatic protection circuits, and signal wiring concentrating areas that occupy a large space in the array substrate are placed in an area close to the edge of the display area AA, for example, placed in the first row of pixels 10 In the space corresponding to the second row of pixels 10, or in the space corresponding to the last row of pixels 10 and the penultimate row of pixels 10, the layout of each circuit structure in the array substrate can be designed more reasonably, and the display area AA of the array substrate can be effectively provided. Utilization of space within.
  • an electrostatic protection circuit 32 and signal wiring are provided in the space of a part of the row of pixels 10 or a part of the column of pixels 10 extending inwardly from the edge area of the display area AA or its surrounding edges.
  • the concentrating area 33 is convenient to realize its electrical connection with an external input circuit (such as an integrated circuit IC) through the side structure 300 located on the side of the substrate 100, for example, through the fan-out structure 200 corresponding to the side structure 300 and the external input Circuit binding.
  • the static electricity protection circuit 32 and the signal wiring collection area 33 may be arranged in a ring shape along the edge of the display area AA.
  • a data strobe circuit 31 is arranged in the space of some rows of pixels 10 extending inward from the peripheral edge of the display area AA, and a pixel driving sub-circuit group 20 and a shift register are arranged in the space of some columns of pixels 10 in the display area AA. Circuit 4 can effectively reduce the overlap of the two signals to reduce the signal transmission delay.
  • each type of signal line (such as the light-emitting signal line EM, the enable signal line Vinit, the reset signal line Reset or the reference voltage line Vref, etc.) in the display area AA of the array substrate is connected in a grid pattern, and The form of global input of the entire panel can reasonably reduce the difference of corresponding signal input.
  • the structure of the pixel driving sub-circuit 21 is as shown in FIG. 9.
  • the pixel driving sub-circuit 21 includes: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a first storage capacitor C1, and a light emitting device D.
  • the first electrode of the first transistor T1 is connected to the initial voltage signal terminal Vint.
  • the second electrode of the first transistor T1 is connected to the second electrode of the first storage capacitor C1, the first electrode of the second transistor T2 and the control electrode of the third transistor T3.
  • the control electrode of the first transistor T1 is connected to the reset signal terminal Reset.
  • the second electrode of the second transistor T2 is connected to the second electrode of the third transistor T3 and the first electrode of the sixth transistor T6.
  • the gate of the second transistor T2 is connected to the gate scan signal line Gate.
  • the first pole of the third transistor T3 is connected to the first power supply voltage terminal VDD.
  • the first electrode of the fourth transistor T4 is connected to the data line Data.
  • the second electrode of the fourth transistor T4 is connected to the second electrode of the fifth transistor T5, the second electrode of the seventh transistor T7 and the first electrode of the first storage capacitor C1.
  • the gate of the fourth transistor T4 is connected to the gate scan signal line Gate.
  • the first electrode of the fifth transistor T5 is connected to the reference voltage signal terminal Vref.
  • the control electrode of the fifth transistor T5 is connected to the light-emitting scanning signal line EM.
  • the second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting device D.
  • the control electrode of the sixth transistor T6 is connected to the light-emitting scanning signal line EM.
  • the first electrode of the seventh transistor T7 is connected to the reference voltage signal terminal Vref.
  • the control electrode of the seventh transistor T7 is connected to the reset signal terminal Reset.
  • the second pole of the light emitting device is connected to the second power supply voltage terminal VSS.
  • the shift register circuit 4 includes a plurality of cascaded shift registers, wherein the structure of each shift register is as shown in FIG. 9.
  • the shift register includes: an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, and a second storage capacitor C2 and the third storage capacitor C3.
  • the first electrode of the eighth transistor T8 is connected to the signal input terminal Input.
  • the second terminal of the eighth transistor T8 is connected to the N1 node.
  • the control electrode of the eighth transistor T8 is connected to the first clock signal terminal CLK.
  • the first pole of the ninth transistor T9 is connected to the first clock signal terminal CLK.
  • the second electrode of the ninth transistor T9 is connected to the N2 node.
  • the control electrode of the ninth transistor T9 is connected to the N1 node.
  • the first pole of the tenth transistor T10 is connected to the low-level signal terminal VGL.
  • the second electrode of the tenth transistor T10 is connected to the N2 node.
  • the control electrode of the tenth transistor T10 is connected to the first clock signal terminal CLK.
  • the first pole of the eleventh transistor T11 is connected to the high-level signal terminal VGH and the second pole of the third storage capacitor C3.
  • the second pole of the eleventh transistor T11 is connected to the signal output terminal Output.
  • the control electrode of the eleventh transistor T11 is connected to the N2 node.
  • the first pole of the third storage capacitor C3 is connected to the N2 node.
  • the first pole of the twelfth transistor T12 is connected to the second clock signal terminal CLKB.
  • the second pole of the twelfth transistor T12 is connected to the second pole of the second storage capacitor C2 and the signal output terminal Output.
  • the control electrode of the twelfth transistor T12 is connected to the first electrode of the second storage capacitor C2.
  • the first pole of the thirteenth transistor T13 is connected to the high-level signal terminal VGH.
  • the second electrode of the thirteenth transistor T13 is connected to the first electrode of the fourteenth transistor T14.
  • the control electrode of the thirteenth transistor T13 is connected to the N2 node.
  • the second electrode of the fourteenth transistor T14 is connected to the N1 node.
  • the control electrode of the fourteenth transistor T14 is connected to the second clock signal terminal CLKB.
  • the first pole of the fifteenth transistor T15 is connected to the N1 node.
  • the second electrode of the fifteenth transistor T15 is connected to the first electrode of the second storage capacitor C2.
  • the data strobe circuit 31 includes a sixteenth transistor T16, a seventeenth transistor T17, and an eighteenth transistor T18.
  • the first pole of the sixteenth transistor T16, the first pole of the seventeenth transistor T17, and the first pole of the eighteenth transistor T18 are connected together, and the data voltage lead-in line Data1' is connected to the source driver (in the figure) Not shown) connection.
  • the second electrode of the sixteenth transistor T16 is connected to the first data line Data11, and the control electrode of the sixteenth transistor T16 is connected to the first output terminal of the timing controller (not shown in the figure).
  • the second electrode of the seventeenth transistor T17 is connected to the second data line Data12, and the control electrode of the seventeenth transistor T17 is connected to the second output terminal of the timing controller.
  • the second electrode of the eighteenth transistor T18 is connected to the third data line Data13, and the control electrode of the eighteenth transistor T18 is connected to the third output terminal of the timing controller.
  • the transistors used in some of the above examples may be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistors used are symmetrical, there is no difference between the source and the drain.
  • the source and drain of a transistor are distinguished.
  • One of the electrodes is called the first electrode, the other is called the second electrode, and the gate is called the control electrode.
  • transistors can be divided into N-type and P-type.
  • the first pole is the source of the P-type transistor
  • the second pole is the drain of the P-type transistor.
  • the source and drain are turned on.
  • the first pole is the source of the N-type transistor
  • the second pole is the drain of the N-type transistor.
  • the gate is input with a high level, the source and drain are turned on.
  • the transistors in the above-mentioned pixel driving sub-circuit 21 are all described using N-type transistors as an example. It is conceivable that the implementation of P-type transistors can be easily thought of by those skilled in the art without creative work. Therefore, it is also within the scope of protection of the present disclosure.
  • the array substrate 101 adopts the structure shown above, and a certain side connection line 301 in the side structure 300 is connected to a signal connection line 201 in the corresponding fan-out structure 200, and is connected to the display area AA.
  • a corresponding pixel driving sub-circuit 21 is connected to the pixel driving sub-circuit 21 to transmit a data signal.
  • the connection structure of the side connecting line 301 with the corresponding signal connecting line 201 and the corresponding pixel driving sub-circuit 21 is shown in FIG. 12.
  • FIG. 12 is only a schematic illustration of the positional relationship of the film layers in the edge portion of the array substrate 101, and does not limit the structure of the array substrate 101.
  • FIG. 12 only illustrates some devices, such as the fourth transistor T4, the sixth transistor T6, etc., wherein the fourth transistor T4 and the sixth transistor T3 are top-gate thin film transistors as an example for description.
  • the array substrate 101 includes: a substrate 100, a buffer layer 110 located on the second surface S1 of the substrate 100; an active layer of a fourth transistor T4 located on the buffer layer 110 and arranged in the same layer and The active layer of the sixth transistor T6; the gate insulating layer 120 located on the active layer of the fourth transistor T4 and the active layer of the sixth transistor T6; located on the gate insulating layer 120 and in the same layer
  • the gate of the fourth transistor T4 and the gate of the sixth transistor T6 are provided; the first insulating layer 130 on the layer where the gate of the fourth transistor T4 and the gate of the sixth transistor T6 are located; and the first insulating layer Above 130, the source and drain of the fourth transistor T4, the source and drain of the sixth transistor T6, and the data line Data connected to the source of the fourth transistor T4 are arranged in the same layer; located in the fourth transistor T4
  • the first electrode of the light emitting device D is electrically connected to the first conductive pad 171 through the fifth via hole penetrating the third passivation layer 180, and the second electrode is electrically connected to the first conductive pad 171 through the fifth via hole penetrating the third passivation layer 180. It is electrically connected to the second conductive pad 172.
  • a signal connection line 201 is provided on the second surface of the substrate 100, a fourth passivation layer 190 is located on the signal connection line 201; the signal binding terminal 202 and the second solder are located on the fourth passivation layer 190 Disk 192; wherein the second pad 192 is connected to one end of the signal connection line 201 through a sixth via hole that penetrates the fourth passivation layer 190, and the signal binding end 202 is connected through a seventh via hole that penetrates the fourth passivation layer 190 Connected to the other end of the signal connection line 201; the first sub-signal lead-in line 151 is connected to the first pad 191 of the signal wiring hub area, and the first pad 191 is connected to the second side of the substrate 100 through the side connection line 301 The second pad 192 on the surface is connected.
  • the control IC 5 is electrically connected to the middle signal binding end 202 of the array substrate substrate 100, and is configured to output a control signal to the signal binding end 202.
  • the first conductive pad 171 and the second conductive pad 172 are respectively electrically connected to the two pins of the light emitting device D.
  • the light emitting device D may be a miniature inorganic light emitting diode, and further, it may be a current type light emitting diode, such as a miniature light emitting diode. Micro Light Emitting Diode (Micro LED) or Mini Light Emitting Diode (Mini LED).
  • the light emitting device D may also be an organic light emitting diode (OLED), so that one of the first electrode and the second electrode of the light emitting device D is the anode, and the other The one is the cathode.
  • OLED organic light emitting diode
  • Some embodiments of the present disclosure provide a display panel and a display driving method.
  • the display panel 1001 includes the array substrate 101 as described in the above embodiments.
  • the display driving method is applied to the display panel 1001.
  • the display driving method includes: controlling each pixel driving sub-circuit group 20 in the at least one pixel circuit group 2 to provide pixels corresponding to two rows of sub-pixels 11 or two columns of sub-pixels 11 that are adjacent and electrically connected to it. Drive signal.
  • the beneficial effects that can be achieved by the display panel 1001 and the display driving method provided by some embodiments of the present disclosure are the same as the beneficial effects that can be achieved by the array substrate 101 described in the foregoing embodiments, and will not be repeated here.
  • the display panel 1001 further includes a control integrated circuit (Integrated Circuit, IC for short) 5.
  • the control IC 5 is located on the second surface S2 of the substrate 100 of the array substrate 101.
  • the control IC 5 is electrically connected to a plurality of signal connection lines 201 of the corresponding fan-out structure 200 in the array substrate 101 and is configured to output control signals to the plurality of signal connection lines 201.
  • control signals output by the control IC 5 to the multiple signal connection lines 201 can be transmitted to the circuit structures in the display area AA of the array substrate 101 via the side connection lines 301 in the corresponding side structure 300.
  • the display driving method applied to the display panel 1001 further includes: controlling the IC5 to transmit to the at least one pixel circuit group located on the first surface S1 of the substrate 100 of the array substrate 101 through the at least one side structure 300 2 and/or shift register circuit 4 respectively transmit control signals.
  • control IC5 is located on the second surface S2 of the substrate 100, and the control IC5 can input control signals on the back of the display area AA of the array substrate 101, thereby effectively reducing the array
  • the requirement of the substrate 101 for the non-display area on the first surface S1 can reduce or even eliminate the frame of the array substrate 101 to facilitate seamless splicing.
  • the display panel 1001 further includes a flexible printed circuit (FPC) on the second surface S2 of the substrate 100 of the array substrate 101.
  • the flexible circuit board may be electrically connected to a plurality of signal connection lines 201 of the corresponding fan-out structure 200 in the array substrate 101 through a flip chip film or a lead, and is configured to output signals to the plurality of signal connection lines 201.
  • the display panel 1001 is a Micro-Light Emitting Diode (Micro-LED) display panel or a Mini Light Emitting Diode (Mini-LED) display panel.
  • the above-mentioned display panel 1001 may be a liquid crystal display (LCD) or an organic light-emitting diode (OLED) display panel.
  • the spliced display panel 1000 includes at least two display panels 1001 as described in the above embodiments that are spliced to each other.
  • the spliced display panel is formed by seamless splicing of four display panels 1001. There is no splicing gap in the display picture of the spliced display panel, or the splicing gap is extremely small and difficult to be observed.
  • the spliced display panel can have a large-sized display screen and excellent display image quality.
  • Each display panel in the spliced display panel of some embodiments of the present disclosure is the same as the display panel described in some of the above embodiments, and the beneficial effects that can be achieved will not be repeated here.

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Abstract

一种阵列基板（101），包括：显示区（AA）、至少一个像素组（1）和至少一个像素电路组（2）。至少一个像素组（1）位于显示区（AA）内，至少一个像素组（1）中的每个包括阵列设置的多个像素（10）。至少一个像素电路组（2）中的每个位于对应的像素组（1）内相邻两行像素（10）或相邻两列像素（10）之间。

Description

阵列基板、显示面板、拼接显示面板及显示驱动方法 技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板、显示面板、拼接显示面板及显示驱动方法。
背景技术
随着显示技术的不断发展，消费者对显示装置在屏幕尺寸、边框宽度、显示亮度和显示画质等方面的性能要求越来越高，例如需要显示屏具有较大的屏幕尺寸、较窄的边框以及较好的显示亮度均一性。
发明内容
一方面，提供一种阵列基板。所述阵列基板包括：显示区、至少一个像素组和至少一个像素电路组。所述至少一个像素组位于所述显示区内，所述至少一个像素组中的每个包括阵列设置的多个像素。所述至少一个像素电路组中的每个位于对应的所述像素组内相邻两行像素或相邻两列像素之间。
在一些实施例中，所述多个像素中的每个包括至少一个子像素。所述至少一个像素电路组包括至少一个像素驱动子电路组。所述至少一个像素驱动子电路组中的每个与对应相邻的两行子像素或相邻的两列子像素电连接，且配置为向与其电连接的各子像素提供像素驱动信号。
在一些实施例中，所述至少一个像素组为至少两个像素组。所述至少两个像素组沿行方向分布。所述每个像素驱动子电路组位于对应的所述像素组内相邻的两列子像素之间。所述每个像素驱动子电路组沿列方向的长度小于所述像素组沿列方向的长度。所述至少一个像素电路组还包括沿列方向位于所述每个像素驱动子电路组的至少一侧的至少一个功能子电路，所述功能子电路包括数据选通电路、静电防护电路或信号走线集线区。
在另一些实施例中，所述至少一个像素组为至少两个像素组。所述至少两个像素组沿列方向分布。所述每个像素驱动子电路组位于对应的所述像素组内相邻的两行子像素之间。所述每个像素驱动子电路组沿行方向的长度小 于所述像素组沿行方向的长度。所述至少一个像素电路组还包括沿行方向位于所述每个像素驱动子电路组的至少一侧的至少一个功能子电路，所述功能子电路包括数据选通电路、静电防护电路或信号走线集线区。
在一些实施例中，所述阵列基板还包括一移位寄存器电路。所述移位寄存器电路与所述至少一个像素驱动子电路组分别位于不同的两行像素或两列像素之间。所述移位寄存器电路与所述至少一个像素驱动子电路组对应电连接，且配置为向所述至少一个像素驱动子电路组提供扫描驱动信号。
在一些实施例中，所述至少一个像素组为至少两个像素组。所述至少两个像素组沿行方向分布。所述移位寄存器电路位于两个所述像素组之间或位于对应的所述像素组内相邻的两列子像素之间。所述移位寄存器电路的沿列方向的长度小于所述像素组沿列方向的长度。所述至少一个像素电路组还包括沿列方向位于所述移位寄存器电路的至少一侧的至少一个功能子电路；所述功能子电路包括数据选通电路、静电防护电路或信号走线集线区。
在另一些实施例中，所述至少一个像素组为至少两个像素组。所述至少两个像素组沿列方向分布。所述移位寄存器电路位于两个所述像素组之间或位于对应的所述像素组内相邻的两行子像素之间。所述移位寄存器电路的沿行方向的长度小于所述像素组沿行方向的长度。所述至少一个像素电路组还包括沿行方向位于所述移位寄存器电路的至少一侧的至少一个功能子电路；所述功能子电路包括数据选通电路、静电防护电路或信号走线集线区。
在一些实施例中，所述至少一个像素驱动子电路组为多个像素驱动子电路组。所述移位寄存器电路包括第一移位寄存器电路和第二移位寄存器电路。所述第一移位寄存器电路和所述第二移位寄存器电路分别与所述多个像素驱动子电路组对应电连接。
在一些实施例中，所述至少一个像素驱动子电路组为多个像素驱动子电路组。所述移位寄存器电路包括第一移位寄存器电路和第二移位寄存器电路。所述第一移位寄存器电路与所述多个像素驱动子电路组中的一部分像素驱动子电路组对应电连接，所述第二移位寄存器电路与所述多个像素驱动子电路 中的另一部分像素驱动子电路组对应电连接。
在一些实施例中，所述第一移位寄存器电路和所述第二移位寄存器电路沿行方向或列方向相邻设置。
在一些实施例中，所述第一移位寄存器电路和所述第二移位寄存器电路分别位于不同的两行像素或两列像素之间。
在一些实施例中，所述移位寄存器电路，还包括第一备份电路和第二备份电路。所述第一备份电路为所述第一移位寄存器电路的备份，配置为在所述第一移位寄存器电路发生故障的情况下，与对应的像素驱动子电路组电连接，并向对应的像素驱动子电路组提供扫描驱动信号。所述第二备份电路为所述第二移位寄存器电路的备份，配置为在所述第二移位寄存器电路发生故障的情况下，与对应的像素驱动子电路组电连接，并向对应的像素驱动子电路组提供扫描驱动信号。
在一些实施例中，所述第一备份电路和所述第一移位寄存器电路位于相同的两行像素或两列像素之间。所述第二备份电路和所述第二移位寄存器电路位于相同的两行像素或两列像素之间。
在一些实施例中，所述阵列基板，还包括：衬底、至少一个扇出结构和至少一个侧边结构。所述衬底包括第一面以及背离所述第一面的第二面。所述至少一个像素组和所述至少一个像素电路组位于所述第一面上。所述至少一个扇出结构位于所述第二面上。所述至少一个扇出结构中的每个扇出结构包括多条信号连接线，所述多条信号连接线由所述第二面的边缘向所述第二面的非边缘区域延伸。所述至少一个侧边结构中的每个包括多条侧边连接线。
在一些示例中，所述多条侧边连接线中每条侧边连接线的一端与对应扇出结构中的一条信号连接线电连接，其另一端接入对应的所述功能子电路中。
在另一些示例中，阵列基板包括移位寄存器电路，所述移位寄存器电路位于所述第一面上。所述多条侧边连接线中每条侧边连接线的一端与对应扇出结构中的一条信号连接线电连接，其另一端接入对应的所述功能子电路中或所述移位寄存器电路中。
另一方面，提供一种显示面板。所述显示面板包括：如上一些实施例所述的阵列基板。
在一些实施例中，所述显示面板还包括控制集成电路。所述控制集成电路位于所述阵列基板的衬底的第二面上。所述控制集成电路与所述阵列基板中对应的扇出结构中的多条信号连接线电连接，配置为向所述多条信号连接线输出控制信号。
又一方面，提供一种拼接显示面板。所述拼接显示面板包括：相互拼接的如上一些实施例所述的至少两个显示面板。
又一方面，提供一种显示驱动方法。所述显示驱动方法，应用于如上一些实施例所述的显示面板。所述显示驱动方法，包括：控制所述至少一个像素电路组中的每个像素驱动子电路组，向对应相邻且与其电连接的两行子像素或两列子像素，提供像素驱动信号。
在一些实施例中，所述显示驱动方法，还包括：位于所述阵列基板的衬底的第二面上的控制集成电路，通过至少一个侧边结构，向位于所述阵列基板的衬底的第一面上的所述至少一个像素电路组和/或移位寄存器电路分别传输控制信号。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开一些实施例所涉及的产品的实际尺寸以及方法的实际流程等的限制。
图1为根据一些实施例中的一种阵列基板的布线示意图；
图2为根据一些实施例中的另一种阵列基板的布线示意图；
图3为根据一些实施例中的又一种阵列基板的布线示意图；
图4为根据一些实施例中的又一种阵列基板的布线示意图；
图5为根据一些实施例中的又一种阵列基板的布线示意图；
图6为根据一些实施例中的一种阵列基板的第二面的结构图；
图7为根据一些实施例中的一种阵列基板的边缘部分的剖面图；
图8为根据一些实施例中的另一种阵列基板的边缘部分的剖面图；
图9为根据一些实施例中的一种像素驱动子电路的结构图；
图10为根据一些实施例中的一种移位寄存器的结构图；
图11为根据一些实施例中的一种数据选通电路的结构图；
图12为根据一些实施例中的又一种阵列基板的边缘部分的剖面图；
图13为根据一些实施例中的一种显示面板的结构图；
图14为根据一些实施例中的一种拼接显示面板的结构图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第 二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
随着显示技术的不断发展，消费者对显示装置的屏幕尺寸的要求愈来愈大，使得拼接显示面板应运而生。传统的拼接显示面板通常由多个显示面板拼接构成。
在一些示例中，各显示面板均为液晶(Liquid Crystal Display，简称LCD)显示面板，但由于LCD显示面板中封框胶以及虚拟像素的存在，因此，由各LCD显示面板拼接构成的拼接显示面板难免会存在有拼缝，从而无法实现完美的无缝拼接。
在另一些示例中，各显示面板均为有机发光二极管(Organic Light-Emitting Diode，简称OLED)显示面板。但是，由于OLED显示面板中各OLED的阴极一般通过蒸镀的方式形成，且需要对OLED发光器件进行以阻隔空气中的水氧，保证显示面板的寿命，故各OLED显示面板拼接构成的拼接显示面板也难免会存在有拼缝，从而无法实现无缝拼接。
对于迷你发光二极管(Mini Light-Emitting Diode，Mini-LED)显示面板和微型发光二极管(Micro Light-Emitting Diode，Micro-LED)显示面板，因现阶段生产工艺中巨量转移技术(Mass Transfer Technology)发展水平的限制，Mini-LED显示面板和Micro-LED显示面板在直接实现高分辨率大尺寸的方向上存在诸多阻碍，而通过无缝拼接技术便可以有效弥补目前巨量转移技术的不足，以便于利用Mini-LED显示面板或Micro-LED显示面板实现巨幕显示。
基于此，本公开一些实施例提供了一种阵列基板。请参阅图1～图3，所述阵列基板101，包括：显示区AA、至少一个像素组1和至少一个像素电路组2。所述至少一个像素组1位于显示区AA内，所述至少一个像素组1中的每个包括阵列设置的多个像素10。所述至少一个像素电路组2中的每个位于对应的像素组1内相邻两行像素10或相邻两列像素10之间。
此处，每个像素10包括至少一个子像素11。所述至少一个像素电路组2 包括至少一个像素驱动子电路组20。每个像素驱动子电路组20与对应相邻的两行子像素11或相邻的两列子像素11电连接，且配置为向与其电连接的各子像素11提供像素驱动信号。
可选的，阵列基板采用RGB色彩显示模式。每个像素10包括三个子像素11，分别为红色子像素R、绿色子像素G和蓝色子像素B。如图3所示，每个像素驱动子电路组20包括多个独立的像素驱动子电路21，其中，一个像素驱动子电路21对应连接一个像素10的三个子像素。
本公开一些实施例，将每个像素驱动子电路组20放置于对应的相邻两行像素10或两列像素10之间，并利用每个像素驱动子电路组20分别向对应相邻的两行或两列像素10中的各子像素11提供像素驱动信号，能够有效实现像素驱动子电路21的集成，也即将阵列基板101上各子像素11对应的像素驱动子电路21模块化的集中排列在部分行或部分列的像素10之间，从而能够在阵列基板的显示区AA内留出较多空间，以利用该空间模块化地放置阵列基板101显示所需的其他电路，例如移位寄存器电路、数据选通(MUX)电路或静电防护(Electro-Static discharge，简称ESD)电路等。如此可以有效减小甚至消除阵列基板101的边框，以利于实现显示面板的无缝拼接。
上述像素组1的数量及每个像素组1内像素10的数量，可以根据实际需求选择设置，例如根据阵列基板所在显示面板的分辨率进行。例如，每个像素组1包括12(2×6)个像素10，其中2为列数，6为行数。如此，上述的每个像素驱动子电路组20可以位于对应的像素组1内的两列像素10之间。此外，示例的，每个像素组1的沿行方向或列方向的宽度以能实现对应像素驱动子电路组20在其内的分布为限。每相邻两个像素组1的沿行方向或列方向之间的间隔中至少存在一个间隔大于70μm。
可以理解的是，上述阵列基板101应用于Micro-LED显示面板或者Mini-LED显示面板中。由于Micro-LED或Mini-LED具有较小的尺寸以及较高的发光强度，使得Micro-LED或Mini-LED在阵列基板101的每个像素10中最小可以只占用该像素10面积的10％，因此阵列基板101的各像素10内 或其相邻的像素10之间存在有足够的空间以设置各电路的电气元件。
在一些示例中，请参阅图1，像素组1的数量为至少两个。该至少两个像素组1沿行方向分布，也即将阵列基板101上的各像素10沿行方向划分为至少两个组。每个像素驱动子电路组20位于对应的像素组1内相邻的两列子像素11之间。每个像素驱动子电路组20沿列方向的长度小于像素组1沿列方向的长度，也即将每个像素驱动子电路组20集中设置在对应两列像素10中的部分像素10之间，可以使得每个像素驱动子电路组20沿列方向的至少一侧会留有空间。如此，所述至少一个像素电路组2还包括沿列方向位于每个像素驱动子电路组20的至少一侧的至少一个功能子电路30。所述功能子电路30包括数据选通(MUX)电路、静电防护(ESD)电路或信号走线集线区。
当然，功能子电路30的类型并不仅限于此，阵列基板101显示所需的具有一定驱动或补偿或检测等功能的其他电路均可包括在内。信号走线集线区是指显示区AA内多条信号线的集中引出端，配置为将各信号线与外部输入电路绑定，例如电源电压端、公共电压端和时钟信号端等。
如图1所示，各像素组1沿行方向分布，例如等间距分布，这样位于每个像素驱动子电路组20的沿列方向的至少一侧表现为位于阵列基板101对应于列方向的至少一侧(例如图1中所示的顶侧、底侧或顶底两侧)。从而可以有效提高阵列基板101显示区AA的空间利用率，以合理且容易地放置阵列基板101显示所需的其他功能子电路30，例如移位寄存器电路、数据选通(MUX)电路或静电防护(Electro-Static discharge，简称ESD)电路等。进而可以有效减小甚至消除阵列基板101的边框，以利于实现显示面板的无缝拼接。并且，阵列基板101中的各像素驱动子电路组20以及各功能子电路30呈模块化的规整分布于显示区AA内，还可以有效减小形成静电及额外电容的风险。
上述阵列基板101的尺寸根据实际需求选择设置，例如设置为一较小的尺寸。这样以每一阵列基板101对应的显示面板作为一个最小的可拼接单元，便可通过拼接的方式形成任意尺寸的大尺寸显示面板。
此外，需要说明的是，将每个像素驱动子电路组20集中设置在对应两列像素10中越少数目的像素10之间，便可以获得越多的富裕空间设置。考虑到信号传输的均一性，每个像素驱动子电路组20中的每一像素驱动子电路21与对应子像素11之间的导线电阻需要相等或大略相等。可选的，每个像素驱动子电路组20中的任意两个像素驱动子电路21与对应子像素11之间的导线电阻的差值不大于100欧姆，这样所述任意两个像素驱动子电路21向对应子像素11传输的信号的延时最大不会超过0.01μs，可以满足显示均一化的需求。
类似的，在另一些示例中，请参阅图2，像素组1的数量为至少两个。该至少两个像素组1沿列方向分布。每个像素驱动子电路组20位于对应的像素组1内相邻的两行子像素11之间。每个像素驱动子电路组20沿行方向的长度小于像素组1沿行方向的长度。所述至少一个像素电路组2还包括沿行方向位于每个像素驱动子电路组20的至少一侧的至少一个功能子电路30，所述功能子电路30包括数据选通(MUX)电路、静电防护(ESD)电路或信号走线集线区(Side wire pin bonding)。
如图2所示，各像素组1沿列方向分布，例如，等间距分布，这样位于每个像素驱动子电路组20的沿行方向的至少一侧表现为位于阵列基板101对应于行方向的至少一侧(例如图2中所示的左侧、右侧或左右两侧)。如此，采用上述结构的阵列基板101所能具有的有益效果，可参阅前述的各像素组1沿行线性分布时对应的阵列基板101的有益效果。此处不再赘述。
可以理解的是，阵列基板101的每个像素驱动子电路组20中的各像素驱动子电路21通常需要移位寄存器电路输出的移位控制信号依次开启工作。在一些实施例中，请继续参阅图1～图3，阵列基板101还包括一移位寄存器电路4。移位寄存器电路4与上述至少一个像素驱动子电路组20分别位于不同的两行像素10或两列像素10之间。可选的，移位寄存器电路4位于相邻的两个像素组1沿行方向或列方向之间的间隔内，或位于对应的像素组10内相邻的两行子像素11或两列子像素11之间的间隔内，所述间隔大于70μm。
本公开一些实施例，将移位寄存器电路4放置于对应的两行像素10或两 列像素10之间，可以有效减小甚至消除阵列基板101的边框，以利于实现显示面板的无缝拼接。并且，移位寄存器电路4采用如上设置方式，不仅可以避免对移位寄存器电路4进行拆分，以降低由此带来的信号传输延迟，还有利于简化阵列基板101布线版图的设计难度(例如：实现小尺寸版图单元的版图阵列)，从而提高版图设计效率以及后续对应的检测效率。
此外，移位寄存器电路4中的各薄膜晶体管等电子元件无需拆分并分散至每个像素10中，可以有效减小阵列基板101的布线复杂度，降低额外的寄生电容，以及避免阵列基板101出现开口率降低和静电干扰等的问题。
上述移位寄存器电路4与上述至少一个像素驱动子电路组20对应电连接，且配置为向所述至少一个像素驱动子电路组20提供扫描驱动信号。
此处，需要说明的是，至少一行或至少一列的多个像素10对应的像素驱动子电路21电连接同一条扫描信号线。移位寄存器电路4与上述至少一个像素驱动子电路组20对应电连接，表现为移位寄存器电路4通过每条扫描信号线与对应的各像素驱动子电路21电连接，以向每个像素驱动子电路21提供扫描驱动信号。
可选的，所述扫描信号线包括栅扫描信号线或发光扫描信号线。栅扫描信号线和发光扫描信号线的结果及其使用功能参见相关技术即可，此处不再详述。在一些实施例中，请参阅图1，像素组1的数量为至少两个。该至少两个像素组1沿行方向分布。移位寄存器电路4位于两个像素组10之间或位于对应的像素组10内相邻的两列子像素11之间。移位寄存器电路4的沿列方向的长度小于像素组1沿列方向的长度，也即将移位寄存器电路4集中设置在对应两列像素10中的部分像素10之间，可以使得移位寄存器电路4沿列方向的至少一侧会留有空间。如此，所述至少一个像素电路组2还包括沿列方向位于移位寄存器电路4的至少一侧的至少一个功能子电路30；所述功能子电路30包括数据选通(MUX)电路、静电防护(ESD)电路或信号走线集线区。
如图1所示，各像素组1沿行方向线性分布，这样位于移位寄存器电路4 的至少一侧表现为位于阵列基板101对应于列方向的至少一侧(例如图1中所示的顶侧、底侧或顶底两侧)。从而可以进一步提高阵列基板101显示区AA内的空间利用率，以合理且容易地放置阵列基板101显示所需的其他功能子电路30。进而有效减小甚至消除阵列基板101的边框，以利于实现显示面板的无缝拼接。
此外，需要说明的是，将移位寄存器电路4集中设置在对应两列像素10中越少的部分像素10之间，便可以获得越多的富裕空间。考虑到信号传输的均一性，移位寄存器电路4与每一扫描信号线之间的导线电阻需要相等或大略相等。可选的，移位寄存器电路4与各扫描信号线中的任意两条扫描信号线之间的导线电阻的差值不大于100欧姆，这样移位寄存器电路4向所述任意两条扫描信号线传输的信号的延时最大不会超过0.01μs，可以满足显示均一化的需求。
类似的，在另一些实施例中，请参阅图2，像素组1的数量为至少两个。所述至少两个像素组1沿列方向分布。移位寄存器电路4位于两个像素组1之间或位于对应的像素组1内相邻的两行子像素11之间。移位寄存器电路4的沿行方向的长度小于像素组1沿行方向的长度。所述至少一个像素电路组2还包括沿行方向位于移位寄存器电路4的至少一侧的至少一个功能子电路3；所述功能子电路3包括数据选通(MUX)电路、静电防护(ESD)电路或信号走线集线区。
如图2所示，各像素组1沿列方向线性分布，这样位于移位寄存器电路4的至少一侧表现为位于阵列基板101对应于行方向的至少一侧(例如图2中所示的左侧、右侧或左右两侧)。如此，采用上述结构的阵列基板所能具有的有益效果，可参阅前述的各像素组1沿行线性分布时对应的阵列基板101的有益效果。此处不再赘述。
在一些实施例中，请参阅图4和图5，移位寄存器电路4包括第一移位寄存器电路41和第二移位寄存器电路42，方便于实线扫描信号的双边驱动，从而有效提高阵列基板101所在显示面板的显示均一性。
可以根据实际需求设置第一移位寄存器电路41和第二移位寄存器电路42在显示区AA内的位置。例如图4所示，第一移位寄存器电路41和第二移位寄存器电路42位于显示区AA内的中间区域，也即第一移位寄存器电路41和第二移位寄存器电路42分别从显示区AA内的中间区域向其两侧传输扫描驱动信号。当然，如图5所示，第一移位寄存器电路41和第二移位寄存器电路42分别位于显示区AA两侧边缘向内延伸的部分，也即第一移位寄存器电路41和第二移位寄存器电路42可以分别从显示区AA内的两侧向中心传输扫描驱动信号，也是允许的。本公开一些实施例对此不做限定。
在一些示例中，第一移位寄存器电路41和第二移位寄存器电路42在阵列基板101中的设置位置，根据阵列基板101中形成于相邻两行或两列像素10之间的间隔大小确定。可选的，第一移位寄存器电路41和第二移位寄存器电路42沿行方向或列方向相邻设置，方便于布线设计及制作。可选的，第一移位寄存器电路41和第二移位寄存器电路42分别位于不同的两行像素10或两列像素10之间，有利于提高显示均一性。
在一些示例中，阵列基板包括多个像素驱动子电路组20，第一移位寄存器电路41和第二移位寄存器电路42分别与各像素驱动子电路组20对应电连接，也即第一移位寄存器电路41和第二移位寄存器电路42分别电连接至相同的像素驱动子电路组20。在另一些示例中，第一移位寄存器电路41与各像素驱动子电路组20中的一部分像素驱动子电路组20对应电连接。第二移位寄存器电路42与各像素驱动子电路组20中的另一部分像素驱动子电路组20对应电连接。也即第一移位寄存器电路41和第二移位寄存器电路42分别电连接不同的像素驱动子电路组20。
在上述一些实施例中，第一移位寄存器电路41与像素驱动子电路组20对应电连接，表现为第一移位寄存器电路41通过多条扫描信号线与像素驱动子电路组20中的各像素驱动子电路对应电连接。第二移位寄存器电路42与像素驱动子电路组20对应电连接，表现为第二移位寄存器电路42通过多条扫描信号线与像素驱动子电路组20中的各像素驱动子电路对应电连接。
值得一提的是，在一些实施例中，请继续参阅图4和图5，移位寄存器电路4还包括第一备份电路43和第二备份电路44。第一备份电路43为第一移位寄存器电路41的备份，配置为在第一移位寄存器电路41发生故障的情况下，与对应的像素驱动子电路组20电连接，并向对应的像素驱动子电路组提供扫描驱动信号。第二备份电路44为第二移位寄存器电路42的备份，配置为在第二移位寄存器电路42发生故障的情况下，与对应的像素驱动子电路组20电连接，并向对应的像素驱动子电路组20提供扫描驱动信号。
此处，第一备份电路43为第一移位寄存器电路41的备份，是指二者包括的电子元件及其连接方式、工作原理都相同。第一备份电路43通常空置于阵列基板101中(也即其不与其他电路电连接，以冗余电路的形式存在)。这样在第一移位寄存器电路41出现故障的情况下，通过激光修复等的方式将第一备份电路43与对应的像素驱动子电路组20电连接，便可以利用第一备份电路43替代第一移位寄存器电路41，向对应的像素驱动子电路组提供扫描驱动信号，以确保阵列基板的正常使用。可以理解的是，第一备份电路43和第一移位寄存器电路41可以位于不同的膜层，如此，第一备份电路43还能够对第一移位寄存器电路41进行静电防护，从而有效提高阵列基板及对应显示面板的良率。
第二备份电路44和第二移位寄存器电路42之间的关系，可对应参考上述第一备份电路43和第一移位寄存器电路41之间的相关表述，此处不再详述。
此外，在一些示例中，第一备份电路43和第一移位寄存器电路41位于相同的两行像素10或两列像素10之间。第二备份电路44和第二移位寄存器电路42位于相同的两行像素10或两列像素10之间。
基于第一备份电路43和第一移位寄存器电路41位于不同的膜层，第一备份电路43和第一移位寄存器电路41在阵列基板中衬底上的正投影重合或大略重合或不重合，均是允许的。同理，第二备份电路44和第二移位寄存器电路42在阵列基板中衬底上的正投影重合或大略重合或不重合，也均是允许 的。
请参阅图6～图8，阵列基板101的衬底100包括第一面S1以及背离第一面S1的第二面S2。上述一些实施例中的各像素组1、各像素电路组2和移位寄存器电路4分别位于衬底100的第一面S1上。
在一些实施例中，请继续参阅图6～图8，阵列基板101还包括位于衬底100的第二面S2上的至少一个扇出结构200，以及位于衬底100的第一面S1和第二面S2之间的侧面上的至少一个侧边结构300。
每个扇出结构200包括多条信号连接线201，所述多条信号连接线201由衬底100的第二面S2的边缘向其非边缘区域延伸。每个扇出结构200还包括与所述多条信号连接线201电连接的信号绑定端202，该信号绑定端202配置为与外部输入电路绑定。外部输入电路包括控制集成电路、柔性电路板或印刷电路板等。
每个侧边结构300包括多条侧边连接线301，其中，每条侧边连接线301的一端与对应扇出结构200中的一条信号连接线201电连接，其另一端接入对应的功能子电路3中或移位寄存器电路4中。
此处，扇出结构200和侧边结构300可以一一对应，也可以多个侧边结构300对应一个扇出结构200。扇出结构200和侧边结构300的数量及其具***置可以根据实际需求选择设置，以便于布线并能准确实现对应线路的电连接为限。
各信号连接线201和各侧边连接线301采用导电材料制作形成，示例的，该导电材料为金属或者导电银胶，其中，金属包括银或铜等中的至少一种，可以确保各信号连接线201和各侧边连接线301具有良好的导电性。
此外，侧边结构300位于衬底100的第一面S1和第二面S2之间的侧面上，可以有多种设置方式。例如，侧边结构300在衬底100的第二面S2上的正投影与对应扇出结构200在所述第二面S2上的正投影无重叠(如图7所示)或部分重叠(如图8所示)。
本公开一些实施例在衬底100的第二面S2上设置扇出结构200，在衬底 100的侧面上设置侧边结构300，能够将原先位于阵列基板的非显示区内的各信号走线设置于衬底100的侧面以及第二面S2上，从而能够进一步减小甚至消除阵列基板的边框尺寸，以利于实现无缝拼接。
在制备上述一些实施例中的阵列基板时，可以先在衬底100的第一面S1上形成各像素组1、各像素电路组2和移位寄存器电路4等电路结构，再在衬底100的第二面S2上形成各扇出结构200；或者，也可以先在衬底100的第二面S2上形成各扇出结构200，再在衬底100的第一面S1上形成各像素组1、各像素电路组2和移位寄存器电路4等。这也就是说，本公开一些实施例对于制备在衬底100的第一面S1上的电路结构与制备在衬底100的第二面S2上的扇出结构的先后顺序不作限定。
最后，在衬底100的位于第一面S1和第二面S2之间的侧面上形成各侧边结构300。各侧边结构300可以采用3D打印、影印、溅镀(Sputter)或者刻蚀等方法中的一种进行制备。
需要说明的是，上述一些实施例中的附图仅是对阵列基板101中的电路版图进行的示意性说明，也即仅是针对阵列基板101中各不同电路结构的设置位置进行了空间方位上的限定。该各不同电路结构中的电气元件以及相互间的对应电连接关系，可以参照相关技术中的有关方案进行。
为了更清楚的说明上述一些实施例中的阵列基板101，以下以Micro-LED显示面板或者Mini-LED显示面板中的阵列基板为例进行了说明。
在Micro-LED显示面板或者Mini-LED显示面板的阵列基板中，如图3所示，基于LED的巨量转移工艺及其导通特性，每一像素10中各子像素的LED绑定端位于该像素10的中间区域，且靠近显示区AA的边缘的各LED绑定端距离其对应边缘的尺寸L通常为固定值，例如在150μm～200um之间。因此，将阵列基板中占用空间较大的数据选通电路、静电防护电路以及信号走线集线区等功能子电路30放置于靠近显示区AA边缘的区域内，例如放置于第一行像素10及第二行像素10对应的空间内，或最后一行像素10及倒数第二行像素10对应的空间内，能够更合理的设计阵列基板中各电路结构的版 图，有效提供阵列基板的显示区AA内的空间利用率。
示例性的，如图4和图5所示，在显示区AA的边缘区域或其四周边缘向内延伸的部分行像素10或部分列像素10的空间内，设置静电防护电路32和信号走线集线区33，方便于通过位于衬底100的侧面的侧边结构300实现其与外部输入电路(如集成电路IC)的电连接，例如通过侧边结构300对应的扇出结构200与外部输入电路绑定。此处，静电防护电路32和信号走线集线区33可以沿显示区AA的边缘呈环形设置。
在显示区AA的四周边缘向内延伸的部分行像素10的空间内设置数据选通电路31，并在显示区AA内的部分列像素10的空间内设置像素驱动子电路组20和移位寄存器电路4，能够有效减小二者信号的交迭，以降低信号的传输延迟。
在一些示例中，阵列基板的显示区AA内的每种类型的信号线(例如发光信号线EM、使能信号线Vinit、复位信号线Reset或基准电压线Vref等)呈网格状连接，采用整个面板全局(Global)输入的形式，从而能够合理减小对应信号输入的差异性。
在一些示例中，像素驱动子电路21的结构如图9所示。像素驱动子电路21包括：第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、第一存储电容C1以及发光器件D。其中，第一晶体管T1的第一极连接初始电压信号端Vint。第一晶体管T1的第二极连接第一存储电容C1的第二极、第二晶体管T2的第一极和第三晶体管T3的控制极。第一晶体管T1的控制极连接复位信号端Reset。第二晶体管T2的第二极连接第三晶体管T3的第二极和第六晶体管T6的第一极。第二晶体管T2的控制极连接栅扫描信号线Gate。第三晶体管T3的第一极连接第一电源电压端VDD。第四晶体管T4的第一极连接数据线Data。第四晶体管T4的第二极连接第五晶体管T5的第二极、第七晶体管T7的第二极和第一存储电容C1的第一极。第四晶体管T4的控制极连接栅扫描信号线Gate。第五晶体管T5的第一极连接基准电压信号端Vref。第五晶体管T5的控制极 连接发光扫描信号线EM。第六晶体管T6的第二极连接发光器件D的第一极。第六晶体管T6的控制极连接发光扫描信号线EM。第七晶体管T7的第一极连接基准电压信号端Vref。第七晶体管T7的控制极连接复位信号端Reset。发光器件的第二极连接第二电源电压端VSS。
在一些示例中，移位寄存器电路4包括级联的多个移位寄存器，其中，每个移位寄存器的结构如图9所示。所述移位寄存器包括：第八晶体管T8、第九晶体管T9、第十晶体管T10、第十一晶体管T11、第十二晶体管T12、第十三晶体管T13、第十四晶体管T14、第二存储电容C2和第三存储电容C3。其中，第八晶体管T8的第一极连接信号输入端Input。第八晶体管T8的第二端连接N1节点。第八晶体管T8的控制极连接第一时钟信号端CLK。第九晶体管T9的第一极连接第一时钟信号端CLK。第九晶体管T9的第二极连接N2节点。第九晶体管T9的控制极连接N1节点。第十晶体管T10的第一极连接低电平信号端VGL。第十晶体管T10的第二极连接N2节点。第十晶体管T10的控制极连接第一时钟信号端CLK。第十一晶体管T11的第一极连接高电平信号端VGH和第三存储电容C3的第二极。第十一晶体管T11的第二极连接信号输出端Output。第十一晶体管T11的控制极连接N2节点。第三存储电容C3的第一极连接N2节点。第十二晶体管T12的第一极连接第二时钟信号端CLKB。第十二晶体管T12的第二极连接第二存储电容C2的第二极和信号输出端Output。第十二晶体管T12的控制极连接第二存储电容C2的第一极。第十三晶体管T13的第一极连接高电平信号端VGH。第十三晶体管T13的第二极连接第十四晶体管T14的第一极。第十三晶体管T13的控制极连接N2节点。第十四晶体管T14的第二极连接N1节点。第十四晶体管T14的控制极连接第二时钟信号端CLKB。第十五晶体管T15的第一极连接N1节点。第十五晶体管T15的第二极连接第二存储电容C2的第一极。第十五晶体管T15的控制极连接低电平端VGL。
在一些示例中，数据选通电路31包括：第十六晶体管T16、第十七晶体管T17和第十八晶体管T18。其中，第十六晶体管T16的第一极、第十七晶 体管T17的第一极和第十八晶体管T18的第一极连接在一起，且通过数据电压引入线Data1'与源极驱动器(图中未示)连接。第十六晶体管T16的第二极连接第一数据线Data11，第十六晶体管T16的控制极连接时序控制器(图中未示)的第一输出端。第十七晶体管T17的第二极连接第二数据线Data12，第十七晶体管T17的控制极连接时序控制器的第二输出端。第十八晶体管T18的第二极连接第三数据线Data13，第十八晶体管T18的控制极连接时序控制器的第三输出端。
上述一些示例中所采用的晶体管可以为薄膜晶体管或场效应管或其他特性的相同器件，由于其采用的晶体管的源极和漏极是对称的，所以其源极、漏极是没有区别的。
上述一些示例为区分晶体管的源极和漏极，将其中一极称为第一极，另一极称为第二极，栅极称为控制极。并且，按照晶体管的特性区分，可以将晶体管分为N型和P型。当采用P型晶体管时，第一极为P型晶体管的源极，第二极为P型晶体管的漏极，栅极输入低电平时，源漏极导通。当采用N型晶体管时，第一极为N型晶体管的源极，第二极为N型晶体管的漏极，栅极输入高电平时，源漏极导通。
此外，上述的像素驱动子电路21中的各晶体管均是以N型晶体管为例进行说明的，可以想到的是采用P型晶体管实现是本领域技术人员可以在没有付出创造性劳动前提下轻易想到的，因此也是在本公开的保护范围内的。
在一些实施例中，阵列基板101采用如上所示的结构，其侧边结构300中的某一条侧边连接线301与对应扇出结构200中的一条信号连接线201连接，且与显示区AA内对应的一个像素驱动子电路21连接，以向该像素驱动子电路21传输数据信号。该侧边连接线301与对应信号连接线201以及对应像素驱动子电路21的连接结构如图12所示。
图12仅是对阵列基板101中边缘部分的各膜层的位置关系进行了一种示意性地说明，并非对阵列基板101的结构限定。并且，图12也只是示意了部分器件，例如：第四晶体管T4、第六晶体管T6等，其中，以第四晶体管T4 和第六晶体管T3为顶栅型薄膜晶体管为例进行说明。
如图12所示，阵列基板101包括：衬底100，位于衬底100第二面S1上的缓冲层110；位于缓冲层110之上、且同层设置的第四晶体管T4的有源层和第六晶体管T6的有源层；位于第四晶体管T4的有源层和第六晶体管T6的有源层所在层之上的栅极绝缘层120；位于栅极绝缘层120之上、且同层设置的第四晶体管T4的栅极和第六晶体管T6的栅极；位于第四晶体管T4的栅极和第六晶体管T6的栅极所在层之上的第一绝缘层130；位于第一绝缘层130之上，且同层设置的第四晶体管T4的源极和漏极，第六晶体管T6的源极和漏极，以及与第四晶体管T4源极连接的数据线Data；位于第四晶体管T4的源极和漏极，第六晶体管T6的源极和漏极，以及与第四晶体管T4源极连接的数据线Data所在层之上的第一平坦化层141；位于第一平坦化层141之上的第一钝化层142；位于第一平坦化层141之上，且同层设置的第二子信号引入线152和第一连接电极160；第二子信号引入线152通过贯穿第一平坦化层141和第一钝化层142的第一过孔与数据线Data连接，第一连接电极160通过贯穿第一平坦化层141和第一钝化层142的第三过孔与第六晶体管T6的漏极连接；位于第二子信号引入线152和第一连接电极160所在层之上的第二平坦化层143；位于第二平坦化层143之上的第二钝化层144；位于第二钝化层144之上，且同层设置的第一子信号引入线151、第一导电衬垫171、第二导电衬垫172；第一子信号引入线151由显示区延伸至信号走线集线区，且通过贯穿第二平坦化层143和第二钝化层144的第二过孔与第二子信号引入线152连接；第一导电衬垫171通过贯穿第二平坦化层143和第二钝化层144的第四过孔与第一连接电极160连接；位于第一子信号引入线151、第一导电衬垫171、第二导电衬垫172上的第三钝化层180，其中，发光器件D的第一极通过贯穿第三钝化层180的第五过孔与第一导电衬垫171电连接，第二极通过贯穿第三钝化层180的第五过孔与第二导电衬垫172电连接。在衬底100的第二面上设置有信号连接线201，位于信号连接线201之上的第四钝化层190；位于第四钝化层190之上的信号绑定端202和第二焊盘192；其中，第 二焊盘192通过贯穿第四钝化层190的第六过孔与信号连接线201的一端连接，信号绑定端202通过贯穿第四钝化层190的第七过孔与信号连接线201的另一端连接；第一子信号引入线151与信号走线集线区的第一焊盘191连接，第一焊盘191通过侧边连接线301与衬底100的第二面上的第二焊盘192连接。控制IC 5位于阵列基板衬底100的中信号绑定端202电连接，配置为向所述信号绑定端202输出控制信号。
上述第一导电衬垫171和第二导电衬垫172分别与发光器件D的两个引脚电连接，该发光器件D可以是微型无机发光二极管，进一步地，可以为电流型发光二极管，如微型发光二极管(Micro Light Emitting Diode，Micro LED)或者迷你发光二极管(Mini Light Emitting Diode，Mini LED)。
当然，在另一些实施例中，发光器件D还可以是有机电致发光二极管(Organic Light Emitting Diode，OLED)，这样发光器件D的第一极和第二极中的一者为阳极，另一者为阴极。
本公开一些实施例提供一种显示面板以及一种显示驱动方法。请参阅图13，所述显示面板1001包括如上一些实施例所述的阵列基板101。所述显示驱动方法应用于所述显示面板1001。所述显示驱动方法，包括：控制所述至少一个像素电路组2中的每个像素驱动子电路组20，向对应相邻且与其电连接的两行子像素11或两列子像素11，提供像素驱动信号。
本公开一些实施例提供的显示面板1001以及显示驱动方法所能实现的有益效果，与前述一些实施例中所述的阵列基板101所能实现的有益效果相同，此处不再赘述。
在一些实施例中，请继续参阅图13，显示面板1001还包括控制集成电路(Integrated Circuit，简称IC)5。控制IC5位于阵列基板101的衬底100的第二面S2上。控制IC5与阵列基板101中对应的扇出结构200的多条信号连接线201电连接，配置为向所述多条信号连接线201输出控制信号。
此处，控制IC 5向所述多条信号连接线201输出的控制信号，可以经由对应侧边结构300中的侧边连接线301传输入阵列基板101的显示区AA内 的各电路结构中。
应用于所述显示面板1001的所述显示驱动方法，还包括：控制IC5通过至少一个侧边结构300，向位于阵列基板101的衬底100的第一面S1上的所述至少一个像素电路组2和/或移位寄存器电路4分别传输控制信号。
在本公开一些实施例提供的显示面板1001中，控制IC5位于衬底100的第二面S2上，控制IC5可以在阵列基板101的显示区AA的背面进行控制信号的输入，从而有效减小阵列基板101对第一面S1上非显示区的需求，也即能够减小甚至消除阵列基板101的边框，以利于实现无缝拼接。
可以理解的是，在另一些示例中，显示面板1001还包括位于阵列基板101的衬底100的第二面S2上的柔性电路板(Flexible Printed Circuit，简称FPC)。柔性电路板可以通过覆晶薄膜或引线等与阵列基板101中对应的扇出结构200的多条信号连接线201电连接，配置为向所述多条信号连接线201输出信号。
本公开一些实施例对显示面板1001的类型不作限定。示例的，显示面板1001为微型发光二极管(Micro Light Emitting Diode，Micro-LED)显示面板、或者迷你发光二极管(Mini Light Emitting Diode，Mini-LED)显示面板。当然，上述显示面板1001为液晶显示面板(Liquid Crystal Display，LCD)或有机发光二极管(Organic Light-Emitting Diode，OLED)显示面板，也是可以的。
本公开一些实施例提供一种拼接显示面板。如图14所示，所述拼接显示面板1000包括相互拼接的如上一些实施例所述的至少两个显示面板1001。
示例的，如图14所示，所述拼接显示面板由四个显示面板1001无缝拼接构成。所述拼接显示面板的显示画面中不存在拼接缝隙，或其拼接缝隙极小而不易被观测到。所述拼接显示面板能够具有大尺寸的显示屏幕，以及优良的显示画质。
本公开一些实施例的拼接显示面板中各显示面板和上述一些实施例所述的显示面板相同，其所能实现的有益效果此处不再赘述。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (15)

  1. 一种阵列基板，包括：
    显示区；
    至少一个像素组，位于所述显示区内，所述至少一个像素组中的每个包括阵列设置的多个像素；
    至少一个像素电路组，所述至少一个像素电路组中的每个位于对应的所述像素组内的相邻两行像素或相邻两列像素之间。
  2. 根据权利要求1所述的阵列基板，其中，
    所述多个像素中的每个包括至少一个子像素；
    所述至少一个像素电路组包括至少一个像素驱动子电路组，所述至少一个像素驱动子电路组中的每个与对应相邻的两行子像素或相邻的两列子像素电连接，且配置为向与其电连接的各子像素提供像素驱动信号。
  3. 根据权利要求2所述的阵列基板，其中，所述至少一个像素组为至少两个像素组；
    所述至少两个像素组沿行方向分布；所述每个像素驱动子电路组位于对应的所述像素组内相邻的两列子像素之间，所述每个像素驱动子电路组沿列方向的长度小于所述像素组沿列方向的长度；所述至少一个像素电路组还包括沿列方向位于所述每个像素驱动子电路组的至少一侧的至少一个功能子电路，所述功能子电路包括数据选通电路、静电防护电路或信号走线集线区；
    或，所述至少两个像素组沿列方向分布；所述每个像素驱动子电路组位于对应的所述像素组内相邻的两行子像素之间，所述每个像素驱动子电路组沿行方向的长度小于所述像素组沿行方向的长度；所述至少一个像素电路组还包括沿行方向位于所述每个像素驱动子电路组的至少一侧的至少一个功能子电路，所述功能子电路包括数据选通电路、静电防护电路或信号走线集线区。
  4. 根据权利要求2所述的阵列基板，还包括一移位寄存器电路；
    所述移位寄存器电路与所述至少一个像素驱动子电路组分别位于不同的 两行像素或两列像素之间；
    所述移位寄存器电路与所述至少一个像素驱动子电路组对应电连接，且配置为向所述至少一个像素驱动子电路组提供扫描驱动信号。
  5. 根据权利要求4所述的阵列基板，其中，所述至少一个像素组为至少两个像素组；
    所述至少两个像素组沿行方向分布；所述移位寄存器电路位于两个所述像素组之间或位于对应的所述像素组内相邻的两列子像素之间；所述移位寄存器电路的沿列方向的长度小于所述像素组沿列方向的长度；所述至少一个像素电路组还包括沿列方向位于所述移位寄存器电路的至少一侧的至少一个功能子电路；所述功能子电路包括数据选通电路、静电防护电路或信号走线集线区；
    或，所述至少两个像素组沿列方向分布；所述移位寄存器电路位于两个所述像素组之间或位于对应的所述像素组内相邻的两行子像素之间；所述移位寄存器电路的沿行方向的长度小于所述像素组沿行方向的长度；所述至少一个像素电路组还包括沿行方向位于所述移位寄存器电路的至少一侧的至少一个功能子电路；所述功能子电路包括数据选通电路、静电防护电路或信号走线集线区。
  6. 根据权利要求4所述的阵列基板，其中，
    所述至少一个像素驱动子电路组为多个像素驱动子电路组；
    所述移位寄存器电路包括第一移位寄存器电路和第二移位寄存器电路；
    所述第一移位寄存器电路和所述第二移位寄存器电路分别与所述多个像素驱动子电路组对应电连接；或，所述第一移位寄存器电路与所述多个像素驱动子电路组中的一部分像素驱动子电路组对应电连接，所述第二移位寄存器电路与所述多个像素驱动子电路组中的另一部分像素驱动子电路组对应电连接。
  7. 根据权利要求6所述的阵列基板，其中，
    所述第一移位寄存器电路和所述第二移位寄存器电路沿行方向或列方向 相邻设置；
    或，所述第一移位寄存器电路和所述第二移位寄存器电路分别位于不同的两行像素或两列像素之间。
  8. 根据权利要求6或7所述的阵列基板，其中，所述移位寄存器电路，还包括：
    第一备份电路，所述第一备份电路为所述第一移位寄存器电路的备份，配置为在所述第一移位寄存器电路发生故障的情况下，与对应的像素驱动子电路组电连接，并向对应的像素驱动子电路组提供扫描驱动信号；
    第二备份电路，所述第二备份电路为所述第二移位寄存器电路的备份，配置为在所述第二移位寄存器电路发生故障的情况下，与对应的像素驱动子电路组电连接，并向对应的像素驱动子电路组提供扫描驱动信号。
  9. 根据权利要求8所述的阵列基板，其中，
    所述第一备份电路和所述第一移位寄存器电路位于相同的两行像素或两列像素之间；
    所述第二备份电路和所述第二移位寄存器电路位于相同的两行像素或两列像素之间。
  10. 根据权利要求3或5所述的阵列基板，还包括：
    衬底；所述衬底包括第一面以及背离所述第一面的第二面；所述至少一个像素组和所述至少一个像素电路组位于所述第一面上；
    至少一个扇出结构；所述至少一个扇出结构位于所述第二面上；所述至少一个扇出结构中的每个扇出结构包括多条信号连接线，所述多条信号连接线由所述第二面的边缘向所述第二面的非边缘区域延伸；
    至少一个侧边结构；所述至少一个侧边结构中的每个包括多条侧边连接线；
    其中，所述多条侧边连接线中每条侧边连接线的一端与对应扇出结构中的一条信号连接线电连接，其另一端接入对应的所述功能子电路中；
    在阵列基板包括移位寄存器电路的情况下，所述移位寄存器电路位于所 述第一面上；所述多条侧边连接线中每条侧边连接线的一端与对应扇出结构中的一条信号连接线电连接，其另一端接入对应的所述功能子电路中或所述移位寄存器电路中。
  11. 一种显示面板，包括：如权利要求1～10任一项所述的阵列基板。
  12. 根据权利要求11所述的显示面板，还包括控制集成电路；
    所述控制集成电路位于所述阵列基板的衬底的第二面上，所述控制集成电路与所述阵列基板中对应的扇出结构中的多条信号连接线电连接，配置为向所述多条信号连接线输出控制信号。
  13. 一种拼接显示面板，包括：相互拼接的如权利要求11或12所述的至少两个显示面板。
  14. 一种显示驱动方法，应用于如权利要求11或12所述的显示面板；所述显示驱动方法，包括：
    控制所述至少一个像素电路组中的每个像素驱动子电路组，向对应相邻且与其电连接的两行子像素或两列子像素，提供像素驱动信号。
  15. 根据权利要求14所述的显示驱动方法，还包括：
    位于所述阵列基板的衬底的第二面上的控制集成电路，通过至少一个侧边结构，向位于所述阵列基板的衬底的第一面上的所述至少一个像素电路组和/或移位寄存器电路分别传输控制信号。
PCT/CN2019/122210 2019-11-29 2019-11-29 阵列基板、显示面板、拼接显示面板及显示驱动方法 WO2021103014A1 (zh)

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