WO2021102988A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

Info

Publication number
WO2021102988A1
WO2021102988A1 PCT/CN2019/122156 CN2019122156W WO2021102988A1 WO 2021102988 A1 WO2021102988 A1 WO 2021102988A1 CN 2019122156 W CN2019122156 W CN 2019122156W WO 2021102988 A1 WO2021102988 A1 WO 2021102988A1
Authority
WO
WIPO (PCT)
Prior art keywords
spacer
base substrate
pixel
signal line
opening
Prior art date
Application number
PCT/CN2019/122156
Other languages
English (en)
French (fr)
Inventor
都蒙蒙
董向丹
刘琦
何帆
张波
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2019/122156 priority Critical patent/WO2021102988A1/zh
Priority to EP19945468.7A priority patent/EP4068378A4/en
Priority to CN201980002732.5A priority patent/CN113196494B/zh
Priority to US16/977,866 priority patent/US11974473B2/en
Priority to US17/416,078 priority patent/US20220077244A1/en
Priority to PCT/CN2020/097124 priority patent/WO2021103504A1/zh
Priority to CN202080001059.6A priority patent/CN114679914B/zh
Priority to EP20892526.3A priority patent/EP4068381A4/en
Publication of WO2021102988A1 publication Critical patent/WO2021102988A1/zh
Priority to US18/591,771 priority patent/US20240206267A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/871—Self-supporting sealing arrangements
    • H10K59/8723—Vertical spacers, e.g. arranged between the sealing arrangement and the OLED
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/351—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels comprising more than three subpixels, e.g. red-green-blue-white [RGBW]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/352—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels the areas of the RGB subpixels being different
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels

Definitions

  • the embodiments of the present disclosure relate to a display substrate, a preparation method thereof, and a display device.
  • OLED Organic Light Emitting Diode
  • the functional layers such as the organic light-emitting layer of the OLED display panel are usually prepared by evaporation and other methods using high-precision metal masks (Fine Metal Mask). During preparation, the FMM is usually at a certain distance from the display substrate to prevent the FMM from scratching the display. Functional structure on the substrate.
  • At least one embodiment of the present disclosure provides a display substrate.
  • the display substrate includes a base substrate, a pixel defining layer, and at least one spacer.
  • the pixel defining layer is disposed on the base substrate and includes a plurality of openings, and at least one spacer is disposed on a side of the pixel defining layer away from the base substrate.
  • the distance between any point of the bottom of the at least one spacer in contact with the pixel defining layer and the sidewall of the upper surface of the plurality of openings is greater than or equal to 5 ⁇ m.
  • the display substrate provided by at least one embodiment of the present disclosure further includes a pixel circuit structure.
  • the pixel circuit structure is disposed between the base substrate and the pixel defining layer, and includes a first signal line and a second signal that are arranged in parallel with each other. Line, wherein the first orthographic projection of the at least one spacer provided on the base substrate is located at the second orthographic projection of the first signal line on the base substrate and the second signal line Between the third orthographic projection on the base substrate.
  • the first signal line is a light-emitting control signal line
  • the second signal line is a reset signal line
  • the distance between the center of the first orthographic projection and the central axis of the second orthographic projection is greater than the distance from the center of the first orthographic projection to the third orthographic projection The distance of the central axis.
  • the at least one spacer includes a plurality of spacers arranged in multiple rows and multiple columns;
  • the pixel circuit structure includes a plurality of spacers arranged in multiple rows and multiple columns.
  • Pixel circuits, each row of pixel circuits shares a light-emission control signal line and a reset signal line, wherein the orthographic projection of the light-emission control signal line of one row of pixel circuits on the base substrate and the reset signal of the next row of pixel circuits
  • the orthographic projections of lines on the base substrate include orthographic projections of a row of spacers on the base substrate.
  • one spacer is provided for every four adjacent pixel circuits.
  • the at least one spacer includes a plurality of spacers arranged in multiple rows and multiple columns, a plurality of spacers located in odd rows and a plurality of spacers located in even rows. Multiple spacers are misaligned by 1/2 pitch.
  • the plurality of openings include a first opening for blue sub-pixels, a second opening for red sub-pixels, and a third opening for green sub-pixels. , And the opening sizes of the first opening, the second opening, and the third opening are sequentially reduced.
  • one blue sub-pixel, one red sub-pixel, and two green sub-pixels are used as a repeating unit, and the display substrate includes multiple rows arranged in multiple rows and multiple columns.
  • the third opening of the pixel surrounds.
  • the line connecting the center of the third opening of the two green sub-pixels in each repeating unit passes through the spacer, and the line is parallel to The length direction of the spacer.
  • the length direction of the spacer is the horizontal display direction of the display substrate.
  • the projections overlap.
  • the height of the at least one spacer is 0.8 m-1.5 m.
  • the orthographic projection shape of the at least one spacer on the base substrate is a rectangle.
  • the length of the rectangle is 20 ⁇ m-30 ⁇ m, and the width of the rectangle is 10 ⁇ m-16 ⁇ m.
  • the material of the at least one spacer is polyimide.
  • the at least one spacer includes a plurality of spacers arranged in an array.
  • the plurality of openings include a first opening for blue sub-pixels, a second opening for red sub-pixels, and a third opening for green sub-pixels. , And the opening sizes of the first opening, the second opening, and the third opening are sequentially reduced.
  • the display substrate includes a base substrate, a pixel circuit structure, which is arranged on the base substrate, and includes a first signal line and a second signal line arranged in parallel with each other, and pixels A defining layer is arranged on the side of the pixel circuit structure away from the base substrate, and includes a plurality of openings, and at least one spacer, arranged on the side of the pixel defining layer away from the base substrate
  • the first orthographic projection of the at least one spacer provided on the base substrate is located at the second orthographic projection of the first signal line on the base substrate and the second signal line is at Between the third orthographic projection on the base substrate.
  • the first signal line is a light-emitting control signal line
  • the second signal line is a reset signal line
  • the pixel circuit structure further includes a power supply line, and the associated power supply line includes a plurality of first parts and a plurality of second parts that are alternately connected; the plurality of first parts are parallel to each other
  • the extension direction is the same as the extension direction of the first signal line and the second signal line, the extension direction of the second part intersects the extension direction of the first part; the first part is on the substrate
  • the orthographic projection on the substrate partially overlaps the first orthographic projection
  • the orthographic projection of the second portion on the base substrate partially overlaps the first orthographic projection.
  • the pixel circuit structure further includes a data line, and the extension direction of the data line is perpendicular to the extension direction of the first signal line and the second signal line,
  • the orthographic projection of the data line on the base substrate does not overlap with the first orthographic projection.
  • At least one embodiment of the present disclosure provides a display substrate.
  • the display substrate includes a base substrate, a pixel defining layer, which is disposed on the base substrate, includes a plurality of openings, and at least one spacer, which is disposed on the base substrate.
  • the at least one Both sides of the spacer are the first opening and the second opening, and in the second direction perpendicular to the first direction, both sides of the at least one spacer are the third Open up.
  • the first opening includes a blue light-emitting layer
  • the second opening includes a red light-emitting layer
  • the third opening includes a green light-emitting layer.
  • the shape of the first opening is a first square
  • the shape of the second opening is a second square
  • the side length of the first square is larger than that of the first square.
  • Two square sides, the shape of the third opening is a rectangle, the long side of the rectangle is parallel to the side length of the adjacent first square of the first opening, and the short side of the rectangle is adjacent to the The sides of the second square of the second opening are parallel.
  • At least one embodiment of the present disclosure provides a display device including any one of the above-mentioned display substrates.
  • At least one embodiment of the present disclosure provides a method for preparing a display substrate, including: providing a base substrate, forming a pixel defining layer on the base substrate, the pixel defining layer including a plurality of openings, and defining the pixels At least one spacer is formed on the side of the layer away from the base substrate; wherein, any point of the bottom of the at least one spacer in contact with the pixel defining layer is away from the sidewalls of the upper surface of the plurality of openings The distance is greater than or equal to 5 ⁇ m.
  • forming at least one spacer on a side of the pixel defining layer away from the base substrate includes: positioning the at least one spacer The formation position is such that the distance between any point of the bottom of the at least one spacer formed in contact with the pixel defining layer and the sidewall of the upper surface of the plurality of openings is greater than or equal to 5 ⁇ m.
  • the method for preparing a display substrate further includes: forming a pixel circuit structure between the base substrate and the pixel defining layer, and the pixel circuit structure includes first signals arranged in parallel to each other.
  • Line and a second signal line wherein locating the formation position of the at least one spacer includes: locating the position of the first signal line and the second signal line so that the first signal line and the second signal line
  • the position of the two signal lines is a reference to locate the formation position of the at least one spacer, so that the first orthographic projection of the at least one spacer formed on the base substrate is located on the first signal line.
  • the second orthographic projection on the base substrate and the second signal line are between the third orthographic projection on the base substrate.
  • the first signal line is a light-emission control signal line
  • the second signal line is a reset signal line
  • the material of the at least one spacer is polyimide
  • forming the at least one spacer includes: A polyimide material layer is formed on one side of the base substrate, and the polyimide material layer is exposed and developed through a mask plate to form the at least one spacer.
  • FIG. 1A is a schematic plan view of a display substrate provided by at least one embodiment of the present disclosure
  • FIG. 1B is another schematic plan view of a display substrate provided by at least one embodiment of the present disclosure.
  • FIGS. 2A and 2B are circuit diagrams of a pixel circuit in a display substrate provided by at least one embodiment of the present disclosure
  • FIG. 3 is a schematic plan view of a display substrate provided by at least one embodiment of the present disclosure.
  • 4A-4E are schematic plan views of partial functional layers of a pixel circuit structure of a display substrate provided by at least one embodiment of the present disclosure
  • FIG. 4F is a schematic cross-sectional view of the display substrate in FIG. 4E along A-A';
  • FIG. 5 is a schematic plan view of a spacer of a display substrate provided by at least one embodiment of the present disclosure
  • FIG. 6 is a flowchart of a method for manufacturing a display substrate provided by at least one embodiment of the present disclosure
  • FIG. 7 is a schematic cross-sectional view of a display substrate in a manufacturing process provided by at least one embodiment of the present disclosure.
  • FIG. 8 is another schematic cross-sectional view of a display substrate in a manufacturing process according to at least one embodiment of the present disclosure.
  • the FMM is usually a certain distance from the display substrate to prevent the FMM from scratching the display.
  • Functional layer on the substrate due to gravity and other reasons, the middle part of the display substrate or FMM will be concave, so that the distance between the display substrate and the FMM becomes smaller, and the display substrate may even contact the FMM.
  • spacers Photo Space, PS
  • the placement position of the spacer and the structure of the spacer will affect the supporting effect of the spacer and also affect the evaporation uniformity of the evaporation material in the subsequent evaporation process.
  • At least one embodiment of the present disclosure provides a display substrate, a preparation method thereof, and a display device.
  • the display substrate includes a base substrate, a pixel defining layer, and at least one spacer.
  • the pixel defining layer is disposed on the base substrate and includes a plurality of openings, and each opening defines a light-emitting area of a sub-pixel.
  • At least one spacer is arranged on a side of the pixel defining layer away from the base substrate. On the surface of the pixel defining layer away from the base substrate, the distance between any point of the bottom of at least one spacer that is in contact with the pixel defining layer and the boundary of the plurality of openings directly adjacent to it is greater than or equal to 5 ⁇ m.
  • the spacer can support the FMM and isolate the FMM from the display substrate, thereby preventing the FMM from scratching the functional layer on the display substrate; in addition, the spacer and the pixel defining layer have a boundary distance greater than or Equal to 5 ⁇ m, because the deformed part of the FMM or the display substrate is mainly in the part supported by the spacer, and the part far away from the spacer deforms less and more uniformly, so that the bottom of the opening of the pixel defining layer is basically parallel to the FMM , And the deformation of the FMM or the display substrate between the adjacent spacers will not cause a large change in the parallel relationship between the bottom of the opening of the pixel defining layer and the FMM, so that the FMM is evaporated to the pixel definition.
  • the material in the opening of the layer is more uniform, which improves the quality of the display substrate.
  • FIG. 1A shows a schematic plan view of the display substrate.
  • the display substrate includes a base substrate 101, a pixel defining layer, and at least one spacer 402.
  • the pixel defining layer is disposed on the base substrate 101 and includes a plurality of openings 401, and a light-emitting layer for light-emitting elements is formed in the plurality of openings 401.
  • At least one spacer 402 is disposed on a side of the pixel defining layer away from the base substrate 101.
  • any point of the bottom of the at least one spacer 402 that is in contact with the pixel defining layer is away from the upper edge of the side wall of the plurality of openings 401 (that is, the edge of the side wall of the plurality of openings 401 away from the base substrate 101, or , Is the distance D between the edges of the plurality of openings 401 on the surface where the pixel defining layer contacts the spacer 402) is greater than or equal to 5 ⁇ m.
  • the plurality of openings include a first opening 4011, a second opening 4012, and a third opening 4013 with different opening sizes.
  • spacers 402 On the surface of the pixel defining layer away from the base substrate 101, spacers 402 The shortest distance D from the boundary of each opening directly adjacent to it, that is, the shortest distance D from any point of the bottom of the spacer 402 that is in contact with the pixel defining layer to the boundary of the multiple openings 401 directly adjacent to it is greater than or equal to 5 ⁇ m.
  • the display substrate includes a plurality of sub-pixels that can emit light of different colors (for example, red, blue, and green). Due to the difference in luminous efficiency and lifetime of light-emitting layers that can emit light of different colors, light-emitting layers that can emit light of different colors can be respectively formed in openings of different sizes to form multiple sub-pixels that can emit light of different colors.
  • different colors for example, red, blue, and green.
  • a light-emitting layer of a sub-pixel with a lower luminous efficiency or a light-emitting layer of a sub-pixel with a smaller number of openings is formed in an opening with a larger opening size, and a light-emitting layer of a sub-pixel with a higher luminous efficiency is formed in an opening with a smaller opening size.
  • the light-emitting layer of the sub-pixels with a large number of openings thereby balancing the light-emitting brightness of the sub-pixels of different colors.
  • the blue light-emitting layer, the red light-emitting layer, and the green light-emitting layer may be respectively formed in the first opening 4011, the second opening 4012, and the third opening 4013 whose opening sizes are sequentially reduced, whereby the first The opening 4011 is used for forming the blue sub-pixel, the second opening 4012 is used for the red sub-pixel, and the third opening 4013 is used for forming the green sub-pixel, thereby balancing the light-emitting brightness of the sub-pixels of different colors.
  • the spacer 102 is surrounded by the first opening 4011, the second opening 4012, and the two third openings 4013.
  • first direction D1 ie, the vertical direction in FIG. 1A
  • second direction D2 perpendicular to the first direction D1 (ie, the horizontal direction in FIG. 1A )
  • both sides of the spacer 402 are third openings 4013.
  • the shape of the first opening 4011 is a first square
  • the shape of the second opening 4012 is a second square
  • the side length of the first square is greater than the side length of the second square
  • the shape of the third opening 4013 is a rectangle
  • the long side of the rectangle is parallel to the side length of the first square of the adjacent first opening 4011
  • the short side of the rectangle is parallel to the side length of the second square of the adjacent second opening 4012 .
  • the shape of the first opening 4011 can also be replaced with a first circle
  • the shape of the second opening 4012 can also be replaced with a second circle
  • the shape of the third opening 4013 can also be replaced with an oval.
  • the diameter of the first circle is greater than the diameter of the second circle, the line with the long axis of the ellipse passes through the centers of the two adjacent second openings 4012, and the line with the short axis of the ellipse passes through Pass the center of the two adjacent first openings 4011.
  • the spacer 402 is separated from the multiple openings, that is, the distance between the first opening 4011, the second opening 4012, and the third opening 4013 is substantially the same, so that the spacer provides sufficient and uniform support for the FMM around each opening. Therefore, the material vaporized into each opening through the FMM is more uniform.
  • the above-mentioned opening 401 is generally designed as a regular shape, such as a quadrilateral, pentagon, hexagon, circle, or ellipse.
  • the shape of the formed opening 401 generally has a certain deviation from the regular shape designed as described above.
  • the corners of the aforementioned regular shape may become rounded corners. Therefore, the shape of the opening 401 may be a rounded corner figure.
  • the shape of the actually manufactured opening 401 may also have other changes from the designed shape.
  • the shape of the effective light-emitting area designed as a rectangle may become approximately elliptical in actual manufacturing.
  • the above-mentioned square or rectangle may be formed as a square with rounded corners or a rectangle with rounded corners.
  • each repeating unit can be provided with two spacers, and in this case, each spacer is provided on the display substrate Between every two adjacent third openings 4013, and a plurality of spacers are uniformly arranged on the display substrate in an array arranged in multiple rows and multiple columns.
  • the shapes of the two third openings 4013 are mirror-symmetrical, and the line connecting the centers of the two third openings 4013 passes through the spacer 402 between the two. And the line of the two third openings 4013 closest to the top corner of the spacer 402 also passes through the spacer 402 between the two.
  • the line connecting the center of the first opening 4011 and the center of the second opening 4012 passes through the spacer 402, for example, through the center of the spacer 402, that is, the center of the first opening 4011, the center of the second opening 4012, and the center of the spacer 402.
  • the center of the spacer 402 is located on a straight line.
  • the length direction of the spacer 402 is parallel to the connecting direction of the centers of the two third openings 4013, and the width direction of the spacer 402 is parallel to the connecting direction of the center of the first opening 4011 and the center of the second opening 4012. .
  • each repeating unit may be provided with a spacer corresponding to it.
  • the spacer 402 may be disposed between the two third openings 4013 of each repeating unit.
  • a plurality of spacers 402 are staggered and evenly distributed on the display substrate; for example, the spacers in odd rows and the spacers in even rows are shifted by 1/2 pitch, and a pitch means that the spacers in each row are relative to each other.
  • each spacer can be arranged in every four repeating units. Between the two third openings 4013 of the repeating unit at the same position. Under the above arrangement, the spacers can all show a sufficient and uniform support effect.
  • the display substrate further includes a pixel circuit structure, and the pixel circuit structure is disposed between the base substrate and the pixel defining layer.
  • the pixel circuit structure includes a first signal line (such as the EM line shown in FIG. 1A, which will be described in detail later) and a second signal line (such as the RST line shown in FIG. 1A, which will be described in detail later) arranged in parallel to each other,
  • the first orthographic projection of at least one spacer 402 on the base substrate is located between the second orthographic projection of the first signal line on the base substrate and the third orthographic projection of the second signal line on the base substrate, namely The first orthographic projection is within the range defined by the second orthographic projection and the third orthographic projection.
  • the distance between the center of the first orthographic projection and the central axis of the second orthographic projection is greater than the distance between the center of the first orthographic projection and the central axis of the third orthographic projection (e.g. EM0 shown in FIG. 1A), that is, at least one spacer 402 is between the first signal line and the second signal line and is closer to the second signal line.
  • the pixel circuit structure of the display substrate includes a pixel circuit for driving multiple sub-pixels to emit light, such as 2T1C (that is, including two thin film transistors T and a storage capacitor C) pixel circuit, and 3T1C (that is, including three thin film transistors T and one Storage capacitor C) pixel circuit or 7T1C (that is, including seven thin film transistors T and one storage capacitor C) pixel circuit, etc.
  • the two signal lines arranged in parallel in the driving circuit can be implemented as the first signal line and the second signal line described above. Below, take the 7T1C drive circuit as an example to introduce.
  • FIG. 2A shows a circuit diagram of a 7T1C pixel circuit.
  • the pixel circuit includes a driving circuit 122, a data writing circuit 126, a compensation circuit 128, a storage circuit 127, a first light emission control circuit 123, a second light emission control circuit 124, and a reset circuit 129.
  • the driving circuit 122 includes a control terminal 131, a first terminal 132, and a second terminal 133, which are configured to control the driving current flowing through the light-emitting element 120, and the control terminal 131 of the driving circuit 122 is connected to the first node N1, and the driving circuit The first end 132 of the 122 is connected to the second node N2, and the second end 133 of the driving circuit 122 is connected to the third node N3.
  • the data writing circuit 126 includes a control terminal, a first terminal, and a second terminal.
  • the control terminal is configured to receive a first scan signal
  • the first terminal is configured to receive a data signal
  • the second terminal is connected to the first terminal of the driving circuit 122.
  • 132 (the second node N2) is connected and configured to write the data signal into the first terminal 132 of the driving circuit 122 in response to the first scan signal Ga1.
  • the first terminal of the data writing circuit 126 is connected to the data line 12 to receive the data signal
  • the control terminal is connected to the scan line 11 to receive the first scan signal Ga1.
  • the data writing circuit 126 can be turned on in response to the first scan signal Ga1, so that the data signal can be written into the first terminal 132 (the second node N2) of the driving circuit 122, and the data signal It is stored in the storage circuit 127 to generate a driving current for driving the light-emitting element 120 to emit light according to the data signal during, for example, the light-emitting phase.
  • the compensation circuit 128 includes a control terminal, a first terminal, and a second terminal.
  • the control terminal is configured to receive the second scan signal Ga2, and the first terminal and the second terminal are respectively connected to the control terminal 131 and the second terminal of the driving circuit 122.
  • 133 is electrically connected, and the compensation circuit is configured to perform threshold compensation on the driving circuit 120 in response to the second scan signal.
  • the storage circuit 127 is electrically connected to the control terminal 131 and the first voltage terminal VDD of the driving circuit 122, and is configured to store the data signal written by the data writing circuit 126.
  • the compensation circuit 128 can be turned on in response to the second scan signal Ga2, so that the data signal written by the data writing circuit 126 can be stored in the storage circuit 127.
  • the compensation circuit 128 can electrically connect the control terminal 131 and the second terminal 133 of the drive circuit 122, so that the threshold voltage information of the drive circuit 122 can be stored in the storage accordingly.
  • the stored data signal and the threshold voltage can be used to control the driving circuit 122 during the light-emitting phase, so that the output of the driving circuit 122 is compensated.
  • the first light emission control circuit 123 is connected to the first terminal 132 (the second node N2) of the driving circuit 122 and the first voltage terminal VDD, and is configured to respond to the first light emission control signal to change the first voltage terminal VDD to the first terminal 132 (the second node N2).
  • the power supply voltage is applied to the first terminal 132 of the driving circuit 122.
  • the first light emission control circuit 123 is connected to the first light emission control terminal EM1, the first voltage terminal VDD, and the second node N2.
  • the second light-emitting control circuit 124 and the second light-emitting control terminal EM2 are connected, and are configured to respond to the second light-emitting control signal so that the driving current can be Applied to the light-emitting element 122.
  • the second light-emission control circuit 123 is turned on in response to the second light-emission control signal provided by the second light-emission control terminal EM2, so that the driving circuit 122 can apply a driving current to the light-emitting element 120 through the second light-emission control circuit 123
  • the second light-emitting control circuit 123 is turned off in response to the second light-emitting control signal, so as to avoid current flowing through the light-emitting element 120 to cause it to emit light, which can improve the contrast of the corresponding display device.
  • the second light-emitting control circuit 124 can also be turned on in response to the second light-emitting control signal, so that the reset circuit can be combined to perform a reset operation on the driving circuit 122 and the light-emitting element 120.
  • the second light emission control signal EM2 can be the same as or different from the first light emission control signal EM1, for example, the two can be connected to the same or different signal output terminals.
  • the reset circuit 129 is connected to the reset voltage terminal Vinit and the first terminal 134 (fourth node N4) of the light emitting element 122, and is configured to apply a reset voltage to the first terminal 134 of the light emitting element 120 in response to a reset signal.
  • the reset signal may also be applied to the control terminal 131 of the driving circuit, that is, the first node N1.
  • the reset signal is the second scan signal, and the reset signal may also be another signal synchronized with the second scan signal, which is not limited in the embodiment of the present disclosure. For example, as shown in FIG.
  • the reset circuit 129 is respectively connected to the first terminal 134 of the light-emitting element 120, the reset voltage terminal Vinit, and the reset control terminal Rst (reset control line).
  • the reset circuit 129 can be turned on in response to a reset signal, so that a reset voltage can be applied to the first terminal 134 and the first node N1 of the light-emitting element 120, so that the driving circuit 122, the compensation circuit 128, and the light-emitting The element 120 performs a reset operation to eliminate the influence of the previous light-emitting stage.
  • the light-emitting element 120 includes a first terminal 134 and a second terminal 135.
  • the first terminal 134 of the light-emitting element 120 is configured to receive a driving current from the second terminal 133 of the driving circuit 122, and the second terminal 135 of the light-emitting element 120 is configured to The second voltage terminal VSS is connected.
  • the first end 134 of the light-emitting element 120 may be connected to the third node N3 through the second light-emitting circuit 124.
  • the embodiments of the present disclosure include but are not limited to this situation.
  • the light-emitting element 120 can be various types of OLEDs, such as top-emission, bottom-emission, double-side emission, etc., which can emit red light, green light, blue light, or white light.
  • the first electrode and the second electrode of the OLED serve as The first end 134 and the second end 135 of the light-emitting element.
  • the embodiments of the present disclosure do not limit the specific structure of the light-emitting element.
  • the first node N1, the second node N2, the third node N3, and the fourth node N4 do not necessarily represent actual components, but rather represent the connections of related circuits in the circuit diagram. Meeting point.
  • the symbol Vd can represent both the data signal terminal and the level of the data signal.
  • the compliance Ga1 and Ga2 can both represent the first scan signal and the second scan signal.
  • the signal can also represent the first scan signal terminal and the second scan signal terminal.
  • Rst can represent both the reset control terminal and the reset signal.
  • the symbol Vinit can represent both the reset voltage terminal and the reset voltage.
  • the symbol VDD can both represent the first A voltage terminal can also represent the first power supply voltage
  • the symbol VSS can represent both the second voltage terminal and the second power supply voltage.
  • FIG. 2B is a circuit diagram of a specific implementation example of the pixel circuit shown in FIG. 2A.
  • the pixel circuit includes: first to seventh transistors T1, T2, T3, T4, T5, T6, T7, and a storage capacitor Cst.
  • the first transistor T1 is used as a driving transistor, and the other second to seventh transistors are used as switching transistors.
  • the driving circuit 122 may be implemented as a first transistor T1.
  • the gate of the first transistor T1 serves as the control terminal 131 of the drive circuit 122 and is connected to the first node N1;
  • the first pole of the first transistor T1 serves as the first terminal 132 of the drive circuit 122 and is connected to the second node N2;
  • the second pole of the transistor T1 serves as the second terminal 133 of the driving circuit 122 and is connected to the third node N3.
  • the data writing circuit 126 may be implemented as a second transistor T2.
  • the gate of the second transistor T2 is connected to the first scan line (first scan signal terminal Ga1) to receive the first scan signal, and the first pole of the second transistor T2 is connected to the data line (data signal terminal Vd) to receive the data signal ,
  • the second pole of the second transistor T2 is connected to the first terminal 132 (the second node N2) of the driving circuit 122.
  • the second transistor T2 is a P-type transistor, for example, the active layer is a thin film transistor with low-temperature doped polysilicon.
  • the compensation circuit 128 may be implemented as a third transistor T3.
  • the gate of the third transistor T3 is configured to be connected to the second scan line (the second scan signal terminal Ga2) to receive the second scan signal, and the first pole of the third transistor T3 is connected to the control terminal 131 (the first node of the driving circuit 122). N1) is connected, and the second electrode of the third transistor T3 is connected to the second terminal 133 (third node N3) of the driving circuit 122.
  • the storage circuit 127 may be implemented as a storage capacitor Cst.
  • the storage capacitor Cst includes a first capacitor electrode Ca and a second capacitor electrode Cb.
  • the first capacitor electrode Ca is connected to the first voltage terminal VDD.
  • the second capacitor electrode Cb is connected to the control terminal 131 of the driving circuit 122.
  • the first light emission control circuit 123 may be implemented as a fourth transistor T4.
  • the gate of the fourth transistor T4 is connected to the first emission control line (first emission control terminal EM1) to receive the first emission control signal, and the first pole of the fourth transistor T4 is connected to the first voltage terminal VDD to receive the first power supply Voltage, the second pole of the fourth transistor T4 is connected to the first terminal 132 (the second node N2) of the driving circuit 122.
  • the light-emitting element 120 may be embodied as an OLED, and its first electrode 134 (here, an anode) and the fourth node N4 are connected and configured to receive a driving current from the second end 133 of the driving circuit 122 through the second light-emitting control circuit 124,
  • the second electrode 135 (here, the cathode) of the light emitting element 120 is configured to be connected to the second voltage terminal VSS to receive the second power supply voltage.
  • the second voltage terminal can be grounded, that is, VSS can be 0V.
  • the second light emission control circuit 124 may be implemented as a fifth transistor T5.
  • the gate of the fifth transistor T5 is connected to the second emission control line (the second emission control terminal EM2) to receive the second emission control signal, and the first pole of the fifth transistor T5 is connected to the second terminal 133 (the third emission control terminal EM2) of the driving circuit 122.
  • the node N3) is connected, and the second electrode of the fifth transistor T5 is connected to the first end 134 (fourth node N4) of the light emitting element 120.
  • the reset circuit 129 may include a first reset circuit configured to apply a first reset voltage Vini1 to the first node N1 in response to a first reset signal Rst1 and a second reset circuit configured to The second reset voltage Vini2 is applied to the fourth node N4 in response to the second reset signal Rst2.
  • the first reset circuit is implemented as a sixth transistor T6, and the second reset circuit is implemented as a seventh transistor T7.
  • the gate of the sixth transistor T6 is configured to be connected to the first reset control terminal Rst1 to receive the first reset signal Rst1, and the first pole of the sixth transistor T6 is connected to the first reset voltage terminal Vinit1 to receive the first reset voltage Vinit1.
  • the second pole of the six transistor T6 is configured to be connected to the first node N1.
  • the gate of the seventh transistor T7 is configured to be connected to the second reset control terminal Rst2 to receive the second reset signal Rst2, and the first pole of the seventh transistor T7 is connected to the second reset voltage terminal Vinit2 to receive the second reset voltage Vinit2.
  • the second pole of the seven transistor T7 is configured to be connected to the fourth node N4.
  • the transistors used in the embodiments of the present disclosure may all be thin film transistors or field effect transistors or other switching devices with the same characteristics.
  • thin film transistors are used as examples for description.
  • the source and drain of the transistor used here can be symmetrical in structure, so the source and drain of the transistor can be structurally indistinguishable.
  • one pole is directly described as the first pole and the other pole is the second pole.
  • the first signal line is the light-emitting control line EM, which is used to transmit the above-mentioned first light-emitting control signal and the second light-emitting control signal;
  • the second signal line is the reset control line RST, which is used to transmit the above-mentioned first reset signal. Rst1 and the second reset signal Rst2.
  • the first orthographic projection of the spacer 402 on the base substrate 101 is located at the second orthographic projection of the emission control line EM on the base substrate 101 and the third orthographic projection of the reset control line RST on the base substrate 101. In between, for example, closer to the third orthographic projection.
  • FIG. 1A there is a reset voltage line VT between the light-emitting control line EM and the reset control line RST for transmitting the above-mentioned first reset voltage Vinit1 and second reset voltage Vini2.
  • the orthographic projection of the spacer 402 on the base substrate 101 partially overlaps the orthographic projection of the reset voltage line VT on the base substrate 101.
  • FIG. 3 is a schematic plan view of a display substrate provided by at least one embodiment of the present disclosure.
  • the display substrate includes a base substrate 101, a plurality of sub-pixels 100 are located on the base substrate 101, and are arranged on the base substrate 101 along the row direction (ie the horizontal direction in the figure) and the column direction (ie the vertical direction in the figure) For the array. It is assumed that the column direction of the sub-pixel array is the first direction D1, the row direction is the second direction D2, and the first direction D1 and the second direction D2 intersect, for example, orthogonally.
  • FIG. 1 is the first direction D1
  • the row direction is the second direction D2
  • the first direction D1 and the second direction D2 intersect, for example, orthogonally.
  • 3 exemplarily shows the pixel circuit of four sub-pixels (ie, the first sub-pixel 100a, the second sub-pixel 100b, the third sub-pixel 100c, and the fourth sub-pixel 100d) directly adjacent to each other in a row of sub-pixel circuits
  • the dashed frame shows the area where the pixel circuit of each sub-pixel is located, and the embodiment of the present disclosure is not limited to this layout.
  • FIG. 4A corresponds to FIG. 3 and illustrates the semiconductor layer 102 and the first conductive layer (gate layer) 201 of the transistors T1-T7 in the four sub-pixels 100
  • FIG. 4B also shows the second conductive layer on the basis of FIG. 4A
  • FIG. 4C also shows a third conductive layer 203 on the basis of FIG. 4B
  • FIG. 4D also shows a fourth conductive layer 204 on the basis of FIG. 4C.
  • the figure only schematically shows the corresponding structure of four adjacent sub-pixels in a row of sub-pixels, but this should not be regarded as a limitation of the present disclosure.
  • the semiconductor layer 102, the first conductive layer 201, the second conductive layer 202, the third conductive layer 203, and the fourth conductive layer 204 are sequentially disposed on the base substrate 101, thereby forming the structure of the display substrate as shown in FIG. 3.
  • Tng, Tns, Tnd, and Tna are used to denote the gate, the first electrode, the second electrode, and the active layer of the n-th transistor Tn, respectively, where n is 1-7.
  • the “same layer arrangement” in the present disclosure refers to a structure formed by two (or more than two) structures formed by the same deposition process and patterned by the same patterning process. Their materials Can be the same or different.
  • the "integrated structure” in the present disclosure refers to two (or more than two) structures that are formed by the same deposition process and patterned by the same patterning process, and their materials can be the same or different. .
  • the first conductive layer 201 includes the gate of each transistor and some scan lines and control lines.
  • a large dashed frame shows the area where the pixel circuit of each sub-pixel 100 is located, and a small dashed frame shows the gates T1g-T7g of the first to seventh transistors T1-T7 in one sub-pixel 100.
  • the semiconductor layer 102 includes the active layers T1a-T7a of the first to seventh transistors T1-T7. As shown in FIG. 3A, the active layers T1a-T7a of the first to seventh transistors T1-T7 are connected to each other as an integral structure.
  • the semiconductor layer 20 in each column of sub-pixels is an integrated structure connected to each other, and the semiconductor layers in two adjacent columns of sub-pixels are spaced apart from each other.
  • the first conductive layer 104 includes the gates T1g-T7g of the first to seventh transistors T1-T7.
  • the third transistor T3 and the sixth transistor T6 adopt a double gate structure, which can improve the gate control capability of the transistor and reduce the leakage current.
  • the first conductive layer 104 further includes a plurality of scan lines 210, a plurality of reset control lines 220/RST, and a plurality of light emission control lines 230/EM that are insulated from each other.
  • each row of sub-pixels is respectively connected to a scan line 210, a reset control line 220/RST, and a light emission control line 230/EM.
  • the scan line 210 is electrically connected to the gate of the second transistor T2 in the corresponding row of sub-pixels (or in an integrated structure) to provide the first scan signal Ga1, and the reset control line 220/RST is connected to the sixth transistor in the corresponding row of sub-pixels.
  • the gate of T6 is electrically connected to provide the first reset signal Rst1
  • the emission control line 230/EM is electrically connected to the gate of the fourth transistor T4 in the corresponding row of sub-pixels to provide the first emission control signal EM1.
  • the scan line 210 is also electrically connected to the gate of the third transistor T3 to provide a second scan signal Ga2; the light emission control line 230/EM is also electrically connected to the gate of the fifth transistor T5 to The second light emission control signal EM2 is provided, that is, the first light emission control signal EM1 and the second light emission control signal EM2 are the same signal.
  • the gate of the seventh transistor T7 of the sub-pixels in the current row is electrically connected to the reset control line 220/RST corresponding to the sub-pixels in the next row to receive the second reset signal Rst2.
  • the row direction line dividing the pixel circuit area of the sub-pixel may be the reset control line 220/RST or the light emission control line 230/EM.
  • the display substrate 20 adopts a self-aligned process, using the first conductive layer 201 as a mask to conduct a conductive treatment (for example, doping treatment) on the semiconductor layer 102, so that the semiconductor layer 102 is not
  • a conductive treatment for example, doping treatment
  • the portion covered by the first conductive layer 201 is conductive, so that the portions of the active layer of each transistor located on both sides of the channel region are conductive to form the first electrode and the second electrode of the transistor, respectively.
  • the second conductive layer 202 includes the first capacitor electrodes Ca of the first to seventh transistors T1-T7.
  • the first capacitor electrode Ca overlaps with the gate T1g of the first transistor T1 in the direction perpendicular to the base substrate 101 to form a storage capacitor Cst, that is, the gate T1g of the first transistor T1 serves as the first transistor of the storage capacitor Cst.
  • the first capacitor electrode Ca includes a via 301 that exposes at least part of the gate T1g of the first transistor T1, so that the gate T1g is electrically connected to other structures.
  • the second conductive layer 202 may further include a plurality of reset voltage lines 240/VT, and the plurality of reset voltage lines 240/VT are connected to a plurality of rows of sub-pixels in a one-to-one correspondence.
  • the reset voltage line 240/VT is electrically connected to the first pole of the sixth transistor T6 in the corresponding row of sub-pixels to provide the first reset voltage Vinit1.
  • the first pole of the seventh transistor T7 in the sub-pixels in the current row is electrically connected to the reset voltage line 240/VT corresponding to the sub-pixels in the next row to receive the second reset voltage Vinit2.
  • the second conductive layer 202 may further include a shielding electrode 221 that overlaps the first electrode T2s of the second transistor T2 in a direction perpendicular to the base substrate 101 so as to protect the The signal in the first pole T2s of the second transistor T2 is not interfered by other signals. Since the first electrode T2s of the second transistor T2 is configured to receive the data signal Vd, and the data signal Vd determines the display gray scale of the sub-pixel, the shield electrode 221 improves the stability of the data signal, thereby improving the display performance.
  • the third conductive layer 203 includes a plurality of first power lines 250 extending along the first direction D1.
  • the plurality of first power lines 250 are electrically connected to a plurality of columns of sub-pixels in a one-to-one correspondence to provide the first power voltage VDD.
  • the first power line 250 is electrically connected to the first capacitor electrode Ca in the corresponding column of sub-pixels through the via hole 302, and is electrically connected to the first electrode of the fourth transistor T4 through the via hole 303.
  • the first power line 250 is also electrically connected to the shield electrode 221 through the via 304, so that the shield electrode 221 has a fixed potential, which improves the shielding ability of the shield electrode.
  • the third conductive layer 203 further includes the plurality of data lines 12.
  • the multiple data lines 12 are electrically connected to multiple columns of sub-pixels in a one-to-one correspondence to provide data signals.
  • the data line 12 is electrically connected to the first electrode T2s of the second transistor T2 in the corresponding column of sub-pixels through the via 305 to provide the data signal.
  • the third conductive layer 203 further includes a first connection electrode 231.
  • One end of the first connection electrode 231 is connected to the gate T1g of the first transistor T1 through the via 301, that is, the second capacitor electrode.
  • Cb is electrically connected, and the other end is electrically connected to the first electrode of the third transistor T3, so that the second capacitor electrode Cb is electrically connected to the first electrode T3s of the third transistor T3.
  • the third conductive layer 203 further includes a second connecting electrode 232, and both ends of the second connecting electrode 232 are connected to the first electrode T6s of the sixth transistor T6 and the reset voltage line 240/VT respectively. Connected so that the first pole T6s of the sixth transistor T6 can receive the first reset voltage Vinit1 from the reset voltage line 240/VT.
  • the third conductive layer 203 further includes a third connection electrode 233, which is electrically connected to the second electrode T5d of the fifth transistor T5, and is used for the second electrode T5d of the fifth transistor T5.
  • the second electrode T5d is electrically connected to the first electrode 134 of the light-emitting element, which will be described in detail later.
  • the fourth conductive layer 204 includes a second power line 260 that extends along the second direction D2 and electrically connects a plurality of first power lines 240 to form a mesh The power cord structure.
  • This structure helps to reduce the resistance of the power line, thereby reducing the voltage drop of the power line, and helps to uniformly transmit the first power supply voltage to each sub-pixel of the display substrate.
  • the fourth conductive layer 204 further includes a plurality of third power lines 270 that extend along the first direction D1 and are electrically connected to the plurality of first power lines 250 in a one-to-one correspondence.
  • the third power line 270 and the corresponding first power line 250 overlap each other in a direction perpendicular to the base substrate 101, and are electrically connected to each other through the via 306.
  • one via 306 is provided corresponding to each sub-pixel, so that each third power line 270 and the corresponding first power line 250 form a parallel structure, which helps to reduce the resistance of the power line.
  • the second power line 260 and the third power line 270 are electrically connected to each other or form an integral structure, so that the plurality of first power lines 250, the plurality of second power lines 260, and the plurality of third power lines 270 are formed as Mesh power cord structure.
  • the fourth conductive layer 204 further includes a fourth connection electrode 234 insulated from the third power line 270, and the fourth connection electrode 234 is electrically connected to the third connection electrode 233 through a via 307, so that the fifth transistor
  • the second electrode T5d of T5 is electrically connected to the first electrode 134 of the light-emitting element.
  • FIG. 4E also shows a fifth conductive layer 205 on the basis of FIG. 4D, and the fifth conductive layer 205 includes the first electrode 134 of the light emitting element 120.
  • the second power supply line 260 does not overlap in the direction perpendicular to the base substrate 101. This arrangement can prevent the first electrode 134 of the light emitting element from being uneven due to overlapping with the second power line 260.
  • the light-emitting layer of the light-emitting element 120 is directly formed on the first electrode 134 and an effective light-emitting area (open area) is formed.
  • the flatness of the first electrode 134 directly affects the light-emitting efficiency of the light-emitting layer, thereby affecting the light-emitting performance of the light-emitting element 120.
  • the second power line 260 may have a curved structure to match the pattern of the first electrode 134.
  • two adjacent second power lines 260 define a row of sub-pixels 100.
  • the second power cord 260 includes a first portion 261 and a second portion 262 that are alternately connected.
  • the extension direction of the first portion 261 is parallel to each other and parallel to the second direction D2
  • the extension direction of the second portion 262 is parallel to each other and parallel to the second direction D2.
  • the direction intersects both the first direction D1 and the second direction D2.
  • each column of sub-pixels corresponds to a first part 261 respectively.
  • FIG. 4E shows the first electrodes 134a, 134b, 134c, and 134d of the four adjacent sub-pixels, and then a pixel defining layer is formed on the first electrodes 134a, 134b, 134c, and 134d, and a plurality of the pixel defining layers
  • the openings respectively expose these first electrodes.
  • the first opening 4011 exposes the first electrode 134c.
  • the shape of the first opening 4011 may be the same as or similar to the shape of the first electrode 134c, and the size of the first opening 4011 may be slightly smaller than that of the first electrode 134c.
  • the second opening 4012 exposes the first electrode 134a, and the second opening 4012
  • the shape of the first electrode 134a may be the same or similar, and the size of the second opening 4012 may be slightly smaller than the size of the first electrode 134a, so that the orthographic projection of the second opening 4012 on the base substrate 101 is completely located on the first electrode 134a
  • the shape of the two third openings 4013 may be the same as or similar to the shape of the first electrode 134b and the first electrode 134d, and the size of the two third openings 4013 may be slightly smaller than that of the first electrode 134b.
  • One electrode 134b and the first electrode 134d so that the orthographic projections of the two third openings 4013 on the base substrate 101 are completely located in the orthographic projections of the first electrode 134b and the first electrode 134d on the base substrate 101, respectively.
  • a light-emitting layer and a second electrode are formed on the first electrodes 134a, 134b, 134c, and 134d, respectively, so as to form the light-emitting elements of the first sub-pixel 100a, the second sub-pixel 100b, the third sub-pixel 100c, and the fourth sub-pixel 100d.
  • the first sub-pixel 100a, the second sub-pixel 100b, the third sub-pixel 100c, and the fourth sub-pixel 100d constitute a repeating unit of the display substrate.
  • the color of the light emitted by the light-emitting element of the second sub-pixel 100b and the color of the light emitted by the light-emitting element of the fourth sub-pixel 100d are the same, that is, the second sub-pixel 100b and the fourth sub-pixel 100b
  • the sub-pixels 100d are sub-pixels of the same color.
  • the second sub-pixel 100b and the fourth sub-pixel 100d are sensitive color sub-pixels.
  • the above-mentioned sensitive color is green, that is, the second sub-pixel 100b and the fourth sub-pixel
  • the pixels 100d are all green sub-pixels.
  • the first sub-pixel 100a may be a red sub-pixel
  • the third sub-pixel 100c may be a blue sub-pixel.
  • each repeating unit may form two dummy pixels, and the first sub-pixel 100a and the third sub-pixel 100c in the repeating unit are respectively shared by the two dummy pixels.
  • the sub-pixels in the multiple repeating units form a pixel array.
  • the sub-pixel density is 1.5 times the virtual pixel density
  • the sub-pixel density is 1.5 times the virtual pixel density
  • the second sub-pixel 100b and the fourth sub-pixel 100d belong to two virtual pixels, respectively.
  • each virtual pixel is not limited.
  • the division of virtual pixels is related to the driving mode, and the specific division mode of virtual pixels can be determined according to the actual driving mode, which is not specifically limited in the present disclosure.
  • the shape and size of the multiple opening regions corresponding to the sub-pixel 100 can be changed according to the luminous efficiency and service life of the light-emitting layer that emits light of different colors.
  • the corresponding opening of the light-emitting layer with a shorter light-emitting life can be changed.
  • the area is set larger to improve the stability of light emission.
  • the sizes of the openings of the blue sub-pixel, red sub-pixel, and green sub-pixel can be sequentially reduced. Since the opening area is provided on the first electrode 134, correspondingly, as shown in FIG. 4, the first electrodes 134a, 121b of the first sub-pixel 100a, the second sub-pixel 100b, the third sub-pixel 100c, and the fourth sub-pixel 100d The areas of, 121c and 121d decrease sequentially.
  • two adjacent rows of repeating units are staggered by 1/2 pitch in the row direction, and the pitch is the distance between the centers of two first sub-pixels 100a in two adjacent repeating units in the row direction.
  • the pitch may also be the distance between the centers of the two third sub-pixels 100c in two adjacent repeating units along the row direction; the aforementioned center may be the geometric center of the sub-pixel.
  • the embodiments of the present disclosure include but are not limited to this, and two adjacent rows of repeating units may also be misaligned by other distances, or not positioned correctly.
  • the positions of the first sub-pixel and the third sub-pixel in the two adjacent repeating units in the column direction are interchanged, and the second sub-pixel corresponds to the fourth sub-pixel.
  • the first sub-pixels and the third sub-pixels are alternately arranged in rows or columns in the row and column directions
  • the second sub-pixels and the fourth sub-pixels are arranged in rows or columns in the row and column directions.
  • the rows composed of the first sub-pixels and the third sub-pixels and the rows composed of the second sub-pixels and the fourth sub-pixels are alternately arranged in the column direction.
  • the columns composed of the first sub-pixels and the third sub-pixels and the columns composed of the second sub-pixels and the fourth sub-pixels are alternately arranged in the row direction.
  • the sub-pixel or a fourth sub-pixel is located in the virtual rectangle, wherein the two first sub-pixels cover the two vertex corners on the diagonal of the virtual rectangle, and the two third sub-pixels cover the other corners of the virtual rectangle.
  • the two top corners on a diagonal are two first sub-pixels and two third sub-pixels distributed in two rows and two columns forming a 2*2 matrix respectively cover the vertices of a virtual rectangle
  • a second The sub-pixel or a fourth sub-pixel is located in the virtual rectangle, wherein the two first sub-pixels cover the two vertex corners on the diagonal of the virtual rectangle, and the two third sub-pixels cover the other corners of the virtual rectangle.
  • the two top corners on a diagonal are two top corners on a diagonal.
  • the first electrode 134 of each sub-pixel is electrically connected to the fourth connection electrode 234 through the via 308, so that the second electrode T5d of the fifth transistor T5 is electrically connected to the first electrode 134 of the light-emitting element 120. connection.
  • the position of at least one spacer 402 formed on the pixel defining layer is as shown by the dashed frame.
  • the first orthographic projection of the spacer 402 on the base substrate and each first electrode The orthographic projections of 134a, 134b, 134c, and 134d on the base substrate do not overlap, and the shortest distance between the boundary of the spacer 402 and its directly adjacent first opening 4011, the second opening 4012 and the third opening 4013 is greater than Or equal to 5 ⁇ m.
  • each repeating unit is correspondingly provided with a spacer, and the spacer is disposed on the first of the two green sub-pixels (that is, the second sub-pixel 100b and the fourth sub-pixel 100d) of each repeating unit.
  • No spacers are provided between the three openings 4013 and the third openings 4013 of the two green sub-pixels of adjacent repeating units. At this time, the ratio of the number of spacers on the display substrate to the number of green sub-pixels It is 1:2.
  • a line connecting the centers of the third openings 4013 of two green sub-pixels passes through the spacer 402 between them, and the line is parallel to the length direction of the spacer 402.
  • the length direction is the extending direction of the long sides of the rectangle.
  • the length direction of the spacer 402 is the horizontal display direction of the display substrate, that is, the horizontal direction of the image seen by the human eye when the display substrate performs display.
  • both sides of the spacer 402 in the horizontal direction are green sub-pixels, when the viewer views the display substrate from both sides, the sub-pixels that may be blocked by the spacer 402 are the same sub-pixels. Therefore, when the viewer views from different sides of the display substrate, the color shift phenomenon will not occur.
  • the orthographic projection of the first part 261 of the second power cord on the base substrate partially overlaps the first orthographic projection of the spacer 402 on the base substrate, and the second part 262 of the second power cord is on the base substrate.
  • the orthographic projection of is also partially overlapped with the first orthographic projection of the spacer 402 on the base substrate.
  • the orthographic projection of the third power line 270 on the base substrate also partially overlaps with the first orthographic projection of the spacer 402 on the base substrate.
  • the spacer 402 is formed at a position where the first part 261, the second part 262 and the third power line 270 of the second power line intersect.
  • the orthographic projection of each data line 12 on the base substrate does not overlap with the first orthographic projection of the spacer 402 on the base substrate.
  • the spacer 402 is formed between two adjacent data lines 12, that is, between the data line of the pixel circuit of the current column and the data line of the pixel circuit of the next column.
  • the data line 12 on the side is the data line of the pixel circuit of the current column
  • the data line 12 located on the right side of the second opening 4012 is the data line of the pixel circuit of the next column.
  • At least one spacer 402 is located on the emission control line 230/EM (for driving the fourth thin film transistor T4 and T4 and T4 of the pixel circuit of the current row) of the pixel circuit of the current row (for example, a row of pixel circuits framed in FIG. 4A and FIG. 4B).
  • the fifth row of thin film transistors T5) and the reset control line 220/RST of the pixel circuit of the next row are closer Reset control line 220/RST.
  • the orthographic projection of at least one spacer 402 on the base substrate 101 and the orthographic projection of the reset voltage line 240/VT on the base substrate 101 partially overlap.
  • each repeating unit may be provided with two spacers 402 corresponding to each other.
  • a spacer 402 is arranged between each adjacent second sub-pixel 100b and fourth sub-pixel 100d, and a plurality of spacers 402 are uniformly arranged on the display substrate in multiple rows and multiple columns.
  • the plurality of spacers 402 arranged in an array can isolate the display substrate and the FMM at multiple positions of the display substrate, preventing the FMM from contacting the display substrate and scratching the display substrate.
  • each repeating unit may be provided with a spacer corresponding to the situation shown in FIGS. 1A, 1B, and 4E.
  • a plurality of spacers 402 are staggered and evenly distributed on the display substrate.
  • the spacers in the odd-numbered rows are misaligned with the spacers in the even-numbered rows by 1/2 pitch.
  • a pitch refers to the distance between two adjacent spacers in each row of spacers; or, it can be One spacer is provided for every two repeating units; alternatively, one spacer may be provided for every four repeating units (for example, the four repeating units are arranged in a 2 ⁇ 2 array). Under the above arrangement, the spacers can all show a sufficient and uniform support effect.
  • each repeating unit corresponds to a spacer.
  • the ratio of the number of spacers 402 on the display substrate to the total number of sub-pixels is approximately It is 1:4.
  • the orthographic projection of the spacer 402 on the base substrate and the area where the pixel circuit of the red sub-pixel is located is on the base substrate.
  • the orthographic projections overlap, and at this time, the ratio of the number of spacers 402 on the display substrate to the number of red sub-pixels is approximately 1:1.
  • the above proportional relationship is defined according to the central area of the display area. For some areas of the edge, consider the peripheral structure or the design of redundant pixels. Some locations may have missing spacers, or the position and number of spacers. The adjustment of, or the adjustment of the position and number of sub-pixels, so the above proportional relationship can fluctuate, for example, it can fluctuate within a range of 10% up and down.
  • the orthographic projection shape of the spacer 402 on the base substrate 101 may be a rectangle.
  • the length L of the rectangle may be 20 ⁇ m-30 ⁇ m, such as 22 ⁇ m, 25 ⁇ m, or 28 ⁇ m.
  • the width W of the rectangle may be 10 ⁇ m-16 ⁇ m, for example, 12 ⁇ m or 15 ⁇ m.
  • the center O of the first orthographic projection of the spacer 402 on the base substrate 101 is the center of the rectangle.
  • the shape of the first orthographic projection of the spacer 402 on the base substrate 101 may also be a circle, an ellipse, a triangle, or other polygons.
  • the spacer 402 is on the base substrate 101.
  • the center O of the first orthographic projection above is the center of a circle or an ellipse or the center of gravity of a triangle or other polygon.
  • the shape of the first orthographic projection of the spacer 402 on the base substrate 101 may also be an irregular pattern. At this time, the first orthographic projection of the spacer 402 on the base substrate 101 is The center O is the center of gravity of the irregular figure.
  • the height of the spacer 402 may be 0.8 ⁇ m-1.5 ⁇ m, such as 1 ⁇ m or 1.2 ⁇ m.
  • the spacer 402 can sufficiently isolate the FMM and the display substrate, and prevent the FMM from contacting the display substrate and scratching the display substrate.
  • the material of the spacer 402 may be polyimide (PI). Since polyimide is a photosensitive material and can be used as a photoresist material, during the manufacturing process, the spacer 402 can be directly formed through an exposure process and a development process.
  • PI polyimide
  • Fig. 4F shows a schematic cross-sectional view of the display substrate in Fig. 4E along A-A'.
  • the semiconductor layer 102, the first insulating layer 103, the first conductive layer 201, the second insulating layer 104, the second conductive layer 202, the third insulating layer 105, the third conductive layer 203, and the fourth insulating layer 106, the fourth conductive layer 204, the fifth insulating layer 107, and the fifth conductive layer 205 are sequentially disposed on the base substrate 101, thereby forming the structure of the display substrate as shown in FIG. 4E.
  • the display substrate further includes a pixel defining layer 430 on the first electrode 134a of the light emitting element 120.
  • An opening 401 (the second opening 4012 in the cross-sectional view) is formed in the pixel defining layer 430 to define a light-emitting area of one sub-pixel.
  • the light-emitting layer 136 is formed in the opening 401, and the second electrode 135 is formed on the light-emitting layer 136 to form the light-emitting element 120.
  • the second electrode 135 is a common electrode, and the entire surface is arranged in the display substrate.
  • the spacer 402 is disposed on the pixel defining layer, and the first orthographic projection of the spacer 402 on the base substrate 101 is located on the second orthographic projection of the light-emitting control line 230/EM on the base substrate 101.
  • the projection and reset control line 220/RST is between the third orthographic projection on the base substrate 101 and is closer to the third orthographic projection.
  • the orthographic projections overlap.
  • the first orthographic projection of the spacer 402 on the base substrate 101 and the orthographic projection of the first electrode 134a on the base substrate 101 do not overlap, and the spacer 402 is directly adjacent to the opening 401 (the second opening).
  • the shortest distance D of the boundary of 4012) is greater than or equal to 5 ⁇ m.
  • the base substrate 101 may be a rigid substrate, such as a glass substrate, a silicon substrate, etc., or may be formed of a flexible material with excellent heat resistance and durability, such as polyimide (PI).
  • PI polyimide
  • PC Polycarbonate
  • PET polyethylene terephthalate
  • PET polyethylene
  • PAT polyacrylate
  • PAT polyarylate
  • Petherimide polyethersulfone
  • PET polyethylene glycol terephthalate
  • PMMA polypropylene
  • PSF polysulfone
  • PMMA polymethyl methacrylate
  • TAC cellulose triacetate
  • COP cyclic olefin polymer
  • COC cyclic olefin copolymer
  • the material of the semiconductor layer 102 includes, but is not limited to, silicon-based materials (a-Si, polysilicon, p-Si, etc.), metal oxide semiconductors (IGZO, ZnO, AZO, IZTO, etc.), and organic materials (hexathiophene , Polythiophene, etc.).
  • the material of the first to fourth conductive layers may include gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W) and the above Alloy materials composed of metals; or conductive metal oxide materials, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), zinc aluminum oxide (AZO), etc.
  • the light-emitting element 120 has a top-emitting structure
  • the first electrode 134 has reflectivity
  • the second electrode 135 has transmissive or semi-transmissive properties.
  • the first electrode 134 is a high work function material to act as an anode, such as an ITO/Ag/ITO laminate structure
  • the second electrode 135 is a low work function material to act as a cathode, such as a semi-transmissive metal or metal alloy
  • the material is, for example, an Ag/Mg alloy material.
  • the first insulating layer 103, the second insulating layer 104, and the third insulating layer 105 are, for example, inorganic insulating layers, such as silicon oxides such as silicon oxide, silicon nitride, and silicon oxynitride, silicon nitrides, or silicon nitrides. Oxides, or aluminum oxide, titanium nitride, etc. include metal oxynitride insulating materials.
  • the fourth insulating layer 106, the fifth insulating layer 107, and the pixel defining layer 108 include organic insulating materials, such as polyimide (PI), acrylate, epoxy, polymethylmethacrylate (PMMA), etc. Organic insulating materials.
  • the fourth insulating layer 106 and the fifth insulating layer 107 are planarization layers.
  • the first orthographic projection of the spacer 402 on the base substrate 101 is located on the second orthographic projection of the first signal line on the base substrate 101 and the second orthographic projection of the second signal line on the base substrate 101 between the third orthographic projection on 101, that is, the first orthographic projection of the spacer 402 on the base substrate 101 does not exceed the second orthographic projection of the first signal line on the base substrate 101 and the second signal line on the base substrate 101 Within the range defined by the third orthographic projection on the base substrate 101, when preparing the spacer 402, the position of the first signal line and the second signal line can be used as a reference to accurately locate the formation position of the spacer 402.
  • the center O of the first orthographic projection of the spacer 402 on the base substrate 101 is distanced from the second orthographic projection of the first signal line (for example, the emission control line EM) on the base substrate 101
  • the distance of the central axis EM0 is greater than the distance between the center O of the first orthographic projection and the central axis RST0 of the third orthographic projection of the second signal line (for example, the reset control line RST) on the base substrate 101.
  • the spacer 402 is closer to the second signal line than the first signal line and the second signal line.
  • the distance between the spacer 402 and the bottom of the pixel defining layer can be ensured.
  • the distance between the sidewalls of the upper surface of the plurality of openings 401 is greater than or equal to 5 ⁇ m, and the distance between the spacer 402 and the plurality of openings 401 is closer or substantially the same.
  • At least one embodiment of the present disclosure provides a display device including any of the above-mentioned display substrates.
  • the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and so on.
  • At least one embodiment of the present disclosure provides a method for preparing a display substrate. As shown in FIG. 6, the method includes steps S101-S103.
  • Step S101 Provide a base substrate.
  • the provided base substrate 101 may be various types of substrates such as a glass substrate and a silicon substrate, which are not limited in the embodiment of the present disclosure.
  • a stack of barrier layers and buffer layers may be formed on the base substrate 101 to prevent impurities in the base substrate 101 from entering functional layers such as pixel circuit structures to be formed later.
  • a pixel circuit structure is formed on the stack of the barrier layer and the buffer layer.
  • the pixel circuit structure includes a pixel circuit for driving the display panel for display.
  • the pixel circuit can be a 2T1C drive circuit, a 3T1C drive circuit, or a 7T1C drive circuit. Drive circuit, etc.
  • the embodiment of the present disclosure does not limit the type and formation method of the driving circuit.
  • FIG. 7 shows a schematic partial cross-sectional view of the display substrate during the preparation process.
  • forming a pixel circuit structure includes forming a plurality of thin film transistors on a stacked layer of a barrier layer and a buffer layer.
  • the capacitor and the first electrode 134a of the light-emitting element 120, etc., the method for preparing the pixel circuit structure will be described in detail below.
  • the method for preparing the pixel circuit structure includes steps S11-S22 of the pixel circuit structure.
  • Step S11 forming a semiconductor material layer on the base substrate, and performing a patterning process on the semiconductor material layer to form a semiconductor layer 102 as shown in FIG. 4A.
  • the semiconductor layer 102 includes the first to seventh transistors in each sub-pixel area T1-T7 active layers T1a-T7a and doped region patterns (that is, corresponding to the source regions and drain regions of the first to seventh transistors T1-T7), and the active layer patterns of each transistor in the same pixel region It is integrated with the doped region pattern.
  • the active layer may include an integrally formed low-temperature polysilicon layer, in which the source region and the drain region may be conductive through doping or the like to achieve electrical connection of each structure. That is, the active semiconductor layer of each transistor of each sub-pixel is an overall pattern formed of p-silicon, and each transistor in the same pixel region includes a doped region pattern (ie, a source region and a drain region) and an active layer Pattern, the active layers of different transistors are separated by doped structures.
  • Step S12 forming a first insulating layer 103 (for example, a transparent layer) on the semiconductor layer 102, such as a gate insulating layer, and forming a plurality of first insulating layer via holes on the first insulating layer for subsequent formation
  • the pattern of the third conductive layer 203 is connected.
  • corresponding first insulating layer via holes are formed in the first insulating layer, that is, the first insulating layer via holes are respectively connected to the source region and the drain region in the semiconductor layer.
  • the drain region overlaps for the source region and the drain region and the data line 12, the first power line 250, the first connection electrode 231, the second connection electrode 232, and the third connection electrode 233 in the third conductive layer Connect with other structures, such as vias 402, vias 405, vias 303, and vias 305 that penetrate the first insulating layer.
  • Step S13 forming a first conductive material layer on the first insulating layer, and performing a patterning process on the first conductive material layer to form a first conductive layer 201 as shown in FIG.
  • the scanning line 210, the reset control line 220, and the light emission control line 230 extending in the direction.
  • the correspondingly connected reset control lines 220, scan lines 210, and light emission control lines 230 are sequentially arranged along the first direction.
  • the first conductive layer 201 further includes the gates T1g-T7g of the first to seventh transistors T1-T7.
  • the gate T6g of the sixth transistor T6 and the reset control line 220 are integrated, that is, a part of the reset control line 220 serves as the gate T6g of the sixth transistor T6;
  • the gate T2g of the second transistor T2 and the scan line 210 are The integrated structure, that is, the part of the scan line 210 serves as the gate T2g of the second transistor T2;
  • the gate T4g of the fourth transistor T4 and the gate T5g of the fifth transistor T5 are both integrated with the light emission control line 230, that is, light emission
  • a part of the control line 230 serves as the gate T4g of the fourth transistor T4 and the gate T5g of the fifth transistor T5;
  • the gate T7g of the seventh transistor T7 and the reset control line 220 corresponding to the next row of pixel circuits are integrated.
  • the sixth transistor T6 and the third transistor T3 both have a double-gate structure
  • the two gates T6g of the sixth transistor T6 are both part of the reset control line 220
  • one gate of the third transistor T3 is a part of the scan line 210.
  • the other gate of the third transistor T3 is a part that is integrally connected to the scan line 210 and protrudes toward the reset control line 220.
  • the overlapping portion of the semiconductor layer 102 and the first conductive layer 201 in a direction perpendicular to the base substrate defines the active layers (channel regions) T1a-T7a of the first to seventh transistors T1-T7.
  • the gate of the second transistor for example, a data writing transistor
  • the gate of the third transistor for example, a threshold compensation transistor
  • the sixth transistor for example, the first reset transistor
  • the gate of the seventh transistor (for example, the second reset transistor) and the gate of the seventh transistor (for example, the second reset transistor) T7 are located on the first side of the gate of the first transistor (for example, the driving transistor) T1, and the fourth transistor (for example, the first light-emitting control transistor)
  • the gate of T4 and the gate of the fifth transistor (for example, the second light-emitting control transistor) T5 are both located on the second side of the gate of the first transistor T1.
  • the first side of the gate of the first transistor T1 in the same pixel area may be the upper side of the gate of the first transistor T1, and the second side of the gate of the first transistor T1 It may be the lower side of the gate of the first transistor T1.
  • the lower side for example, the side of the display substrate for bonding the IC is the lower side of the display substrate, and the lower side of the gate of the first transistor T1 is the side closer to the IC of the gate of the first transistor T1 .
  • the upper side is the opposite side of the lower side, for example, the side of the gate of the first transistor T1 further away from the IC.
  • the gate of the second transistor T2 and the gate of the fourth transistor T4 are both located on the third side of the gate of the first transistor T1, and the first gate of the third transistor T3 (and the scan line 210 is an integrated gate), the gate of the fifth transistor T5 and the gate of the seventh transistor T7 are all located on the fourth side of the gate of the first transistor T1.
  • the third side and the fourth side of the gate of the first transistor T1 in the same pixel area are opposite sides of the gate of the first transistor T1 in the D2 direction.
  • the third side of the gate of the first transistor T1 in the same pixel area may be the left side of the gate of the first transistor T1
  • the fourth side of the gate of the first transistor T1 may be The right side of the gate of the first transistor T1.
  • the left and right sides for example, in the same pixel area (the area where the pixel circuit is located), the data line is on the left side of the first power line 250, and the first power line 250 is on the right side of the data line.
  • Step S14 As shown in FIG. 4A, a self-aligned process is used to conduct a conductive treatment (for example, doping treatment) on the semiconductor layer 102 using the first conductive layer 201 as a mask, so that the semiconductor layer 102 is not exposed to the semiconductor layer 102.
  • the portion covered by the first conductive layer 201 is made conductive, so that the portions of the semiconductor layer 102 located on both sides of the active layer of each transistor are made conductive to form the source regions or drains of the first to seventh transistors T1-T7, respectively.
  • the pole regions that is, the first pole (T1s-T7s) and the second pole (T1d-T2d) of the first to seventh transistors T1-T7.
  • Step S15 forming a second insulating layer 104 (for example, a transparent layer) on the first conductive layer 201, for example, a second gate insulating layer. At least a second insulating layer via hole corresponding to the first insulating layer via hole is formed on the second insulating layer.
  • the via holes corresponding to at least the first insulating layer and the second insulating layer include at least via 402, via 405, via 303, via 305, and so on.
  • Step S16 forming a second conductive material layer on the second insulating layer 104 and on the second insulating layer, and performing a patterning process on the second conductive material layer to form a second conductive layer 202 as shown in FIG. 4B, that is, The shield electrode 221, the first capacitor electrode Ca, and the reset voltage line 240 extending in the first direction are formed to be insulated from each other.
  • the shield electrode 221 overlaps the first electrode T2s of the second transistor T2 in a direction perpendicular to the base substrate 101 to protect the signal in the first electrode T2s of the second transistor T2 from interference by other signals.
  • the first capacitor electrode Ca and the gate T1g of the first transistor T1 at least partially overlap in a direction perpendicular to the base substrate 101.
  • the patterning process also forms a via 301 in the first capacitor electrode Ca, and the via 301 exposes at least part of the gate T1g of the first transistor T1.
  • Step S17 forming a third insulating layer 105 on the second conductive layer 202.
  • the third insulating layer may be, for example, an interlayer insulating layer.
  • a via hole is formed in the third insulating layer for connection with the third conductive layer formed later. At least part of the vias correspond to the positions of the first insulating layer vias and the second insulating layer vias, and pass through the first insulating layer, the second insulating layer and the third insulating layer at the same time, such as vias 402, vias 405, and vias 303, via 305.
  • Step S18 A third conductive material layer is formed on the third insulating layer 105, and a patterning process is performed on the third conductive material layer to form a third conductive layer 203 as shown in FIG. 4C, that is, to form data lines 12 insulated from each other. , The first power line 250, the first connection electrode 231, the second connection electrode 232, and the third connection electrode 233. The data line 12 and the first power line 250 extend along the first direction D1.
  • the data line 12 overlaps with the first electrode T2s of the second transistor T2 in a direction perpendicular to the base substrate 101 and is electrically connected to the first electrode T2s of the second transistor T2 through the via 305.
  • the via 305 penetrates the first insulating layer 103, the second insulating layer 104, and the third insulating layer 105, for example.
  • the first power line 250 overlaps the shield electrode 221 in a direction perpendicular to the base substrate 101 and is electrically connected to the shield electrode 221 through a via 304, such as the via 304 penetrates the third insulating layer 105.
  • the first power line 250 is electrically connected to the first capacitor electrode Ca in the corresponding column of sub-pixels through the via 302, and is electrically connected to the first electrode T4s of the fourth transistor T4 through the via 303.
  • Electric connection For example, the via hole 302 penetrates the third insulating layer 105, and the via hole 303 penetrates the first insulating layer 103, the second insulating layer 104 and the third insulating layer 105.
  • one end of the first connecting electrode 231 passes through the via 301 in the first capacitor electrode Ca and the via 401 in the insulating layer and the gate T1g of the first transistor T1, namely The second capacitor electrode Cb is electrically connected, and the other end is electrically connected to the first electrode of the third transistor T3 through the via 402, so that the second capacitor electrode Cb is electrically connected to the first electrode T3s of the third transistor T3.
  • the via hole 401 penetrates the second insulating layer 104 and the third insulating layer 105
  • the via hole 402 penetrates the first insulating layer 103, the second insulating layer 104 and the third insulating layer 105.
  • one end of the second connecting electrode 232 is electrically connected to the reset voltage line through the via 403, and the other end is electrically connected to the sixth transistor T6 through the via 404, so that the first The terminal T6s can receive the first reset voltage Vinit1 from the reset voltage line 240.
  • the via hole 403 penetrates the third insulating layer 105
  • the via hole 404 penetrates the first insulating layer 103, the second insulating layer 104 and the third insulating layer 105.
  • the third connecting electrode 233 is electrically connected to the second electrode T5d of the fifth transistor T5 through the via 405, and is used to connect the second electrode T5d of the fifth transistor T5 to the light emitting diode.
  • the first electrode 134 of the element is electrically connected.
  • the via 405 penetrates the first insulating layer 103, the second insulating layer 104 and the third insulating layer 105.
  • Step S19 forming a fourth insulating layer 106 on the third conductive layer 203. And forming a via hole in the third insulating layer for connecting with the fourth conductive layer to be formed later.
  • the fourth insulating layer 106 includes a first planar layer.
  • the fourth insulating layer 106 includes two layers of a passivation layer and a first flat layer, and the via hole formed in the fourth insulating layer needs to penetrate through the two layers of the passivation layer and the first flat layer.
  • the first flat layer is located on the side of the passivation layer away from the third conductive layer.
  • Step S20 A fourth conductive material layer is formed on the fourth insulating layer 106, and a patterning process is performed on the fourth conductive material layer to form a fourth conductive layer 204 as shown in FIG. 4D, that is, a second power line 260, The third power line 270 and the fourth connection electrode 234 are connected to each other and the second power line 260 and the third power line 270 are insulated from the fourth connection electrode 234.
  • the plurality of third power lines 270 extend along the first direction D1, and are respectively electrically connected to the plurality of first power lines 250 through the vias 306 in a one-to-one correspondence.
  • each third power supply line 270 and the corresponding first power supply line 250 overlap each other in a direction perpendicular to the base substrate 101.
  • the via 306 penetrates the fourth insulating layer 106.
  • the fourth connection electrode 234 and the third connection electrode 233 overlap in a direction perpendicular to the base substrate 101, and the third connection electrode 234 passes through a via 307 penetrating the fourth insulating layer 106. It is electrically connected to the third connection electrode 233.
  • the manufacturing method of the display substrate may further include forming a fifth insulating layer 107 on the fourth conductive layer 204, and forming a fifth insulating layer 107 in the fifth insulating layer 107 for subsequent formation.
  • the fifth insulating layer 107 may be a second flat layer.
  • the fifth insulating layer via hole is used to connect the drain of the first transistor and the first electrode of the light-emitting device.
  • the fifth insulating layer via hole and the drain of the first transistor may overlap, or may not overlap, or overlap.
  • a connecting wire connection may be additionally provided in the third conductive layer, and the connection mode is related to the sub-pixel arrangement structure, such as the position and shape of the first electrode.
  • Step S22 A fifth conductive material layer is formed on the fifth insulating layer 107, and a patterning process is performed on the fifth conductive material layer to form a fifth conductive layer 205, that is, a plurality of first insulating layers for forming light-emitting elements are formed. Electrode 134 (shown as 134a in the figure).
  • each first electrode 134 includes a main body portion 141 and a connection portion 142.
  • the main body portion 141 is mainly used to drive the light-emitting layer to emit light
  • the connection portion 142 is mainly used to electrically connect with the pixel circuit.
  • the connecting portion 142 is electrically connected to the fourth connecting electrode 234 through a via 308 in the fifth insulating layer 107, for example, in a direction parallel to the surface of the base substrate 101, the via 308 Compared with the via 307, it is farther away from the main body portion 141 of the first electrode 134, that is, the opening 401 of the sub-pixel, that is, the orthographic projection of the via 308 on the substrate 101 is compared with that of the via 307 on the substrate. The orthographic projection on the substrate 101 is farther away from the orthographic projection of the opening 401 on the base substrate.
  • the manufacturing method of the display substrate may further include sequentially forming a pixel defining layer 108 on the fifth conductive layer 205, and in the pixel defining layer 108 corresponding to the main body of each first electrode 134
  • the portion 141 forms an opening 401, and then at least a light-emitting layer 136 is formed in the opening 401, and a second electrode 135 is formed on the light-emitting layer.
  • the material of the semiconductor material layer includes, but is not limited to, silicon-based materials (a-Si, polysilicon, p-Si, etc.), metal oxide semiconductors (IGZO, ZnO, AZO, IZTO, etc.) and organic materials (hexathiophene , Polythiophene, etc.).
  • silicon-based materials a-Si, polysilicon, p-Si, etc.
  • metal oxide semiconductors IGZO, ZnO, AZO, IZTO, etc.
  • organic materials hexathiophene , Polythiophene, etc.
  • the materials of the first conductive material layer, the second conductive material layer, the third conductive material layer, the fourth conductive material layer, the fifth conductive material layer, and the second electrode may include gold (Au), silver (Ag), Copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W), and alloy materials combined with the above metals; or transparent metal oxide conductive materials, such as indium tin oxide (ITO), Indium zinc oxide (IZO), zinc oxide (ZnO), zinc aluminum oxide (AZO), etc.
  • ITO indium tin oxide
  • IZO Indium zinc oxide
  • ZnO zinc oxide
  • AZO zinc aluminum oxide
  • the first insulating layer 103, the second insulating layer 104, the third insulating layer 105, the fourth insulating layer 106, and the fifth insulating layer 107 are, for example, inorganic insulating layers, such as silicon oxide, silicon nitride, and silicon oxynitride.
  • the oxide, silicon nitride or silicon oxynitride, or aluminum oxide, titanium nitride, etc. include metal oxynitride insulating materials.
  • some of these insulating layers may also be organic materials, such as the first flat layer and the second flat layer, such as polyimide (PI), acrylate, epoxy, polymethylmethacrylate (PMMA), etc.
  • PI polyimide
  • PMMA polymethylmethacrylate
  • the fourth insulating layer 106 and the fifth insulating layer 107 may include a flat layer.
  • the above-mentioned patterning process may use a conventional photolithography process, for example, including the steps of photoresist coating, exposure, development, drying, and etching.
  • Step S102 forming a pixel defining layer on the base substrate.
  • a pixel defining layer 403 is formed by a patterning process.
  • the pixel defining layer 403 includes a plurality of openings 401, and each opening 401 exposes the first electrode 134 for forming a sub-pixel.
  • the light emitting element 120 is a pixel defining layer 403 formed by a patterning process.
  • a patterning process includes multiple steps of photoresist coating, exposure, development, and etching.
  • a patterning process may only include the steps of exposure and development.
  • the material of the pixel defining layer 403 may be polyimide (PI). Since polyimide itself can be used as a photoresist material, it is possible to coat a polyimide material layer on the pixel circuit structure, and then The polyimide material layer is exposed and developed to form a pixel defining layer with a plurality of openings.
  • PI polyimide
  • Step S103 forming at least one spacer on the side of the pixel defining layer away from the base substrate.
  • forming at least one spacer includes forming a plurality of spacers arranged in an array, and each spacer has a similar formation position.
  • any point of the bottom of the formed spacer contacting the pixel defining layer is distance D from the side wall of the upper surface of the plurality of openings Greater than or equal to 5 ⁇ m.
  • the formation position of the spacer may be located by the position of the plurality of openings in the pixel defining layer.
  • the spacer is formed between the plurality of openings, and the distance D between any point of the bottom of the formed spacer that is in contact with the pixel defining layer and the sidewall of the upper surface of the plurality of openings is greater than or equal to 5 m.
  • the pixel circuit structure formed on the display substrate includes a first signal line and a second signal line arranged in parallel with each other.
  • the positions of the first signal line and the second signal line can be located, and then the first signal line and the second signal line can be positioned.
  • the positions of a signal line and a second signal line are the reference positioning spacer formation positions, so that the first orthographic projection of the formed spacer on the base substrate is located at the second orthographic projection of the first signal line on the base substrate.
  • the projection and the second signal line are between the third orthographic projection on the base substrate.
  • an optical detection device can be used to scan the positions of the first signal line and the second signal line, and then the formation position of the spacer is set based on the position of the first signal line and the second signal line, and then The position of the mask for forming the spacer is set so that the spacer formed by the mask is located at the above-mentioned set position.
  • the first signal line may be the light emission control signal line 230/EM
  • the second signal line may be the reset signal line 220/RST.
  • the distance between the center of the first orthographic projection of the spacer on the base substrate and the central axis of the second orthographic projection of the first signal line on the base substrate is greater than the center distance of the first orthographic projection.
  • the distance between the central axis of the third orthographic projection of the two signal lines on the base substrate, that is, the spacer is between the first signal line and the second signal line and is closer to the second signal line.
  • the material of the spacer may be polyimide (PI). Since polyimide itself can be used as a photoresist material, at this time, as shown in FIG. 7, forming the spacer 402 includes: A polyimide material layer is formed on the side of 403 away from the base substrate 101, and the polyimide material layer is exposed and developed through a mask to form spacers 402. For example, when the required height H of the spacer is 0.8 ⁇ m-1.5 ⁇ m, the formation thickness of the polyimide material layer is 0.8 ⁇ m-1.5 ⁇ m, such as 1 ⁇ m or 1.2 ⁇ m.
  • PI polyimide
  • the material of the spacer may be the same as the material of the pixel defining layer.
  • the spacer may be formed integrally with the pixel defining layer.
  • a halftone mask is used to form spacers and pixel defining layers through a patterning process.
  • each sub-pixel includes a pixel circuit structure and a light-emitting device.
  • the part of the light-emitting device located in the opening of the pixel defining layer is the actual light-emitting area.
  • the positional relationship with each signal line is described in terms of the pixel circuit area, that is, the area surrounded by the dashed line as shown in FIG. 4B.
  • the positional relationship between the spacer and the first electrode of each sub-pixel or the opening of the pixel defining layer is based on The actual position and coverage area of the opening of the first electrode or pixel defining layer will be described.
  • the orthographic projection shape of the spacer 402 on the base substrate 101 is a rectangle, and the length L of the rectangle may be 20 ⁇ m-30 ⁇ m, such as 22 ⁇ m, 25 ⁇ m, or 28 ⁇ m, etc., and the width D of the rectangle may be 10 ⁇ m. -16 ⁇ m, such as 12 ⁇ m or 15 ⁇ m, etc.
  • the shape of the first orthographic projection of the spacer 402 on the base substrate 101 may also be a circle, an ellipse, a triangle, or other polygons. The specific shape is not limited.
  • the light-emitting layer 136 can be formed in the plurality of openings 401 of the pixel defining layer 403 through a mask 420 (for example, FMM) using inkjet printing or evaporation methods.
  • the light-emitting layer 136 at least covers the opening of the pixel defining layer, and can also cover a part of the surface of the pixel defining layer away from the base substrate, so as to ensure that the light-emitting layer in the opening is more uniform and reliable.
  • the distance between the spacer 402 and the mask plate 420 is often relatively close. Due to gravity and other reasons, the spacer 402 and the middle part of the mask plate 420 may come into contact. 402 can support the mask 420 to prevent the mask 420 from scratching the functional structure that has been formed on the display substrate.
  • a second electrode 135 is formed on the light-emitting layer 136 by a method such as sputtering.
  • the second electrode 135 may be formed on the entire surface of the display substrate.
  • an encapsulation layer 410 is formed on the second electrode 135 to encapsulate and protect the display substrate.
  • the encapsulation layer 410 may include a plurality of encapsulation sub-layers, such as a stack of a plurality of inorganic sub-insulation layers and organic sub-insulation layers.
  • the material of the inorganic encapsulation sublayer includes inorganic materials such as silicon oxide, silicon nitride, or silicon oxynitride
  • the material of the organic encapsulation sublayer includes organic materials such as resin and polyimide.
  • the inorganic sub-insulating layer can be formed by deposition or the like, and the organic encapsulation sublayer can be formed by coating or the like.
  • the display substrate may also be covered with other structures such as a transparent cover plate, and the embodiments of the present disclosure do not specifically limit other structures of the display substrate.
  • the position, shape, and size of the spacer are designed so that the spacer can function as a mask (for example, FMM) provided on it. Sufficient support function to prevent the mask from scratching other functional structures formed on the display substrate. Therefore, the display substrate obtained by the preparation method has better reliability.
  • a mask for example, FMM

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种显示基板及其制备方法、显示装置。该显示基板包括衬底基板(101)、像素界定层(403)以及至少一个隔垫物(402)。像素界定层设置在衬底基板(101)上，包括多个开口(401)，至少一个隔垫物(402)设置在像素界定层(403)的远离衬底基板(101)的一侧。至少一个隔垫物(402)的与像素界定层(403)接触的底部的任意一点距离多个开口(401)的侧壁的上边缘的距离大于或等于5μm。该显示基板的制备过程中，隔垫物(402)具有更好的支撑效果，可以防止制备过程中使用的FMM刮伤显示基板的结构，因此该显示基板具有更好的信赖性。

Description

显示基板及其制备方法、显示装置 技术领域
本公开的实施例涉及一种显示基板及其制备方法、显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)显示面板具有自发光、对比度高、清晰度高、视角宽、功耗低、响应速度快、以及制造成本低等一系列优势，已经成为新一代显示面板的重点发展方向之一，因此受到越来越多的关注。
OLED显示面板的有机发光层等功能层通常利用高精度金属掩模板(Fine Metal Mask,FMM)通过蒸镀等方式制备，制备时，FMM通常与显示基板相距一定的距离，以防止FMM刮坏显示基板上的功能结构。
发明内容
本公开至少一实施例提供一种显示基板，该显示基板包括衬底基板、像素界定层以及至少一个隔垫物。像素界定层设置在衬底基板上，包括多个开口，至少一个隔垫物设置在所述像素界定层的远离所述衬底基板的一侧。所述至少一个隔垫物的与所述像素界定层接触的底部的任意一点距离多个所述开口的上表面的侧壁的距离大于或等于5μm。
例如，本公开至少一实施例提供的显示基板还包括像素电路结构，像素电路结构设置在所述衬底基板与所述像素界定层之间，包括相互平行设置的第一信号线和第二信号线，其中，所述至少一个隔垫物设置在所述衬底基板上的第一正投影位于所述第一信号线在所述衬底基板上的第二正投影和所述第二信号线在所述衬底基板上的第三正投影之间。
例如，本公开至少一实施例提供的显示基板中，所述第一信号线为发光控制信号线，所述第二信号线为复位信号线。
例如，本公开至少一实施例提供的显示基板中，所述第一正投影的中心距离所述第二正投影的中轴线的距离大于所述第一正投影的中心距离所述第三正投影的中轴线的距离。
例如，本公开至少一实施例提供的显示基板中，所述至少一个隔垫物包括排布为多行多列的多个隔垫物；所述像素电路结构包括排列为多行多列的多个像素电路，每行像素电路共用一条发光控制信号线和一条复位信号线，其中，其中，一行像素电路的发光控制信号线在所述衬底基板上的正投影和下一行像素电路的复位信号线在所述衬底基板上的正投影之间包括一行隔垫物在所述衬底基板的正投影。
例如，本公开至少一实施例提供的显示基板中，在每行像素电路中，每四个相邻的像素电路对应设置一个所述隔垫物。
例如，本公开至少一实施例提供的显示基板中，所述至少一个隔垫物包括排布为多行多列的多个隔垫物，位于奇数行的多个隔垫物与位于偶数行的多个隔垫物错位1/2节距。
例如，本公开至少一实施例提供的显示基板中，所述多个开口包括用于蓝色子像素的第一开口、用于红色子像素的第二开口和用于绿色子像素的第三开口，并且所述第一开口、所述第二开口和所述第三开口的开口大小依次减小。
例如，本公开至少一实施例提供的显示基板中，以一个蓝色子像素、一个红色子像素和两个绿色子像素为一个重复单元，所述显示基板包括排布为多行多列的多个重复单元；每个所述重复单元对应设置一个所述隔垫物；在每个重复单元中，所述两个绿色子像素的第三开口沿行方向排列，所述蓝色子像素的第一开口和所述红色子像素的第三开口沿列方向排列，所述隔垫物被所述两个绿色子像素的第三开口、所述蓝色子像素的第一开口和所述红色子像素的第三开口围绕。
例如，本公开至少一实施例提供的显示基板中，每个重复单元中两个绿色子像素的所述第三开口的中心的连线穿过所述隔垫物，且所述连线平行于所述隔垫物的长度方向。
例如，本公开至少一实施例提供的显示基板中，所述隔垫物的长度方向为所述显示基板的水平显示方向。
例如，本公开至少一实施例提供的显示基板中，所述隔垫物在所述衬底基板上的正投影与所述红色子像素的像素电路所在的区域在所述衬底基板上的正投影重叠。
例如，本公开至少一实施例提供的显示基板中，所述至少一个隔垫物的 高度为0.8μm-1.5μm。
例如，本公开至少一实施例提供的显示基板中，所述至少一个隔垫物在所述衬底基板上的正投影形状为矩形。
例如，本公开至少一实施例提供的显示基板中，所述矩形的长为20μm-30μm，所述矩形的宽为10μm-16μm。
例如，本公开至少一实施例提供的显示基板中，所述至少一个隔垫物的材料为聚酰亚胺。
例如，本公开至少一实施例提供的显示基板中，所述至少一个隔垫物包括呈阵列排布的多个隔垫物。
例如，本公开至少一实施例提供的显示基板中，所述多个开口包括用于蓝色子像素的第一开口、用于红色子像素的第二开口和用于绿色子像素的第三开口，并且所述第一开口、所述第二开口和所述第三开口的开口大小依次减小。
本公开至少一实施例提供一种显示基板，该显示基板包括：衬底基板，像素电路结构，设置在所述衬底基板上，包括相互平行设置的第一信号线和第二信号线，像素界定层，设置在所述像素电路结构的远离所述衬底基板的一侧，包括多个开口，以及至少一个隔垫物，设置在所述像素界定层的远离所述衬底基板的一侧；其中，所述至少一个隔垫物设置在所述衬底基板上的第一正投影位于所述第一信号线在所述衬底基板上的第二正投影和所述第二信号线在所述衬底基板上的第三正投影之间。
例如，本公开至少一实施例提供的显示基板中，所述第一信号线为发光控制信号线，所述第二信号线为复位信号线。
例如，本公开至少一实施例提供的显示基板中，所述像素电路结构还包括电源线，所属电源线包括交替连接的多个第一部分和多个第二部分；所述多个第一部分彼此平行且延伸方向与所述第一信号线和所述第二信号线的延伸方向相同，所述第二部分的延伸方向与所述第一部分的延伸方向均相交；所述第一部分在所述衬底基板上的正投影与所述第一正投影部分重叠，所述第二部分在所述衬底基板上的正投影与所述第一正投影部分重叠。
例如，本公开至少一实施例提供的显示基板中，所述像素电路结构还包括数据线，所述数据线的延伸方向与所述第一信号线和所述第二信号线的延伸方向垂直，所述数据线在所述衬底基板上的正投影与所述第一正投影不重 叠。
本公开至少一实施例提供一种显示基板，该显示基板包括：衬底基板，像素界定层，设置在所述衬底基板上，包括多个开口，以及至少一个隔垫物，设置在所述像素界定层的远离所述衬底基板的一侧；其中，所述多个开口包括开口大小依次减小的第一开口、第二开口和第三开口，在第一方向上，所述至少一个隔垫物的两侧分别为所述第一开口和所述第二开口，在与所述第一方向垂直的第二方向上，所述至少一个隔垫物的两侧均为所述第三开口。
例如，本公开至少一实施例提供的显示基板中，所述第一开口内包括蓝色发光层，所述第二开口内包括红色发光层，所述第三开口内包括绿色发光层。
例如，本公开至少一实施例提供的显示基板中，所述第一开口的形状为第一正方形，所述第二开口的形状为第二正方形，所述第一正方形的边长大于所述第二正方形的边长，所述第三开口的形状为长方形，所述长方形的长边与相邻的所述第一开口的第一正方形的边长平行，所述长方形的短边与相邻的所述第二开口的第二正方形的边长平行。
本公开至少一实施例提供一种显示装置，该显示装置包括上述任一所述的显示基板。
本公开至少一实施例提供一种显示基板的制备方法，包括：提供衬底基板，在所述衬底基板上形成像素界定层，所述像素界定层包括多个开口，以及在所述像素界定层的远离所述衬底基板的一侧形成至少一个隔垫物；其中，所述至少一个隔垫物的与像素界定层接触的底部的任意一点距离多个所述开口的上表面的侧壁的距离大于或等于5μm。
例如，本公开至少一实施例提供的显示基板的制备方法中，在所述像素界定层的远离所述衬底基板的一侧形成至少一个隔垫物包括：定位所述至少一个隔垫物的形成位置，使得形成的所述至少一个隔垫物的与像素界定层接触的底部的任意一点距离多个所述开口的上表面的侧壁的距离大于或等于5μm。
例如，本公开至少一实施例提供的显示基板的制备方法还包括：在所述衬底基板与所述像素界定层之间形成像素电路结构，所述像素电路结构包括相互平行设置的第一信号线和第二信号线，其中，定位所述至少一个隔垫物的形成位置包括：定位所述第一信号线和所述第二信号线的位置，以所述第 一信号线和所述第二信号线的位置为基准定位所述至少一个隔垫物的形成位置，使得形成的所述至少一个隔垫物设置在所述衬底基板上的第一正投影位于所述第一信号线在所述衬底基板上的第二正投影和所述第二信号线在所述衬底基板上的第三正投影之间。
例如，本公开至少一实施例提供的显示基板的制备方法中，所述第一信号线为发光控制信号线，所述第二信号线为复位信号线。
例如，本公开至少一实施例提供的显示基板的制备方法中，所述至少一个隔垫物的材料为聚酰亚胺，形成所述至少一个隔垫物包括：在所述像素界定层的远离所述衬底基板的一侧形成聚酰亚胺材料层，通过掩模板对所述聚酰亚胺材料层进行曝光和显影，以形成所述至少一个隔垫物。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1A为本公开至少一实施例提供的一种显示基板的平面示意图；
图1B为本公开至少一实施例提供的一种显示基板的另一平面示意图；
图2A和图2B为本公开至少一实施例提供的一种显示基板中像素电路的电路图；
图3为本公开至少一实施例提供的一种显示基板的平面示意图；
图4A-图4E为本公开至少一实施例提供的一种显示基板的像素电路结构的部分功能层的平面示意图；
图4F为图4E中的显示基板沿A-A’的截面示意图；
图5为本公开至少一实施例提供的一种显示基板的隔垫物的平面示意图；
图6为本公开至少一实施例提供的一种显示基板的制备方法的流程图；
图7为本公开至少一实施例提供的一种显示基板在制备过程中的截面示意图；以及
图8为本公开至少一实施例提供的一种显示基板在制备过程中的另一截面示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在显示基板的制备工艺中，有机发光层等功能层通常利用高精度金属掩模板(FMM)通过蒸镀等方式形成，此时，FMM通常与显示基板相距一定的距离，以防止FMM刮坏显示基板上的功能层。但是，在制备过程中，显示基板或者FMM由于重力等原因，中间部位会下凹，使得显示基板与FMM的距离变小，甚至显示基板会与FMM接触。此时，可以在显示基板上设置隔垫物(Photo Space,PS)以支撑FMM，由此避免FMM与显示基板上的功能结构接触而刮坏显示基板上的功能结构。此时，隔垫物的设置位置以及隔垫物的结构等会影响隔垫物的支撑效果，同时也会影响后续蒸镀工艺中蒸镀材料的蒸镀均匀性。
本公开至少一实施例提供一种显示基板及其制备方法、显示装置。该显示基板包括衬底基板、像素界定层以及至少一个隔垫物。像素界定层设置在衬底基板上，包括多个开口，每个开口限定一个子像素的发光区域。至少一个隔垫物设置在像素界定层的远离衬底基板的一侧。在像素界定层远离衬底基板一侧的表面上，至少一个隔垫物的与像素界定层接触的底部的任意一点距离与其直接相邻的多个开口的边界的距离大于或等于5μm。
在上述显示基板的制备过程中，隔垫物可以支撑FMM并隔离FMM与 显示基板，从而防止FMM刮坏显示基板上的功能层；另外，隔垫物与像素界定层的开口的边界距离大于或等于5μm，由于FMM或显示基板产生凹陷时变形的部位主要在被隔垫物支撑的部位，而远离隔垫物的部位变形较小且较均匀，使得像素界定层的开口底部与FMM基本保持平行，而不会因为FMM或显示基板在相邻的隔垫物之间产生的下凹等变形造成像素界定层的开口底部与FMM的平行关系产生较大变化，从而使得通过FMM蒸镀到像素界定层的开口中的材料更均匀，提高显示基板的质量。
下面通过几个具体的实施例对本公开一些实施例的显示基板及其制备方法、显示装置进行说明。
本公开至少一实施例提供一种显示基板，图1A示出了该显示基板的平面示意图。如图1A所示，该显示基板包括衬底基板101、像素界定层以及至少一个隔垫物402。像素界定层设置在衬底基板101上，包括多个开口401，多个开口401中形成用于发光元件的发光层等。至少一个隔垫物402设置在像素界定层的远离衬底基板101的一侧。至少一个隔垫物402的与像素界定层接触的底部的任意一点距离多个开口401的侧壁的上边缘(即多个开口401的侧壁的远离衬底基板101一侧的边缘，或者说，是像素界定层与隔垫物402接触的表面上多个开口401的边缘)的距离D大于或等于5μm。
例如，如图1A所示，多个开口包括开口大小不同的第一开口4011、第二开口4012和第三开口4013，在像素界定层远离衬底基板101一侧的表面上，隔垫物402距离与其直接相邻的各开口的边界的最短距离D，即隔垫物402的与像素界定层接触的底部的任意一点距离与其直接相邻的多个开口401的边界的最短距离D大于或等于5μm。
例如，在一些实施例中，显示基板包括可发出不同颜色光(例如红色、蓝色和绿色)的多个子像素。由于可发出不同颜色光的发光层的发光效率和寿命的不同，因此可以在大小不同的开口中分别形成可发出不同颜色光的发光层，以形成可发出不同颜色光的多个子像素。例如，开口大小较大的开口中形成发光效率较小的子像素的发光层或者开口数量较少的子像素的发光层，开口大小较小的开口中形成发光效率较大的子像素的发光层或者开口数量较多的子像素的发光层，由此平衡不同颜色子像素的发光亮度。
例如，在一个示例中，蓝色发光层、红色发光层和绿色发光层可分别形成在开口大小依次减小的第一开口4011、第二开口4012和第三开口4013 中，由此，第一开口4011用于形成蓝色子像素，第二开口4012用于红色子像素，第三开口4013用于形成绿色子像素，由此平衡不同颜色子像素的发光亮度。
例如，隔垫物102被第一开口4011、第二开口4012和两个第三开口4013环绕。例如，在一些示例中，如图1A所示，在第一方向D1(即图1A中的竖直方向)上，隔垫物402的两侧分别为第一开口4011和第二开口4012，在与第一方向D1垂直的第二方向D2(即图1A中的水平方向)上，隔垫物402的两侧均为第三开口4013。
例如，第一开口4011的形状为第一正方形，第二开口4012的形状为第二正方形，第一正方形的边长大于第二正方形的边长。第三开口4013的形状为长方形，长方形的长边与相邻的第一开口4011的第一正方形的边长平行，长方形的短边与相邻的第二开口4012的第二正方形的边长平行。例如，在其他实施例中，第一开口4011的形状也可以替换为第一圆形，第二开口4012的形状也可以替换为第二圆形，第三开口4013的形状也可以替换为椭圆形，此时，第一圆形的直径大于第二圆形的直径，椭圆形的长轴所在的直线穿过与其相邻的两个第二开口4012的中心，椭圆形的短轴所在的直线穿过与其相邻的两个第一开口4011的中心。由此，隔垫物402距离多个开口，即第一开口4011、第二开口4012和第三开口4013的距离基本相同，使得隔垫物在各个开口周围对FMM产生充分且均匀的支撑作用，从而通过FMM蒸镀到各个开口中的材料更均匀。
需要说明的是，上述开口401一般会设计为规则的形状，比如四边形、五边形、六边形、圆形或椭圆形等。然而，在实际制造工艺中，所形成的开口401的形状一般会与上述设计的规则形状有一定的偏差。例如，上述规则的形状的各个角可能会变成圆角，因此，开口401的形状可以为圆角图形。此外，实际制造的开口401的形状还可能会与设计的形状有其他的变化。例如，设计为矩形的有效发光区的形状在实际制造中可能变成近似椭圆形。此时，上述正方形或长方形可能形成为圆角正方形或圆角长方形。
例如，以第一开口4011、第二开口4012和两个第三开口4013作为一个重复单元，每个重复单元可以对应设置两个隔垫物，此时，每个隔垫物设置在显示基板上每相邻的两个第三开口4013之间，并且多个隔垫物在显示基板上均匀设置为呈多行多列排布的阵列。
例如，如图1A所示，在每个重复单元中，两个第三开口4013的形状呈镜像对称，两个第三开口4013的中心的连线穿过二者之间的隔垫物402，并且两个第三开口4013的最靠近隔垫物402的顶角的连线也穿过二者之间的隔垫物402。例如，第一开口4011的中心和第二开口4012的中心的连线穿过隔垫物402，例如穿过隔垫物402的中心，即第一开口4011的中心、第二开口4012的中心和隔垫物402的中心位于一条直线上。例如，隔垫物402的长度方向与两个第三开口4013的中心的连线方向平行，隔垫物402的宽度方向与第一开口4011的中心和第二开口4012的中心的连线方向平行。
在一些实施例中，也可以每个重复单元对应设置一个隔垫物，此时，如图1B所示，该隔垫物402可以设置在每个重复单元的两个第三开口4013之间，多个隔垫物402在显示基板上交错且均匀分布；例如位于奇数行的隔垫物与位于偶数行的隔垫物错位1/2节距，一个节距是指每行隔垫物中相邻的两个隔垫物的距离；或者，也可以每两个重复单元对应设置一个隔垫物，此时，每个隔垫物可以设置相间隔的重复单元的两个第三开口4013之间；或者，也可以每四个重复单元(该四个重复单元例如排列为2×2的阵列)对应设置一个隔垫物，此时，每个隔垫物可以设置在每四个重复单元中位于相同位置的重复单元的两个第三开口4013之间。在上述排布下，隔垫物均可以显示充分且均匀的支撑效果。
例如，显示基板还包括像素电路结构，该像素电路结构设置在衬底基板与像素界定层之间。像素电路结构包括相互平行设置的第一信号线(例如图1A中示出的EM线，稍后详细介绍)和第二信号线(例如图1A中示出的RST线，稍后详细介绍)，至少一个隔垫物402在衬底基板上的第一正投影位于第一信号线在衬底基板上的第二正投影和第二信号线在衬底基板上的第三正投影之间，即第一正投影在第二正投影和第三正投影限定的范围内。
例如，在一些示例中，第一正投影的中心距离第二正投影的中轴线(例如图1A中示出的EM0)线的距离大于第一正投影的中心距离第三正投影的中轴线(例如图1A中示出的RST0线)的距离，即至少一个隔垫物402在第一信号线和第二信号线之间且更靠近第二信号线。
例如，显示基板的像素电路结构包括用于驱动多个子像素发光的像素电路，例如2T1C(即包括两个薄膜晶体管T和一个存储电容C)像素电路、3T1C(即包括三个薄膜晶体管T和一个存储电容C)像素电路或者7T1C(即 包括七个薄膜晶体管T和一个存储电容C)像素电路等。该驱动电路中的两条平行设置的信号线可以实现为上述第一信号线和第二信号线。下面，以7T1C驱动电路为例进行介绍。
例如，图2A示出了一种7T1C像素电路的电路图。如图2A所示，该像素电路包括驱动电路122、数据写入电路126、补偿电路128、存储电路127、第一发光控制电路123、第二发光控制电路124及复位电路129。
例如，驱动电路122包括控制端131、第一端132和第二端133，其配置为控制流经发光元件120的驱动电流，且驱动电路122的控制端131和第一节点N1连接，驱动电路122的第一端132和第二节点N2连接，驱动电路122的第二端133和第三节点N3连接。
例如，数据写入电路126包括控制端、第一端和第二端，其控制端配置为接收第一扫描信号，第一端配置为接收数据信号，第二端与驱动电路122的第一端132(第二节点N2)连接，且配置为响应于该第一扫描信号Ga1将该数据信号写入驱动电路122的第一端132。例如，数据写入电路126的第一端与数据线12连接以接收该数据信号，控制端与扫描线11连接以接收该第一扫描信号Ga1。
例如，在数据写入阶段，数据写入电路126可以响应于第一扫描信号Ga1而开启，从而可以将数据信号写入驱动电路122的第一端132(第二节点N2)，并将数据信号存储在存储电路127中，以在例如发光阶段时可以根据该数据信号生成驱动发光元件120发光的驱动电流。
例如，补偿电路128包括控制端、第一端和第二端，其控制端配置为接收第二扫描信号Ga2，其第一端和第二端分别与驱动电路122的控制端131和第二端133电连接，该补偿电路配置为响应于该第二扫描信号对该驱动电路120进行阈值补偿。
例如，存储电路127与驱动电路122的控制端131及第一电压端VDD电连接，配置为存储数据写入电路126写入的数据信号。例如，在数据写入和补偿阶段，补偿电路128可以响应于该第二扫描信号Ga2而开启，从而可以将数据写入电路126写入的数据信号存储在该存储电路127中。例如，同时在数据写入和补偿阶段，补偿电路128可以将驱动电路122的控制端131和第二端133电连接，从而可以使驱动电路122的阈值电压的相关信息也相应地存储在该存储电路中，从而例如在发光阶段可以利用存储的数据信号以 及阈值电压对驱动电路122进行控制，使得驱动电路122的输出得到补偿。
例如，第一发光控制电路123与驱动电路122的第一端132(第二节点N2)以及第一电压端VDD连接，且配置为响应于第一发光控制信号将第一电压端VDD的第一电源电压施加至驱动电路122的第一端132。例如，如图2A所示，第一发光控制电路123和第一发光控制端EM1、第一电压端VDD以及第二节点N2连接。
例如，第二发光控制电路124和第二发光控制端EM2、发光元件120的第一端510以及驱动电路122的第二端132连接，且配置为响应于第二发光控制信号使得驱动电流可被施加至发光元件122。
例如，在发光阶段，第二发光控制电路123响应于第二发光控制端EM2提供的第二发光控制信号而开启，从而驱动电路122可以通过第二发光控制电路123将驱动电流施加至发光元件120以使其发光；而在非发光阶段，第二发光控制电路123响应于第二发光控制信号而截止，从而避免有电流流过发光元件120而使其发光，可以提高相应的显示装置的对比度。
又例如，在初始化阶段，第二发光控制电路124也可以响应于第二发光控制信号而开启，从而可以结合复位电路以对驱动电路122以及发光元件120进行复位操作。
例如，第二发光控制信号EM2可以与第一发光控制信号EM1相同或不同，例如二者可以连接到相同或不同的信号输出端。
例如，复位电路129与复位电压端Vinit以及发光元件122的第一端134(第四节点N4)连接，且配置为响应于复位信号将复位电压施加至发光元件120的第一端134。在另一些示例中，如图2A所示，该复位信号还可以施加至驱动电路的控制端131，也即第一节点N1。例如，复位信号为该第二扫描信号，复位信号还可以是和第二扫描信号同步的其他信号，本公开的实施例对此不作限制。例如，如图2A所示，该复位电路129分别和发光元件120的第一端134、复位电压端Vinit以及复位控制端Rst(复位控制线)连接。例如，在初始化阶段，复位电路129可以响应于复位信号而开启，从而可以将复位电压施加至发光元件120的第一端134及第一节点N1，从而可以对驱动电路122、补偿电路128以及发光元件120进行复位操作，消除之前的发光阶段的影响。
例如，发光元件120包括第一端134和第二端135，发光元件120的第 一端134配置为从驱动电路122的第二端133接收驱动电流，发光元件120的第二端135配置为与第二电压端VSS连接。例如，在一个示例中，如图2A所示，发光元件120的第一端134可以通过第二发光电路124连接至第三节点N3。本公开的实施例包括但不限于此情形。例如，发光元件120可以为各种类型的OLED，例如顶发射、底发射、双侧发射等，可以发红光、绿光、蓝光或白光等，该OLED的第一电极和第二电极分别作为该发光元件的第一端134和第二端135。本公开的实施例对发光元件的具体结构不作限制。
需要注意的是，在本公开实施例的说明中，第一节点N1、第二节点N2、第三节点N3和第四节点N4并非一定表示实际存在的部件，而是表示电路图中相关电路连接的汇合点。
需要说明的是，在本公开的实施例的描述中，符号Vd既可以表示数据信号端又可以表示数据信号的电平，同样地，符合Ga1、Ga2既可以表示第一扫描信号、第二扫描信号，也可以表示第一扫描信号端和第二扫描信号端，Rst既可以表示复位控制端又可以表示复位信号，符号Vinit既可以表示复位电压端又可以表示复位电压，符号VDD既可以表示第一电压端又可以表示第一电源电压，符号VSS既可以表示第二电压端又可以表示第二电源电压。以下各实施例与此相同，不再赘述。
图2B为图2A所示的像素电路的一种具体实现示例的电路图。如图2B所示，该像素电路包括：第一至第七晶体管T1、T2、T3、T4、T5、T6、T7以及包括存储电容Cst。例如，第一晶体管T1被用作驱动晶体管，其他的第二至第七晶体管被用作开关晶体管。
例如，如图2B所示，驱动电路122可以实现为第一晶体管T1。第一晶体管T1的栅极作为驱动电路122的控制端131，和第一节点N1连接；第一晶体管T1的第一极作为驱动电路122的第一端132，和第二节点N2连接；第一晶体管T1的第二极作为驱动电路122的第二端133，和第三节点N3连接。
例如，如图2B所示，数据写入电路126可以实现为第二晶体管T2。第二晶体管T2的栅极和第一扫描线(第一扫描信号端Ga1)连接以接收第一扫描信号，第二晶体管T2的第一极和数据线(数据信号端Vd)连接以接收数据信号，第二晶体管T2的第二极和驱动电路122的第一端132(第二节 点N2)连接。例如，该第二晶体管T2为P型晶体管，例如有源层为低温掺杂多晶硅的薄膜晶体管。
例如，如图2B所示，补偿电路128可以实现为第三晶体管T3。第三晶体管T3的栅极配置为和第二扫描线(第二扫描信号端Ga2)连接以接收第二扫描信号，第三晶体管T3的第一极和驱动电路122的控制端131(第一节点N1)连接，第三晶体管T3的第二极和驱动电路122的第二端133(第三节点N3)连接。
例如，如图2B所示，存储电路127可以实现为存储电容Cst，该存储电容Cst包括第一电容电极Ca和第二电容电极Cb，该第一电容电极Ca和第一电压端VDD连接，该第二电容电极Cb和驱动电路122的控制端131连接。
例如，如图2B所示，第一发光控制电路123可以实现为第四晶体管T4。第四晶体管T4的栅极和第一发光控制线(第一发光控制端EM1)连接以接收第一发光控制信号，第四晶体管T4的第一极和第一电压端VDD连接以接收第一电源电压，第四晶体管T4的第二极和驱动电路122的第一端132(第二节点N2)连接。
例如，发光元件120可以具体实现为OLED，其的第一电极134(这里为阳极)和第四节点N4连接配置为通过第二发光控制电路124从驱动电路122的第二端133接收驱动电流，发光元件120的第二电极135(这里为阴极)配置为和第二电压端VSS连接以接收第二电源电压。例如第二电压端可以接地，即VSS可以为0V。
例如，第二发光控制电路124可以实现为第五晶体管T5。第五晶体管T5的栅极和第二发光控制线(第二发光控制端EM2)连接以接收第二发光控制信号，第五晶体管T5的第一极和驱动电路122的第二端133(第三节点N3)连接，第五晶体管T5的第二极和发光元件120的第一端134(第四节点N4)连接。
例如，复位电路129可以包括第一复位电路和第二复位电路，该第一复位电路配置为响应于第一复位信号Rst1将第一复位电压Vini1施加到第一节点N1，该第二复位电路配置为响应于第二复位信号Rst2将第二复位电压Vini2施加到第四节点N4。例如，如图2B所示，该第一复位电路实现为第六晶体管T6，该第二复位电路实现为第七晶体管T7。第六晶体管T6的栅 极配置为和第一复位控制端Rst1连接以接收第一复位信号Rst1，第六晶体管T6的第一极和第一复位电压端Vinit1连接以接收第一复位电压Vinit1，第六晶体管T6的第二极配置为和第一节点N1连接。第七晶体管T7的栅极配置为和第二复位控制端Rst2连接以接收第二复位信号Rst2，第七晶体管T7的第一极和第二复位电压端Vinit2连接以接收第二复位电压Vinit2，第七晶体管T7的第二极配置为和第四节点N4连接。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。
例如，参见图1A，第一信号线为发光控制线EM，用于传输上述第一发光控制信号和第二发光控制信号；第二信号线为复位控制线RST，用于传输上述第一复位信号Rst1和第二复位信号Rst2。由此，隔垫物402在衬底基板101上的第一正投影位于发光控制线EM在衬底基板101上的第二正投影和复位控制线RST在衬底基板101上的第三正投影之间，例如更靠近第三正投影。
例如，在图1A中，发光控制线EM和复位控制线RST之间具有复位电压线VT，用于传输上述第一复位电压Vinit1和第二复位电压Vini2。例如，隔垫物402在衬底基板101上的正投影与上述复位电压线VT在衬底基板101上的正投影部分重叠。
下面详细介绍上述像素电路的版图设计。
图3为本公开至少一个实施例提供的显示基板的平面示意图。该显示基板包括衬底基板101，多个子像素100位于该衬底基板101上，且在衬底基板101上且沿行方向(即图中的横向)和列方向(即图中的纵向)排列为阵列。设定该子像素阵列的列方向为第一方向D1，行方向为第二方向D2，第一方向D1与第二方向D2交叉，例如正交。图3中示例性地示出了一行子像素电路中直接相邻的四个子像素(即第一子像素100a、第二子像素100b、第三子像素100c和第四子像素100d)的像素电路，虚线框示出了各个子像素的像素电路所在的区域，本公开的实施例不限于此布局。
图4A对应于图3示意出了该四个子像素100中晶体管T1-T7的半导体层102和第一导电层(栅极层)201，图4B在图4A的基础上还示出了第二导电层202，图4C在图4B的基础上还示出了第三导电层203，图4D在图4C的基础上还示出了第四导电层204。需要说明的是，图中仅示意性地示出了一行子像素中相邻的四个子像素的相应结构，但这不应作为对本公开的限制。该半导体层102、第一导电层201、第二导电层202、第三导电层203、第四导电层204依次设置于衬底基板101上，从而形成如图3所示的显示基板的结构。
为了方便说明，在以下的描述中用Tng、Tns、Tnd、Tna分别表示第n晶体管Tn的栅极、第一极、第二极和有源层，其中n为1-7。
需要说明的是，本公开中所称的“同层设置”是指两种(或两种以上)结构通过同一道沉积工艺形成并通过同一道构图工艺得以图案化而形成的结构，它们的材料可以相同或不同。本公开中的“一体的结构”是指两种(或两种以上)结构通过同一道沉积工艺形成并通过同一道构图工艺得以图案化而形成的彼此连接的结构，它们的材料可以相同或不同。
例如，如图4A所示，该第一导电层201包括每个晶体管的栅极以及一些扫描线和控制线。图4A中用大虚线框示出了每个子像素100的像素电路所在的区域，用小虚线框示出了一个子像素100中第一到第七晶体管T1-T7的栅极T1g-T7g。
该半导体层102包括第一到第七晶体管T1-T7的有源层T1a-T7a。如图3A所示，该第一到第七晶体管T1-T7的有源层T1a-T7a彼此连接为一体的结构。例如，每一列子像素中的半导体层20为彼此连接的一体的结构，相邻两列子像素中的半导体层彼此间隔。
例如，如图4A所示，该第一导电层104包括第一到第七晶体管T1-T7的栅极T1g-T7g。例如，第三晶体管T3和第六晶体管T6采用双栅结构，这样可以提高晶体管的栅控能力，降低漏电流。
例如，该第一导电层104还包括彼此绝缘的多条扫描线210、多条复位控制线220/RST和多条发光控制线230/EM。例如，每行子像素分别对应连接一条扫描线210、一条复位控制线220/RST和一条发光控制线230/EM。
扫描线210与对应一行子像素中的第二晶体管T2的栅极电连接(或为一体的结构)以提供第一扫描信号Ga1，复位控制线220/RST与对应一行子 像素中的第六晶体管T6的栅极电连接以提供第一复位信号Rst1，发光控制线230/EM与对应一行子像素中的第四晶体管T4的的栅极电连接以提供第一发光控制信号EM1。
例如，如图4A所示，该扫描线210还与第三晶体管T3的栅极电连接以提供第二扫描信号Ga2；该发光控制线230/EM还与第五晶体管T5的栅极电连接以提供第二发光控制信号EM2，也即该第一发光控制信号EM1和第二发光控制信号EM2为同一信号。
例如，如图4A所示，本行子像素的第七晶体管T7的栅极与下一行子像素所对应的复位控制线220/RST电连接以接收第二复位信号Rst2。
例如，从图4A可知，划分子像素的像素电路区的行方向的线可以是该复位控制线220/RST或该发光控制线230/EM。
例如，如图4A所示，该显示基板20采用自对准工艺，利用第一导电层201作为掩膜对该半导体层102进行导体化处理(例如掺杂处理)，使得该半导体层102未被该第一导电层201覆盖的部分被导体化，从而各晶体管的有源层位于沟道区两侧的部分被导体化而形成分别该晶体管的第一极和第二极。
例如，如图4B所示，该第二导电层202包括第一到第七晶体管T1-T7的第一电容电极Ca。该第一电容电极Ca在垂直于衬底基板101的方向上与第一晶体管T1的栅极T1g重叠从而形成存储电容Cst，也即该第一晶体管T1的栅极T1g充当该存储电容Cst的第二电容电极Cb。例如，该第一电容电极Ca包括过孔301，该过孔301暴露出该第一晶体管T1的栅极T1g的至少部分，以便于该栅极T1g与其它结构电连接。
例如，该第二导电层202还可以包括多条复位电压线240/VT，该多条复位电压线240/VT与多行子像素一一对应连接。该复位电压线240/VT与对应一行子像素中的第六晶体管T6的第一极电连接以提供第一复位电压Vinit1。
例如，如图4B所示，本行子像素中的第七晶体管T7的第一极与下一行子像素所对应的复位电压线240/VT电连接以接收第二复位电压Vinit2。
例如，如图4B所示，该第二导电层202还可以包括屏蔽电极221，该屏蔽电极221与第二晶体管T2的第一极T2s在垂直于衬底基板101的方向上重叠从而可以保护该第二晶体管T2的第一极T2s中的信号不受其它信号 的干扰。由于该第二晶体管T2的第一极T2s配置为接收数据信号Vd，而该数据信号Vd决定了该子像素的显示灰阶，因此该屏蔽电极221提高了数据信号的稳定性，从而提高了显示性能。
例如，如图4C所示，该第三导电层203包括沿第一方向D1延伸的多条第一电源线250。例如，该多条第一电源线250与多列子像素一一对应电连接以提供第一电源电压VDD。该第一电源线250通过过孔302与所对应的一列子像素中的第一电容电极Ca电连接，通过过孔303与第四晶体管T4的第一极电连接。例如，该第一电源线250还通过过孔304与屏蔽电极221电连接，从而使得屏蔽电极221具有固定电位，提高了该屏蔽电极的屏蔽能力。
例如，该第三导电层203还包括该多条数据线12。该多条数据线12与多列子像素一一对应电连接以提供数据信号。例如，该数据线12与所对应的的一列子像素中的第二晶体管T2的第一极T2s通过过孔305电连接以提供该数据信号。
例如，如图4C所示，该第三导电层203还包括第一连接电极231，该第一连接电极231的一端通过过孔301与该第一晶体管T1的栅极T1g，即第二电容电极Cb电连接，另一端与该第三晶体管T3的第一极电连接，从而将该第二电容电极Cb与该第三晶体管T3的第一极T3s电连接。
例如，如图4C所示，该第三导电层203还包括第二连接电极232，该第二连接电极232的两端分别与第六晶体管T6的第一极T6s以及复位电压线240/VT电连接，使得该第六晶体管T6的第一极T6s可以从该复位电压线240/VT接收第一复位电压Vinit1。
例如，如图4C所示，该第三导电层203还包括第三连接电极233，该第三连接电极233与第五晶体管T5的第二极T5d电连接，并用于将该第五晶体管T5的第二极T5d与发光元件的第一电极134电连接，后文将对此详细说明。
例如，如图4D所示，该第四导电层204包括第二电源线260，该第二电源线260沿第二方向D2延伸，并将多条第一电源线240电连接，从而形成网状的电源线结构。这种结构有助于降低电源线上的电阻从而降低电源线的压降，并有助于将第一电源电压均匀地输送至显示基板的各个子像素中。
例如，该第四导电层204还包括多条第三电源线270，该第三电源线270 沿第一方向D1延伸，且分别与多条第一电源线250一一对应电连接。如图3D所示，该第三电源线270与对应的第一电源线250在垂直于衬底基板101的方向上彼此重叠，并通过过孔306彼此电连接。例如，对应于每个子像素分别设置一个该过孔306，从而每条第三电源线270与对应的第一电源线250形成并联结构，这有助于降低电源线的电阻。
例如，该第二电源线260与第三电源线270彼此电连接或为一体的结构，从而该多条第一电源线250、多条第二电源线260及多条第三电源线270形成为网状的电源线结构。
例如，该第四导电层204还包括与该第三电源线270绝缘的第四连接电极234，该第四连接电极234通过过孔307与第三连接电极233电连接，以将该第五晶体管T5的第二极T5d与发光元件的第一电极134电连接。
图4E在图4D的基础上还示出了第五导电层205，该第五导电层205包括发光元件120的第一电极134。如图4E所示，第二电源线260在垂直于衬底基板101的方向上不重叠。这种设置可以避免发光元件的第一电极134因与第二电源线260重叠而不平整。该第一电极134上直接形成发光元件120的发光层并形成有效发光区域(开口区)，第一电极134的平整度会直接影响发光层的发光效率，从而影响发光元件120的发光性能。
例如，该第二电源线260可以为曲线结构以与第一电极134的图案相适应。例如，相邻的两条第二电源线260界定一行子像素100。例如，如图4所示，该第二电源线260包括交替连接的第一部分261和第二部分262，该第一部分261的延伸方向彼此平行并平行于第二方向D2，第二部分262的延伸方向与第一方向D1及第二方向D2均相交。例如，每列子像素分别对应一个第一部分261。
图4E示出了该相邻的四个子像素的第一电极134a、134b、134c和134d，之后该第一电极134a、134b、134c和134d上形成像素界定层，并且像素界定层中的多个开口分别暴露这些第一电极。对应于图1A，第一开口4011暴露第一电极134c，此时，第一开口4011的形状可以与第一电极134c的形状相同或相似，第一开口4011的尺寸可以略小于第一电极134c的尺寸，从而第一开口4011在衬底基板101上的正投影完全位于第一电极134c在衬底基板101上的正投影内；相应地，第二开口4012暴露第一电极134a，第二开口4012的形状可以与第一电极134a的形状相同或相似，第二开口4012的 尺寸可以略小于第一电极134a的尺寸，从而第二开口4012在衬底基板101上的正投影完全位于第一电极134a在衬底基板101上的正投影内；两个第三开口4013的形状可以分别与第一电极134b和第一电极134d的形状相同或相似，两个第三开口4013的尺寸可以分别略小于第一电极134b和第一电极134d，从而两个第三开口4013在衬底基板101上的正投影分别完全位于第一电极134b和第一电极134d在衬底基板101上的正投影内。
例如，第一电极134a、134b、134c和134d上分别形成发光层和第二电极，从而形成第一子像素100a、第二子像素100b、第三子像素100c和第四子像素100d的发光元件。第一子像素100a、第二子像素100b、第三子像素100c和第四子像素100d构成该显示基板的重复单元。
例如，在每个重复单元中，第二子像素100b的发光元件发出的光的颜色和第四子像素100d的发光元件发出的光的颜色相同，也就是说，第二子像素100b和第四子像素100d为相同颜色的子像素。例如，第二子像素100b和第四子像素100d为敏感颜色子像素，当显示基板采用红绿蓝(RGB)显示模式时，上述的敏感颜色为绿色，即第二子像素100b和第四子像素100d均为绿色子像素。例如，第一子像素100a可以为红色子像素，第三子像素100c可以为蓝色子像素。
例如，每个重复单元中的四个子像素可以形成两个虚拟像素，重复单元中的第一子像素100a和第三子像素100c分别被所述两个虚拟像素共用。多个重复单元中的子像素形成像素阵列，在像素阵列的行方向上，子像素密度是虚拟像素密度的1.5倍，在像素阵列的列方向上，子像素密度是虚拟像素密度的1.5倍。例如，第二子像素100b和第四子像素100d分别属于两个虚拟像素。
需要说明的是，第一，由于第一子像素100a和第三子像素100c是被相邻的两个虚拟像素共享，因而每个虚拟像素的边界也是非常模糊的，因而，本公开实施例并不对每个虚拟像素的形状进行限定。第二、虚拟像素的划分与驱动方式相关，虚拟像素的具体划分方式可以根据实际的驱动方式确定，本公开对此不作具体限制。
例如，子像素100对应的多个开口区的形状和大小可以根据发出不同颜色的光的发光层的发光效率、使用寿命等而改变，例如，可以将发光寿命较短的发光层的对应的开口区设置得较大，从而提高发光的稳定性。例如，可 以将蓝色子像素、红色子像素、绿色子像素的开口的大小依次减小。由于开口区设置于第一电极134上，相应地，如图4所示，第一子像素100a、第二子像素100b、第三子像素100c和第四子像素100d的第一电极134a、121b、121c和121d的面积依次减小。
例如，相邻的两行重复单元沿行方向错位1/2节距设置，节距为沿行方向相邻的两个重复单元中的两个第一子像素100a的中心之间的距离。需要说明的是，节距也可为沿行方向相邻的两个重复单元中的两个第三子像素100c的中心之间的距离；上述的中心可为子像素的几何中心。当然，本公开实施例包括但不限于此，相邻的两行重复单元也可以错位其他距离，或者不错位。
例如，相邻的两行重复单元中，列方向相邻的两个重复单元中第一子像素和第三子像素位置互换，第二子像素和第四子像素位置对应。
例如，第一子像素和第三子像素在行和列方向交替排列成行或列，第二子像素和第四子像素在行和列方向排列成行或列。第一子像素和第三子像素组成的行与第二子像素和第四子像素组成的行在列方向交替排列。第一子像素和第三子像素组成的列与第二子像素和第四子像素组成的列在行方向交替排列。第一子像素和第三子像素组成的矩阵中，分布于两行两列形成2*2矩阵的两个第一子像素和两个第三子像素分别覆盖一个虚拟矩形的顶点，一个第二子像素或一个第四子像素位于该虚拟矩形内，其中，两个第一子像素覆盖该虚拟矩形的一对角线上的两个顶角，两个第三子像素覆盖该虚拟矩形的另一对角线上的两个顶角。
例如，如图4E所示，各子像素的第一电极134通过过孔308与第四连接电极234电连接，从而使得第五晶体管T5的第二极T5d与发光元件120的第一电极134电连接。
如图4E所示，之后在像素界定层上形成的至少一个隔垫物402的位置如虚线框所示，此时，隔垫物402在衬底基板上的第一正投影与各第一电极134a、134b、134c和134d在衬底基板上的正投影均不重叠，并且隔垫物402与其直接相邻的第一开口4011、第二开口4012和第三开口4013的边界的最短距离均大于或等于5μm。
例如，在一些示例中，每个重复单元对应设置一个隔垫物，该隔垫物设置在每个重复单元的两个绿色子像素(即第二子像素100b和第四子像素 100d)的第三开口4013之间，而相邻重复单元的两个绿色子像素的第三开口4013之间不设置隔垫物，此时，显示基板上的隔垫物的数量与绿色子像素的数量之比为1:2。
例如，在每个重复单元中，两个绿色子像素的第三开口4013的中心的连线穿过二者之间的隔垫物402，且该连线平行于隔垫物402的长度方向。例如，当隔垫物402的形状为矩形时，该长度方向为矩形的长边的延伸方向。
例如，隔垫物402的长度方向为显示基板的水平显示方向，即在显示基板进行显示时，人眼所看到的图像的水平方向。此时，由于隔垫物402在该水平方向上的两侧均为绿色子像素，因此当观看者从两侧分别观看显示基板时，可能被隔垫物402遮挡的子像素为相同的子像素，从而观看者从显示基板的不同侧进行观看时，也不会产生色偏现象。
例如，第二电源线的第一部分261在衬底基板上的正投影与隔垫物402在衬底基板上的第一正投影部分重叠，第二电源线的第二部分262在衬底基板上的正投影也与隔垫物402在衬底基板上的第一正投影部分重叠。例如，第三电源线270在衬底基板上的正投影也与隔垫物402在衬底基板上的第一正投影部分重叠。此时，隔垫物402形成在第二电源线的第一部分261、第二部分262以及第三电源线270相交的位置。
例如，每条数据线12在衬底基板上的正投影与隔垫物402在衬底基板上的第一正投影均不重叠。例如，隔垫物402形成在相邻的两条数据线12之间，即本列像素电路的数据线和后一列像素电路的数据线之间，例如在图4E中，位于第二开口4012左侧的数据线12即为本列像素电路的数据线，位于第二开口4012右侧的数据线12为后一列像素电路的数据线。
例如，至少一个隔垫物402位于本行像素电路(例如如图4A和图4B框出的一行像素电路)的发光控制线230/EM(用于驱动本行像素电路的第四薄膜晶体管T4和第五行薄膜晶体管T5)与下一行像素电路的复位控制线220/RST(用于驱动本行像素电路的第七薄膜晶体管T7和下一行像素电路的第六薄膜晶体管T6)之间，且更靠近复位控制线220/RST。
例如，上述发光控制线230/EM与上述复位控制线220/RST之间还具有下一行像素电路的复位电压线240/VT(电连接本行像素电路的第七薄膜晶体管T7的第一极和下一行像素电路的第六薄膜晶体管T6的第一极)。此时，至少一个隔垫物402在衬底基板101上的正投影与该复位电压线240/VT在 衬底基板101上的正投影部分重叠。
例如，在上述以第一子像素100a、第二子像素100b、第三子像素100c和第四子像素100d构成该显示基板的重复单元时，每个重复单元可以对应设置两个隔垫物402，此时，每相邻的第二子像素100b和第四子像素100d之间均设置一个隔垫物402，多个隔垫物402在显示基板上均匀设置为呈多行多列排布的阵列。由此，呈阵列排布的多个隔垫物402可以在显示基板的多个位置隔离显示基板和FMM，防止FMM与显示基板相接触而刮坏显示基板。
在一些实施例中，也可以每个重复单元对应设置一个隔垫物，即图1A、图1B以及图4E示出的情况，此时，多个隔垫物402在显示基板上交错且均匀分布，例如位于奇数行的隔垫物与位于偶数行的隔垫物错位1/2节距，一个节距是指每行隔垫物中相邻的两个隔垫物的距离；或者，也可以每两个重复单元对应设置一个隔垫物；或者，也可以每四个重复单元(该四个重复单元例如排列为2×2的阵列)对应设置一个隔垫物。在上述排布下，隔垫物均可以显示充分且均匀的支撑效果。
例如，在图3和图4A-图4F示出的示例中，每个重复单元对应设置一个隔垫物，此时，显示基板上隔垫物402的数量与子像素的总的数量的比大致为1:4。例如，在每个重复单元中，隔垫物402在衬底基板上的正投影与红色子像素的像素电路所在的区域(即虚线框框出的子像素100a的像素电路的区域)在衬底基板上的正投影重叠，此时显示基板上隔垫物402的数量与红色子像素的数量的比大致为1:1。需要说明的是，以上比例关系是按照显示区中部区域来限定的，对于边缘的部分区域，考虑周边结构或冗余像素的设计，有些位置可以有隔垫物缺失，或者隔垫物位置和数量的调整，或者子像素位置和数量的调整，所以以上比例关系可以有所浮动，例如可以上下10％范围内浮动。
例如，如图4E所示，隔垫物402在衬底基板101上的正投影形状可以为矩形，如图5所示，该矩形的长L可以为20μm-30μm，例如22μm、25μm或者28μm等，所述矩形的宽W可以为10μm-16μm，例如12μm或者15μm等。此时，隔垫物402在衬底基板101上的第一正投影的中心O即为矩形的中心。
例如，在其他示例中，隔垫物402在衬底基板101上的第一正投影的形 状也可以为圆形、椭圆形、三角形或者其他多边形，此时，隔垫物402在衬底基板101上的第一正投影的中心O即为圆形或椭圆形的中心或者三角形或者其他多边形的重心。当然，在一些示例中，隔垫物402在衬底基板101上的第一正投影的形状也可以为不规则图形，此时，隔垫物402在衬底基板101上的第一正投影的中心O即为该不规则图形的重心。
例如，在一些实施例中，隔垫物402的高度可以为0.8μm-1.5μm，例如1μm或者1.2μm等。由此，隔垫物402可以充分隔离FMM与显示基板，防止FMM与显示基板相接触而刮坏显示基板。
例如，隔垫物402的材料可以为聚酰亚胺(PI)。由于聚酰亚胺是一种光敏材料，并可作为光刻胶材料，因此在制备过程中，隔垫物402可以直接通过曝光工艺和显影工艺形成。
图4F示出了图4E中的显示基板沿A-A’的截面示意图。如图4F所示，半导体层102、第一绝缘层103、第一导电层201、第二绝缘层104、第二导电层202、第三绝缘层105、第三导电层203、第四绝缘层106、第四导电层204、第五绝缘层107、第五导电层205依次设置于衬底基板101上，从而形成如图4E所示的显示基板的结构。
例如，如图4F所示，显示基板还包括位于发光元件120的第一电极134a上的像素界定层430。像素界定层430中形成开口401(截面图中为第二开口4012)从而限定一个子像素的发光区域。发光层136形成于该开口401内，第二电极135形成于发光层136上从而形成该发光元件120。例如，该第二电极135为公共电极，整面布置于该显示基板中。
如图4F所示，隔垫物402设置在像素界定层上，并且隔垫物402在衬底基板101上的第一正投影位于发光控制线230/EM在衬底基板101上的第二正投影和复位控制线220/RST在衬底基板101上的第三正投影之间，并且更靠近第三正投影。发光控制线230/EM和复位控制线220/RST之间具有复位电压线240/VT，隔垫物402在衬底基板101上的正投影与复位电压线240/VT在衬底基板101上的正投影重叠。另外，隔垫物402在衬底基板101上的第一正投影与第一电极134a在衬底基板101上的正投影不重叠，并且隔垫物402与其直接相邻的开口401(第二开口4012)的边界的最短距离D均大于或等于5μm。
例如，在上述显示基板中，衬底基板101可以为刚性基板，例如玻璃基 板、硅基板等，也可以由具有优良的耐热性和耐久性的柔性材料形成，例如聚酰亚胺(PI)、聚碳酸酯(PC)、聚乙烯对苯二甲酸乙二醇酯(PET)、聚乙烯、聚丙烯酸酯、多芳基化合物、聚醚酰亚胺、聚醚砜、聚乙二醇对苯二甲酸酯(PET)、聚乙烯(PE)、聚丙烯(PP)、聚砜(PSF)、聚甲基丙烯酸甲酯(PMMA)、三醋酸纤维素(TAC)、环烯烃聚合物(COP)和环烯烃共聚物(COC)等。
例如，该半导体层102的材料包括但不限于硅基材料(非晶硅a-Si，多晶硅p-Si等)、金属氧化物半导体(IGZO，ZnO，AZO，IZTO等)以及有机物材料(六噻吩，聚噻吩等)。
例如，该第一到第四导电层的材料可以包括金(Au)、银(Ag)、铜(Cu)、铝(Al)、钼(Mo)、镁(Mg)、钨(W)以及以上金属组合而成的合金材料；或者导电金属氧化物材料，例如氧化铟锡(ITO)、氧化铟锌(IZO)、氧化锌(ZnO)、氧化锌铝(AZO)等。
例如，该发光元件120为顶发射结构，第一电极具134有反射性而第二电极135具有透射性或半透射性。例如，第一电极134为高功函数的材料以充当阳极，例如为ITO/Ag/ITO叠层结构；第二电极135为低功函数的材料以充当阴极，例如为半透射的金属或金属合金材料，例如为Ag/Mg合金材料。
例如，第一绝缘层103、第二绝缘层104、第三绝缘层105例如为无机绝缘层，例如氧化硅、氮化硅、氮氧化硅等硅的氧化物、硅的氮化物或硅的氮氧化物，或者氧化铝、氮化钛等包括金属氮氧化物绝缘材料。例如，第四绝缘层106、第五绝缘层107和像素界定层108包括有机绝缘材料，例如为聚酰亚胺(PI)、丙烯酸酯、环氧树脂、聚甲基丙烯酸甲酯(PMMA)等有机绝缘材料。例如，第四绝缘层106和第五绝缘层107为平坦化层。例如，在第四绝缘层106和第三导电层之间还可以有一层无机绝缘层，例如为钝化层，例如为氧化硅、氮化硅、氮氧化硅等硅的氧化物、硅的氮化物或硅的氮氧化物，或者氧化铝、氮化钛等包括金属氮氧化物绝缘材料。
在上述显示基板的制备过程中，由于隔垫物402在衬底基板101上的第一正投影位于第一信号线在衬底基板101上的第二正投影和第二信号线在衬底基板101上的第三正投影之间，即隔垫物402在衬底基板101上的第一正投影不超出第一信号线在衬底基板101上的第二正投影和第二信号线在衬底基板101上的第三正投影限定的范围内，因此在制备隔垫物402时，可以以 第一信号线和第二信号线的位置为参考，精准定位隔垫物402的形成位置。
例如，在一些实施例中，隔垫物402在衬底基板101上的第一正投影的中心O距离第一信号线(例如发光控制线EM)在衬底基板101上的第二正投影的中轴线EM0的距离大于第一正投影的中心O距离第二信号线(例如复位控制线RST)在衬底基板101上的第三正投影的中轴线RST0的距离。此时，隔垫物402相对于第一信号线和第二信号线来说更靠近第二信号线。由于像素电路与像素界定层中的多个开口的相对位置是确定的，当隔垫物402更靠近第二信号线时，可以保证隔垫物402的与像素界定层接触的底部的任意一点距离多个开口401的上表面的侧壁的距离大于或等于5μm，并且隔垫物402距离多个开口401的距离更接近或者基本相同。
本公开至少一实施例提供一种显示装置，该显示装置包括上述任一的显示基板。该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开至少一实施例提供一种显示基板的制备方法，如图6所示，该方法包括步骤S101-S103。
步骤S101：提供衬底基板。
例如，如图7所示，提供的衬底基板101可以是玻璃基板、硅基板等各种类型的基板，本公开的实施例对此不做限定。
例如，衬底基板101上可以形成阻挡层和缓冲层的叠层(图中未示出)，以防止衬底基板101中的杂质进入到之后将要形成的像素电路结构等功能层中。
例如，在阻挡层和缓冲层的叠层上形成像素电路结构，像素电路结构包括用于驱动显示面板进行显示的像素电路，如上所述，该像素电路可以为2T1C驱动电路、3T1C驱动电路或者7T1C驱动电路等。本公开的实施例对驱动电路的类型以及形成方式不做限定。
例如，图7示出了显示基板在制备过程中的部分截面示意图，参考图4A-图4E以及图7，形成像素电路结构包括在阻挡层和缓冲层的叠层上形成多个薄膜晶体管、存储电容以及发光元件120的第一电极134a等，下面将详细介绍像素电路结构的制备方法，例如，该像素电路结构的制备方法包括步骤S11-S22像素电路结构。
步骤S11：在衬底基板上形成半导体材料层，并对该半导体材料层进行 构图工艺从而形成如图4A所示的半导体层102，半导体层102包括在每个子像素区内第一到第七晶体管T1-T7的有源层T1a-T7a和掺杂区图案(即对应第一到第七晶体管T1-T7的源极区域和漏极区域)，且同一像素区中的各晶体管的有源层图案和掺杂区图案一体设置。
需要说明的是，有源层可以包括一体形成的低温多晶硅层，其中的源极区域和漏极区域可以通过掺杂等进行导体化实现各结构的电连接。也就是每个子像素的各晶体管的有源半导体层为由p-硅形成的整体图案，且同一像素区中的各晶体管包括掺杂区图案(即源极区域和漏极区域)和有源层图案，不同晶体管的有源层之间由掺杂结构隔开。
步骤S12：在半导体层102层上形成第一绝缘层103(例如可以为透明层)，例如为栅绝缘层，并在第一绝缘层上形成多个第一绝缘层过孔用于与后续形成的第三导电层203的图案连接。例如对应半导体层中的源极区域和漏极区域的位置，分别在第一绝缘层中形成对应的第一绝缘层过孔，即第一绝缘层过孔分别与半导体层中的源极区域和漏极区域交叠，以用于源极区域和漏极区域与第三导电层中的数据线12、第一电源线250、第一连接电极231、第二连接电极232和第三连接电极233等结构进行连接，例如贯穿第一绝缘层的过孔402，过孔405，过孔303，过孔305等。
步骤S13：在第一绝缘层上形成第一导电材料层，并对该第一导电材料层进行构图工艺从而形成如图4A所示的第一导电层201，也即形成彼此绝缘且沿第二方向延伸的扫描线210、复位控制线220和发光控制线230。例如，对于一行像素电路，其对应连接的复位控制线220、扫描线210和发光控制线230沿第一方向依次排布。
例如，该第一导电层201还包括第一到第七晶体管T1-T7的栅极T1g-T7g。例如，第六晶体管T6的栅极T6g和复位控制线220为一体的结构，即复位控制线220的一部分作为第六晶体管T6的栅极T6g；第二晶体管T2的栅极T2g和扫描线210为一体的结构，即扫描线210的部分作为第二晶体管T2的栅极T2g；第四晶体管T4的栅极T4g和第五晶体管T5的栅极T5g均与发光控制线230为一体的结构，即发光控制线230的一部分作为第四晶体管T4的栅极T4g和第五晶体管T5的栅极T5g；第七晶体管T7的栅极T7g与下一行像素电路所对应的复位控制线220为一体的结构。例如，第六晶体管T6和第三晶体管T3均为双栅结构，第六晶体管T6的两个栅极T6g均为 复位控制线220的一部分，第三晶体管T3的一个栅极为扫描线210的一部分，第三晶体管T3的另一个栅极为在扫描线210一体连接并朝向复位控制线220上突出的一部分。
例如，该半导体层102与该第一导电层201在垂直于衬底基板的方向上重叠的部分定义出该第一到第七晶体管T1-T7的有源层(沟道区)T1a-T7a。
例如，在D1方向上，第二晶体管(例如为数据写入晶体管)T2的栅极、第三晶体管(例如为阈值补偿晶体管)T3的栅极、第六晶体管(例如为第一复位晶体管)T6的栅极和第七晶体管(例如为第二复位晶体管)T7的栅极均位于第一晶体管(例如为驱动晶体管)T1的栅极的第一侧，第四晶体管(例如为第一发光控制晶体管)T4的栅极、第五晶体管(例如为第二发光控制晶体管)T5的栅极均位于第一晶体管T1的栅极的第二侧。在平行于衬底基板的平面内，同一个像素区的第一晶体管T1的栅极的第一侧可以为第一晶体管T1的栅极的上侧，第一晶体管T1的栅极的第二侧可以为第一晶体管T1的栅极的下侧。所述下侧，例如显示基板的用于绑定IC的一侧为显示基板的下侧，第一晶体管T1的栅极的下侧，为第一晶体管T1的栅极的更靠近IC的一侧。所述上侧为下侧的相对侧，例如为第一晶体管T1的栅极的更远离IC的一侧。
例如，在D2方向上，第二晶体管T2的栅极和第四晶体管T4的栅极均位于第一晶体管T1的栅极的第三侧，第三晶体管T3的第一个栅极(与扫描线210为一体的栅极)、第五晶体管T5的栅极和第七晶体管T7的栅极均位于第一晶体管T1的栅极的第四侧。例如同一像素区(像素电路所在的区域)的第一晶体管T1的栅极的第三侧和第四侧为在D2方向上第一晶体管T1的栅极的彼此相对的两侧。例如，同一像素区(像素电路所在的区域)的第一晶体管T1的栅极的第三侧可以为第一晶体管T1的栅极的左侧，第一晶体管T1的栅极的第四侧可以为第一晶体管T1的栅极的右侧。所述左侧和右侧，例如在同一像素区(像素电路所在的区域)中，数据线在第一电源线250左侧，第一电源线250在数据线右侧。
步骤S14：如图4A所示，采用自对准工艺，利用该第一导电层201作为掩膜对该半导体层102进行导体化处理(例如掺杂处理)，从而使得该半导体层102未被该第一导电层201覆盖的部分被导体化，从而使得该半导体层102位于各晶体管的有源层两侧的部分被导体化而分别形成第一到第七晶 体管T1-T7的源极区域或漏极区域,也即第一到第七晶体管T1-T7的第一极(T1s-T7s)和第二极(T1d-T2d)。
步骤S15：在第一导电层201上形成第二绝缘层104(例如可以为透明层)，例如可以为第二栅绝缘层。并在第二绝缘层上至少形成与第一绝缘层过孔对应的第二绝缘层过孔。例如对应至少贯穿第一绝缘层和第二绝缘层的过孔至少包括过孔402，过孔405，过孔303，过孔305等。
步骤S16：在该第二绝缘层104并在该第二绝缘层上形成第二导电材料层，对该第二导电材料层进行构图工艺形成如图4B所示的第二导电层202，也即形成彼此绝缘的屏蔽电极221、第一电容电极Ca以及沿第一方向延伸的复位电压线240。
例如，该屏蔽电极221与第二晶体管T2的第一极T2s在垂直于衬底基板101的方向上重叠从而可以保护该第二晶体管T2的第一极T2s中的信号不受其它信号的干扰。
例如，该第一电容电极Ca与该第一晶体管T1的栅极T1g在垂直于衬底基板101的方向上至少部分重叠。该构图工艺还在该第一电容电极Ca中形成过孔301，该过孔301暴露出第一晶体管T1的栅极T1g的至少部分。
步骤S17：在该第二导电层202上形成第三绝缘层105。第三绝缘层例如可以为层间绝缘层。在第三绝缘层中形成用于连接与后续形成的第三导电层的连接的过孔。至少部分过孔与第一绝缘层过孔和第二绝缘层过孔位置对应，且同时贯穿第一绝缘层、第二绝缘层和第三绝缘层，例如过孔402，过孔405，过孔303，过孔305。
步骤S18：在该第三绝缘层105上形成第三导电材料层，对该第三导电材料层进行构图工艺形成如图4C所示的第三导电层203，也即形成彼此绝缘的数据线12、第一电源线250、第一连接电极231、第二连接电极232和第三连接电极233。该数据线12和该第一电源线250沿第一方向D1延伸。
例如，如图4C所示，该数据线12与第二晶体管T2的第一极T2s在垂直于衬底基板101的方向上重叠并通过过孔305与该第二晶体管T2的第一极T2s电连接，该过孔305例如贯穿第一绝缘103、第二绝缘层104和第三绝缘层105。
例如，如图4C和图7所示，该第一电源线250与该屏蔽电极221在垂直于衬底基板101的方向上重叠并通过过孔304与该屏蔽电极221电连接， 例如该过孔304贯穿第三绝缘层105。
例如，如图4C所示，该第一电源线250通过过孔302与所对应的一列子像素中的第一电容电极Ca电连接，并通过过孔303与第四晶体管T4的第一极T4s电连接。例如，该过孔302贯穿第三绝缘层105，该过孔303贯穿第一绝缘103、第二绝缘层104和第三绝缘层105。
例如，如图4C和图7所示，该第一连接电极231的一端通过第一电容电极Ca中的过孔301以及绝缘层中的过孔401与该第一晶体管T1的栅极T1g，即第二电容电极Cb电连接，另一端通过过孔402与该第三晶体管T3的第一极电连接，从而将该第二电容电极Cb与该第三晶体管T3的第一极T3s电连接。例如，该过孔401贯穿第二绝缘层104和第三绝缘层105，该过孔402贯穿第一绝缘层103、第二绝缘层104和第三绝缘层105。
例如，如图4C所示，该第二连接电极232的一端通过过孔403与复位电压线电连接，另一端通过过孔404与第六晶体管T6电连接，使得该第六晶体管T6的第一极T6s可以从该复位电压线240接收第一复位电压Vinit1。例如，该过孔403贯穿第三绝缘层105，该过孔404贯穿第一绝缘层103、第二绝缘层104和第三绝缘层105。
例如，如图4C和图7所示，该第三连接电极233通过通过过孔405与第五晶体管T5的第二极T5d电连接，并用于将该第五晶体管T5的第二极T5d与发光元件的第一电极134电连接，例如，该过孔405贯穿第一绝缘层103、第二绝缘层104和第三绝缘层105。
步骤S19：在第三导电层203上形成第四绝缘层106。并在第三绝缘层中形成用于与后续形成的第四导电层连接的过孔。在一些实施例中，例如第四绝缘层106包括第一平坦层。在另一些实施例中，例如第四绝缘层106包括钝化层和第一平坦层两层，则形成在第四绝缘层中的过孔需要贯穿钝化层和第一平坦层两层。例如，第一平坦层位于钝化层远离第三导电层的一侧。
步骤S20：在该第四绝缘层106上形成第四导电材料层，对该第四导电材料层进行构图工艺形成如图4D所示的第四导电层204，也即形成第二电源线260、第三电源线270以及第四连接电极234，该第二电源线260和该第三电源线270彼此连接，并与第四连接电极234绝缘。
例如，如图4D所示，多条第三电源线270沿第一方向D1延伸，并分别与多条第一电源线250通过过孔306一一对应电连接。例如，每条第三电 源线270与对应的第一电源线250在垂直于衬底基板101的方向上彼此重叠。例如，该过孔306贯穿第四绝缘层106。
例如，如图4D所示，该第四连接电极234与第三连接电极233在垂直于衬底基板101的方向上重叠，并且该第三连接电极234通过贯穿第四绝缘层106的过孔307与第三连接电极233电连接。
步骤S21：例如，参考图7，该显示基板的制作方法还可以包括在该第四导电层204上形成第五绝缘层107，并在第五绝缘层107中形成用于与后续形成的第五导电层进行连接的过孔。例如第五绝缘层107可以为第二平坦层。第五绝缘层过孔例如用于连接第一晶体管漏极和发光器件的第一电极，第五绝缘层过孔与第一晶体管的漏极可以有交叠，也可以没有交叠，没有交叠的情况，可以额外在第三导电层中设置连接线连接，哪种连接方式与子像素排列结构例如第一电极的位置和形状有关。
步骤S22：在该第五绝缘层107上形成第五导电材料层，对该第五导电材料层进行构图工艺形成第五导电层205，即形成彼此绝缘的多个用于形成发光元件的第一电极134(图中示出为134a)。
例如，每个第一电极134包括主体部141和连接部142，主体部141主要用于驱动发光层发光，连接部142主要用于与像素电路进行电连接。
例如，如图7所示，该连接部142通过第五绝缘层107中的过孔308与第四连接电极234电连接，例如，在平行于衬底基板101板面的方向上，过孔308相较于过孔307更加远离第一电极134的主体部141，也即该子像素的开口401，也即该过孔308在衬底基板101上的正投影相较于过孔307在衬底基板101上的正投影更加远离该开口401在衬底基板上的正投影。
例如，如图7所示，该显示基板的制作方法还可以包括依次在该第五导电层205上形成像素界定层108，并在该像素界定层108中对应于每个第一电极134的主体部141形成开口401，然后至少在该开口401中形成发光层136，并在该发光层上形成第二电极135。
例如，该半导体材料层的材料包括但不限于硅基材料(非晶硅a-Si，多晶硅p-Si等)、金属氧化物半导体(IGZO，ZnO，AZO，IZTO等)以及有机物材料(六噻吩，聚噻吩等)。
例如，上述第一导电材料层、第二导电材料层、第三导电材料层、第四导电材料层、第五导电材料层及第二电极的材料可以包括金(Au)、银(Ag)、 铜(Cu)、铝(Al)、钼(Mo)、镁(Mg)、钨(W)以及以上金属组合而成的合金材料；或者透明金属氧化物导电材料，例如氧化铟锡(ITO)、氧化铟锌(IZO)、氧化锌(ZnO)、氧化锌铝(AZO)等。
例如，第一绝缘层103、第二绝缘层104、第三绝缘层105、第四绝缘层106、第五绝缘层107例如为无机绝缘层，例如氧化硅、氮化硅、氮氧化硅等硅的氧化物、硅的氮化物或硅的氮氧化物，或者氧化铝、氮化钛等包括金属氮氧化物绝缘材料。例如，这些绝缘层部分层也可以是有机材料，例如第一平坦层和第二平坦层，例如聚酰亚胺(PI)、丙烯酸酯、环氧树脂、聚甲基丙烯酸甲酯(PMMA)等，本公开实施例对此不作限制。例如，第四绝缘层106和第五绝缘层107可以包括平坦层。
例如，上述构图工艺可以采用常规的光刻工艺，例如包括光刻胶的涂布、曝光、显影、烘干、刻蚀等步骤。
步骤S102：在衬底基板上形成像素界定层。
例如，参考图7，在上述像素电路结构形成后，通过构图工艺形成像素界定层403，该像素界定层403包括多个开口401，每个开口401暴露第一电极134，用于形成一个子像素的发光元件120。
例如，一次构图工艺包括光刻胶的涂覆、曝光、显影、刻蚀等多个步骤，当被构图的材料本身即是光刻胶材料时，一次构图工艺可以仅包括曝光和显影的步骤。
例如，像素界定层403的材料可以为聚酰亚胺(PI)，由于聚酰亚胺本身可作为光刻胶材料，因此可以通过在像素电路结构上涂覆聚酰亚胺材料层，然后对聚酰亚胺材料层进行曝光与显影而形成具有多个开口的像素界定层。
步骤S103：在像素界定层的远离衬底基板的一侧形成至少一个隔垫物。
例如，形成至少一个隔垫物包括形成呈阵列排布的多个隔垫物，每个隔垫物具有相似的形成位置。
例如，首先定位隔垫物的形成位置，然后在该位置形成隔垫物，使得形成的隔垫物的与像素界定层接触的底部的任意一点距离多个开口的上表面的侧壁的距离D大于或等于5μm。
例如，可以采用多种方法定位隔垫物的形成位置。例如，在一个示例中，可以通过像素界定层中多个开口的位置定位隔垫物的形成位置。由此将隔垫 物形成在多个开口之间，并使得形成的隔垫物的与像素界定层接触的底部的任意一点距离多个开口的上表面的侧壁的距离D大于或等于5μm。
例如，在一个示例中，显示基板上形成的像素电路结构包括相互平行设置的第一信号线和第二信号线，此时，可以定位第一信号线和第二信号线的位置，然后以第一信号线和第二信号线的位置为基准定位隔垫物的形成位置，使得形成的隔垫物在衬底基板上的第一正投影位于第一信号线在衬底基板上的第二正投影和第二信号线在衬底基板上的第三正投影之间。
例如，在制备工艺中，可以采用光学检测装置扫描第一信号线和第二信号线的位置，然后以第一信号线和第二信号线的位置为基准设定隔垫物的形成位置，进而设置用于形成隔垫物的掩模板的位置，使得利用该掩膜板形成的隔垫物位于上述设定的位置。
例如，如上所示，第一信号线可以为发光控制信号线230/EM，第二信号线可以为复位信号线220/RST。
例如，通过定位后，隔垫物在衬底基板上的第一正投影的中心距离第一信号线在衬底基板上的第二正投影的中轴线的距离大于第一正投影的中心距离第二信号线在衬底基板上的第三正投影的中轴线的距离，即隔垫物在第一信号线和第二信号线之间且更靠近第二信号线。
例如，隔垫物的材料可以为聚酰亚胺(PI)，由于聚酰亚胺本身可作为光刻胶材料，此时，如图7所示，形成隔垫物402包括：在像素界定层403的远离衬底基板101的一侧形成聚酰亚胺材料层，通过掩模板对聚酰亚胺材料层进行曝光和显影，以形成隔垫物402。例如，当所需求的隔垫物的高度H为0.8μm-1.5μm时，聚酰亚胺材料层的形成厚度即为0.8μm-1.5μm，例如1μm或者1.2μm等。
例如，隔垫物的材料可以和像素界定层的材料相同。例如，隔垫物可以和像素界定层一体形成。例如采用半色调掩膜通过一次构图工艺形成隔垫物和像素界定层。
需要说明的是，每个子像素包括像素电路结构和发光器件，发光器件位于像素界定层开口内的部分为实际发光区域，本发明实施例中，隔垫物与像素电路结构的重叠关系中，例如与各条信号线的位置关系，是以像素电路区域即如图4B所示的虚线框的区域进行说明，隔垫物与各个子像素的第一电极或像素界定层开口的位置关系，是以第一电极或像素界定层开口的实际位 置和覆盖区域进行说明。
例如，参考图4，隔垫物402在衬底基板101上的正投影形状为矩形，该矩形的长L可以为20μm-30μm，例如22μm、25μm或者28μm等，该矩形的宽D可以为10μm-16μm，例如12μm或者15μm等。例如，在其他实施例中，隔垫物402在衬底基板101上的第一正投影的形状也可以为圆形、椭圆形、三角形或者其他多边形等，本公开的实施例对隔垫物402的具体形状不做限定。
例如，如图7所示，在隔垫物402形成好后，可以采用喷墨打印或者蒸镀等方法通过掩模板420(例如FMM)在像素界定层403的多个开口401中形成发光层136，发光层136至少覆盖像素界定层的开口，还可以覆盖部分像素界定层远离衬底基板的表面，以保证位于开口内的发光层更均匀可靠。在设置掩模板420的过程中，隔垫物402和掩模板420的设置距离往往较近，由于重力等原因，隔垫物402和掩模板420的中间部分可能会接触，此时，隔垫物402可以对掩模板420起到支撑作用，以避免掩模板420刮伤显示基板上已经形成好的功能结构。
如图8所示，在发光层136形成后，采用溅射等方法在发光层136上形成第二电极135。例如，第二电极135可以在显示基板上整面形成。之后，在第二电极135上形成封装层410，以对显示基板进行封装与保护。
例如，封装层410可以包括多个封装子层，例如多个无机子绝缘层和有机子绝缘层的叠层。例如无机封装子层的材料包括氧化硅、氮化硅或者氮氧化硅等无机材料，有机封装子层的材料包括树脂、聚酰亚胺等有机材料。其中，无机子绝缘层可以采用沉积等方式形成，有机封装子层可以采用涂覆等方式形成。
例如，显示基板上还可以覆盖有透明盖板等其他结构，本公开的实施例对显示基板的其他结构不做具体限定。
在利用本公开实施例提供的制备方法制备显示基板的过程中，通过对隔垫物的位置以及形状、大小等的设计，使得隔垫物可以对其上设置的掩模板(例如FMM)起到充分地支撑作用，以避免掩模板刮伤显示基板上已形成的其他功能结构。因此，利用该制备方法得到的显示基板具有更好的信赖性。
还有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他 结构可参考通常设计。
(2)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大或缩小，即这些附图并非按照实际的比例绘制。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”或者可以存在中间元件。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。

Claims (29)

  1. 一种显示基板，包括：
    衬底基板，
    像素界定层，设置在所述衬底基板上，包括多个开口，以及
    至少一个隔垫物，设置在所述像素界定层的远离所述衬底基板的一侧；
    其中，所述至少一个隔垫物的与所述像素界定层接触的底部的任意一点距离多个所述开口的侧壁的上边缘的距离大于或等于5μm。
  2. 根据权利要求1所述的显示基板，还包括：
    像素电路结构，设置在所述衬底基板与所述像素界定层之间，包括相互平行设置的第一信号线和第二信号线，
    其中，所述至少一个隔垫物在所述衬底基板上的第一正投影位于所述第一信号线在所述衬底基板上的第二正投影和所述第二信号线在所述衬底基板上的第三正投影之间。
  3. 根据权利要求2所述的显示基板，其中，所述第一信号线为发光控制信号线，所述第二信号线为复位信号线。
  4. 根据权利要求3所述的显示基板，其中，所述第一正投影的中心距离所述第二正投影的中轴线的距离大于所述第一正投影的中心距离所述第三正投影的中轴线的距离。
  5. 根据权利要求1-4任一所述的显示基板，其中，所述至少一个隔垫物包括排布为多行多列的多个隔垫物；所述像素电路结构包括排列为多行多列的多个像素电路，每行像素电路共用一条发光控制信号线和一条复位信号线，
    其中，一行像素电路的发光控制信号线在所述衬底基板上的正投影和下一行像素电路的复位信号线在所述衬底基板上的正投影之间包括一行隔垫物在所述衬底基板的正投影。
  6. 根据权利要求5所述的显示基板，其中，在每行像素电路中，每四个相邻的像素电路对应设置一个所述隔垫物。
  7. 根据权利要求1-4任一所述的显示基板，其中，所述至少一个隔垫物包括排布为多行多列的多个隔垫物，
    位于奇数行的多个隔垫物与位于偶数行的多个隔垫物错位1/2节距。
  8. 根据权利要求7所述的显示基板，其中，所述多个开口包括用于蓝色子像素的第一开口、用于红色子像素的第二开口和用于绿色子像素的第三开口，并且所述第一开口、所述第二开口和所述第三开口的开口大小依次减小。
  9. 根据权利要求8所述的显示基板，其中，以一个蓝色子像素、一个红色子像素和两个绿色子像素为一个重复单元，所述显示基板包括排布为多行多列的多个重复单元；每个所述重复单元对应设置一个所述隔垫物；
    在每个重复单元中，所述两个绿色子像素的第三开口沿行方向排列，所述蓝色子像素的第一开口和所述红色子像素的第三开口沿列方向排列，所述隔垫物被所述两个绿色子像素的第三开口、所述蓝色子像素的第一开口和所述红色子像素的第三开口围绕。
  10. 根据权利要求9所述的显示基板，其中，每个重复单元中两个绿色子像素的所述第三开口的中心的连线穿过所述隔垫物，且所述连线平行于所述隔垫物的长度方向。
  11. 根据权利要求10所述的显示基板，其中，所述隔垫物的长度方向为所述显示基板的水平显示方向。
  12. 根据权利要求9所述的显示基板，其中，所述隔垫物在所述衬底基板上的正投影与所述红色子像素的像素电路所在的区域在所述衬底基板上的正投影重叠。
  13. 根据权利要求1-12任一所述的显示基板，其中，所述至少一个隔垫物的高度为0.8μm-1.5μm。
  14. 根据权利要求1-13任一所述的显示基板，其中，所述至少一个隔垫物在所述衬底基板上的正投影形状为矩形。
  15. 根据权利要求14所述的显示基板，其中，所述矩形的长为20μm-30μm，所述矩形的宽为10μm-16μm。
  16. 根据权利要求1-15任一所述的显示基板，其中，所述至少一个隔垫物的材料为聚酰亚胺。
  17. 一种显示基板，包括：
    衬底基板，
    像素电路结构，设置在所述衬底基板上，包括相互平行设置的第一信号线和第二信号线，
    像素界定层，设置在所述像素电路结构的远离所述衬底基板的一侧，包括多个开口，以及
    至少一个隔垫物，设置在所述像素界定层的远离所述衬底基板的一侧；
    其中，所述至少一个隔垫物设置在所述衬底基板上的第一正投影位于所述第一信号线在所述衬底基板上的第二正投影和所述第二信号线在所述衬底基板上的第三正投影之间。
  18. 根据权利要求17所述的显示基板，其中，所述第一信号线为发光控制信号线，所述第二信号线为复位信号线。
  19. 根据权利要求17所述的显示基板，其中，所述像素电路结构还包括电源线，所属电源线包括交替连接的多个第一部分和多个第二部分；
    所述多个第一部分彼此平行且延伸方向与所述第一信号线和所述第二信号线的延伸方向相同，所述第二部分的延伸方向与所述第一部分的延伸方向均相交；
    所述第一部分在所述衬底基板上的正投影与所述第一正投影部分重叠，所述第二部分在所述衬底基板上的正投影与所述第一正投影部分重叠。
  20. 根据权利要求19所述的显示基板，其中，所述像素电路结构还包括数据线，所述数据线的延伸方向与所述第一信号线和所述第二信号线的延伸方向垂直，
    所述数据线在所述衬底基板上的正投影与所述第一正投影不重叠。
  21. 一种显示基板，包括：
    衬底基板，
    像素界定层，设置在所述衬底基板上，包括多个开口，以及
    至少一个隔垫物，设置在所述像素界定层的远离所述衬底基板的一侧；
    其中，所述多个开口包括开口大小依次减小的第一开口、第二开口和第三开口，在第一方向上，所述至少一个隔垫物的两侧分别为所述第一开口和所述第二开口，在与所述第一方向垂直的第二方向上，所述至少一个隔垫物的两侧均为所述第三开口。
  22. 根据权利要求21所述的显示基板，其中，所述第一开口内包括蓝色发光层，所述第二开口内包括红色发光层，所述第三开口内包括绿色发光层。
  23. 根据权利要求21所述的显示基板，其中，所述第一开口的形状为 第一正方形，所述第二开口的形状为第二正方形，所述第一正方形的边长大于所述第二正方形的边长，
    所述第三开口的形状为长方形，所述长方形的长边与相邻的所述第一开口的第一正方形的边长平行，所述长方形的短边与相邻的所述第二开口的第二正方形的边长平行。
  24. 一种显示装置，包括权利要求1-23任一所述的显示基板。
  25. 一种显示基板的制备方法，包括：
    提供衬底基板，
    在所述衬底基板上形成像素界定层，所述像素界定层包括多个开口，以及
    在所述像素界定层的远离所述衬底基板的一侧形成至少一个隔垫物；
    其中，所述至少一个隔垫物的与所述像素界定层接触的底部的任意一点距离多个所述开口的上表面的侧壁的距离大于或等于5μm。
  26. 根据权利要求25所述的显示基板的制备方法，其中，在所述像素界定层的远离所述衬底基板的一侧形成至少一个隔垫物包括：
    定位所述至少一个隔垫物的形成位置，使得形成的所述至少一个隔垫物的与像素界定层接触的底部的任意一点距离多个所述开口的上表面的侧壁的距离大于或等于5μm。
  27. 根据权利要求26所述的显示基板的制备方法，还包括：
    在所述衬底基板与所述像素界定层之间形成像素电路结构，所述像素电路结构包括相互平行设置的第一信号线和第二信号线，
    其中，定位所述至少一个隔垫物的形成位置包括：
    定位所述第一信号线和所述第二信号线的位置，
    以所述第一信号线和所述第二信号线的位置为基准定位所述至少一个隔垫物的形成位置，使得形成的所述至少一个隔垫物设置在所述衬底基板上的第一正投影位于所述第一信号线在所述衬底基板上的第二正投影和所述第二信号线在所述衬底基板上的第三正投影之间。
  28. 根据权利要求27所述的显示基板的制备方法，其中，所述第一信号线为发光控制信号线，所述第二信号线为复位信号线。
  29. 根据权利要求25-28任一所述的显示基板的制备方法，其中，所述至少一个隔垫物的材料为聚酰亚胺，形成所述至少一个隔垫物包括：
    在所述像素界定层的远离所述衬底基板的一侧形成聚酰亚胺材料层，
    通过掩模板对所述聚酰亚胺材料层进行曝光和显影，以形成所述至少一个隔垫物。
PCT/CN2019/122156 2019-11-29 2019-11-29 显示基板及其制备方法、显示装置 WO2021102988A1 (zh)

Priority Applications (9)

Application Number Priority Date Filing Date Title
PCT/CN2019/122156 WO2021102988A1 (zh) 2019-11-29 2019-11-29 显示基板及其制备方法、显示装置
EP19945468.7A EP4068378A4 (en) 2019-11-29 2019-11-29 DISPLAY SUBSTRATE AND METHOD FOR PRODUCTION THEREOF, AND DISPLAY DEVICE
CN201980002732.5A CN113196494B (zh) 2019-11-29 2019-11-29 显示基板及其制备方法、显示装置
US16/977,866 US11974473B2 (en) 2019-11-29 2019-11-29 Display substrate, manufacturing method thereof and display device
US17/416,078 US20220077244A1 (en) 2019-11-29 2020-06-19 Display substrate and manufacturing method thereof, and display device
PCT/CN2020/097124 WO2021103504A1 (zh) 2019-11-29 2020-06-19 显示基板及其制作方法、显示装置
CN202080001059.6A CN114679914B (zh) 2019-11-29 2020-06-19 显示基板及其制作方法、显示装置
EP20892526.3A EP4068381A4 (en) 2019-11-29 2020-06-19 DISPLAY SUBSTRATE AND METHOD FOR MAKING IT, AND DISPLAY DEVICE
US18/591,771 US20240206267A1 (en) 2019-11-29 2024-02-29 Display substrate, manufacturing method thereof and display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2019/122156 WO2021102988A1 (zh) 2019-11-29 2019-11-29 显示基板及其制备方法、显示装置

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US16/977,866 A-371-Of-International US11974473B2 (en) 2019-11-29 2019-11-29 Display substrate, manufacturing method thereof and display device
US18/591,771 Continuation US20240206267A1 (en) 2019-11-29 2024-02-29 Display substrate, manufacturing method thereof and display device

Publications (1)

Publication Number Publication Date
WO2021102988A1 true WO2021102988A1 (zh) 2021-06-03

Family

ID=76129073

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/122156 WO2021102988A1 (zh) 2019-11-29 2019-11-29 显示基板及其制备方法、显示装置

Country Status (4)

Country Link
US (2) US11974473B2 (zh)
EP (1) EP4068378A4 (zh)
CN (1) CN113196494B (zh)
WO (1) WO2021102988A1 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023206399A1 (zh) * 2022-04-29 2023-11-02 京东方科技集团股份有限公司 显示面板和显示装置
WO2023230811A1 (zh) * 2022-05-31 2023-12-07 京东方科技集团股份有限公司 显示基板以及显示装置

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022016685A1 (zh) * 2020-07-24 2022-01-27 武汉华星光电半导体显示技术有限公司 像素驱动电路及其驱动方法、显示面板
CN115835701B (zh) * 2022-04-29 2023-10-31 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150261050A1 (en) * 2014-03-14 2015-09-17 Innolux Corporation Display device
CN108598136A (zh) * 2018-06-21 2018-09-28 武汉天马微电子有限公司 一种显示面板及显示装置
CN108922919A (zh) * 2013-04-26 2018-11-30 三星显示有限公司 有机发光二极管显示器
CN109148522A (zh) * 2018-08-10 2019-01-04 上海天马微电子有限公司 有机发光显示面板、显示面板的制作方法及显示装置
CN109378329A (zh) * 2018-09-28 2019-02-22 昆山国显光电有限公司 有机发光显示装置及其制备方法、制备支撑柱的掩膜板
CN110071158A (zh) * 2019-04-29 2019-07-30 上海天马有机发光显示技术有限公司 一种掩膜版和有机发光显示面板

Family Cites Families (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6738034B2 (en) 2000-06-27 2004-05-18 Hitachi, Ltd. Picture image display device and method of driving the same
KR102096051B1 (ko) 2013-03-27 2020-04-02 삼성디스플레이 주식회사 박막 트랜지스터 어레이 기판 및 이를 포함하는 유기 발광 표시 장치
KR20150005264A (ko) * 2013-07-05 2015-01-14 삼성디스플레이 주식회사 유기 발광 표시 장치 및 그 제조 방법
US9614021B2 (en) * 2013-07-24 2017-04-04 Samsung Display Co., Ltd. Organic light-emitting display apparatus and manufacturing method thereof
KR102211966B1 (ko) 2013-10-14 2021-02-15 삼성디스플레이 주식회사 박막 트랜지스터 어레이 기판 및 이를 포함하는 유기 발광 표시 장치
KR102151639B1 (ko) * 2013-10-16 2020-09-07 삼성디스플레이 주식회사 유기 발광 표시 장치
KR102118920B1 (ko) * 2014-01-28 2020-06-05 삼성디스플레이 주식회사 유기발광 표시장치 및 그 제조방법
CN105720071A (zh) 2014-12-02 2016-06-29 上海和辉光电有限公司 有机发光二极管显示装置
KR102239843B1 (ko) 2014-12-29 2021-04-14 삼성디스플레이 주식회사 표시 장치
KR102525051B1 (ko) 2015-01-30 2023-04-25 삼성디스플레이 주식회사 유기 발광 표시 장치
KR102409500B1 (ko) 2015-02-02 2022-06-15 삼성디스플레이 주식회사 유기 발광 표시 장치
KR102381288B1 (ko) 2015-03-04 2022-03-31 삼성디스플레이 주식회사 유기 발광 표시 장치
KR102426715B1 (ko) 2015-07-23 2022-08-01 삼성디스플레이 주식회사 유기전계발광 표시장치
KR102500271B1 (ko) 2015-08-19 2023-02-16 삼성디스플레이 주식회사 유기 발광 표시 장치 및 유기 발광 표시 장치의 제조 방법
KR102447435B1 (ko) 2016-03-11 2022-09-23 삼성전자주식회사 Emi 감소를 위한 전력 전송 네트워크를 포함하는 기판과 이를 포함하는 장치들
KR20180030363A (ko) 2016-09-13 2018-03-22 삼성디스플레이 주식회사 표시 장치
CN106298865B (zh) 2016-11-16 2019-10-18 京东方科技集团股份有限公司 像素排列结构、有机电致发光器件、显示装置、掩模板
KR102384774B1 (ko) 2017-03-27 2022-04-11 삼성디스플레이 주식회사 유기 발광 표시 장치
CN106910765B (zh) 2017-05-04 2020-02-18 京东方科技集团股份有限公司 一种电致发光显示面板、其制作方法及显示装置
KR102386906B1 (ko) 2017-05-11 2022-04-18 삼성디스플레이 주식회사 표시 장치
KR102391918B1 (ko) 2017-05-23 2022-04-29 삼성디스플레이 주식회사 유기발광표시장치
KR102352312B1 (ko) 2017-09-29 2022-01-19 삼성디스플레이 주식회사 표시 장치
KR102532307B1 (ko) 2017-11-02 2023-05-15 삼성디스플레이 주식회사 표시장치
TWI627577B (zh) * 2017-12-25 2018-06-21 友達光電股份有限公司 觸控顯示裝置
KR102595916B1 (ko) 2018-03-09 2023-10-31 삼성디스플레이 주식회사 표시장치
CN208335702U (zh) 2018-05-14 2019-01-04 北京京东方技术开发有限公司 显示面板及显示装置
KR102571354B1 (ko) 2018-05-16 2023-08-28 엘지디스플레이 주식회사 전계발광 표시장치
KR102541255B1 (ko) 2018-07-31 2023-06-12 삼성디스플레이 주식회사 표시 장치
KR102516058B1 (ko) 2018-08-17 2023-03-31 삼성디스플레이 주식회사 표시 패널
CN109119028B (zh) 2018-09-07 2020-04-28 武汉华星光电半导体显示技术有限公司 Amoled显示面板及相应的显示装置
CN112753064B (zh) 2018-09-28 2023-08-01 夏普株式会社 显示装置
KR102588594B1 (ko) * 2018-10-16 2023-10-16 삼성디스플레이 주식회사 표시 장치 및 그 제조 방법
CN109360851B (zh) 2018-11-30 2021-03-26 武汉天马微电子有限公司 一种显示面板和一种显示装置
TWI742339B (zh) 2019-01-28 2021-10-11 友達光電股份有限公司 顯示面板
CN109962096B (zh) 2019-04-15 2021-02-23 京东方科技集团股份有限公司 显示背板及其制作方法、显示装置
CN110265458B (zh) 2019-06-27 2021-12-03 京东方科技集团股份有限公司 阵列基板及其制作方法、显示面板及显示装置
KR20210028319A (ko) * 2019-09-03 2021-03-12 삼성디스플레이 주식회사 표시장치
US11437457B2 (en) 2019-11-29 2022-09-06 Chengdu Boe Optoelectronics Technology Co., Ltd. Display substrate and display device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108922919A (zh) * 2013-04-26 2018-11-30 三星显示有限公司 有机发光二极管显示器
US20150261050A1 (en) * 2014-03-14 2015-09-17 Innolux Corporation Display device
CN108598136A (zh) * 2018-06-21 2018-09-28 武汉天马微电子有限公司 一种显示面板及显示装置
CN109148522A (zh) * 2018-08-10 2019-01-04 上海天马微电子有限公司 有机发光显示面板、显示面板的制作方法及显示装置
CN109378329A (zh) * 2018-09-28 2019-02-22 昆山国显光电有限公司 有机发光显示装置及其制备方法、制备支撑柱的掩膜板
CN110071158A (zh) * 2019-04-29 2019-07-30 上海天马有机发光显示技术有限公司 一种掩膜版和有机发光显示面板

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4068378A4 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023206399A1 (zh) * 2022-04-29 2023-11-02 京东方科技集团股份有限公司 显示面板和显示装置
WO2023230811A1 (zh) * 2022-05-31 2023-12-07 京东方科技集团股份有限公司 显示基板以及显示装置

Also Published As

Publication number Publication date
US20220399423A1 (en) 2022-12-15
US20240206267A1 (en) 2024-06-20
US11974473B2 (en) 2024-04-30
CN113196494A (zh) 2021-07-30
EP4068378A4 (en) 2023-04-12
EP4068378A1 (en) 2022-10-05
CN113196494B (zh) 2024-04-02

Similar Documents

Publication Publication Date Title
US20220123094A1 (en) Display substrate and display device
JP7453254B2 (ja) 表示基板及び表示装置
WO2021102988A1 (zh) 显示基板及其制备方法、显示装置
CN113196374B (zh) 显示基板及显示装置
US10403696B2 (en) Organic light emitting display device and method of fabricating the same
CN114373774A (zh) 显示基板及其制备方法、显示装置
CN114679914B (zh) 显示基板及其制作方法、显示装置
JP2022539621A (ja) ディスプレイパネル及びその製造方法、表示装置
US20210028259A1 (en) Array substrate and oled display device
WO2021083226A1 (zh) 一种显示基板及其制作方法、显示装置
US20230165052A1 (en) Display panel, method for manufacturing same, and display device
CN218158982U (zh) 触控结构、触控显示面板以及显示装置
WO2022226818A1 (zh) 显示基板、显示面板和显示基板制造方法
WO2023231802A1 (zh) 触控结构、触控显示面板以及显示装置
WO2023184163A1 (zh) 显示基板及显示装置
WO2023000215A1 (zh) 显示基板及显示装置
WO2023137663A1 (zh) 显示基板和显示装置
WO2024113102A1 (zh) 显示基板和显示装置
WO2023030110A1 (zh) 显示基板、显示装置
WO2023039721A1 (zh) 显示面板和显示装置
US20240188357A1 (en) Display substrate and display device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19945468

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 2019945468

Country of ref document: EP

Effective date: 20220629