WO2020178995A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2020178995A1
WO2020178995A1 PCT/JP2019/008748 JP2019008748W WO2020178995A1 WO 2020178995 A1 WO2020178995 A1 WO 2020178995A1 JP 2019008748 W JP2019008748 W JP 2019008748W WO 2020178995 A1 WO2020178995 A1 WO 2020178995A1
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WO
WIPO (PCT)
Prior art keywords
side wall
insulating film
semiconductor device
wall portion
bonding
Prior art date
Application number
PCT/JP2019/008748
Other languages
English (en)
French (fr)
Inventor
育貴 相原
Original Assignee
三菱電機株式会社
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Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to JP2021503322A priority Critical patent/JP7042967B2/ja
Priority to PCT/JP2019/008748 priority patent/WO2020178995A1/ja
Priority to KR1020217027022A priority patent/KR102564086B1/ko
Priority to US17/420,586 priority patent/US11876061B2/en
Priority to CN201980092558.8A priority patent/CN113474871B/zh
Priority to TW109106214A priority patent/TWI735167B/zh
Publication of WO2020178995A1 publication Critical patent/WO2020178995A1/ja

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    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8536—Bonding interfaces of the semiconductor or solid state body
    • H01L2224/85365—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10335—Indium phosphide [InP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance

Definitions

  • This application relates to a semiconductor device.
  • a semiconductor device in which an air gap is provided between an electrode and a substrate in order to reduce the influence of the electrode of the bonding pad having a parasitic capacitance (see, for example, Patent Documents 1 to 3). ..
  • the electrodes are separated from the substrate like a cantilever, and in Patent Document 2, the electrodes are elastically deformed. Therefore, even if the distance between the electrode and the substrate is not stable and the parasitic capacitance is suppressed, it is expected that the influence of the fluctuation will be large.
  • JP-A-61-116848 page 2, upper right column to page 3, upper right column, FIGS. 1 to 3
  • Japanese Patent Laid-Open No. 2010-258342 paragraphs 0015 to 0021, FIGS. 1 to 5 and 8 to 9
  • Japanese Unexamined Patent Publication No. 7-79011 paragraphs 0039 to 0041, FIG. 8)
  • the present application discloses a technique for solving the above problems, and an object thereof is to obtain a semiconductor device capable of stably reducing the parasitic capacitance.
  • a semiconductor device disclosed in the present application includes a conductive semiconductor substrate on which a semiconductor circuit is formed, an insulating film deposited on a main surface of the conductive semiconductor substrate, a fixing portion fixed to the insulating film, and the fixing. And a bonding pad having a side wall portion rising from the side wall portion and an electrode portion connected to the side wall portion and arranged parallel to the main surface, the electrode portion having a space between the insulating film and the insulating film. It is characterized in that a portion that forms a portion and that is continuous with the side wall portion has at least one of a positional relationship of sandwiching a central portion of a bonding region with a bonding wire and surrounding the central portion.
  • the side wall portion is arranged on the outer peripheral side of the electrode to form the void, it is possible to obtain the semiconductor device capable of stably reducing the parasitic capacitance.
  • 1A to 1C are an end view perpendicular to a plan view of a semiconductor device according to a first embodiment and a plan view with a different cutting direction, respectively.
  • 2A to 2F are end views showing states of the semiconductor device according to the first embodiment in stages during the manufacturing process.
  • 3A to 3C are an end view perpendicular to a plan view of the semiconductor device according to the second embodiment and a plan view having a different cutting direction.
  • 4A and 4B are a plan view of a semiconductor device according to a third embodiment and an end view perpendicular to the plan view, respectively.
  • Embodiment 1. 1 and 2 are for explaining the configuration of the semiconductor device and the manufacturing method thereof according to the first embodiment
  • FIG. 1 is a plan view (FIG. 1) of a portion of the semiconductor device in which one bonding pad is formed. 1A) and the end view (FIG. 1B) cut along the line BB of FIG. 1A and the end view cut along the line CC of FIG. 1A as end views perpendicular to the plan view with the bonding wire added. It is the end view (FIG. 1C) which did.
  • 2A to 2F are end views corresponding to FIGS. 1B showing the state of each step in the process of forming the bonding pad on the conductive semiconductor substrate constituting the semiconductor device.
  • directions are displayed with the plane parallel to the main surface of the semiconductor device as the xy plane and the thickness direction as the z direction.
  • a semiconductor device is a semiconductor device in which active elements including semiconductor elements such as switching elements and rectifying elements, and in some cases, passive elements such as resistors and capacitors are formed on a conductive semiconductor substrate. It is a circuit configuration.
  • the bonding pad which is a characteristic part of the present application, is electrically connected to the above-mentioned element constituting the semiconductor circuit via the wiring pattern formed on the insulating film covering the surface of the conductive semiconductor substrate. To electrically connect to the outside.
  • the present application only the portion where one bonding pad is bonded on the insulating film that covers the conductive semiconductor substrate is described, and the description of the other portion including the connection portion between the bonding pad and the wiring pattern is omitted. Then, an explanation will be given.
  • the semiconductor device 1 has an insulating film 3 deposited on a conductive semiconductor substrate 2 and a metal bonding pad 4 formed on the insulating film 3.
  • the bonding pad 4 is a bonding target of the bonding wire 5 by wire bonding, that is, an electrode portion 4j serving as an electrode, and a fixing portion 4s having an end portion electrically connected to a wiring pattern (not shown) and fixed to the insulating film 3. Equipped with.
  • Both the electrode portion 4j and the fixed portion 4s extend in parallel with the main surface of the conductive semiconductor substrate 2 so as to cover a predetermined range in the xy plane.
  • the bonding pad 4 of the semiconductor device 1 according to the first embodiment extends in the direction away from the electrode portion 4j in the xy plane via the side wall portion 4w in which the electrode portion 4j extends in the thickness direction (z direction). It is connected to the fixed portion 4s.
  • the electrode portion 4j has a size that includes the bonding region R5 for bonding the bonding wire 5 in the xy plane, and the side wall portion 4w and the fixing portion 4s are outside the bonding region R5. So, it is divided into four parts along the circumferential direction.
  • a void portion 4g having a distance Dg is formed between the electrode portion 4j and the insulating film 3 including the junction region R5 in the xy plane direction.
  • the central portion of the bonding region R5 of the electrode portion 4j is supported so as to be sandwiched by at least two side wall portions 4w of the four side wall portions 4w, while the void portion 4g has a side wall in the circumferential direction. Except for the part where the part 4w is provided, it communicates with the outside.
  • FIGS. 2A to 2F show the end view corresponding to FIG. 1B as described above, and the state of the portion corresponding to FIG. 1C in which the side wall portion 4w and the fixing portion 4s are not arranged in the circumferential direction. And, the description about the resist and the like for forming the state is omitted.
  • an insulating film 3 is deposited on a conductive semiconductor substrate 2 on which elements (not shown) that form a semiconductor circuit are formed, and a second portion is formed on the insulating film 3 where a void 4g is formed.
  • One photoresist 8 is formed.
  • a power feeding layer 41 made of metal is deposited on the convex surface formed by the first photoresist 8 and the exposed insulating film 3.
  • a second photoresist 9 is formed on the outer edge of the deposited power supply layer 41, as shown in FIG. 2C.
  • the plating layer 42 is formed on the surface of the portion of the power feeding layer 41 exposed from the second photoresist 9, as shown in FIG. 2D.
  • the second photoresist 9 is removed with an organic solvent
  • the portion 41e of the power supply layer 41 covered with the second photoresist 9 is removed by the ion milling method, as shown in FIG. 2E.
  • the first photoresist 8 is removed with an organic solvent through the hollow portion shown in FIG. 1C where the side wall portion 4w in the circumferential direction is not formed.
  • the bonding pad 4 having a two-layer structure of the power feeding layer 41 and the plating layer 42 and having the void portion 4 g between the insulating film 3 is formed.
  • the conductive semiconductor substrate 2 is an n-type InP substrate
  • the insulating film 3 is SiO 2
  • the feeding layer 41 constituting the bonding pad 4 is Ti / Au.
  • Au (gold) was used for the (titanium / gold) laminated structure and the plating layer 42.
  • the semiconductor device 1 having the bonding pad 4 having the structure described in FIG. 1 can be easily obtained by the manufacturing method described in FIG. Further, even in the layer of the same metal type, in the layer formed by deposition by vapor deposition, sputtering method or the like, generally, a portion extending in the direction perpendicular to the surface (z direction) such as the side wall portion 4w is the fixed portion 4s.
  • the electrode portion 4j has a smaller thickness and a lower density than a portion formed in a direction parallel to the surface.
  • the side wall portion 4w portion also has the same thickness and density as the fixing portion 4s portion and the electrode portion 4j portion, so that the strength of the side wall portion 4w is increased and the resistance to be described later is increased. Deformability is improved.
  • the factor that increases the parasitic capacitance of the bonding pad in the semiconductor device is the capacitance of the parallel plate formed by the semiconductor substrate and the bonding pad via the insulating film. This capacitance is proportional to the dielectric constant of the insulating film and the area of the parallel plate, and is inversely proportional to the thickness of the insulating film.
  • the dielectric constant and thickness of the insulating film are determined by the physical properties of the insulating film and the manufacturing method.
  • the relative permittivity is about 4, and the upper limit is determined by the thickness needing to be several ⁇ m or less in consideration of productivity and workability.
  • the parallel plate capacitance is mainly determined by the area where the metal part of the bonding pad and the insulating film are in contact. Therefore, by adopting the structure having the void 4g between the bonding pad 4 and the insulating film 3 as in the present application, it is possible to reduce the parasitic capacitance as compared with the structure in which the entire bonding pad is in contact with the insulating film.
  • the electrode portion 4j can be held without being deformed in the thickness direction against the force applied in the thickness direction (z direction) toward the conductive semiconductor substrate 2 during wire bonding. At that time, even when a force in a direction parallel to the xy plane is applied, the electrode portion 4j can be held without being deformed in either the x direction or the y direction.
  • Patent Document 2 shows a configuration in which the electrode portion is floated by a frame-shaped insulating film.
  • the thickness of the insulating film varies depending on the time or speed of deposition or removal, dimensional controllability is poor.
  • Patent Document 2 since it is premised that the electrodes are elastically deformed originally, it is not necessary to consider such a problem. However, when the accuracy and stability of the interval are required, the dimensional variation is , Becomes a big problem.
  • the case where the four side wall portions 4w are provided along the circumferential direction has been shown, but the number is not limited to this and may be more. Further, three may be arranged along the circumferential direction so as to surround the central portion from three places, or two may be arranged so as to sandwich the central portion between two. For example, even if there are only two combinations of the 3 o'clock direction and the 9 o'clock direction among the four combinations of the side wall part 4w and the fixing part 4s in FIG. 1A, the two side wall parts 4w have electrode parts. The central portion of 4j is sandwiched. Therefore, even if the electrode portion 4j is pressed in the thickness direction, the shape of the void portion 4g formed between the electrode portion 4j and the insulating film 3 (in particular, the distance Dg) is not deformed in the thickness direction. Can hold.
  • the side wall portion 4w includes the central portion of the electrode portion 4j in the direction (y direction) perpendicular to the direction (x direction) of sandwiching the electrode portion 4j, and has a width that covers 1/3 or more of the joint region R5.
  • the electrode portion 4j is not deformed not only in the x direction component but also in the y direction component and The shape of the void 4g formed between the insulating films 3 (in particular, the distance Dg) can be maintained.
  • FIG. 3 is a plan view (FIG. 3A) of a portion of the semiconductor device according to the second embodiment in which one bonding pad is formed, and an end view perpendicular to the plan view in a state where a bonding wire is further added. It is an end view (FIG. 3B) cut along the line BB of FIG. 3A and an end view (FIG. 3C) cut along the line CC of FIG. 3A.
  • the configuration other than the bonding pad portion and the manufacturing method are the same as those described in the first embodiment, and the same portions are described. Is omitted.
  • the electrode portion 4j of the bonding pad 4 has an annular shape having an opening 4ja, and the side wall portion 4w and the fixing portion 4s have an annular shape. It is provided not only on the outer peripheral side but also on the inner peripheral side.
  • the outer peripheral side has the same configuration as that of the side wall portion 4w and the fixed portion 4s, which are denoted by the reference numerals in the first embodiment, and a detailed description thereof will be omitted. Is added to the end and is referred to as a side wall portion 4wo and a fixed portion 4so.
  • the electrode portion 4j extends in parallel with the main surface of the conductive semiconductor substrate 2 so as to cover a predetermined range in the xy plane and has a size including the bonding region R5. It has an annular shape having an opening 4ja having a diameter smaller than that of the region R5.
  • the annular outer peripheral side is similar to that of the first embodiment as described above, but the inner peripheral side is connected with the cylindrical side wall portion 4wi, which should be referred to as the second side wall portion.
  • the cylindrical side wall portion 4wi extends in the thickness direction (z direction) toward the insulating film 3, has a circular shape corresponding to the opening 4ja, and is closely attached to and fixed to the insulating film 3. Is connected to the fixed part 4si which should be called.
  • a void portion 4g having a space Dg is formed in the annular region between the electrode portion 4j and the insulating film 3 surrounded by the side wall portion 4wo on the outer peripheral side and the side wall portion 4wi on the inner peripheral side. It will be. Since the fixed portion 4si on the inner peripheral side becomes a parallel plate, the effect of reducing the parasitic capacitance is lower than that in the first embodiment. However, for example, even when the diameter of the fixed portion 4si is set to about 1 ⁇ 3 of the outer diameter of the electrode portion 4j, the area where the parallel plate is formed is only about 10% of the range of the electrode portion 4j. It is considered that the parasitic capacitance can be reduced as in the first embodiment.
  • the electrode portion 4j is supported not only by the outer peripheral side wall portion 4w described in the first embodiment but also by the inner peripheral side cylindrical side wall portion 4wi which is the second side wall portion. Therefore, in addition to the outer side wall portion 4wo, the support by the inner peripheral side side wall portion 4wi more reliably suppresses the deformation of the electrode portion 4j in the thickness direction, and is formed between the electrode portion 4j and the insulating film 3.
  • the shape of the void 4g can be maintained.
  • the side wall portion 4wi on the inner peripheral side opposes the force directly pressed in the thickness direction at the time of wire bonding without passing through the electrode portion 4j which is a beam, so that deformation can be prevented more firmly.
  • the side wall portion 4wi on the inner peripheral side is applied, so that the electrode portion 4j is not deformed not only in the x-direction component but also in the y-direction component.
  • the shape of the void 4g formed between the electrode portion 4j and the insulating film 3 can be held more firmly.
  • the side wall portion 4wi on the inner peripheral side has a cylindrical shape, it is structurally highly effective in suppressing deformation in any orientation in the xy plane.
  • FIG. 4 is a plan view (FIG. 4A) of a portion of the semiconductor device according to the third embodiment in which one bonding pad is formed, and an end view perpendicular to the plan view in a state where a bonding wire is further added. It is an end view (FIG. 4B) cut by the BB line of 4A.
  • the side wall portion and the fixing portion described in the first embodiment have a cylindrical shape and an annular shape that are continuous in the circumferential direction, respectively, as shown in FIGS. 4A and 4B. Configured to. In that case, the void portion for removing the first photoresist 8 described in FIGS. 2E and 2F of the first embodiment does not exist on the outer peripheral side of the first photoresist 8, so that the communicating hole is formed in the electrode portion 4j. 4p is provided.
  • the electrode portion 4j spreads in parallel with the main surface of the conductive semiconductor substrate 2 so as to cover a predetermined range in the xy plane, has a size including the bonding region R5, and is bonded to the central portion.
  • a communication hole 4p having a diameter smaller than that of the region R5 is formed.
  • the electrode portion 4j is supported by the side wall portion 4w over the entire circumference. Therefore, it is formed between the electrode portion 4j and the insulating film 3 by suppressing the bending of the electrode portion 4j and reliably suppressing the deformation in the thickness direction, as compared with the structure of holding intermittently shown in the first embodiment.
  • the shape of the void 4g can be maintained.
  • the side wall portion 4w is cylindrical, the effect of suppressing deformation is high in any direction in the xy plane structurally. Since the void 4g covers the same region as that of the first embodiment, the same effect of reducing the parasitic capacitance can be exhibited.
  • the communication hole 4p does not necessarily have to be located in the central portion or in the bonding region R5, and may be formed at any position of the electrode portion 4j as long as the sacrificial layer (first photoresist 8) can be removed. May be. Alternatively, it may be formed on a part of the side wall portion 4w to the extent that the support of the electrode portion 4j is not lowered.
  • the void 4g after bonding becomes a closed space.
  • the sealing resin does not enter the void 4g, and the effect of reducing the parasitic capacitance due to the increase in the dielectric constant is impaired. Absent.
  • the power feeding layer 41 constituting the n-type InP substrate as the conductive semiconductor substrate 2, the SiO 2 as the insulating film 3, and the bonding pad 4 has a Ti / Au laminated structure and the plating layer 42.
  • Au is shown, but the present invention is not limited to this.
  • the example in which the bonding pad 4 is formed by a laminated structure has been shown, but the present invention is not limited to this, and it is sufficient that the elements constituting the semiconductor circuit and the external circuit can be electrically connected by wire bonding.
  • the gap portion 4g may be formed between the electrode portion 4j and the insulating film 3 by the side wall portion 4w that sandwiches the central portion of the bonding region R5 or surrounds the central portion of the bonding region R5.
  • the conductive semiconductor substrate 2 on which the semiconductor circuit is formed the insulating film 3 deposited on the main surface of the conductive semiconductor substrate 2, and the insulating film.
  • a bonding pad 4 having 4j and 4j is provided, the electrode portion 4j forms a gap portion 4g with the insulating film 3, and a portion connected to the side wall portion 4w is a bonding region R5 with the bonding wire 5.
  • an opening 4ja is formed inside the bonding region R5 of the electrode portion 4j, and an insulating film is formed at a portion corresponding to the opening 4ja in a direction parallel to the main surface (xy plane direction). It has a second fixed portion (fixed portion 4si) fixed to 3 and a tubular second side wall portion (side wall portion 4wi) rising from the second fixed portion (fixed portion 4si), and is inside the opening 4ja. If the peripheral portion is configured to be connected to the second side wall portion (side wall portion 4wi), the tubular second side wall portion (side wall portion 4wi) supports the electrode portion 4j from the inner peripheral side, so that the bonding is performed. Deformation of the void portion 4g can be suppressed more firmly.
  • the side wall portion 4w (or the side wall portion 4w) is continuous with the electrode portion 4j over the entire circumference, and a communication hole 4p communicating with the gap portion 4g is formed in at least one of the electrode portion 4j and the side wall portion 4w. Since the side wall portion 4w supports the electrode portion 4j over the entire circumference, it is possible to suppress the deformation of the void portion 4g at the time of bonding regardless of the direction of the force, so that the parasitic capacitance is reduced. It can be reduced stably.
  • the void 4g becomes a closed space, and even if the resin is sealed, the resin is not filled in the void 4g.
  • the parasitic capacitance can be surely reduced without invading.
  • the bonding pad 4 includes a deposition layer (power feeding layer 41) formed on the side of the surface facing the insulating film 3 and a plating layer 42 formed on the side opposite to the power feeding layer 41.
  • a deposition layer power feeding layer 41
  • a plating layer 42 formed on the side opposite to the power feeding layer 41.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

半導体回路が形成された導電性半導体基板（２）と、導電性半導体基板（２）の主面に堆積された絶縁膜（３）と、絶縁膜（３）に固定された固定部（４ｓ）と、固定部（４ｓ）から立ち上がる側壁部（４ｗ）と、側壁部（４ｗ）に連なり、主面に対して平行に配置された電極部（４ｊ）と、を有するボンディングパッド（４）と、を備え、電極部（４ｊ）は、絶縁膜（３）との間に空隙部（４ｇ）を形成し、かつ、側壁部（４ｗ）に連なる部分が、ボンディングワイヤ（５）との接合領域（Ｒ５）の中央部を挟む、および中央部を囲む、の少なくともいずれかの位置関係にあるように構成した。

Description

半導体装置
　本願は、半導体装置に関するものである。
　半導体装置において、ボンディングパッドの電極が寄生容量を有することによる影響を低減するため、電極と基板との間に空隙を設けた半導体装置が開示されている（例えば、特許文献１～３参照。）。しかし、特許文献１に記載の半導体装置では、電極を基板から片持ち梁のように離し、特許文献２では、電極を弾性変形させるように構成していた。そのため、電極と基板との間隔が安定せず、寄生容量が抑制されたとしても、変動による影響が大きくなることが想定される。
特開昭６１－１１６８４８号公報（第２頁右上欄～第３頁右上欄、第１図～第３図） 特開２０１０－２５８３４２号公報（段落００１５～００２１、図１～図５、図８～図９） 特開平７－７９０１１号公報（段落００３９～００４１、図８）
　それに対して、例えば、特許文献３に記載の半導体装置のように、電極と基板との間にポリイミド製の筒を配置することで機械的に安定させることも考えられるが、ポリイミドの比誘電率は３であり、寄生容量を十分低減できるとは言えない。つまり、寄生容量の低減と安定性を両立させることは困難であった。
　本願は、上記のような課題を解決するための技術を開示するものであり、寄生容量を安定して低減できる半導体装置を得ることを目的とする。
　本願に開示される半導体装置は、半導体回路が形成された導電性半導体基板と、前記導電性半導体基板の主面に堆積された絶縁膜と、前記絶縁膜に固定された固定部と、前記固定部から立ち上がる側壁部と、前記側壁部に連なり、前記主面に対して平行に配置された電極部と、を有するボンディングパッドと、を備え、前記電極部は、前記絶縁膜との間に空隙部を形成し、かつ、前記側壁部に連なる部分が、ボンディングワイヤとの接合領域の中央部を挟む、および前記中央部を囲む、の少なくともいずれかの位置関係にあることを特徴とする。
　本願に開示される半導体装置によれば、電極の外周側に側壁部を配置して、空隙を形成するようにしたので、寄生容量を安定して低減できる半導体装置を得ることができる。
図１Ａ～図１Ｃは、それぞれ、実施の形態１にかかる半導体装置の平面図と、切断方向が異なる平面図に垂直な端面図である。 図２Ａ～図２Ｆは、実施の形態１にかかる半導体装置の製造工程中の段階ごとの状態を示す端面図である。 図３Ａ～図３Ｃは、それぞれ、実施の形態２にかかる半導体装置の平面図と、切断方向が異なる平面図に垂直な端面図である。 図４Ａと図４Ｂは、それぞれ、実施の形態３にかかる半導体装置の平面図と、平面図に垂直な端面図である。
実施の形態１．
　図１と図２は、実施の形態１にかかる半導体装置の構成とその製造方法について説明するためのものであり、図１は半導体装置におけるひとつのボンディングパッドが形成された部分の平面図（図１Ａ）と、さらにボンディングワイヤを追加した状態での、平面図に垂直な端面図として、図１ＡのＢ－Ｂ線で切断した端面図（図１Ｂ）と、図１ＡのＣ－Ｃ線で切断した端面図（図１Ｃ）である。また、図２Ａ～図２Ｆは、半導体装置を構成する導電性半導体基板にボンディングパッドを形成する工程での段階ごとの状態を示す、図１Ｂに対応する端面図である。なお、以降の実施の形態も含め、図において、半導体装置における主面に平行な面をｘｙ面、厚み方向をｚ方向として、方向表示している。
　本願の各実施の形態にかかる半導体装置は、スイッチング素子、整流素子等の半導体素子を含む能動素子、場合によれば、抵抗体、コンデンサ等の受動素子を、導電性半導体基板に形成し、半導体回路を構成したものである。そして、本願の特徴部分であるボンディングパッドは、導電性半導体基板の表面を覆う絶縁膜上に形成された配線パターンを介して、上述した半導体回路を構成する素子と電気接続されており、ワイヤボンディングにより、外部と電気接続するためのものである。ただし、本願では、導電性半導体基板を覆う絶縁膜上に、ひとつのボンディングパッドが接合されている部分のみを記載し、ボンディングパッドと配線パターンとの接続部分も含めた他の部分の記載は省略して、説明を行うものとする。
　半導体装置１は、図１Ａ～図１Ｃに示すように、導電性半導体基板２上に、絶縁膜３を堆積し、絶縁膜３上に金属製のボンディングパッド４を形成したものである。ボンディングパッド４は、ワイヤボンディングによるボンディングワイヤ５の接合対象、つまり電極となる電極部４ｊと、図示しない配線パターンと端部が電気接続されるとともに、絶縁膜３に固定されている固定部４ｓとを備えている。
　電極部４ｊ、固定部４ｓは、ともに、ｘｙ面内で所定の範囲を網羅するように導電性半導体基板２の主面と平行に広がっている。そして、本実施の形態１にかかる半導体装置１のボンディングパッド４は、電極部４ｊが厚さ方向（ｚ方向）に延びる側壁部４ｗを介して、ｘｙ面内で電極部４ｊから離れる方向に延びる固定部４ｓに連なっている。具体的には、電極部４ｊは、ｘｙ面内において、ボンディングワイヤ５を接合するための接合領域Ｒ５を包含する大きさを有し、側壁部４ｗおよび固定部４ｓは、接合領域Ｒ５よりも外側で、周方向に沿って４つに分かれて配置している。
　これにより、ｘｙ面方向における接合領域Ｒ５部分を含み、電極部４ｊと絶縁膜３との間には、間隔Ｄｇの空隙部４ｇが形成されることになる。このとき、電極部４ｊの接合領域Ｒ５の中心部分は、４つの側壁部４ｗのうちの、少なくとも２つの側壁部４ｗによって挟まれるように支えられ、一方、空隙部４ｇは、周方向において、側壁部４ｗが設けられている部分以外は、外部と連通している。
　次に製造方法について図２を用いて説明する。なお、図２Ａ～図２Ｆは、上述したように図１Ｂに対応する端面図を示すものであり、周方向において側壁部４ｗと固定部４ｓを配置していない、図１Ｃに対応する部分の状態と、その状態を形成するためのレジスト等についての記載は省略している。
　はじめに、図２Ａに示すように、図示しない半導体回路を構成する素子等が形成された導電性半導体基板２上に絶縁膜３を堆積し、絶縁膜３上の空隙部４ｇを形成する部分に第一フォトレジスト８を形成する。つぎに、第一フォトレジスト８および、露出した絶縁膜３で形成された凸形状の表面に、図２Ｂに示すように、金属からなる給電層４１を堆積する。堆積した給電層４１の外縁部には、図２Ｃに示すように、第二フォトレジスト９を形成する。
　そして、給電層４１のうち、第二フォトレジスト９から露出した部分の表面に、図２Ｄに示すように、電解メッキ法によってメッキ層４２を形成する。その後、第二フォトレジスト９を有機溶剤で除去し、イオンミリング法によって、図２Ｅに示すように、給電層４１の第二フォトレジスト９で覆われていた部分４１ｅを除去する。最後に、周方向における側壁部４ｗが形成されていない図１Ｃで示した抜け部分を介して、第一フォトレジスト８を有機溶剤で除去する。これにより、図２Ｆに示すような、給電層４１とメッキ層４２による２層構造を有し、絶縁膜３との間に空隙部４ｇを有するボンディングパッド４が形成される。
　なお、本実施の形態１および以降の実施の形態においては、導電性半導体基板２として、ｎ型ＩｎＰ基板、絶縁膜３としてＳｉＯ２、ボンディングパッド４を構成する給電層４１には、Ｔｉ／Ａｕ(チタン／金)の積層構造、メッキ層４２は、Ａｕ（金）を用いた。これにより、図１で説明した構造のボンディングパッド４を有する半導体装置１を、図２で説明した製造方法で容易に得ることができる。また、同じ金属種の層でも、蒸着、スパッタ法等の堆積で形成した層は、一般的に、側壁部４ｗのような、面に垂直な方向（ｚ方向）に延びる部分が、固定部４ｓ、電極部４ｊのような、面に平行な方向に形成される部分よりも厚みが薄く、密度も疎になる。しかし、電解メッキで形成されたメッキ層４２部分では、側壁部４ｗ部分も、固定部４ｓ部分、電極部４ｊ部分と同等の厚みおよび密度となるため、側壁部４ｗの強度を高め、後述する耐変形性が向上する。
　つぎに、本願の作用効果について説明する。半導体装置におけるボンディングパッドの寄生容量を増加させる要因として、絶縁膜を介して半導体基板とボンディングパッドが形成する平行平板の容量がある。この容量は、絶縁膜の誘電率と平行平板の面積に比例し、絶縁膜の厚みに反比例する。
　このうち、絶縁膜の誘電率と厚みは、絶縁膜の物性および製造方法によって決まる。例えばプラズマＣＶＤ法により形成するＳｉＯ２であれば、比誘電率は４程度で、厚みは生産性および加工性を考慮すれば、数μｍ以下にする必要があることで上限が決まる。面積（電極部）については、小さければ小さいほど寄生容量が小さくなるが、Ａｕのボンディングワイヤを用いてボールボンディングする場合は、直径５０μｍ程度までしか小さくすることができない。
　平行平板容量は、ボンディングパッドの金属部分と絶縁膜が接触している面積で支配的に決まる。そのため、本願のようにボンディングパッド４と絶縁膜３間に空隙部４ｇを有する構造とすることで、ボンディングパッド全面が絶縁膜と接する構造よりも寄生容量を低減することが可能となる。
　このとき、絶縁膜３と接触していない電極部４ｊの接合領域Ｒ５の中心部分は、４つの側壁部４ｗによって囲まれるように外周側から支えられている。そのため、ワイヤボンディングの際にかかる、導電性半導体基板２に向かって電極部４ｊを厚み方向（ｚ方向）に押し付ける力に対し、電極部４ｊを厚み方向に変形させることなく保持できる。その際、ｘｙ面に平行な方向の力が加わった場合でも、電極部４ｊをｘ方向、あるいはｙ方向のいずれにも変形させることなく保持することができる。
　また、電極部４ｊを支える側壁部４ｗは金属でできているので、空隙部４ｇ形成するための第一フォトレジスト８を除去するときに侵食されることがない。さらに、フォトレジストの厚みは精度よく制御できるので、間隔Ｄｇの精度も高い。それに対して、例えば、特許文献２の変形例には、枠状の絶縁膜で電極部分を浮かす構成が示されている。しかし、絶縁膜は、堆積、あるいは、除去の時間、速度によって、厚みが変動することから、寸法制御性に劣る。もっとも、特許文献２では、元々電極が弾性変形することを前提としているため、このような問題を考慮する必要はないが、間隔の精度と安定性を要件とする場合には、寸法のばらつきは、大きな問題となる。
　なお、本実施の形態１では、側壁部４ｗを周方向に沿って４つ設けた場合を示したが、これに限ることはなく、さらに多数でもよい。また、３か所から中心部分を囲むように、３つを周方向に沿って配置してもよく、２つで中心部分を挟むように、２つ配置するようにしてもよい。例えば、図１Ａにおける、４組の側壁部４ｗと固定部４ｓの組合せのうち、３時方向と９時方向の２組の組合せだけを有する場合であっても、２つの側壁部４ｗが電極部４ｊの中央部を挟み込んでいる。そのため、電極部４ｊが厚み方向に押し付けられても、電極部４ｊを厚み方向に変形させることなく、電極部４ｊと絶縁膜３の間に形成される空隙部４ｇの形状（とくに、間隔Ｄｇ）を保持できる。
　さらに、側壁部４ｗは、電極部４ｊを挟み込む方向（ｘ方向）に垂直な方向（ｙ方向）において、電極部４ｊの中央部を含み、接合領域Ｒ５内の１／３以上を網羅する幅を有している。そのため、電極部４ｊに平行な方向（ｘ方向、ｙ方向）の力が加わった場合でも、電極部４ｊをｘ方向成分はもちろんのこと、ｙ方向成分にも変形させることなく、電極部４ｊと絶縁膜３の間に形成される空隙部４ｇの形状（とくに、間隔Ｄｇ）を保持できる。
実施の形態２．
　上記実施の形態１においては、電極部の外周部分のみに側壁部を設ける例について説明した。本実施の形態２においては、電極部の内周側にも側壁部を設けた例について説明する。図３は実施の形態２にかかる半導体装置におけるひとつのボンディングパッドが形成された部分の平面図（図３Ａ）と、さらにボンディングワイヤを追加した状態での、平面図に垂直な端面図として、図３ＡのＢ－Ｂ線で切断した端面図（図３Ｂ）と、図３ＡのＣ－Ｃ線で切断した端面図（図３Ｃ）である。
　なお、本実施の形態２および後述する実施の形態３にかかる半導体装置において、ボンディングパッド部分以外の構成、および製造方法については、実施の形態１で説明したのと同様であり、同様な部分については、説明を省略する。
　本実施の形態２にかかる半導体装置１では、図３Ａ～図３Ｃに示すように、ボンディングパッド４の電極部４ｊは、開口部４ｊａを有する円環状をなし、側壁部４ｗと固定部４ｓは、外周側だけではなく、内周側にも設けている。外周側については、実施の形態１で側壁部４ｗ、固定部４ｓと符号を付していた部分と同様の構成であり、詳細な説明は省略するが、本実施の形態２においては、外周側を示す「ｏ」を末尾に追加し、側壁部４ｗｏ、固定部４ｓｏと記す。
　電極部４ｊは、ｘｙ面内で所定の範囲を網羅するように導電性半導体基板２の主面と平行に広がり、接合領域Ｒ５を包含する大きさを有しているが、中央部分が、接合領域Ｒ５よりも小さな径の開口部４ｊａを有する円環状となっている。円環状の外周側は上述したように実施の形態１と同様であるが、内周側には、第二の側壁部と称すべき、円筒状の側壁部４ｗｉが連なっている。円筒状の側壁部４ｗｉは、絶縁膜３に向かって、厚さ方向（ｚ方向）に延び、開口部４ｊａに対応した円形をなし、絶縁膜３に密着・固定されている第二の工程部と称すべき固定部４ｓｉに連なる。
　これにより、電極部４ｊと絶縁膜３との間のうち、外周側の側壁部４ｗｏと内周側の側壁部４ｗｉで囲まれる円環状の領域には、間隔Ｄｇの空隙部４ｇが形成されることになる。内周側の固定部４ｓｉ部分が平行平板になってしまうため、実施の形態１と比較すると、寄生容量の低減効果は低くなる。しかし、例えば、固定部４ｓｉの径を、電極部４ｊの外径の１／３程度にした場合でも、平行平板が形成される面積は、電極部４ｊの範囲の１割程度にしかならず、基本的には、実施の形態１と同様に、寄生容量が低減できると考えられる。
　その一方、電極部４ｊは、実施の形態１で説明した外周側の側壁部４ｗのみならず、第二の側壁部たる、内周側の円筒状の側壁部４ｗｉにも支えられることになる。そのため、外側の側壁部４ｗｏに加え、内周側の側壁部４ｗｉによる支持により、電極部４ｊの厚み方向への変形をより確実に抑制し、電極部４ｊと絶縁膜３の間に形成される空隙部４ｇの形状を保持できる。とくに、内周側の側壁部４ｗｉは、ワイヤボンディングの際、梁となる電極部４ｊを介すことなく、直接厚み方向に押し付けられる力に対抗するので、より強固に変形を防止できる。
　また、電極部４ｊに平行な方向の力に対しても、内周側の側壁部４ｗｉが加わったことで、電極部４ｊをｘ方向成分はもちろんのこと、ｙ方向成分にも変形させることなく、電極部４ｊと絶縁膜３の間に形成される空隙部４ｇの形状をより強固に保持できる。とくに、内周側の側壁部４ｗｉは、円筒状なので、構造的にｘｙ面におけるどの方位に対しても、変形を抑制する効果が高い。
実施の形態３．
　上記実施の形態１または２においては、電極部の外周側の側壁部を周方向に沿って分割配置した例について説明した。本実施の形態３においては、外周側の側壁部を周方向で切れ目無く形成する一方、電極部に空隙部と外部を連通する連通孔を設けた例について説明する。図４は実施の形態３にかかる半導体装置におけるひとつのボンディングパッドが形成された部分の平面図（図４Ａ）と、さらにボンディングワイヤを追加した状態での、平面図に垂直な端面図として、図４ＡのＢ－Ｂ線で切断した端面図（図４Ｂ）である。
　本実施の形態３にかかる半導体装置１は、実施の形態１で説明した側壁部と固定部が、図４Ａと図４Ｂに示すように、それぞれ周方向で連続した円筒状と円環状をなすように構成した。その場合、実施の形態１の図２Ｅと図２Ｆで説明した、第一フォトレジスト８を除去するための抜け部分が第一フォトレジスト８の外周側に存在しなくなるため、電極部４ｊに連通孔４ｐを設けた。
　電極部４ｊは、ｘｙ面内で所定の範囲を網羅するように導電性半導体基板２の主面と平行に広がり、接合領域Ｒ５を包含する大きさを有しているが、中央部分に、接合領域Ｒ５よりも小さな径の連通孔４ｐが形成されている。
　このように構成することで、電極部４ｊは、側壁部４ｗにより、全周にわたって支えられることになる。そのため、実施の形態１で示した間欠的に保持する構成よりも、電極部４ｊの撓みを抑えて厚み方向への変形を確実に抑制し、電極部４ｊと絶縁膜３の間に形成される空隙部４ｇの形状を保持できる。とくに、側壁部４ｗは円筒状なので、構造的にｘｙ面におけるどの方向に対しても、変形を抑制する効果が高い。そして、空隙部４ｇは、実施の形態１と同様の領域をカバーするので、同等の寄生容量の低減効果を発揮できる。
　なお、連通孔４ｐについては、必ずしも中央部、あるいは接合領域Ｒ５内に入っている必要はなく、犠牲層（第一フォトレジスト８）を除去できるのであれば、電極部４ｊのどの位置に形成してもよい。あるいは、電極部４ｊの支持を低下させない程度で、側壁部４ｗの一部に形成するようにしてもよい。
　一方、本例のように、連通孔４ｐを接合領域Ｒ５内の、ボンディングによって塞がる位置に形成した場合、ボンディング後の空隙部４ｇは密閉空間となる。この場合、例えば、半導体装置１の主面が樹脂により封止される場合においても、空隙部４ｇに封止樹脂が侵入することがなく、誘電率の増大による寄生容量の低減効果を損なうことはない。
　また、上記各実施の形態では、導電性半導体基板２としてｎ型ＩｎＰ基板、絶縁膜３としてＳｉＯ２、ボンディングパッド４を構成する給電層４１には、Ｔｉ／Ａｕの積層構造、メッキ層４２は、Ａｕを用いた例を示したが、これに限ることはない。さらには、ボンディングパッド４を積層構造で形成した例を示したが、これに限ることはなく、ワイヤボンディングによって、半導体回路を構成する素子と外部回路とを電気接続できればよい。その際、接合領域Ｒ５の中央部を挟む、あるいは接合領域Ｒ５の中央部を囲む側壁部４ｗによって、電極部４ｊと、絶縁膜３との間に空隙部４ｇが形成されればよい。
　さらに、本願は、様々な例示的な実施の形態及び実施例が記載されているが、１つ、または複数の実施の形態に記載された様々な特徴、態様、及び機能は特定の実施の形態の適用に限られるのではなく、単独で、または様々な組み合わせで実施の形態に適用可能である。従って、例示されていない無数の変形例が、本願明細書に開示される技術の範囲内において想定される。例えば、少なくとも１つの構成要素を変形する場合、追加する場合または省略する場合、さらには、少なくとも１つの構成要素を抽出し、他の実施の形態の構成要素と組み合わせる場合が含まれるものとする。
　以上のように、各実施の形態にかかる半導体装置１によれば、半導体回路が形成された導電性半導体基板２と、導電性半導体基板２の主面に堆積された絶縁膜３と、絶縁膜３に固定された固定部４ｓ（あるいは固定部４ｓｏ）と、固定部４ｓから立ち上がる側壁部４ｗ（あるいは側壁部４ｗｏ）と、側壁部４ｗに連なり、主面に対して平行に配置された電極部４ｊと、を有するボンディングパッド４と、を備え、電極部４ｊは、絶縁膜３との間に空隙部４ｇを形成し、かつ、側壁部４ｗに連なる部分が、ボンディングワイヤ５との接合領域Ｒ５の中央部を挟む、および中央部を囲む、の少なくともいずれかの位置関係にあるように構成したので、空隙部４ｇの間隔Ｄｇを精度よく制御でき、ボンディングの際にも空隙部４ｇの変形を抑制できるので、寄生容量を安定して低減することができる。
　さらには、ボンディングパッド４は、電極部４ｊの接合領域Ｒ５の内側に、開口部４ｊａが形成されるとともに、主面に平行な方向（ｘｙ面方向）における開口部４ｊａに対応する部分で絶縁膜３に固定された第二固定部（固定部４ｓｉ）と、第二固定部（固定部４ｓｉ）から立ち上がる筒状の第二側壁部（側壁部４ｗｉ）と、を有し、開口部４ｊａの内周部分が第二側壁部（側壁部４ｗｉ）に連なっているように構成すれば、筒状の第二側壁部（側壁部４ｗｉ）が内周側から電極部４ｊを支えるので、ボンディングの際の空隙部４ｇの変形をさらに強固に抑制できる。
　あるいは、側壁部４ｗ（あるいは側壁部４ｗｏ）は、電極部４ｊと全周にわたって連なっており、電極部４ｊおよび側壁部４ｗの少なくともいずれかに、空隙部４ｇに連通する連通孔４ｐが形成されているように構成すれば、全周にわたって、側壁部４ｗが電極部４ｊを支えるので、どのような方向から力を加えても、ボンディングの際の空隙部４ｇの変形を抑制できるので、寄生容量を安定して低減することができる。
　その際、連通孔４ｐは、ボンディングワイヤ５の接合により塞がれる位置に形成されていれば、空隙部４ｇが密閉空間となり、樹脂による封止が行われた場合でも、空隙部４ｇに樹脂が侵入することなく、寄生容量を確実に低減できる。
　また、ボンディングパッド４は、絶縁膜３への対向面の側に形成された堆積層（給電層４１）と、給電層４１に対して、対向面の反対側に形成されたメッキ層４２との積層構造で構成すれば、容易に精度よく、空隙部４ｇを有するボンディングパッドを形成することができる。また、積層構造を構成する層のうち、少なくとも１層をメッキ層としたので、側壁部４ｗ部分も、固定部４ｓ部分、電極部４ｊ部分と同等の厚みと密度を有することで強度が高くなり、耐変形性も向上する。
　１：半導体装置、　２：導電性半導体基板、　３：絶縁膜、　４：ボンディングパッド、　４ｇ：空隙部、　４ｊ：電極部、　４ｊａ：開口部、　４ｐ：連通孔、　４ｓ：固定部、　４ｓｉ：（第二）固定部、　４ｓｏ：固定部、　４ｗ：側壁部、　４ｗｉ：（第二）側壁部、　４ｗｏ：側壁部、　５：ボンディングワイヤ、　８：第一フォトレジスト、　９：第二フォトレジスト、　４１：給電層（堆積層）、　４２：メッキ層、　Ｄｇ：間隔。

Claims (5)

  1. 　半導体回路が形成された導電性半導体基板と、
    　前記導電性半導体基板の主面に堆積された絶縁膜と、
    　前記絶縁膜に固定された固定部と、前記固定部から立ち上がる側壁部と、前記側壁部に連なり、前記主面に対して平行に配置された電極部と、を有するボンディングパッドと、を備え、
    　前記電極部は、
    　前記絶縁膜との間に空隙部を形成し、かつ、前記側壁部に連なる部分が、ボンディングワイヤとの接合領域の中央部を挟む、および前記中央部を囲む、の少なくともいずれかの位置関係にあることを特徴とする半導体装置。
  2. 　前記ボンディングパッドは、
    　前記電極部の前記接合領域の内側に、開口部が形成されるとともに、
    　前記主面に平行な方向における前記開口部に対応する部分で前記絶縁膜に固定された第二固定部と、前記第二固定部から立ち上がる筒状の第二側壁部と、を有し、
    　前記開口部の内周部分が前記第二側壁部に連なっていることを特徴とする請求項１に記載の半導体装置。
  3. 　前記側壁部は、前記電極部と全周にわたって連なっており、
    　前記電極部および前記側壁部の少なくともいずれかに、前記空隙部に連通する連通孔が形成されていることを特徴とする請求項１または２に記載の半導体装置。
  4. 　前記連通孔は、前記ボンディングワイヤの接合により塞がれる位置に形成されていることを特徴とする請求項３に記載の半導体装置。
  5. 　前記ボンディングパッドは、前記絶縁膜への対向面の側に形成された堆積層と、前記堆積層に対して、前記対向面の反対側に形成されたメッキ層との積層構造で構成していることを特徴とする請求項１から４のいずれか１項に記載の半導体装置。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0779011A (ja) * 1993-09-09 1995-03-20 Mitsubishi Electric Corp 半導体受光素子
US20090020878A1 (en) * 2007-01-25 2009-01-22 Samsung Electronics Co., Ltd. Semiconductor packages and methods of fabricating the same
JP2010225654A (ja) * 2009-03-19 2010-10-07 Toyota Central R&D Labs Inc 半導体装置
JP2012142498A (ja) * 2011-01-05 2012-07-26 Mitsubishi Electric Corp 配線パターン

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61116848A (ja) 1984-07-11 1986-06-04 Hitachi Ltd 半導体装置およびその製造方法
JPH06310612A (ja) * 1993-04-27 1994-11-04 Hitachi Ltd 半導体集積回路の配線構造及びその製造方法
JP3248818B2 (ja) * 1994-09-20 2002-01-21 シャープ株式会社 半導体素子の電極パッドおよびその製造方法
JP4486103B2 (ja) * 2007-03-19 2010-06-23 Ｏｋｉセミコンダクタ株式会社 加速度センサ、及び加速度センサの製造方法
US7732937B2 (en) * 2008-03-04 2010-06-08 Infineon Technologies Ag Semiconductor package with mold lock vent
JP5195619B2 (ja) 2009-04-28 2013-05-08 株式会社豊田中央研究所 半導体基板
JP5821429B2 (ja) * 2011-09-01 2015-11-24 三菱電機株式会社 半導体装置及びその製造方法
JP5926988B2 (ja) * 2012-03-08 2016-05-25 ルネサスエレクトロニクス株式会社 半導体装置
US8836133B2 (en) * 2012-10-12 2014-09-16 Freescale Semiconductor, Inc. Chip-level humidity protection
JP2017224753A (ja) * 2016-06-16 2017-12-21 セイコーエプソン株式会社 半導体装置及びその製造方法
US10297561B1 (en) * 2017-12-22 2019-05-21 Micron Technology, Inc. Interconnect structures for preventing solder bridging, and associated systems and methods
US11387155B2 (en) * 2019-12-12 2022-07-12 Texas Instruments Incorporated IC having a metal ring thereon for stress reduction
CN115188733A (zh) * 2021-04-07 2022-10-14 川奇光电科技（扬州）有限公司 显示装置及其制造方法
US20230005881A1 (en) * 2021-06-30 2023-01-05 Texas Instruments Incorporated Package for stress sensitive component and semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0779011A (ja) * 1993-09-09 1995-03-20 Mitsubishi Electric Corp 半導体受光素子
US20090020878A1 (en) * 2007-01-25 2009-01-22 Samsung Electronics Co., Ltd. Semiconductor packages and methods of fabricating the same
JP2010225654A (ja) * 2009-03-19 2010-10-07 Toyota Central R&D Labs Inc 半導体装置
JP2012142498A (ja) * 2011-01-05 2012-07-26 Mitsubishi Electric Corp 配線パターン

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