WO2020151257A1 - 一种显示基板、拼接屏及其制作方法 - Google Patents

一种显示基板、拼接屏及其制作方法 Download PDF

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Publication number
WO2020151257A1
WO2020151257A1 PCT/CN2019/110005 CN2019110005W WO2020151257A1 WO 2020151257 A1 WO2020151257 A1 WO 2020151257A1 CN 2019110005 W CN2019110005 W CN 2019110005W WO 2020151257 A1 WO2020151257 A1 WO 2020151257A1
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Prior art keywords
electrode
data line
electroplating
display
substrate
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PCT/CN2019/110005
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English (en)
French (fr)
Inventor
刘英伟
梁爽
梁志伟
狄沐昕
王珂
曹占锋
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to JP2020571439A priority Critical patent/JP7422688B2/ja
Priority to US16/650,690 priority patent/US11488987B2/en
Priority to KR1020207029790A priority patent/KR102361329B1/ko
Priority to EP19911581.7A priority patent/EP3916785A4/en
Publication of WO2020151257A1 publication Critical patent/WO2020151257A1/zh

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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
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    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
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    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate

Definitions

  • the present disclosure relates to the technical field of display devices, in particular to a display substrate, a splicing screen and a manufacturing method thereof.
  • the display substrate of the flexible display substrate includes a display area and a frame area.
  • the frame area is provided with fanout wires and binding electrodes that are electrically connected to the gate lines 01 and data lines 02 of the display area in a one-to-one correspondence.
  • the binding electrode is electrically connected with the flexible circuit board 03 to realize the transmission of the scanning signal and the data signal.
  • the production of large-area flexible splicing screens requires the splicing of flexible display substrates with narrow borders, and the fanout wiring and binding electrodes in the frame area are not conducive to the production of large-area splicing screens.
  • the present disclosure provides a display substrate, including:
  • a plurality of signal lines, and the plurality of signal lines are located on one side of the flexible substrate;
  • a plurality of electroplating electrodes are located on the side of the signal line facing the flexible substrate, and the orthographic projection of each electroplating electrode on the flexible substrate and a signal line on the flexible substrate Part of the orthographic projection of the substrate overlaps, and is electrically connected to the signal line at the overlapped position;
  • a plurality of bonding electrodes the bonding electrode is located on the side of the flexible substrate away from the signal line, and the orthographic projection of the bonding electrode on the flexible substrate is in the same position as the first through hole
  • the orthographic projections of the flexible substrate overlap, and each of the binding electrodes is electrically connected to the corresponding electroplating electrode through the conductive material in the corresponding first through hole.
  • the signal line includes: multiple gate lines;
  • the electroplating electrode includes a plurality of gate line electroplating electrodes, the gate line electroplating electrode corresponds to the gate line one-to-one, and the gate line electroplating electrode corresponds to the end of the corresponding gate line.
  • the gate line electroplating electrodes are sequentially arranged in a first direction, and the first direction is parallel to the surface where the gate line is located and perpendicular to the extending direction of the gate line.
  • the display substrate further includes: a first gate insulating layer located between the gate line and a layer where the gate line plating electrode is located;
  • the gate line plating electrode is electrically connected to the gate line through a second through hole penetrating the first gate insulating layer.
  • the signal line further includes: a plurality of data lines located on a side of the gate line away from the flexible substrate;
  • the electroplating electrode further includes: a plurality of data line electroplating electrodes, the data line electroplating electrode corresponds to the data line one-to-one, and the data line electroplating electrode corresponds to the end of the corresponding data line.
  • the data line electroplating electrodes are sequentially arranged in a second direction, and the second direction is parallel to the surface where the data line is located and perpendicular to the extending direction of the data line.
  • the gate line plating electrode and the data line plating electrode are located on the same layer.
  • the display substrate further includes: a data line connection electrode located between the layer where the data line is located and the layer where the plating electrode of the data line is located;
  • the data line and the data line electroplating electrode are electrically connected through the data line connection electrode.
  • the data line connection electrode includes: a first data line connection electrode, and a second data line connection electrode located on a side of the first data line connection electrode facing the data line.
  • the first data line connection electrode and the gate line are located on the same layer.
  • a second gate insulating layer is further provided between the second data line connection electrode and the first data line connection electrode;
  • the second data line connection electrode is electrically connected to the first data line connection electrode through a third through hole penetrating the second gate insulating layer;
  • the first data line connection electrode is electrically connected to the data line electroplating electrode through a fourth through hole penetrating the first gate insulating layer.
  • the display substrate further includes: an interlayer dielectric layer located between the second data line connection electrode and the data line;
  • the data line is electrically connected to the second data line connection electrode through a fifth through hole penetrating the interlayer dielectric layer.
  • the display substrate further includes: a common electrode located on a side of the data line away from the gate line;
  • the electroplating electrode further includes: a common electroplating electrode electrically connected to the common electrode, and the common electroplating electrode and the gate line electroplating electrode are located on the same layer.
  • the display substrate further includes: a first common connection electrode on the same layer as the data line, and a second common connection electrode on the same layer as the second data line connection electrode, A third common connection electrode located on the same layer as the first data line connection electrode;
  • the common electrode is electrically connected to the common electroplating electrode through the first common connection electrode, the second common connection electrode, and the third common connection electrode in sequence.
  • the display substrate further includes: a third data line connection electrode located on the same layer as the common electrode, and a third data line connection electrode is also provided between the layer where the common electrode is located and the layer where the data line is located.
  • the display substrate further includes a thin film transistor including a source electrode and a drain electrode in the same layer as the data line, the source electrode is electrically connected to the data line, and the drain electrode passes through the flat
  • the sixth through hole of the layer is electrically connected to the third data line connection electrode.
  • the display substrate further includes: a plurality of boss structures located on a side of the common electrode facing away from the flat layer, and a side of the boss structure facing away from the common electrode is further provided There are multiple groups of binding pad groups corresponding to the boss structure one-to-one, and each of the binding pad groups includes: a first binding pad and a second binding pad that are insulated from each other;
  • the first binding pad covers a part of the surface of the boss structure facing away from the common electrode and a part of the third data line connection electrode;
  • the second binding pad covers a part of the surface of the boss structure facing away from the common electrode and a part of the common electrode.
  • the display substrate further includes a black matrix located on the side of the binding pad group away from the flat layer, and the black matrix covers other areas except the binding pad group .
  • a buffer layer is formed between the flexible substrate and the plurality of electroplating electrodes, and the first through hole also penetrates the buffer layer.
  • the material of the binding electrode is metal or indium tin oxide.
  • the display substrate further includes a plurality of micro light emitting diodes, and the micro light emitting diodes include a first electrode and a second electrode;
  • the first electrode of the micro light emitting diode is bound with the first binding pad, and the second electrode is bound with the second binding pad.
  • the embodiment of the present disclosure also provides a splicing screen, which includes at least two of the flexible display substrates provided in the embodiment of the present disclosure.
  • the embodiment of the present disclosure also provides a method for making the splicing screen provided in the embodiment of the present disclosure, which includes:
  • the display mother board including a flexible substrate having a plurality of first through holes
  • the multiple display substrates are spliced.
  • the providing a display mother board with multiple display areas includes:
  • the manufacturing method further includes: removing the second rigid substrate.
  • the forming a plurality of signal lines on a side of the electroplating electrode away from the flexible substrate includes:
  • a plurality of gate lines are formed on the side of the electroplating electrode away from the flexible substrate, and at the same time, a first short-circuit electrode extending along perpendicular to the gate line is formed in the gap between adjacent display areas, The gate lines of each of the display areas are electrically connected to the first short-circuit electrode;
  • a plurality of data lines are formed on the side of the gate line away from the flexible substrate, and at the same time, a second short-circuit electrode extending perpendicular to the data line is formed in the gap between adjacent display areas, The data lines of each display area are electrically connected to the second short-circuit electrode.
  • the forming a conductive material in the first through holes of each of the display areas includes:
  • a conductive material is formed in the first through hole by the electroplating device.
  • the manufacturing method further includes:
  • binding electrodes corresponding to the first through holes are formed one-to-one, and the binding electrodes pass through the conductive electrodes in the corresponding first through holes.
  • the material is electrically connected to the corresponding electroplating electrode.
  • a plurality of electroplating electrodes and signal lines for transmitting display signals are formed on the flexible substrate, the signal lines are electrically connected to the electroplating electrodes, and the flexible substrate is connected to each
  • a first through hole is formed in the area opposite to the plating electrode, the first through hole is filled with conductive material, and the side of the flexible substrate away from the plurality of plating electrodes is formed with binding electrodes corresponding to the first through holes one-to-one.
  • the bonding electrode is electrically connected to its corresponding electroplating electrode through the conductive material in the corresponding first through hole.
  • the above structure can directly lead the signal line to the back of the flexible substrate through the arrangement of the electroplating electrode, the conductive material and the bonding electrode, and The flexible circuit board connection of the external circuit realizes the transmission of the signal line to the display signal. Because the bonding electrode is directly arranged on the side of the flexible substrate away from the signal line layer, and the fan-out wiring on the display substrate is omitted, Realize the design of extremely narrow frame or no frame, and then can realize the production of large-area splicing screen.
  • FIG. 1 is a schematic structural diagram of a display substrate provided in the prior art
  • FIG. 2 is a schematic diagram of a cross-sectional structure of a display substrate provided by an embodiment of the disclosure
  • FIG. 3 is a schematic structural diagram of a display substrate provided by an embodiment of the disclosure.
  • FIG. 4 is a flow chart of a method for manufacturing a splicing screen provided by an embodiment of the disclosure
  • FIG. 5 is a schematic diagram of a method for manufacturing a splicing screen provided by an embodiment of the disclosure
  • 6 to 12 are state diagrams of a display substrate manufacturing process provided by embodiments of the disclosure.
  • the present disclosure provides a display substrate, including:
  • a plurality of signal lines (specifically may include a gate line 301 and a data line 701), and the plurality of signal lines are located on one side of the flexible substrate 1;
  • a plurality of electroplating electrodes 2 are located on the side of the signal line facing the flexible substrate 1, and are electrically connected to the signal lines one by one.
  • a plurality of first through holes correspond to the electroplating electrodes 2 one-to-one, the orthographic projection of the first through holes on the flexible substrate 1 and the orthographic projection of the electroplating electrodes 2 on the flexible substrate 1 overlap, and the first through holes
  • the hole penetrates the flexible substrate 1 and exposes the electroplating electrode 2.
  • the first through hole is filled with conductive material 4.
  • the orthographic projection area of the first through hole on the flexible substrate 1 may be larger than that of the electroplated electrode 2 on the flexible substrate 1.
  • the orthographic projection area that is, the orthographic projection of the first through hole on the flexible substrate 1 completely covers the orthographic projection of the electroplating electrode 2 on the flexible substrate 1;
  • a plurality of bonding electrodes 5, the bonding electrode 5 is located on the side of the flexible substrate 1 facing away from the signal line, and corresponds to the first through hole one-to-one, and the orthographic projection of the bonding electrode 2 on the flexible substrate 1 and the first through hole
  • the orthographic projection of the flexible substrate 1 overlaps, and each binding electrode 5 is electrically connected to the corresponding electroplating electrode 2 through the conductive material 4 in the corresponding first through hole.
  • the binding electrode 2 is on the flexible substrate 1
  • the area of the orthographic projection can be greater than the area of the orthographic projection of the first through hole on the flexible substrate 1, that is, the orthographic projection of the binding electrode 2 on the flexible substrate 1 completely covers the orthographic projection of the first through hole on the flexible substrate 1. .
  • a plurality of electroplating electrodes 2 and signal lines for transmitting display signals are formed on the flexible substrate 1.
  • the signal lines are electrically connected to the electroplating electrodes 2, and the flexible substrate 1 is connected to each electroplating electrode.
  • a first through hole is formed in the opposite area, the first through hole is filled with conductive material 4, and the side of the flexible substrate 1 away from the plurality of electroplating electrodes 2 is formed with binding electrodes 5 corresponding to the first through holes one to one.
  • the binding electrode 5 is electrically connected to its corresponding electroplating electrode 2 through the conductive material 4 in the corresponding first through hole.
  • the above structure can directly lead the signal line to the electroplating electrode 2, the conductive material 4 and the binding electrode 5
  • the side of the flexible substrate away from the signal line is connected to the flexible circuit board of the external circuit to realize the transmission of the signal line to the display signal. Because the bonding electrode 5 is directly arranged on the side of the flexible substrate 1 away from the thin film transistor TFT device layer, and The setting of fan-out wiring on the display substrate is omitted, so that an extremely narrow frame or frameless design can be realized, and a large-area splicing screen can be produced.
  • a buffer layer 6 is further formed between the flexible substrate 1 and the plurality of electroplating electrodes 2, and the first through hole also penetrates the buffer layer 6, that is, the flexible substrate 1 and the buffer layer 6 and A first through hole is formed in the area facing each electroplating electrode, and a conductive material 4 is formed in the first through hole.
  • the arrangement of the buffer layer 6 can enhance the bending ability of the flexible display substrate and improve the water and oxygen barrier ability of the display substrate. Thermal insulation effect.
  • the material of the binding electrode 5 may be indium tin oxide, which has excellent photoelectric properties.
  • the material of the binding electrode 5 is determined according to the actual selection, and there is no limitation here.
  • the binding electrode 5 covers the first through hole, which can not only realize the conductive effect, but also realize the protection of the conductive material in the first through hole.
  • the signal line includes: a plurality of gate lines 301;
  • the electroplating electrode 2 includes: a plurality of gate line plating electrodes 201, the gate line plating electrode 201 corresponds to the gate line 301 one-to-one, and the gate line
  • the electroplating electrode 201 corresponds to the end of the corresponding gate line 301 (as shown in conjunction with FIG.
  • the bonding electrode 5 of the gate line 301 is arranged in a direction perpendicular to the gate line 301, that is, the upper part of the bonding electrode 5 arranged horizontally is
  • the bonding electrode 5 corresponding to the gate line 301 since the plating electrode 2 corresponds to the position of the first through hole, and the first through hole corresponds to the bonding electrode 5, the position of the bonding electrode 5 can also be considered as the plating electrode 2), a plurality of gate line electroplating electrodes 201 are sequentially arranged in a first direction, and the first direction is parallel to the surface of the gate line 301 and perpendicular to the extending direction of the gate line 301.
  • the display substrate further includes: a first gate insulating layer 901 located between the gate line 301 and the layer where the gate line electroplating electrode 201 is located; the gate line electroplating electrode 201 penetrates the first gate The second through hole of the insulating layer 901 is electrically connected to the gate line 301.
  • the signal line further includes: a plurality of data lines 701 located on the side of the gate line 301 away from the flexible substrate 1; the electroplating electrode 2 also includes: a plurality of data line electroplating electrodes 202, data lines
  • the plating electrode 202 corresponds to the data line 701 one-to-one, and the data line plating electrode 202 corresponds to the end of the corresponding data line 701 (as shown in conjunction with FIG. 3, the bonding electrode 5 of the data line 701 is along a direction perpendicular to the data line 701 Arrangement, that is, the bonding electrode 5 arranged vertically at the lower part is the bonding electrode 5 corresponding to the data line 701.
  • the electroplating electrode 2 corresponds to the position of the first through hole
  • the first through hole corresponds to the bonding electrode 5.
  • the location of the binding electrode 5 can also be considered as the location of the electroplating electrode 2)
  • the multiple data line electroplating electrodes 202 are sequentially arranged in the second direction, and the second direction is parallel to the surface of the data line and perpendicular to the data line The extension direction.
  • the gate line electroplating electrode 201 and the data line electroplating electrode 202 are located on the same layer. In the embodiment of the present disclosure, the gate line electroplating electrode 201 and the data line electroplating electrode 202 are located in the same layer, and the gate line electroplating electrode 201 and the data line electroplating electrode 202 can be formed at the same time during production, simplifying the production process.
  • the display substrate further includes: a data line connection electrode located between the layer where the data line 701 is located and the layer where the data line plating electrode 202 is located; the data line 701 and the data line plating electrode 202 pass through the data line
  • the connection electrode is electrically connected.
  • the data line connection electrode includes: a first data line connection electrode 302, and a second data line connection electrode 304 on the side of the first data line connection electrode 302 facing the data line 701.
  • the first data line connection electrode 302 and the gate line 301 may be located on the same layer.
  • the second data line connection electrode 304 may further have a second gate insulating layer 902 between the first data line connection electrode 302; the second data line connection electrode 304 passes through the second gate insulating layer 902
  • the third through hole is electrically connected to the first data line connection electrode 302; the first data line connection electrode 302 is electrically connected to the data line plating electrode 202 through a fourth through hole penetrating the first gate insulating layer 901.
  • the display substrate further includes: an interlayer dielectric layer 11 between the second data line connection electrode 304 and the data line 701; the data line 701 passes through the fifth interlayer dielectric layer 11 The through hole is electrically connected to the second data line connection electrode 304.
  • the display substrate further includes: a common electrode 17 located on the side of the data line 701 away from the gate line 201; the electroplating electrode 2 further includes: a common electroplating electrode 203 electrically connected to the common electrode 17, The common plating electrode 203 and the gate line plating electrode 201 are located on the same layer.
  • the display substrate further includes: a first common connection electrode 704 on the same layer as the data line 701, a second common connection electrode 305 on the same layer as the second data line connection electrode 304, The third common connection electrode 306 on the same layer as the first data line connection electrode 302; the common electrode 17 is electrically connected to the common plating electrode 203 through the first common connection electrode 704, the second common connection electrode 305, and the third common connection electrode 306 in sequence. connection.
  • the electrical connection can be realized by punching.
  • the display substrate further includes: a third data line connection electrode 13 on the same layer as the common electrode 17, and a flat layer is also provided between the layer where the common electrode 17 is located and the layer where the data line 701 is located. 12;
  • the display substrate also includes a thin film transistor, which includes a source 702 and a drain 703 in the same layer as the data line 701, and the source 702 is electrically connected to the data line 701 (the connection is not shown in FIG. 2, but can be in other Electrical connection is made at the position), the drain 703 is electrically connected to the third data line connection electrode 13 through a sixth through hole penetrating the planar layer 12.
  • the display substrate further includes: a plurality of boss structures 14 on the side of the common electrode 17 facing away from the flat layer 12, and the side of the boss structure 14 facing away from the common electrode 17 is also provided with convex
  • the pad 151 covers a part of the surface of the boss structure 14 facing away from the common electrode 17 and a part of the third data line connection electrode 13; the second bonding pad 152 covers a part of the boss structure 14 facing away from the common electrode 17, and The portion of the common electrode 17 is covered.
  • the display substrate further includes a black matrix 10 on the side of the binding pad group 15 facing away from the flat layer 12, and the black matrix 10 covers other areas except the binding pad group 15.
  • the projection of the black matrix 10 on the flexible substrate 1 covers the projection of the first through hole on the flexible substrate 1, and this configuration can avoid light leakage of the display substrate.
  • the signal lines and the electroplating electrodes are electrically connected in a one-to-one correspondence to realize signal transmission.
  • the signal line includes a plurality of gate lines and a plurality of data lines 701 insulated from each other, and the plurality of electroplating electrodes 2 includes gate line electroplating electrically connected to the gate lines 301 in a one-to-one correspondence.
  • the thin film transistor TFT device layer may specifically include, as shown in FIG. 2, an active layer 8, a second gate insulating layer 902, a first gate metal layer, The second gate line insulating layer 902, the second gate metal layer, the interlayer dielectric layer 11, the first source and drain metal layer, the flat layer 12, the protective layer 16, the boss structure 14 and the device for binding to the display device Binding pad group 15.
  • the active layer 8 can be provided in the same layer as the electroplating electrode 2;
  • the first gate metal layer is provided with a gate line 301 and a first data line connection electrode 302, and the gate line 301 is electrically connected to the gate line plating electrode 201;
  • the second gate metal layer is provided with a gate line electrode 303 that forms a capacitance with the first gate metal layer and a second data line connection electrode 304;
  • the first source and drain metal layer is formed with a data line 701 and a source electrode 702.
  • the source electrode 702 is electrically connected to the active layer 8.
  • the data line 701 is connected to the data line through the first data line connection electrode 302 and the second data line connection electrode 304
  • the electroplating electrode 202 is electrically connected to avoid difficulty in bonding due to excessively high film gap;
  • the third data line connection electrode 13 is electrically connected to the source electrode 702.
  • the function of the third data line connection electrode 13 is mainly due to the fact that the third data line is provided when the display device bound to the binding pad group 15 shows a relatively large display current.
  • the connection electrode 13 can reduce the resistance on the data line 701 and reduce the IR voltage drop.
  • the display device may be a Micro LED display device;
  • the function of the protective layer 16 is to protect the third data line connection electrode 13 from damage during the manufacturing process
  • the boss structure 14 facilitates the binding of the binding pad group 15 with the display device.
  • the embodiment of the present disclosure also provides a flexible display substrate, which includes the display substrate as provided in the embodiment of the present disclosure.
  • the flexible display substrate further includes a plurality of micro light emitting diodes, the micro light emitting diodes include a first electrode and a second electrode; the first electrode of the micro light emitting diode is bound to the first binding pad, and the second electrode is Two binding pad binding.
  • the embodiments of the present disclosure also provide a splicing screen, which includes at least two flexible display substrates as provided in the embodiments of the present disclosure.
  • multiple flexible display substrates provided by the embodiments of the present disclosure can be fixed to the same carrier through a fixing member to obtain a large-size splicing screen.
  • the fixing part can be a magnet.
  • the carrier can be provided with magnets of opposite polarity to adsorb the flexible display substrate on the carrier; the fixing part can also be a colloid, that is, a plurality of flexible display substrates are bonded to the carrier. on.
  • the embodiment of the present disclosure also provides a method for making a splicing screen as provided in the embodiment of the present disclosure, as shown in FIG. 4 and FIG. 5, which includes:
  • Step S101 providing a display mother board with a plurality of display areas, the display mother board including a flexible substrate, the flexible substrate having a plurality of first through holes;
  • Step S102 forming conductive materials in the plurality of first through holes
  • Step S103 cutting the display mother board into multiple display substrates along the edge of each of the multiple display areas
  • Step S104 splicing multiple display substrates.
  • two adjacent display areas in the same row in the display motherboard have a first distance
  • two adjacent display areas in the same column have a second distance, so as to be the first short-circuit electrode, the second short-circuit electrode, The gate wiring area and the area provided during cutting.
  • the specific first distance may be 2 mm to 3 mm
  • the second distance may be 2 mm to 3 mm.
  • step S101 providing a display mother board with multiple display areas may include:
  • a flexible substrate, a plurality of electroplating electrodes, and a plurality of signal lines are sequentially formed on one side of the first rigid substrate.
  • the first rigid substrate may be a first glass plate.
  • the signal lines may include gate lines and data lines; specifically, it may be One side of a rigid substrate is sequentially formed: flexible substrate 1, buffer layer 6, electroplating electrode 2, first insulating layer 901, gate layer (specifically, it may include gate 30, gate line 301, first data line connection electrode 302, The third common connection electrode 306), the second insulating layer 902, the second data line connection electrode 304 (the second common connection electrode 305 and the gate line electrode 303 can also be formed at the same time), the interlayer dielectric layer 11, the source and drain layer ( Specifically, it may include a source electrode 702, a data line 701, a drain electrode 703, a first common connection electrode 704), a common electrode 17 (at the same time a third data line connection electrode 13 may also be formed), a protective layer 16, a boss structure 14, a binding Fixed liner
  • a second rigid substrate is attached to the side of the signal line away from the first rigid substrate, and the second rigid substrate may be a second glass plate;
  • step S103 that is, before cutting the display motherboard into a plurality of display substrates along the edge of each of the plurality of display areas, the manufacturing method of the embodiment of the present disclosure further includes: removing the second rigid substrate.
  • a plurality of signal lines are formed on the side of the electroplating electrode away from the flexible substrate, including:
  • a plurality of gate lines 301 are formed on the side of the electroplating electrode away from the flexible substrate.
  • a first short-circuit electrode 310 extending perpendicular to the gate line 301 is formed in the gap between adjacent display areas.
  • the wires 301 are electrically connected to the first short-circuit electrode 310;
  • a plurality of data lines 701 are formed on the side of the gate line 301 away from the flexible substrate, and at the same time, a second short-circuit electrode 710 extending perpendicular to the data line 701 is formed in the gap between adjacent display areas.
  • the wires 701 are all electrically connected to the second short-circuit electrode 710.
  • forming a conductive material in the first through hole of each display area includes:
  • a conductive material is formed in the first through hole by an electroplating device.
  • the manufacturing method further includes:
  • a binding electrode corresponding to the first through hole is formed on the side of the flexible substrate away from the plating electrode, and the binding electrode is electrically connected to the corresponding plating electrode through the conductive material in the corresponding first through hole.
  • a plurality of electroplating electrodes and thin film transistor TFT device layers are formed on the flexible substrate.
  • the thin film transistor TFT device layer includes signal lines, which are electrically connected to the electroplating electrodes, and then are connected to each A first through hole is formed in the area opposite to the electroplating electrode, a conductive material is electroplated in the first through hole, and finally a binding electrode corresponding to the first through hole is formed on the side of the flexible substrate away from the plurality of electroplating electrodes.
  • the binding electrode is electrically connected to its corresponding electroplating electrode through the conductive material in the corresponding first through hole.
  • This method can directly lead the thin film transistor TFT device layer to the flexible substrate through the arrangement of the electroplating electrode, the conductive material and the binding electrode
  • the side away from the thin film transistor TFT device layer is connected to the flexible circuit board of the external circuit to realize the transmission of the display signal from the thin film transistor TFT device layer.
  • the binding electrode is directly arranged on the side of the flexible substrate away from the thin film transistor TFT device layer, Moreover, the setting of fan-out wiring on the display substrate is omitted, so that a very narrow frame or a frameless design can be realized, and a large-area splicing screen can be produced.
  • a buffer layer is also formed between the flexible substrate and a plurality of electroplating electrodes. After perforating on the flexible substrate, the buffer layer is etched by a dry etching process, thereby forming an electrode opposite to each electroplating electrode. The first through hole penetrates the buffer layer and the flexible substrate.
  • the specific manufacturing steps of the above-mentioned display substrate may include (the following is only the manufacturing process of a display substrate on the motherboard for illustration):
  • S505 Use laser drilling technology to punch holes on the flexible substrate in the area opposite to the electroplating electrode, and use a dry etching process to etch the buffer layer and the area opposite to the electroplated electrode 2 to form a hole through the flexible substrate 1 and the buffer layer 6.
  • the first through hole as shown in Figure 9 and Figure 10;
  • S506 Form a conductive material 4 in the first through hole by electroplating, as shown in FIG. 11;
  • S508 Remove the second glass B and the adhesive C, and cut off the excess area of the display substrate, as shown in FIGS. 2 and 3.
  • manufacturing the thin film transistor TFT device layer includes manufacturing signal lines that are electrically connected to the electroplating electrodes in a one-to-one correspondence.
  • the signal lines may include gate lines and data lines.
  • manufacturing the thin film transistor TFT device layer may include manufacturing the active layer 8, the first gate insulating layer 901, and the first gate metal layer formed sequentially on the side of the base substrate 1 as shown in FIG. Layer 31, second gate insulating layer 902, second gate metal layer 32, interlayer dielectric layer 11, first source and drain metal layer 7, flat layer 12, third data line connection electrode 13, protective layer 16, Boss structure 14, binding pad 15.
  • the active layer 8 in the thin film transistor TFT device layer can be arranged in the same layer as the electroplating electrode 2; when the active layer and the electroplating electrode are arranged in the same layer, a plurality of electroplating electrodes 2 can be made in the manufacturing process of the display substrate, and then The active layer 8 is fabricated on the same layer, or the active layer 8 in the thin film transistor TFT device layer can be fabricated first, and then a plurality of electroplating electrodes 2 can be fabricated on the same layer;
  • the first gate metal layer 31 is provided with a gate line 301 and a first data line connection electrode 302, and the gate line 301 is electrically connected to the gate line plating electrode 201;
  • the second gate metal layer 32 is provided with a gate line electrode 303 that forms a capacitance with the first gate metal layer 31 and a second data line connection electrode 304;
  • the first source-drain metal layer 7 is formed with a data line 701 and a source electrode 702.
  • the source electrode 702 is electrically connected to the active layer 8.
  • the data line 701 is connected to the data line through the first data line connection electrode 302 and the second data line connection electrode 304.
  • Wire plating electrode 202 is electrically connected;
  • the third data line connection electrode 13 is electrically connected to the source electrode 702.
  • the signal lines are directly connected to the first during the process of making the thin film transistor TFT device layer.
  • the signal line may be broken due to the different expansion coefficients of the flexible substrate and the metal material.
  • the electroplating electrode corresponding to the signal line is made by electroplating on the flexible substrate before the thin film transistor TFT device layer is fabricated.
  • the first through hole, the conductive material is formed in the first through hole through the electroplating process, to ensure that the signal on the thin film transistor TFT device layer can be transmitted to the side of the flexible substrate away from the thin film transistor TFT device layer, to avoid the signal line disconnection, and electroplating
  • the electrode is connected with the conductive material formed by electroplating to make the signal transmission more accurate.
  • the electroplating material 4 in the first through hole may be conductive metal such as copper, and the material of the flexible substrate may be polyimide or the like.

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Abstract

一种显示基板、拼接屏及其制作方法，涉及显示设备技术领域。该显示基板包括柔性衬底（1）；多条信号线，多条所述信号线位于所述柔性衬底（1）的一侧；多个电镀电极（2），所述电镀电极（2）位于所述信号线的面向所述柔性衬底（1）的一面，与所述信号线一一对应电连接；多个第一通孔，所述第一通孔与所述电镀电极（2）一一对应，且所述第一通孔贯穿所述柔性衬底（1）并暴露所述电镀电极（2），所述第一通孔内填充有导电材料（4）；多个绑定电极（5），所述绑定电极（5）位于所述柔性衬底（1）的背离所述信号线的一面，与所述第一通孔一一对应，每个所述绑定电极（5）通过对应的所述第一通孔内的所述导电材料（4）与对应的所述电镀电极（2）电连接。

Description

一种显示基板、拼接屏及其制作方法
相关申请的交叉引用
本申请要求在2019年01月23日提交中国专利局、申请号为201910062179.6、申请名称为“一种阵列基板及其制作方法、柔性显示面板、拼接屏”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示设备技术领域，特别涉及一种显示基板、拼接屏及其制作方法。
背景技术
目前，柔性显示基板的显示基板包括显示区以及边框区，如图1所示，边框区设置有与显示区的栅线01以及数据线02一一对应电连接的扇出走线Fanout以及绑定电极，绑定电极与柔性电路板03电连接实现扫描信号以及数据信号的传输。而制作大面积柔性拼接屏需要窄边框的柔性显示基板拼接，边框区的扇出走线Fanout以及绑定电极不利于大面积拼接屏的制作。
基于此，如何实现更窄边框或者无边框的柔性显示产品，是本领域技术人员亟待解决的技术问题。
发明内容
本公开提供了一种显示基板，包括：
多条信号线，多条所述信号线位于所述柔性衬底的一侧；
多个电镀电极，所述电镀电极位于所述信号线的面向所述柔性衬底的一面，且每一所述电镀电极在所述柔性衬底的正投影与一所述信号线在所述柔性衬底的部分正投影交叠，并在交叠位置处与所述信号线电连接；
多个第一通孔，所述第一通孔在所述柔性衬底的正投影与所述电镀电极 在所述柔性衬底的正投影交叠，且所述第一通孔贯穿所述柔性衬底并暴露所述电镀电极，所述第一通孔内填充有导电材料；
多个绑定电极，所述绑定电极位于所述柔性衬底的背离所述信号线的一面，且所述绑定电极在所述柔性衬底的正投影与所述第一通孔在所述柔性衬底的正投影交叠，每个所述绑定电极通过对应的所述第一通孔内的所述导电材料与对应的所述电镀电极电连接。
在一种可能的实施方式中，所述信号线包括：多条栅线；
所述电镀电极包括：多个栅线电镀电极，所述栅线电镀电极与所述栅线一一对应，且所述栅线电镀电极与相应的所述栅线的端部对应，多个所述栅线电镀电极在第一方向依次排列，所述第一方向为平行于所述栅线所在面且垂直于所述栅线的延伸方向。
在一种可能的实施方式中，所述显示基板还包括：位于所述栅线与所述栅线电镀电极所在层之间的第一栅极绝缘层；
所述栅线电镀电极通过贯穿所述第一栅极绝缘层的第二通孔与所述栅线电连接。
在一种可能的实施方式中，所述信号线还包括：位于所述栅线的背离所述柔性衬底一面的多条数据线；
所述电镀电极还包括：多个数据线电镀电极，所述数据线电镀电极与所述数据线一一对应，且所述数据线电镀电极与相应的所述数据线的端部对应，多个所述数据线电镀电极在第二方向依次排列，所述第二方向为平行于所述数据线所在面且垂直于所述数据线的延伸方向。
在一种可能的实施方式中，所述栅线电镀电极与所述数据线电镀电极位于同一层。
在一种可能的实施方式中，所述显示基板还包括：位于所述数据线所在层与所述数据线电镀电极所在层之间的数据线连接电极；
所述数据线与所述数据线电镀电极通过所述数据线连接电极电连接。
在一种可能的实施方式中，所述数据线连接电极包括：第一数据线连接 电极，以及位于所述第一数据线连接电极的面向所述数据线一面的第二数据线连接电极。
在一种可能的实施方式中，所述第一数据线连接电极与所述栅线位于同一层。
在一种可能的实施方式中，所述第二数据线连接电极与所述第一数据线连接电极之间还具有第二栅极绝缘层；
所述第二数据线连接电极通过贯穿所述第二栅极绝缘层的第三通孔与所述第一数据线连接电极电连接；
所述第一数据线连接电极通过贯穿所述第一栅极绝缘层的第四通孔与所述数据线电镀电极电连接。
在一种可能的实施方式中，所述显示基板还包括：位于所述第二数据线连接电极与所述数据线之间的层间介质层；
所述数据线通过贯穿所述层间介质层的第五通孔与所述第二数据线连接电极电连接。
在一种可能的实施方式中，所述显示基板还包括：位于所述数据线的背离所述栅线一面的公共电极；
所述电镀电极还包括：与所述公共电极电连接的一公共电镀电极，所述公共电镀电极与所述栅线电镀电极位于同一层。
在一种可能的实施方式中，所述显示基板还包括：与所述数据线位于同一层的第一公共连接电极，与所述第二数据线连接电极位于同一层的第二公共连接电极，与所述第一数据线连接电极位于同一层的第三公共连接电极；
所述公共电极依次通过所述第一公共连接电极、第二公共连接电极、第三公共连接电极与所述公共电镀电极电连接。
在一种可能的实施方式中，所述显示基板还包括：与所述公共电极位于同一层的第三数据线连接电极，所述公共电极所在层与所述数据线所在层之间还设置有平坦层；
所述显示基板还包括：薄膜晶体管，所述薄膜晶体管包括与所述数据线 同层的源极和漏极，所述源极与所述数据线电连接，所述漏极通过贯穿所述平坦层的第六通孔与所述第三数据线连接电极电连接。
在一种可能的实施方式中，所述显示基板还包括：位于所述公共电极的背离所述平坦层一面的多个凸台结构，所述凸台结构的背离所述公共电极的一面还设置有与所述凸台结构一一对应的多组绑定衬垫组，每一所述绑定衬垫组包括：相互绝缘的第一绑定衬垫和第二绑定衬垫；
所述第一绑定衬垫覆盖所述凸台结构的背离所述公共电极的部分表面，以及覆盖所述第三数据线连接电极的部分；
所述第二绑定衬垫覆盖所述凸台结构的背离所述公共电极的部分表面，以及覆盖所述公共电极的部分。
在一种可能的实施方式中，所述显示基板还包括位于所述绑定衬垫组的背离所述平坦层一面的黑矩阵，所述黑矩阵覆盖所述绑定衬垫组以外的其它区域。
在一种可能的实施方式中，所述柔性衬底与所述多个电镀电极之间形成有缓冲层，所述第一通孔还贯穿所述缓冲层。
在一种可能的实施方式中，所述绑定电极的材料为金属或铟锡氧化物。
在一种可能的实施方式中，所述显示基板还包括多个微发光二极管，所述微发光二极管包括第一电极和第二电极；
所述微发光二极管的所述第一电极与所述第一绑定衬垫绑定，所述第二电极与所述第二绑定衬垫绑定。
本公开实施例还提供一种拼接屏，其中，包括至少两个如本公开实施例提供的所述柔性显示基板。
本公开实施例还提供一种制作如本公开实施例提供的所述拼接屏的方法，其中，包括：
提供具有多个显示区的显示母板，所述显示母板包括柔性衬底，所述柔性衬底具有多个第一通孔；
在多个所述第一通孔内形成导电材料；
沿所述多个显示区的每个的边缘将所述显示母板切割为多个显示基板；
将多个所述显示基板进行拼接。
在一种可能的实施方式中，所述提供具有多个显示区的显示母板，包括：
在第一刚性基板的一面依次形成柔性衬底、多个电镀电极、多条信号线；
在所述信号线的背离所述第一刚性基板的一面贴附第二刚性基板；
去除所述第一刚性基板，暴露所述柔性衬底；
通过激光打孔工艺在所述柔性衬底的与所述电镀电极一一对应的位置处形成第一通孔；
在沿所述多个显示区的每个的边缘将所述显示母板切割为多个显示基板之前，所述制作方法还包括：去除所述第二刚性基板。
在一种可能的实施方式中，所述在所述电镀电极的背离所述柔性衬底的一侧形成多条信号线，包括：
在所述电镀电极的背离所述柔性衬底的一侧形成多条栅线，同时，在相邻所述显示区之间的间隙处形成沿垂直于所述栅线延伸的第一短路电极，各所述显示区的所述栅线均与所述第一短路电极电连接；
在所述栅线的背离所述柔性衬底的一侧形成多条数据线，同时，在相邻所述显示区之间的间隙处形成沿垂直于所述数据线延伸的第二短路电极，各所述显示区的所述数据线均与所述第二短路电极电连接。
在一种可能的实施方式中，所述在各个所述显示区的所述第一通孔内形成导电材料，包括：
将所述第一短路电极和所述第二短路电极与电镀设备电连接；
通过所述电镀设备在所述第一通孔内形成导电材料。
在一种可能的实施方式中，在通过所述电镀设备在所述第一通孔内形成导电材料之后，所述制作方法还包括：
在所述柔性衬底的背离所述电镀电极的一侧形成与所述第一通孔一一对应的绑定电极，所述绑定电极通过对应的所述第一通孔内的所述导电材料与对应的所述电镀电极电连接。
本公开有益效果如下：本公开实施例提供的显示基板中，柔性衬底上形成有多个电镀电极以及用于传输显示信号的信号线，信号线与电镀电极电连接，柔性衬底与每个电镀电极相对的区域形成有第一通孔，第一通孔内填充有导电材料，柔性衬底背离多个电镀电极的一侧形成有与所述第一通孔一一对应的绑定电极，绑定电极通过其对应的第一通孔内的导电材料与其对应的电镀电极电连接，上述结构可以通过电镀电极、导电材料以及绑定电极的设置直接将信号线引到柔性基板的背面，与外部电路的柔性电路板连接，实现信号线对显示信号的传输，由于绑定电极直接设置于柔性衬底背离信号线层的一侧，并且省去了显示基板上扇出走线的设置，从而可以实现极窄边框或者无边框的设计，进而可以实现大面积的拼接屏的制作。
附图说明
图1为现有技术中提供的一种显示基板的结构示意图；
图2为本公开实施例提供的一种显示基板的截面结构示意图；
图3为本公开实施例提供的一种显示基板的结构示意图；
图4为本公开实施例提供的一种拼接屏的制作方法流程图；
图5为本公开实施例提供的一种拼接屏的制作方法示意图；
图6-图12为本公开实施例提供的一种显示基板制作过程状态图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
请参考图2，本公开提供一种显示基板，包括：
柔性衬底1；
多条信号线(具体可以包括栅线301、数据线701)，多条信号线位于柔 性衬底1的一侧；
多个电镀电极2，电镀电极2位于信号线的面向柔性衬底1的一面，与信号线一一对应电连接，每一电镀电极2在柔性衬底1的正投影与一信号线在柔性衬底1的部分正投影交叠，并在交叠位置处与信号线电连接；
多个第一通孔，第一通孔与电镀电极2一一对应，第一通孔在柔性衬底1的正投影与电镀电极2在柔性衬底1的正投影交叠，且第一通孔贯穿柔性衬底1并暴露电镀电极2，第一通孔内填充有导电材料4，具体的，第一通孔在柔性衬底1的正投影面积可以大于电镀电极2在柔性衬底1的正投影面积，即，第一通孔在柔性衬底1的正投影完全覆盖电镀电极2在柔性衬底1的正投影；
多个绑定电极5，绑定电极5位于柔性衬底1的背离信号线的一面，与第一通孔一一对应，且绑定电极2在柔性衬底1的正投影与第一通孔在柔性衬底1的正投影交叠，每个绑定电极5通过对应的第一通孔内的导电材料4与对应的电镀电极2电连接，具体的，绑定电极2在柔性衬底1的正投影的面积可以大于第一通孔在柔性衬底1的正投影的面积，即，绑定电极2在柔性衬底1的正投影完全覆盖第一通孔在柔性衬底1的正投影。
上述公开实施例提供的显示基板中，柔性衬底1上形成有多个电镀电极2以及用于传输显示信号的信号线，信号线与电镀电极2电连接，柔性衬底1与每个电镀电极相对的区域形成有第一通孔，第一通孔内填充有导电材料4，柔性衬底1背离多个电镀电极2的一侧形成有与第一通孔一一对应的绑定电极5，绑定电极5通过其对应的第一通孔内的导电材料4与其对应的电镀电极2电连接，上述结构可以通过电镀电极2、导电材料4以及绑定电极5的设置直接将信号线引到柔性基板背离信号线的一侧，与外部电路的柔性电路板连接，实现信号线对显示信号的传输，由于绑定电极5直接设置于柔性衬底1背离薄膜晶体管TFT器件层的一侧，并且省去了显示基板上扇出走线的设置，从而可以实现极窄边框或者无边框的设计，进而可以实现大面积的拼接屏的制作。
上述公开实施例提供的显示基板中，柔性衬底1与多个电镀电极2之间还形成有缓冲层6，第一通孔还贯穿缓冲层6，即，柔性衬底1以及缓冲层6与每个电镀电极相对的区域形成有第一通孔，第一通孔内形成有导电材料4，缓冲层6的设置能够增强柔性显示基板的弯折能力，并且提高显示基板的水氧阻隔能力以及隔热效果。
可选地，绑定电极5的材料可以为铟锡氧化物，具有优异的光电性能。在应用中，绑定电极5的材料根据实际选择而定，在这里不做限制。优选地，绑定电极5覆盖第一通孔，既可实现导电的作用，又可实现对第一通孔内导电材料的保护。
在具体实施时，参见图2所示，信号线包括：多条栅线301；电镀电极2包括：多个栅线电镀电极201，栅线电镀电极201与栅线301一一对应，且栅线电镀电极201与相应的栅线301的端部对应(结合图3所示，栅线301的绑定电极5沿垂直于栅线301的方向排列，即，上部沿横向排列的绑定电极5为与栅线301对应的绑定电极5，由于电镀电极2与第一通孔的位置对应，第一通孔与绑定电极5对应，则，绑定电极5所在的位置也可以认为是电镀电极2所在的位置)，多个栅线电镀电极201在第一方向依次排列，第一方向为平行于栅线301所在面且垂直于栅线301的延伸方向。
在具体实施时，结合图2所示，显示基板还包括：位于栅线301与栅线电镀电极201所在层之间的第一栅极绝缘层901；栅线电镀电极201通过贯穿第一栅极绝缘层901的第二通孔与栅线301电连接。
在具体实施时，结合图2所示，信号线还包括：位于栅线301的背离柔性衬底1一面的多条数据线701；电镀电极2还包括：多个数据线电镀电极202，数据线电镀电极202与数据线701一一对应，且数据线电镀电极202与相应的数据线701的端部对应(结合图3所示，数据线701的绑定电极5沿垂直于数据线701的方向排列，即，下部沿竖向排列的绑定电极5为与数据线701对应的绑定电极5，由于电镀电极2与第一通孔的位置对应，第一通孔与绑定电极5对应，则，绑定电极5所在的位置也可以认为是电镀电极2所 在的位置)，多个数据线电镀电极202在第二方向依次排列，第二方向为平行于数据线所在面且垂直于数据线的延伸方向。
在具体实施时，栅线电镀电极201与数据线电镀电极202位于同一层。本公开实施例中，栅线电镀电极201与数据线电镀电极202位于同一层，可以在制作时，一并形成栅线电镀电极201与数据线电镀电极202，简化制作工艺。
在具体实施时，参见图2所示，显示基板还包括：位于数据线701所在层与数据线电镀电极202所在层之间的数据线连接电极；数据线701与数据线电镀电极202通过数据线连接电极电连接。具体的，数据线连接电极包括：第一数据线连接电极302，以及位于第一数据线连接电极302的面向数据线701一面的第二数据线连接电极304。
在具体实施时，第一数据线连接电极302可以与栅线301位于同一层。
在具体实施时，第二数据线连接电极304可以与第一数据线连接电极302之间还具有第二栅极绝缘层902；第二数据线连接电极304通过贯穿第二栅极绝缘层902的第三通孔与第一数据线连接电极302电连接；第一数据线连接电极302通过贯穿第一栅极绝缘层901的第四通孔与数据线电镀电极202电连接。
在具体实施时，参见图2所示，显示基板还包括：位于第二数据线连接电极304与数据线701之间的层间介质层11；数据线701通过贯穿层间介质层11的第五通孔与第二数据线连接电极304电连接。
在具体实施时，参见图2所示，显示基板还包括：位于数据线701的背离栅线201一面的公共电极17；电镀电极2还包括：与公共电极17电连接的一公共电镀电极203，公共电镀电极203与栅线电镀电极201位于同一层。
在具体实施时，参见图2所示，显示基板还包括：与数据线701位于同一层的第一公共连接电极704，与第二数据线连接电极304位于同一层的第二公共连接电极305，与第一数据线连接电极302位于同一层的第三公共连接电极306；公共电极17依次通过第一公共连接电极704、第二公共连接电极305、 第三公共连接电极306与公共电镀电极203电连接。当然，在依次电连接时，可通过打孔方式实现电连接。
在具体实施时，参见图2所示，显示基板还包括：与公共电极17位于同一层的第三数据线连接电极13，公共电极17所在层与数据线701所在层之间还设置有平坦层12；显示基板还包括：薄膜晶体管，薄膜晶体管包括与数据线701同层的源极702和漏极703，源极702与数据线701电连接(图2中未示出连接，但可以在其它位置处进行电连接)，漏极703通过贯穿平坦层12的第六通孔与第三数据线连接电极13电连接。
在具体实施时，参见图2所示，显示基板还包括：位于公共电极17的背离平坦层12一面的多个凸台结构14，凸台结构14的背离公共电极17的一面还设置有与凸台结构14一一对应的多组绑定衬垫组15，每一绑定衬垫组15包括：相互绝缘的第一绑定衬垫151和第二绑定衬垫152；第一绑定衬垫151覆盖凸台结构14的背离公共电极17的部分表面，以及覆盖第三数据线连接电极13的部分；第二绑定衬垫152覆盖凸台结构14的背离公共电极17的部分表面，以及覆盖公共电极17的部分。
在具体实施时，参见图2所示，显示基板还包括位于绑定衬垫组15的背离平坦层12一面的黑矩阵10，黑矩阵10覆盖绑定衬垫组15以外的其它区域。黑矩阵10在柔性衬底1上的投影覆盖第一通孔位于柔性衬底1上的投影，此结构设置能够避免显示基板的漏光现象。
上述显示基板中，信号线与电镀电极一一对应电连接，实现对信号的传输。
上述显示基板中，具体地，如图3所示，信号线包括相互绝缘的多条栅线以及多条数据线701，多个电镀电极2包括与栅线301一一对应电连接的栅线电镀电极201以及与数据线701一一对应电连接的数据线电镀电极202，通过导电材料4以及绑定电极5将栅线301与数据线701引到柔性衬底1背离多个电镀电极2的一侧，使绑定电极5与柔性电路板连接进行信号的传输。
具体地，以低温多晶硅技术制作的显示基板为例，薄膜晶体管TFT器件 层中可以具体包括，如图2所示，有源层8、第二栅极绝缘层902、第一栅极金属层、第二栅线绝缘层902、第二栅极金属层、层间介质层11、第一源漏极金属层、平坦层12、保护层16、凸台结构14以及用于与显示器件绑定的绑定衬垫组15。
其中，有源层8可以与电镀电极2同层设置；
第一栅极金属层设置有栅线301以及第一数据线连接电极302，栅线301与栅线电镀电极201电连接；
第二栅极金属层设置有与第一栅极金属层形成电容的栅线电极303以及第二数据线连接电极304；
第一源漏极金属层形成有数据线701以及源极702，源极702与有源层8电连接，数据线701通过第一数据线连接电极302和第二数据线连接电极304与数据线电镀电极202电连接，避免由于膜层断差过高而造成的搭接困难；
第三数据线连接电极13与源极702电连接，设置第三数据线连接电极13的作用主要是由于与绑定衬垫组15绑定的显示器件显示电流比较大时，设置第三数据线连接电极13可以降低数据线701上的电阻，减小IR压降。可选的，显示器件可以为Micro LED显示器件；
保护层16的作用是保护第三数据线连接电极13在制作工艺中不受损伤；
凸台结构14有利于绑定衬垫组15与显示器件绑定。
需要说明的是，上述显示基板的具体结构仅作为本公开中可以实现窄边框或者无边框的一个说明，并不能作为一种限定实施例。
本公开实施例还提供一种柔性显示基板，其中，包括如本公开实施例提供的显示基板。
在具体实施时，柔性显示基板还包括多个微发光二极管，微发光二极管包括第一电极和第二电极；微发光二极管的第一电极与第一绑定衬垫绑定，第二电极与第二绑定衬垫绑定。
本公开实施例还提供一种拼接屏，其中，包括至少两个如本公开实施例提供的柔性显示基板。具体的，可以将本公开实施例提供的多个柔性显示基 板通过固定部件固定于同一载体，以获得大尺寸的拼接屏。固定部件具体可以是磁铁，相应的，载体可以设置有相反极性的磁铁，以将柔性显示基板吸附在载体上；固定部件具体也可以是胶体，即，将多个柔性显示基板粘接在载体上。
本公开实施例还提供一种制作如本公开实施例提供的拼接屏的方法，参见图4和图5所示，其中，包括：
步骤S101、提供具有多个显示区的显示母板，显示母板包括柔性衬底，柔性衬底具有多个第一通孔；
步骤S102、在多个第一通孔内形成导电材料；
步骤S103、沿多个显示区的每个的边缘将显示母板切割为多个显示基板；
步骤S104、将多个显示基板进行拼接。
在具体实施时，显示母板内的同一行的相邻两个显示区具有第一间距，同一列的相邻两个显示区具有第二间距，以便为第一短路电极、第二短路电极、栅线走线区、以及切割时提供区域。具体的第一间距可以为2毫米～3毫米，第二间距可以为2毫米～3毫米。本公开实施例中，在对显示母板进行切割后，可以形成多个显示基板，每一显示基板可以作为后续拼接成任意尺寸显示产品的拼接单元。
在具体实施时，关于步骤S101、提供具有多个显示区的显示母板，可以包括：
在第一刚性基板的一面依次形成柔性衬底、多个电镀电极、多条信号线，第一刚性基板可以为第一玻璃板，信号线可以包括栅线以及数据线；具体的，可以在第一刚性基板的一面依次形成：柔性衬底1、缓冲层6、电镀电极2、第一绝缘层901、栅极层(具体可以包括栅极30、栅线301、第一数据线连接电极302、第三公共连接电极306)、第二绝缘层902、第二数据线连接电极304(同时还可以形成第二公共连接电极305、栅线电极303)、层间介质层11、源漏极层(具体可以包括源极702、数据线701、漏极703、第一公共连接电极704)、公共电极17(同时还可以形成第三数据线连接电极13)、保护层16、 凸台结构14、绑定衬垫组15、黑矩阵10；
在信号线的背离第一刚性基板的一面贴附第二刚性基板，第二刚性基板可以为第二玻璃板；
去除第一刚性基板，暴露柔性衬底；
通过激光打孔工艺在柔性衬底的与电镀电极一一对应的位置处形成第一通孔；
在步骤S103之前，即，在沿多个显示区的每个的边缘将显示母板切割为多个显示基板之前，本公开实施例的制作方法还包括：去除第二刚性基板。
在具体实施时，结合图5所示，在电镀电极的背离柔性衬底的一侧形成多条信号线，包括：
在电镀电极的背离柔性衬底的一侧形成多条栅线301，同时，在相邻显示区之间的间隙处形成沿垂直于栅线301延伸的第一短路电极310，各显示区的栅线301均与第一短路电极310电连接；
在栅线301的背离柔性衬底的一侧形成多条数据线701，同时，在相邻显示区之间的间隙处形成沿垂直于数据线701延伸第二短路电极710，各显示基板的数据线701均与第二短路电极710电连接。
在具体实施时，在各个显示区的第一通孔内形成导电材料，包括：
将第一短路电极和第二短路电极与电镀设备电连接；
通过电镀设备在第一通孔内形成导电材料。
在具体实施时，在通过电镀设备在第一通孔内形成导电材料之后，制作方法还包括：
在柔性衬底的背离电镀电极的一侧形成与第一通孔一一对应的绑定电极，绑定电极通过对应的第一通孔内的导电材料与对应的电镀电极电连接。
上述显示基板的制作方法中，在柔性衬底上形成多个电镀电极以及薄膜晶体管TFT器件层，薄膜晶体管TFT器件层包括信号线，信号线与电镀电极电连接，然后在柔性衬底与每个电镀电极相对的区域形成有第一通孔，在第一通孔内电镀形成导电材料，最后在柔性衬底背离多个电镀电极的一侧形成 有与第一通孔一一对应的绑定电极，绑定电极通过其对应的第一通孔内的导电材料与其对应的电镀电极电连接，该方法可以通过电镀电极、导电材料以及绑定电极的设置直接将薄膜晶体管TFT器件层引到柔性基板背离薄膜晶体管TFT器件层的一侧与外部电路的柔性电路板连接，实现薄膜晶体管TFT器件层对显示信号的传输，由于绑定电极直接设置于柔性衬底背离薄膜晶体管TFT器件层的一侧，并且省去了显示基板上扇出走线的设置，从而可以实现极窄边框或者无边框的设计，进而可以实现大面积的拼接屏的制作。
具体地，在柔性衬底与多个电镀电极之间还形成有缓冲层，在柔性衬底上进行打孔后，通过干法刻蚀工艺刻蚀缓冲层，从而形成与每个电镀电极相对的第一通孔，此第一通孔贯穿缓冲层以及柔性衬底。
在一种可能的实施方式中，上述显示基板的具体制作步骤可以包括(以下仅是母板上的一个显示基板的制作过程进行举例说明)：
S501：在第一玻璃A表面形成柔性衬底1；
S502：在柔性衬底1的一侧形成多个电镀电极2以及薄膜晶体管TFT器件层，如图6所示；
S503：在薄膜晶体管TFT器件层背离柔性衬底的一侧设置第二玻璃B，采用组装设备对第二玻璃进行对盒，其中第二玻璃B通过粘合剂C对盒固定，如图7所示；
S504：采用剥离设备对第一玻璃A进行剥离，如图8所示；
S505：采用激光打孔技术在柔性衬底上与电镀电极相对的区域打孔，采用干法刻蚀工艺刻蚀缓冲层与电镀电极2相对的区域，形成贯穿柔性衬底1与缓冲层6的第一通孔，如图9以及图10所示；
S506：采用电镀的方式在第一通孔内形成导电材料4，如图11所示；
S507：在柔性衬底1背离多个电镀电极2的一侧形成绑定电极5，绑定电极5通过第一通孔内的导电材料4与电镀电极电连接，如图12所示；
S508：去除第二玻璃B和粘合剂C，切除显示基板多余区域，如图2和图3所示。
上述显示基板制作方法中，制作薄膜晶体管TFT器件层包括制作与电镀电极一一对应电连接的信号线，信号线可以包括栅线以及数据线。
在具体的制作方法中，制作薄膜晶体管TFT器件层可以包括制作如图6所示的在衬底基板1一侧依次形成的有源层8、第一栅极绝缘层901、第一栅极金属层31、第二栅极绝缘层902、第二栅极金属层32、层间介质层11、第一源漏极金属层7、平坦层12、第三数据线连接电极13、保护层16、凸台结构14、绑定衬垫15。
其中，薄膜晶体管TFT器件层中有源层8可以与电镀电极2同层设置；当有源层与电镀电极同层设置时，在显示基板的制作过程中可以先制作多个电镀电极2，再在同层制作有源层8，也可以先制作薄膜晶体管TFT器件层中的有源层8，再在同层制作多个电镀电极2；
第一栅极金属层31设置有栅线301以及第一数据线连接电极302，栅线301与栅线电镀电极201电连接；
第二栅极金属层32设置有与第一栅极金属层31形成电容的栅线电极303以及第二数据线连接电极304；
第一源漏极金属层7形成有数据线701以及源极702，源极702与有源层8电连接，数据线701通过第一数据线连接电极302和第二数据线连接电极304与数据线电镀电极202电连接；
第三数据线连接电极13与源极702电连接。
需要说明的是，制作显示基板时，如果先在柔性衬底上制作第一通孔，然后在制作薄膜晶体管TFT器件层的工艺时信号线(栅线、数据线等)直接搭接于第一通孔内，可能由于柔性衬底与金属材料的膨胀系数不同而容易导致信号线断路。而本实施例的制作方法中是在制作薄膜晶体管TFT器件层前先在柔性衬底上先通过电镀的方式制作与信号线对应电连接的电镀电极，在薄膜晶体管TFT器件层工艺结束后，制作第一通孔，在第一通孔内通过电镀工艺形成导电材料，保证薄膜晶体管TFT器件层上的信号能够传输到柔性衬底背离薄膜晶体管TFT器件层的一侧，避免信号线断路，并且电镀电极与电 镀形成的导电材料连接使得信号传输更加精确。
具体地，第一通孔内的电镀材料4可以为铜等导电金属，柔性衬底的材料可以为聚酰亚胺等。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (24)

  1. 一种显示基板，其中，包括：
    柔性衬底；
    多条信号线，多条所述信号线位于所述柔性衬底的一侧；
    多个电镀电极，所述电镀电极位于所述信号线的面向所述柔性衬底的一面，且每一所述电镀电极在所述柔性衬底的正投影与一所述信号线在所述柔性衬底的部分正投影交叠，并在交叠位置处与所述信号线电连接；
    多个第一通孔，所述第一通孔在所述柔性衬底的正投影与所述电镀电极在所述柔性衬底的正投影交叠，且所述第一通孔贯穿所述柔性衬底并暴露所述电镀电极，所述第一通孔内填充有导电材料；
    多个绑定电极，所述绑定电极位于所述柔性衬底的背离所述信号线的一面，且所述绑定电极在所述柔性衬底的正投影与所述第一通孔在所述柔性衬底的正投影交叠，每个所述绑定电极通过对应的所述第一通孔内的所述导电材料与对应的所述电镀电极电连接。
  2. 如权利要求1所述的显示基板，其中，所述信号线包括：多条栅线；
    所述电镀电极包括：多个栅线电镀电极，所述栅线电镀电极与所述栅线一一对应，且所述栅线电镀电极与相应的所述栅线的端部对应，多个所述栅线电镀电极在第一方向依次排列，所述第一方向为平行于所述栅线所在面且垂直于所述栅线的延伸方向。
  3. 如权利要求2所述的显示基板，其中，所述显示基板还包括：位于所述栅线与所述栅线电镀电极所在层之间的第一栅极绝缘层；
    所述栅线电镀电极通过贯穿所述第一栅极绝缘层的第二通孔与所述栅线电连接。
  4. 如权利要求3所述的显示基板，其中，所述信号线还包括：位于所述栅线的背离所述柔性衬底一面的多条数据线；
    所述电镀电极还包括：多个数据线电镀电极，所述数据线电镀电极与所 述数据线一一对应，且所述数据线电镀电极与相应的所述数据线的端部对应，多个所述数据线电镀电极在第二方向依次排列，所述第二方向为平行于所述数据线所在面且垂直于所述数据线的延伸方向。
  5. 如权利要求4所述的显示基板，其中，所述栅线电镀电极与所述数据线电镀电极位于同一层。
  6. 如权利要求5所述的显示基板，其中，所述显示基板还包括：位于所述数据线所在层与所述数据线电镀电极所在层之间的数据线连接电极；
    所述数据线与所述数据线电镀电极通过所述数据线连接电极电连接。
  7. 如权利要求6所述的显示基板，其中，所述数据线连接电极包括：第一数据线连接电极，以及位于所述第一数据线连接电极的面向所述数据线一面的第二数据线连接电极。
  8. 如权利要求7所述的显示基板，其中，所述第一数据线连接电极与所述栅线位于同一层。
  9. 如权利要求7所述的显示基板，其中，所述第二数据线连接电极与所述第一数据线连接电极之间还具有第二栅极绝缘层；
    所述第二数据线连接电极通过贯穿所述第二栅极绝缘层的第三通孔与所述第一数据线连接电极电连接；
    所述第一数据线连接电极通过贯穿所述第一栅极绝缘层的第四通孔与所述数据线电镀电极电连接。
  10. 如权利要求7所述的显示基板，其中，所述显示基板还包括：位于所述第二数据线连接电极与所述数据线之间的层间介质层；
    所述数据线通过贯穿所述层间介质层的第五通孔与所述第二数据线连接电极电连接。
  11. 如权利要求10所述的显示基板，其中，所述显示基板还包括：位于所述数据线的背离所述栅线一面的公共电极；
    所述电镀电极还包括：与所述公共电极电连接的一公共电镀电极，所述公共电镀电极与所述栅线电镀电极位于同一层。
  12. 如权利要求11所述的显示基板，其中，所述显示基板还包括：与所述数据线位于同一层的第一公共连接电极，与所述第二数据线连接电极位于同一层的第二公共连接电极，与所述第一数据线连接电极位于同一层的第三公共连接电极；
    所述公共电极依次通过所述第一公共连接电极、第二公共连接电极、第三公共连接电极与所述公共电镀电极电连接。
  13. 如权利要求11所述的显示基板，其中，所述显示基板还包括：与所述公共电极位于同一层的第三数据线连接电极，所述公共电极所在层与所述数据线所在层之间还设置有平坦层；
    所述显示基板还包括：薄膜晶体管，所述薄膜晶体管包括与所述数据线同层的源极和漏极，所述源极与所述数据线电连接，所述漏极通过贯穿所述平坦层的第六通孔与所述第三数据线连接电极电连接。
  14. 如权利要求13所述的显示基板，其中，所述显示基板还包括：位于所述公共电极的背离所述平坦层一面的多个凸台结构，所述凸台结构的背离所述公共电极的一面还设置有与所述凸台结构一一对应的多组绑定衬垫组，每一所述绑定衬垫组包括：相互绝缘的第一绑定衬垫和第二绑定衬垫；
    所述第一绑定衬垫覆盖所述凸台结构的背离所述公共电极的部分表面，以及覆盖所述第三数据线连接电极的部分；
    所述第二绑定衬垫覆盖所述凸台结构的背离所述公共电极的部分表面，以及覆盖所述公共电极的部分。
  15. 根据权利要求14所述的显示基板，其中，所述显示基板还包括位于所述绑定衬垫组的背离所述平坦层一面的黑矩阵，所述黑矩阵覆盖所述绑定衬垫组以外的其它区域。
  16. 根据权利要求1所述的显示基板，其中，所述柔性衬底与所述多个电镀电极之间形成有缓冲层，所述第一通孔还贯穿所述缓冲层。
  17. 根据权利要求1所述的显示基板，其中，所述绑定电极的材料为金属或铟锡氧化物。
  18. 如权利要求17所述的显示基板，其中，所述显示基板还包括多个微发光二极管，所述微发光二极管包括第一电极和第二电极；
    所述微发光二极管的所述第一电极与所述第一绑定衬垫绑定，所述第二电极与所述第二绑定衬垫绑定。
  19. 一种拼接屏，其中，包括至少两个如权利要求1-18任一项所述的显示基板。
  20. 一种制作如权利要求19所述的拼接屏的方法，其中，包括：
    提供具有多个显示区的显示母板，所述显示母板包括柔性衬底，所述柔性衬底具有多个第一通孔；
    在多个所述第一通孔内形成导电材料；
    沿所述多个显示区的每个的边缘将所述显示母板切割为多个显示基板；
    将多个所述显示基板进行拼接。
  21. 如权利要求20所述的制作方法，其中，
    所述提供具有多个显示区的显示母板，包括：
    在第一刚性基板的一面依次形成柔性衬底、多个电镀电极、多条信号线；
    在所述信号线的背离所述第一刚性基板的一面贴附第二刚性基板；
    去除所述第一刚性基板，暴露所述柔性衬底；
    通过激光打孔工艺在所述柔性衬底的与所述电镀电极一一对应的位置处形成第一通孔；
    在沿所述多个显示区的每个的边缘将所述显示母板切割为多个显示基板之前，所述制作方法还包括：去除所述第二刚性基板。
  22. 如权利要求21所述的制作方法，其中，所述在所述电镀电极的背离所述柔性衬底的一侧形成多条信号线，包括：
    在所述电镀电极的背离所述柔性衬底的一侧形成多条栅线，同时，在相邻所述显示区之间的间隙处形成沿垂直于所述栅线延伸的第一短路电极，各所述显示区的所述栅线均与所述第一短路电极电连接；
    在所述栅线的背离所述柔性衬底的一侧形成多条数据线，同时，在相邻 所述显示区之间的间隙处形成沿垂直于所述数据线延伸的第二短路电极，各所述显示区的所述数据线均与所述第二短路电极电连接。
  23. 如权利要求22所述的制作方法，其中，所述在各个所述显示区的所述第一通孔内形成导电材料，包括：
    将所述第一短路电极和所述第二短路电极与电镀设备电连接；
    通过所述电镀设备在所述第一通孔内形成导电材料。
  24. 如权利要求23所述的制作方法，其中，在通过所述电镀设备在所述第一通孔内形成导电材料之后，所述制作方法还包括：
    在所述柔性衬底的背离所述电镀电极的一侧形成与所述第一通孔一一对应的绑定电极，所述绑定电极通过对应的所述第一通孔内的所述导电材料与对应的所述电镀电极电连接。
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