WO2021138920A1 - 显示面板及显示装置 - Google Patents
显示面板及显示装置 Download PDFInfo
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- WO2021138920A1 WO2021138920A1 PCT/CN2020/071545 CN2020071545W WO2021138920A1 WO 2021138920 A1 WO2021138920 A1 WO 2021138920A1 CN 2020071545 W CN2020071545 W CN 2020071545W WO 2021138920 A1 WO2021138920 A1 WO 2021138920A1
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- substrate
- display panel
- driving signal
- line
- signal line
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
Definitions
- the present disclosure relates to the field of display technology, and in particular to display panels and display devices.
- the display panel and the flexible printed circuit (FPC) are usually bonded at the edge of the display panel, which is not conducive to achieving a narrow frame.
- the base substrate includes a plurality of substrate vias located in the display area of the display panel;
- a plurality of driving signal lines and a plurality of binding terminals are respectively located on different surfaces of the base substrate;
- At least one of the plurality of driving signal lines is electrically connected to at least one of the plurality of binding terminals through the substrate via.
- the display area further includes:
- a plurality of first fan-out lines located on the side of the base substrate away from the driving signal line;
- One of the plurality of first fan-out lines is electrically connected to one of the plurality of binding terminals
- One of the driving signal lines is electrically connected to at least one of the first fan-out lines through the substrate via holes.
- the display area further includes:
- the first insulating layer is located between the layer where the driving signal line is located and the base substrate, and the first insulating layer has a plurality of first via holes;
- a plurality of first auxiliary lines located between the first insulating layer and the base substrate;
- One of the driving signal lines is electrically connected to one of the first auxiliary lines through the first via hole, and one of the first auxiliary lines is electrically connected to at least one of the first fan-out lines through the substrate via hole.
- the orthographic projection of the driving signal line and the first auxiliary line corresponding to each other on the base substrate at least partially overlap, and the driving signal line and the first auxiliary line corresponding to each other pass through A plurality of the first via holes at intervals are electrically connected.
- the pitch between every two adjacent first via holes is the same.
- the distance between the orthographic projection of each binding terminal on the base substrate and the orthographic projection of the corresponding substrate via on the base substrate is approximately the same.
- the area where the binding terminal is located has a first side and a second side opposite to each other; and the first side and the second side are arranged along the first direction;
- the plurality of substrate vias are located on at least one of the first side and the second side.
- part of the substrate vias in the plurality of substrate vias are located on the first side, and the remaining part of the substrate vias in the plurality of substrate vias are located on the second side. side.
- the substrate vias corresponding to the odd-numbered first fan-out lines in the second direction are located on the first side, and the substrate vias corresponding to the even-numbered first fan-out lines are located on the first side. Located on the second side.
- one of the first fan-out lines corresponds to one of the substrate vias
- one of the first auxiliary lines corresponds to the two first fan-out lines through the substrate vias. connection;
- One substrate via corresponding to the same first auxiliary line is located on the first side of the region where the binding terminal is located, and the other substrate via hole is located on the second side of the region where the binding terminal is located.
- the display panel further includes:
- the second insulating layer is located between the layer where the first fan-out line is located and the base substrate, and the second insulating layer has a plurality of second via holes;
- a plurality of second auxiliary lines located between the second insulating layer and the base substrate;
- One of the driving signal lines is electrically connected to one of the second auxiliary lines through the substrate via holes;
- One of the second auxiliary lines is electrically connected to one of the first fan-out lines through the second via hole.
- the pitch between every two adjacent substrate via holes is the same.
- the substrate via holes corresponding to each adjacent driving signal line are arranged on a straight line along the second direction.
- the substrate via holes corresponding to each adjacent driving signal line are arranged in a staggered manner.
- the driving signal line extends along a first direction
- the display area has a symmetry axis along a second direction; the first direction is different from the second direction; all The second via hole is located on the symmetry axis of the display area.
- the display area further includes:
- a plurality of second fan-out lines located between the layer where the driving signal line is located and the base substrate;
- the third insulating layer is located between the layer where the driving signal line is located and the layer where the second fan-out line is located, and the third insulating layer has a plurality of third via holes;
- One of the driving signal lines is electrically connected to one of the second fan-out lines through the third via hole, and one of the second fan-out lines is electrically connected to one of the binding terminals through the substrate via hole.
- the driving signal line extends along a first direction
- the display area has a symmetry axis along a second direction; the first direction is different from the second direction;
- One drive signal line corresponds to one substrate via, and the substrate via is located in an area from the symmetry axis to the edge of the display area.
- all the substrate vias are arranged in a straight line along the second direction.
- all the substrate vias are located on the same side of the symmetry axis and close to the edge of the display area.
- all the substrate vias are located on the symmetry axis.
- the driving signal line includes at least one of a data line, a first power line, and a second power line.
- the embodiment of the present disclosure also provides a display device including the above-mentioned display panel.
- FIG. 1 is a schematic diagram of a top view structure of a display panel in the related art
- FIG. 2 is a schematic cross-sectional structure diagram of the display panel shown in FIG. 1;
- FIG. 3 is a schematic plan view of a display panel provided by an embodiment of the present disclosure.
- 4a is a schematic cross-sectional structure diagram of the display panel shown in FIG. 3 along the AA' direction;
- 4b is a schematic cross-sectional structure diagram of a display panel during the manufacturing process according to an embodiment of the disclosure
- FIG. 5 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure.
- FIG. 6a is a schematic top view of another display panel provided by an embodiment of the present disclosure.
- FIG. 6b is a schematic top view of another display panel according to an embodiment of the present disclosure.
- FIG. 7 is a schematic cross-sectional view of the display panel shown in FIG. 6a along the AA' direction;
- FIG. 8 is a schematic diagram of a partial cross-sectional structure along the edge of a display panel provided by an embodiment of the present disclosure
- FIG. 9 is a schematic top view of another display panel provided by an embodiment of the present disclosure.
- FIG. 10 is a schematic top view of another display panel according to an embodiment of the present disclosure.
- FIG. 11 is a schematic top view of another display panel according to an embodiment of the present disclosure.
- FIG. 12 is a schematic diagram of a top view structure of another display panel provided by an embodiment of the present disclosure.
- FIG. 13 is a schematic top view of another display panel provided by an embodiment of the present disclosure.
- FIG. 14 is a schematic cross-sectional view of the display panel shown in FIG. 13 along the AA' direction;
- FIG. 15 is a schematic top view of another display panel according to an embodiment of the present disclosure.
- FIG. 16 is a schematic top view of another display panel provided by an embodiment of the present disclosure.
- FIG. 17 is a schematic top view of another display panel according to an embodiment of the present disclosure.
- FIG. 18 is a schematic cross-sectional view of the display panel shown in FIG. 17 along the AA' direction.
- FIG. 1 is a schematic top view of the structure of the display panel
- FIG. 2 is a schematic cross-sectional view of the array substrate in the display panel.
- the display panel may include an array substrate 10 and a counter substrate 20 that are disposed oppositely.
- the display panel has a display area A1, a fan-out area A2, and a binding area A3.
- the display area A1 is provided with a signal line
- the fan-out area A2 is provided with a fan-out line
- the binding area A3 is provided with a binding terminal.
- the binding terminal is bound with the flexible circuit board, so that the flexible circuit board transmits
- the signal is input to the signal line through the binding terminal and the fan-out line in turn.
- the display panel is bound to the flexible circuit board
- the border on one side needs to have a certain width.
- the edge of the array substrate and the counter substrate can be aligned.
- the array substrate is provided with binding terminals that need to be electrically connected to the flexible circuit board, so the edge of the array substrate and the counter substrate cannot be aligned. Therefore, when the other side frames of the display panel are extremely narrow, the corresponding frame on the side of the binding area of the display panel is still relatively wide.
- an embodiment of the present disclosure provides a display panel, as shown in FIG. 3 and FIG. 4a, which may include:
- the base substrate 100 includes a plurality of substrate vias 200 located in the display area AA of the display panel; for example, the substrate via 200 may penetrate the base substrate 100;
- the plurality of driving signal lines 110 and the plurality of bonding terminals 120 are respectively located on different surfaces of the base substrate 100; for example, the plurality of driving signal lines 110 are located on one surface M1 of the base substrate 100 and all the driving signal lines 110 are located on the display In area AA, a plurality of bonding terminals 120 are located on the surface M2 of the base substrate 100 away from the driving signal line 110, and the orthographic projection of each bonding terminal 120 on the base substrate 100 is located in the display area AA;
- At least one of the plurality of driving signal lines 110 is electrically connected to at least one of the plurality of bonding terminals 120 through the substrate via 200.
- the orthographic projection of each bound terminal on the base substrate is located in the display area, so that the bound terminals can be arranged in the display area in a direction perpendicular to the plane where the base substrate is located. .
- the driving signal line can be electrically connected to the bonding terminal through the substrate via hole. Connected, so that after the binding terminal is electrically connected to the flexible circuit board, the flexible circuit board can transmit a signal to the driving signal line through the binding terminal.
- the binding terminals are arranged in the display area, and the binding terminals are electrically connected to the flexible circuit board and other components, thereby greatly reducing the width of the frame of the display panel. Achieve a narrow border effect.
- the display panel includes a plurality of pixel units PX, a plurality of gate lines 111 and a plurality of data lines 112; wherein, each pixel unit PX includes a plurality of sub-pixels 130, a row of sub-pixels Correspondingly, at least one gate line is electrically connected, and one column of sub-pixels is correspondingly electrically connected with at least one data line.
- the sub-pixels 130 are arrayed in the display area AA of the display panel.
- the pixel unit may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel. In this way, red, green and blue can be mixed to achieve color display.
- the pixel unit may also include red sub-pixels, green sub-pixels, blue sub-pixels, and white sub-pixels. In this way, red, green, blue and white can be mixed to achieve color display.
- the light-emitting color of the sub-pixels in the pixel unit can be designed and determined according to the actual application environment, which is not limited here.
- the display panel in the embodiment of the present disclosure may be a liquid crystal display panel.
- each sub-pixel may include a pixel electrode and a thin-film transistor (TFT).
- TFT thin-film transistor
- one row of sub-pixels is correspondingly electrically connected to one gate line
- one column of sub-pixels is correspondingly electrically connected to one data line.
- the gate of the TFT in a row of sub-pixels is electrically connected to a gate line
- the source of the TFT in a column of sub-pixels is electrically connected to a data line
- the drain of the TFT in each sub-pixel is electrically connected to the pixel electrode.
- the TFT can be turned on under the control of the signal transmitted on the gate line to turn on the pixel electrode and the data line.
- the specific structure of the liquid crystal display panel may be basically the same as that in the related art, and will not be repeated here.
- the display panel in the embodiment of the present disclosure may be an electroluminescent display panel.
- the sub-pixel may include an electroluminescent diode and a pixel circuit for driving the electroluminescent diode to emit light.
- the electroluminescent diode includes an anode, a light-emitting layer, and a cathode that are stacked.
- the electroluminescent diode may include: at least one of OLED, QLED, and Micro LED.
- a general pixel circuit may include multiple transistors such as a driving transistor, a switching transistor, and a storage capacitor. The specific structure and working principle of the pixel circuit may be the same as those in the related art, which will not be repeated here.
- the display area AA may also be provided with: light-emitting control signal lines, reference voltage signal lines, initialization signal lines, first power lines, second power lines, and other signal lines .
- the light-emitting control signal line can be used to transmit light-emitting control signals
- the reference voltage signal line can be used to transmit a reference voltage signal of a fixed voltage value
- the initialization signal line can be used to transmit an initialization signal of a fixed voltage value.
- the first power line can be used To transmit a high-voltage power signal with a fixed voltage value
- the second power line can be used to transmit a low-voltage power signal with a fixed voltage value.
- its specific structure and working principle can be the same as those in the related art, and will not be repeated here.
- the driving signal line 110 may include at least one of a data line, a first power line, and a second power line.
- the driving signal line 110 can be configured as a data line, so that a signal can be transmitted to the data line through the above-mentioned binding terminal 120.
- the driving signal line 110 may be configured as a first power line, so that a high voltage signal can be transmitted to the first power line through the above-mentioned binding terminal 120.
- the driving signal line 110 can be configured as a second power line, so that a high-voltage signal can be transmitted to the second power line through the above-mentioned binding terminal 120.
- the driving signal line 110 can also be configured as a data line, a first power line, and a second power line, so that corresponding signals can be transmitted to the data line, the first power line, and the second power line through the above-mentioned binding terminal 120 .
- the driving signal line 110 can also be configured as a data line, a first power line, and a second power line, so that corresponding signals can be transmitted to the data line, the first power line, and the second power line through the above-mentioned binding terminal 120 .
- it can be designed and determined according to the actual application environment, which is not limited here.
- the base substrate 100 may be configured as a glass substrate, a flexible substrate, a silicon substrate, etc., which is not limited herein.
- the flexible substrate may include a PI (Polyimide, polyimide) substrate.
- PI Polyimide, polyimide
- the base substrate 100 may be configured as a PI substrate. Due to the small thickness of the PI substrate and the high flexibility of the material, the process of forming through-vias on the PI substrate is less difficult than the process of forming vias on the glass substrate, and the permeability of the formed vias Better.
- the display area AA may further include: a plurality of first fan-out lines located on the side of the base substrate 100 away from the driving signal line 110; One first fan-out line 140 among the first fan-out lines is electrically connected to one of the binding terminals 120 among the plurality of binding terminals 120; one driving signal line 110 is electrically connected to at least one first fan-out line 140 through the substrate via 200 correspondingly .
- one driving signal line 110 can correspond to one first fan-out line 140, so that one driving signal line 110 can be electrically connected to one first fan-out line 140 through the substrate via 200.
- one driving signal line 110 can correspond to one substrate via 200, and then one driving signal line 110 is electrically connected to one first fan-out line 140 through one substrate via 200.
- one drive signal line 110 can also correspond to multiple substrate vias 200, and then one drive signal line 110 can be electrically connected to one first fan-out line 140 through multiple substrate vias 200.
- the base substrate 100 is made of a flexible material, such as polyimide.
- a rigid substrate 01 is provided on the rigid substrate 01.
- the binding terminals 120, the first fan-out line 140 are prepared, and the PI layer, that is, the base substrate 100, is prepared; then, the driving signal line 110 is prepared to bind the micro LEDs until After the various film layers required in the display panel are prepared, the rigid substrate is peeled off.
- the rigid substrate can be peeled off by etching or laser to obtain a flexible display panel.
- the rigid substrate may include a glass substrate or a silicon substrate.
- a glass substrate can be preferably used as a rigid substrate, so that the cost can be reduced.
- the display area AA may further include: a first insulating layer located between the layer where the driving signal line 110 is located and the base substrate 100 710, a plurality of first auxiliary lines 610 located between the first insulating layer 710 and the base substrate 100.
- the first insulating layer 710 may have a plurality of first via holes 711, one driving signal line 110 is electrically connected to one first auxiliary line 610 through the first via hole 711, and one first auxiliary line 610 passes through the substrate via 200 It is electrically connected to at least one first fan-out line 140 correspondingly.
- a driving signal line 110 when a driving signal line 110 is electrically connected through a first via 711 and a first auxiliary line 610 is correspondingly electrically connected through a first via 711, the first auxiliary line 610 only serves to transfer electrical signals. And if one driving signal line 110 is electrically connected through the first via 711 and a first auxiliary line 610 through a plurality of first vias 711, the driving signal line 110 and the first auxiliary line 610 form a parallel structure, which can reduce The voltage drop generated when the electric signal is transmitted on the driving signal line 110.
- the driving signal lines 110 can be extended along the first direction F1, and the driving signal lines 110 can be arranged along the second direction F2.
- the first direction F1 and the second direction F2 are different.
- the first direction F1 and the second direction F2 are perpendicular.
- the first direction F1 may be the column direction of the sub-pixels
- the second direction F2 may be the row direction of the sub-pixels.
- the first direction F1 may be the row direction of the sub-pixels
- the second direction F2 may be the column direction of the sub-pixels, which is not limited here.
- the first auxiliary line 610 may also extend along the first direction F1, and the first auxiliary line 610 may be arranged along the second direction F2.
- the orthographic projection of the driving signal line 110 and the first auxiliary line 610 corresponding to each other on the base substrate 100 can have an overlapping area, and further, the orthographic projection of the driving signal line 110 on the base substrate 100 can be made. Cover the orthographic projection of the first auxiliary line 610 on the base substrate 100.
- the orthographic projection of the driving signal line 110 and the first auxiliary line 610 corresponding to each other on the base substrate 100 can be overlapped, which can further reduce the influence of the first auxiliary line 610 on the display effect.
- the extension length of the first auxiliary line 610 may also be shorter than the length of the corresponding driving signal line 110.
- a plurality of binding terminals are arranged at intervals.
- the binding terminals 120 may be sequentially arranged along the second direction F2.
- the binding terminals 120 may be sequentially arranged on the same straight line along the second direction F2.
- the spacing between adjacent binding terminals 120 may be approximately the same. In this way, the binding terminals 120 can be designed uniformly, so that the binding terminals 120 can be uniformly arranged.
- the area where the binding terminal 120 is located can be used as a boundary, and the display area AA can be divided into a first side C1 and a second side C2 relative to the binding terminal 120; and the first side C1 And the second side C2 are arranged along the first direction F1.
- each binding terminal 120 has a center (such as a geometric center), so that the line connecting the centers of the plurality of binding terminals 120 is used as the boundary, so that the display area AA is divided into the first with respect to the plurality of binding terminals 120 Side C1 and second side C2.
- other methods can also be used to set the above limits, which are not limited here.
- one first auxiliary line 610 can correspond to one first fan-out line 140, and one first auxiliary line 610 corresponds to one substrate via 200, so that one first auxiliary line 610 can pass through one
- the substrate via 200 is electrically connected to a first fan-out line 140 correspondingly.
- all the substrate vias 200 may be located on the first side C1 of the region where the binding terminal 120 is located.
- all the substrate vias 200 can also be located on the second side C2 of the area where the binding terminals 120 are located, which can be designed and determined according to the actual application environment, and is not limited here.
- one first auxiliary line 610 corresponds to two first fan-out lines 140
- one first auxiliary line 610 corresponds to two substrate vias 200
- one first fan-out line 140 corresponds to one.
- the substrate via 200 so that one first auxiliary line 610 can be electrically connected to the two first fan-out lines 140 through the substrate via 200.
- one substrate via 200 corresponding to the same first auxiliary line 610 may be located on the first side C1 of the region where the bonding terminal 120 is located, and the other substrate via 200 may be located on the second side C2 of the region where the bonding terminal 120 is located.
- the substrate vias 200 corresponding to the same first auxiliary line 610 can be dispersedly arranged, and a bonding terminal 120 can be electrically connected to different positions of the driving signal line 110 through the two first fan-out lines 140, so that the driving signal
- the voltages at various places of the line 110 are at the same potential, which in turn can improve the IR droping caused by the excessively long signal line.
- the orthographic projection of the first via 711 on the base substrate 100 and the orthographic projection of the substrate via 200 on the base substrate 100 may not overlap.
- an etching process is used to prepare the vias. It is preferable that the orthographic projection of the first via 711 on the base substrate 100 and the orthographic projection of the substrate via 200 on the base substrate 100 at least partially do not overlap. In one embodiment, , The two may not overlap at all, thereby avoiding the formation of a deeper through hole that may affect the stability of subsequent electrical connections.
- the process steps for preparing the substrate via 200 are earlier than the process steps for preparing the first via 711, which can avoid the influence on the substrate via 200 when the first via 711 is prepared by an etching process.
- the display panel is an electroluminescent display panel and the driving signal line 110 is a data line as an example for description.
- the transistor 132 in the pixel circuit may include: a gate 1321, an active layer 1322 that is insulated from the gate 1321, and a source 1323 that is insulated from the gate 1321 and electrically connected to the active layer 1322; Drain 1324.
- a metal electrode 1325 insulated from both the source 1323 and the drain 1324 is provided between the layer where the source 1323 and the drain 1324 of the transistor 132 are located and the layer where the gate 1321 is located, and the metal electrode 1325 is on the base substrate 100.
- the orthographic projection of the gate 1321 and the orthographic projection of the gate 1321 on the base substrate 100 have an overlap area, and the overlap area forms a storage capacitor in the pixel circuit.
- a buffer layer 311 is provided between the active layer 1322 and the base substrate 100
- a gate insulating layer 312 is provided between the layer where the gate 1321 is located and the active layer 1322, and the layer where the gate 1321 is located and the layer where the metal electrode 1325 is located are different from each other.
- An interlayer dielectric layer 313 is provided therebetween.
- An interlayer insulating layer 314 is provided between the layer where the metal electrode 1325 is located and the layer where the source electrode 1323 and the drain electrode 1324 are located.
- the drain 1324 of the transistor is electrically connected to the anode of the electroluminescent diode through a via hole to provide voltage to the anode.
- the cathode of the electroluminescent diode is loaded with a voltage through the second power line to make the electricity The light-emitting diode emits light, so that the display panel realizes the display function.
- a rigid substrate 01 may be provided first when the display panel is manufactured. 01, the bonding terminal 120, the first fan-out line 140 are sequentially prepared; then a flexible material such as a solution including polyimide is coated to form the PI substrate 100; then the first auxiliary line 610, the buffer layer 311, and the active Layer 1322, gate insulating layer 312, gate 1321, gate line, interlayer dielectric layer 313, metal electrode 1325, interlayer insulating layer 314, source 1323, drain 1324, driving signal line 110 and so on.
- the embodiments of the present disclosure are only described by taking the preparation method described above as an example.
- the display panel improved by the present disclosure can also adopt other preparation methods to prepare the above-mentioned display panel.
- the gate line 111 and the gate 1321 may be provided with the same layer and the same material.
- the gate 1321 and the gate line 111 can be formed by the same patterning process, thereby reducing the difficulty of process preparation.
- the data line 112 may be provided with the same layer and the same material as the source electrode 1323 and the drain electrode 1324.
- the data line 112, the source electrode 1323 and the drain electrode 1324 can be formed by the same patterning process, thereby reducing the difficulty of process preparation.
- at least one of the first power line and the second power line can also be provided with the same layer and the same material as the data line.
- the first insulating layer 710 may include a buffer layer 311, a gate insulating layer 312, an interlayer dielectric layer 313, and an interlayer insulating layer 314.
- the display area AA may further include: a plurality of first connection portions 411 and a plurality of second connection portions 412; wherein, the first connection portion 411 is located between the gate insulating layer 312 and the interlayer dielectric layer 313, and the second connection The portion 412 is located between the interlayer dielectric layer 313 and the interlayer insulating layer 314.
- One data line 112 corresponds to at least one first connection portion 411, at least one second connection portion 412, and one first auxiliary line 610, and the data line 112 passes through the via 513 passing through the interlayer insulating layer 314 and the second connection portion 412 is electrically connected, the second connection portion 412 is electrically connected to the first connection portion 411 through a via 512 that penetrates the interlayer dielectric layer 313, and the first connection portion 411 is electrically connected to the first connection portion 411 through a via 511 that penetrates the gate insulating layer 312 and the buffer layer 311.
- An auxiliary line 610 is electrically connected, and the first auxiliary line 610 is electrically connected to the first fan-out line 140 through the substrate via 200.
- the data line 112 and the first fan-out line 140 can be electrically connected.
- the data line 112 can be electrically connected to the first auxiliary line 610 through the second connection portion 412 and the first connection portion 411 in turn.
- a via hole needs to be provided in the first insulating layer 710. As the first insulating layer 710 is thicker, the via hole of the first insulating layer 710 is relatively thick. If it is deep, there may be a problem that the data line and the first auxiliary line 610 cannot be electrically connected.
- the first via 711 may include: a via 511, a via 512, and a via 513.
- the orthographic projection of the via 511 on the base substrate 100 and the orthographic projection of the via 512 on the base substrate 100 do not overlap, the orthographic projection of the via 512 on the base substrate 100 and the orthographic projection of the via 513 on the base substrate 100 The orthographic projections do not overlap.
- the orthographic projection of the via 511 on the base substrate 100 and the orthographic projection of the via 200 on the base substrate 100 do not overlap.
- the data line 112 can be electrically connected to the first auxiliary line 610 through the second connection portion 412 and the first connection portion 411 in turn.
- first connecting portion 411 and the second connecting portion 412 are not provided, a via hole needs to be provided in the first insulating layer 710.
- the via hole of the first insulating layer 710 is relatively thick. If it is deep, there may be a problem that the data line and the first auxiliary line 610 cannot be electrically connected.
- one data line can correspond to one first via 711, and then one data line can correspond to one first connection portion 411, one second connection portion 412, and one first auxiliary line 610.
- the setting of the vias can be reduced, and the stability of the display panel can be improved.
- the display area AA may have a symmetry axis S0 along the second direction F2.
- the display area AA may be approximately axisymmetric about the symmetry axis S0.
- the substrate via 200 may be located in the area from the symmetry axis S0 to the edge of the display area AA.
- all the substrate vias 200 may be arranged on a straight line L1 along the second direction F2.
- the straight line L1 may be parallel to the symmetry axis S0.
- all the substrate vias 200 may be located on the same side of the symmetry axis S0 and close to the edge of the display area AA.
- the conventional process requires that the bonding terminal 120 is not more than the effective movement range of the base indenter of the bonding device (for example, within 17mm) from the edge of the display panel, and the substrate vias 200 are all close to the edge of the display area AA.
- the bonding equipment in the conventional process can be used to perform the operation of the flexible circuit board bonding, so that no additional design bonding method is required.
- the embodiment of the present disclosure further provides a display panel.
- a schematic structural diagram is shown in FIG. 9, which is modified with respect to the implementation in the above-mentioned embodiment.
- FIG. 9 A schematic structural diagram is shown in FIG. 9, which is modified with respect to the implementation in the above-mentioned embodiment.
- the driving signal line 110 and the first auxiliary line 610 corresponding to each other may be electrically connected through a plurality of first via holes 711 spaced apart.
- a driving signal line 110 and a first auxiliary line 610 can be electrically connected through a plurality of first vias 711 at intervals, so that the driving signal line 110 and the first auxiliary line 610 cannot be electrically connected by using part of the first vias 711.
- the remaining first vias 711 can also be used to achieve electrical connection.
- the number of the first via 711 may be two, four or more, which can be designed and determined according to the actual application environment, which is not limited here.
- the driving signal line 110 is equivalent to the first auxiliary line 610
- the resistance of the driving signal line 110 can be reduced, thereby increasing the signal transmission rate.
- first via 711 corresponding to the same driving signal line 110
- one of every two adjacent first vias 711 may be The distance between them is the same.
- the first via holes 711 can be uniformly designed, which further improves the stability of the display panel.
- the first via 711 corresponding to each adjacent driving signal line 110 may be arranged on a straight line L1 along the second direction F2. , To further improve the stability of the display panel.
- the first via 711 corresponding to each adjacent driving signal line 110 may also be arranged in a staggered manner. In this way, the first via holes 711 can be evenly distributed and designed to further improve the stability of the display panel.
- the embodiment of the present disclosure further provides a display panel.
- a schematic structural diagram is shown in FIG. 10, which is modified with respect to the implementation in the above-mentioned embodiment.
- FIG. 10 A schematic structural diagram is shown in FIG. 10, which is modified with respect to the implementation in the above-mentioned embodiment.
- one driving signal line 110 may correspond to one substrate via 200.
- all substrate vias 200 may be located at the symmetry axis S0.
- the base substrate 100 needs to be cut (for example, laser cutting or knife wheel cutting), which will have thermal or stress effects on the vias during cutting, resulting in defects in the substrate vias 200, which in turn leads to The electrical connection between the signal wires has a bad problem.
- the substrate via 200 by arranging the substrate via 200 at the symmetry axis S0, the substrate via 200 can be located in the middle row of the display area AA, and the influence caused by cutting can be avoided.
- the first auxiliary line 610 is equivalent to a substantially symmetrical pattern also about the symmetry axis S0, which is equivalent to the signal transmitted by the first fan-out line 140 to the first auxiliary line 610.
- the resistance of the terminal is reduced by half, which can effectively reduce the IR drop (voltage drop) and improve the uniformity of the display.
- the embodiments of the present disclosure further provide a display panel.
- the schematic structural diagrams are shown in FIG. 11 and FIG. 12, which are modified from the implementation in the above-mentioned embodiment. The following only describes the differences between this embodiment and the above-mentioned embodiments, and the similarities are not repeated here.
- the orthographic projection of each binding terminal 120 on the base substrate 100 and the corresponding substrate via 200 on the front of the base substrate 100 can be made.
- the distance between the projections is roughly the same.
- the substrate via 200 corresponding to the longer first fan-out line 140 is close to the sub-pixel row corresponding to the region where the binding terminal 120 is located.
- the voltage transmitted to the driving signal line 110 is approximately the same, thereby improving the display uniformity.
- the area where the binding terminal 120 is located may have a first side C1 and a second side C2 opposite to each other; and the first side C1 and the second side C2 is arranged along the first direction F1.
- a plurality of substrate vias 200 may be located on at least one of the first side C1 and the second side C2.
- all the substrate vias 200 may be located on the first side C1. In this way, the above-mentioned substrate via 200 can be uniformly provided.
- part of the substrate vias 200 among the plurality of substrate vias 200 may also be located on the first side C1, and the plurality of substrate vias 200 may be located on the first side C1.
- the remaining part of the substrate via 200 in C2 is located on the second side C2. In this way, the substrate vias 200 can be further dispersed, thereby further improving the stability of the display panel.
- the substrate via 200 corresponding to the odd-numbered first fan-out line 140 in the second direction F2 is located on the first side C1
- the substrate vias 200 corresponding to the even number of first fan-out lines 140 are located on the second side C2. In this way, the distance between the substrate vias 200 corresponding to the adjacent first fan-out lines 140 can be further increased, and the stability of the display panel can be further improved.
- FIGS. 13 to 16 The schematic structural diagrams are shown in FIGS. 13 to 16, which are modified from the implementation in the above-mentioned embodiment. Hereinafter, only the differences between this embodiment and the above-mentioned embodiment will be described, and the similarities will not be repeated here.
- the display panel may further include: a second insulating layer 720 located between the layer where the first fan-out line 140 is located and the base substrate 100, A plurality of second auxiliary lines 620 between the second insulating layer 720 and the base substrate 100.
- the second insulating layer 720 has a plurality of second via holes 721, one driving signal line 110 is electrically connected to a second auxiliary line 620 through the substrate via 200, and one second auxiliary line 620 passes through the second via hole. 721 is electrically connected to a first fan-out line 140 correspondingly.
- the orthographic projections of the driving signal line 110 and the second auxiliary line 620 corresponding to each other on the base substrate 100 overlap. In this way, the influence of the second auxiliary signal line on the display effect can be reduced, and the display effect can be improved.
- one second auxiliary line 620 may correspond to one driving signal line 110, and one second auxiliary line 620 may correspond to one substrate via 200. Therefore, the driving signal line 110 and the second auxiliary line 620 corresponding to each other can be electrically connected through one substrate via 200. In this way, fewer substrate vias 200 can be provided, and the stability of the display panel can be improved.
- one second auxiliary line 620 may correspond to one driving signal line 110, and one second auxiliary line 620 may correspond to a plurality of substrate vias 200. Therefore, the driving signal line 110 and the second auxiliary line 620 corresponding to each other can be electrically connected through a plurality of substrate vias 200 spaced apart. In this way, a driving signal line 110 and a second auxiliary line 620 can be electrically connected through a plurality of substrate vias 200 at intervals, so that the driving signal line 110 and the second auxiliary line 620 cannot be electrically connected by using part of the substrate vias 200. In this case, the remaining substrate vias 200 can also be used to achieve electrical connection. Moreover, this can make the driving signal line 110 and the second auxiliary line 620 parallel to each other, so that the resistance of the driving signal line 110 can be reduced, and the signal transmission rate can be improved.
- the number of substrate vias 200 may be two, four or more, which can be designed and determined according to the actual application environment, which is not limited herein.
- the gap between every two adjacent substrate vias 200 may be The spacing is the same.
- the substrate vias 200 can be uniformly designed, and the stability of the display panel can be further improved.
- the substrate vias 200 corresponding to each adjacent driving signal line 110 may be arranged on a straight line L1 along the second direction F2. In this way, the substrate vias 200 can be uniformly designed to further improve the stability of the display panel.
- the substrate via 200 corresponding to each adjacent driving signal line 110 may also be arranged in a staggered manner.
- the gap between the vias of one driving signal line 110 and the vias of the other driving signal terminal corresponds to the gap.
- the substrate vias 200 can be further uniformly distributed, and the stability of the display panel can be further improved.
- one driving signal line 110 may correspond to one second via hole 721.
- all the second via holes 721 may be located on the symmetry axis S0.
- the base substrate 100 needs to be cut (for example, laser cutting or knife wheel cutting), which will have thermal or stress effects on the vias during cutting, resulting in defects in the second via 721, and thus This leads to poor electrical connections between the signal lines.
- the second via hole 721 by arranging the second via hole 721 at the symmetry axis S0, the second via hole 721 can be located in the middle row of the display area AA, and the influence caused by cutting can be avoided.
- the second auxiliary line 620 is equivalent to a substantially symmetrical pattern also about the symmetry axis S0, which is equivalent to the signal transmitted by the second fan-out line 150 to the second auxiliary line 620.
- the resistance at both ends is reduced by half, which can effectively reduce the IR drop (voltage drop) and improve the uniformity of the display.
- the embodiments of the present disclosure further provide a display panel.
- the schematic structural diagrams are shown in FIG. 17 and FIG. 18, which are modified from the implementation in the above-mentioned embodiment. Hereinafter, only the differences between this embodiment and the above-mentioned embodiment will be described, and the similarities will not be repeated here.
- the display area AA may further include: a plurality of second fan-out lines 150 located between the layer where the driving signal line 110 is located and the base substrate 100 ,
- the third insulating layer 730 located between the layer where the driving signal line 110 is located and the layer where the second fan-out line 150 is located.
- the third insulating layer 730 has a plurality of third via holes 731; one driving signal line 110 may correspond to one second fan-out line 150, and one second fan-out line 150 may correspond to one bonding terminal 120. That is, one driving signal line 110 is electrically connected to one second fan-out line 150 through the third via 731, and one second fan-out line 150 is electrically connected to one bonding terminal 120 through the substrate via 200.
- the display area AA may further include: a plurality of lines between the third insulating layer 730 and the layer where the driving signal line 110 is located.
- the first auxiliary line 610 and the first insulating layer 710 located between the layer where the first auxiliary line 610 is located and the layer where the driving signal line 110 is located. It should be noted that the implementation of the first auxiliary line 610 and the first insulating layer 710 can refer to the above-mentioned embodiment, and will not be repeated here.
- one driving signal line 110 may correspond to one first auxiliary line 610, and one first auxiliary line 610 corresponds to one second fan.
- Outgoing line 150 that is, a driving signal line 110 is electrically connected to a first auxiliary line 610 through a first via 711, and a first auxiliary line 610 is electrically connected to a second fan-out line 150 through a third via 731.
- a second fan-out line 150 is electrically connected to a binding terminal 120 through the substrate via 200.
- one first auxiliary line 610 may correspond to one third via 731.
- the third vias 731 can be arranged on a straight line L1 along the second direction F2.
- the third via holes 731 can also be dispersedly arranged to improve the stability of the base substrate 100.
- the distance between the orthographic projection of the substrate via 200 on the base substrate 100 and the orthographic projection of the third via 731 on the base substrate 100 may be approximately The same, so that the resistance variability of the second fan-out line 150 can be reduced, and the delay variability of the signal input to the first auxiliary line 610 can be reduced.
- embodiments of the present disclosure also provide a display device, including the above-mentioned display panel provided by the embodiments of the present disclosure.
- the principle of solving the problem of the display device is similar to that of the aforementioned display panel. Therefore, the implementation of the display device can refer to the implementation of the aforementioned display panel, and the repetitive points will not be repeated here.
- the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
- a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
- Other indispensable components of the display device are understood by those of ordinary skill in the art, and will not be repeated here, nor should they be used as a limitation to the present disclosure.
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Abstract
本公开公开了显示面板及显示装置,包括:衬底基板,包括位于显示面板的显示区的多个基板过孔;多个驱动信号线和多个绑定端子,分别位于衬底基板的不同表面;多个驱动信号线中的至少一个通过基板过孔与多个绑定端子中的至少一个电连接。
Description
本公开涉及显示技术领域,特别涉及显示面板及显示装置。
随着显示技术的不断发展,消费者对屏占比的要求越来越高,这就要求显示面板具有较小的边框宽度。然而,显示面板和柔性电路板(Flexible Printed Circuit,FPC)通常是在显示面板边缘处进行绑定(Bonding),从而不利于实现窄边框。
发明内容
本公开实施例提供的显示面板,包括:
衬底基板,包括位于所述显示面板的显示区的多个基板过孔;
多个驱动信号线和多个绑定端子,分别位于所述衬底基板的不同表面;
所述多个驱动信号线中的至少一个通过所述基板过孔与所述多个绑定端子中的至少一个电连接。
可选地,在本公开实施例中,所述显示区还包括:
多个第一扇出线,位于所述衬底基板背离所述驱动信号线一侧;
所述多个第一扇出线中的一个所述第一扇出线与所述多个绑定端子中的一个绑定端子电连接;
一个所述驱动信号线通过所述基板过孔与至少一个所述第一扇出线对应电连接。
可选地,在本公开实施例中,所述显示区还包括:
第一绝缘层,位于所述驱动信号线所在层与所述衬底基板之间,且所述第一绝缘层具有多个第一过孔;
多个第一辅助线,位于所述第一绝缘层与所述衬底基板之间;
一个所述驱动信号线通过所述第一过孔与一个所述第一辅助线对应电连接,一个所述第一辅助线通过所述基板过孔与至少一个所述第一扇出线对应电连接。
可选地,在本公开实施例中,相互对应的驱动信号线和第一辅助线在衬底基板的正投影至少部分重叠,且相互对应的所述驱动信号线与所述第一辅助线通过间隔的多个所述第一过孔电连接。
可选地,在本公开实施例中,针对同一所述驱动信号线对应的第一过孔,每相邻的两个所述第一过孔之间的间距相同。
可选地,在本公开实施例中,各绑定端子在所述衬底基板的正投影与对应的所述基板过孔在所述衬底基板的正投影之间的距离大致相同。
可选地,在本公开实施例中,所述绑定端子所在区域具有相对的第一侧和第二侧;且所述第一侧和所述第二侧沿所述第一方向排列;
所述多个基板过孔位于所述第一侧和所述第二侧中的至少一侧。
可选地,在本公开实施例中,所述多个基板过孔中的部分基板过孔位于所述第一侧,所述多个基板过孔中的其余部分基板过孔位于所述第二侧。
可选地,在本公开实施例中,沿所述第二方向上的第奇数个第一扇出线对应的基板过孔位于所述第一侧,第偶数个第一扇出线对应的基板过孔位于所述第二侧。
可选地,在本公开实施例中,一个所述第一扇出线对应一个所述基板过孔,一个所述第一辅助线通过所述基板过孔与两个所述第一扇出线对应电连接;
同一所述第一辅助线对应的一个基板过孔位于所述绑定端子所在区域的第一侧,另一个基板过孔位于所述绑定端子所在区域的第二侧。
可选地,在本公开实施例中,所述显示面板还包括:
第二绝缘层,位于所述第一扇出线所在层与所述衬底基板之间,且所述第二绝缘层具有多个第二过孔;
多个第二辅助线,位于所述第二绝缘层与所述衬底基板之间;
一个所述驱动信号线通过所述基板过孔与一个所述第二辅助线对应电连接;
一个所述第二辅助线通过所述第二过孔与一个所述第一扇出线对应电连接。
可选地,在本公开实施例中,相互对应的驱动信号线和第二辅助线在衬底基板的正投影重叠,且相互对应的所述驱动信号线与所述第二辅助线通过间隔的多个所述基板过孔电连接。
可选地,在本公开实施例中,针对同一所述驱动信号线对应的基板过孔,每相邻的两个所述基板过孔之间的间距相同。
可选地,在本公开实施例中,每相邻的所述驱动信号线对应的基板过孔沿第二方向排列于一条直线上。
可选地,在本公开实施例中,每相邻的所述驱动信号线对应的基板过孔错位排列。
可选地,在本公开实施例中,所述驱动信号线沿第一方向延伸,所述显示区具有沿第二方向的对称轴;所述第一方向与所述第二方向不同;所有所述第二过孔位于所述显示区的对称轴。
可选地,在本公开实施例中,所述显示区还包括:
多个第二扇出线,位于所述驱动信号线所在层与所述衬底基板之间;
第三绝缘层,位于所述驱动信号线所在层与所述第二扇出线所在层之间,且所述第三绝缘层具有多个第三过孔;
一个所述驱动信号线通过所述第三过孔与一个所述第二扇出线对应电连接,一个所述第二扇出线通过所述基板过孔与一个所述绑定端子电连接。
可选地,在本公开实施例中,所述驱动信号线沿第一方向延伸,所述显示区具有沿第二方向的对称轴;所述第一方向与所述第二方向不同;
一个所述驱动信号线对应一个所述基板过孔,所述基板过孔位于所述对称轴至所述显示区的边缘的区域中。
可选地,在本公开实施例中,所有所述基板过孔沿所述第二方向排列于 一条直线上。
可选地,在本公开实施例中,所有所述基板过孔位于所述对称轴的同一侧且靠近所述显示区的边缘。
可选地,在本公开实施例中,所有所述基板过孔位于所述对称轴。
可选地,在本公开实施例中,所述驱动信号线包括数据线、第一电源线以及第二电源线中的至少一种。
本公开实施例还提供了显示装置,包括上述显示面板。
图1为相关技术中的显示面板的俯视结构示意图;
图2为图1所示的显示面板的剖视结构示意图;
图3为本公开实施例提供的一种显示面板的俯视结构意图;
图4a为图3所示的显示面板沿AA’方向的剖视结构示意图;
图4b为本公开实施例提供的一种显示面板制备过程中的剖视结构示意图;
图5为本公开实施例提供的一种显示面板的具有结构示意图;
图6a为本公开实施例提供的又一种显示面板的俯视结构示意图;
图6b为本公开实施例提供的又一种显示面板的俯视结构示意图;
图7为图6a所示的显示面板沿AA’方向的剖视结构示意图;
图8为本公开实施例提供的显示面板沿的局部具有剖视结构示意图;
图9为本公开实施例提供的又一种显示面板的俯视结构示意图;
图10为本公开实施例提供的又一种显示面板的俯视结构示意图;
图11为本公开实施例提供的又一种显示面板的俯视结构示意图;
图12为本公开实施例提供的又一种显示面板的俯视结构示意图;
图13为本公开实施例提供的又一种显示面板的俯视结构示意图;
图14为图13所示的显示面板沿AA’方向的剖视结构示意图;
图15为本公开实施例提供的又一种显示面板的俯视结构示意图;
图16为本公开实施例提供的又一种显示面板的俯视结构示意图;
图17为本公开实施例提供的又一种显示面板的俯视结构示意图;
图18为图17所示的显示面板沿AA’方向的剖视结构示意图。
为使本公开实施例的目的、技术方案和优点更加清楚,下面将结合本公开实施例的附图,对本公开实施例的技术方案进行清楚、完整地描述。显然,所描述的实施例是本公开的一部分实施例,而不是全部的实施例。并且在不冲突的情况下,本公开中的实施例及实施例中的特征可以相互组合。基于所描述的本公开的实施例,本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例,都属于本公开保护的范围。
除非另外定义,本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性,而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同,而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接,而是可以包括电性的连接,不管是直接的还是间接的。
需要注意的是,附图中各图形的尺寸和形状不反映真实比例,目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
结合图1和图2所示,其中,图1为显示面板的俯视结构示意图,图2为显示面板中的阵列基板的剖视结构示意图。显示面板可以包括相对设置的阵列基板10和对向基板20。显示面板具有显示区A1、扇出区A2以及绑定区A3。其中,显示区A1中设置有信号线,扇出区A2中设置有扇出线,绑定区A3中设置有绑定端子,绑定端子与柔性电路板进行绑定,从而使柔性电路板传输的信号依次通过绑定端子、扇出线输入到信号线上。
通常情况下,无论是采用COF(Chip On Film,即覆晶薄膜)技术,还是 COG(Chip On Glass,即芯片被直接绑定在玻璃基板上)技术,显示面板与柔性电路板进行绑定的一侧的边框需要有一定的宽度。而显示面板的非绑定区对应的侧边中,阵列基板与对向基板边缘可以对齐。但在显示面板的绑定区对应的侧边中,由于阵列基板上设置有需要与柔性电路板电连接的绑定端子,而无法做到阵列基板与对向基板边缘对齐。因此,当显示面板的其它侧边框做到极窄时,显示面板的绑定区一侧对应的边框仍然比较宽。
有鉴于此,本公开实施例提供了一种显示面板,如图3与图4a所示,可以包括:
衬底基板100,包括位于显示面板的显示区AA的多个基板过孔200;例如,基板过孔200可以贯穿衬底基板100;
多个驱动信号线110和多个绑定端子120,分别位于衬底基板100的不同表面;例如,多个驱动信号线110位于衬底基板100的一个表面M1且所有驱动信号线110均位于显示区AA,多个绑定端子120位于衬底基板100背离驱动信号线110的表面M2,且各绑定端子120在衬底基板100的正投影位于显示区AA;
多个驱动信号线110中的至少一个通过基板过孔200与多个绑定端子120中的至少一个电连接。
本公开实施例提供的上述显示面板,通过使各绑定端子在衬底基板的正投影位于显示区,从而在垂直于衬底基板所在平面的方向上,可以使绑定端子设置在显示区中。并且,通过使绑定端子和驱动信号线分别位于衬底基板的不同表面,且通过在显示区设置贯穿衬底基板的基板过孔,以使驱动信号线可以通过基板过孔与绑定端子电连接,从而在绑定端子与柔性电路板电连接后,柔性电路板可以通过绑定端子向驱动信号线传输信号。这样在垂直于衬底基板所在平面的方向上,使绑定端子设置在显示区中,并且通过该绑定端子与柔性电路板等部件电连接,从而可以大大减小显示面板的边框的宽度,实现窄边框效果。
在具体实施时,结合图3与图5所示,显示面板包括多个像素单元PX, 多条栅线111以及多条数据线112;其中,各像素单元PX包括多个子像素130,一行子像素对应电连接至少一条栅线,一列子像素对应电连接至少一条数据线。子像素130阵列排布于显示面板的显示区AA中。示例性地,像素单元可以包括红色子像素,绿色子像素以及蓝色子像素,这样可以通过红绿蓝进行混色,以实现彩色显示。或者,像素单元也可以包括红色子像素,绿色子像素、蓝色子像素以及白色子像素,这样可以通过红绿蓝白进行混色,以实现彩色显示。当然,在实际应用中,像素单元中的子像素的发光颜色可以根据实际应用环境来设计确定,在此不作限定。
在具体实施时,本公开实施例中的显示面板可以为液晶显示面板。进一步地,各子像素可以包括像素电极和薄膜晶体管(Thin-film transistor,TFT)。示例性地,一行子像素对应电连接一条栅线,一列子像素对应电连接一条数据线。具体地,一行子像素中的TFT的栅极与一条栅线电连接,一列子像素中的TFT的源极与一条数据线电连接,每个子像素中的TFT的漏极与像素电极电连接。TFT可以在栅线上传输的信号的控制下导通,以将像素电极和数据线导通。并且,液晶显示面板的具体结构可以与相关技术中的基本相同,在此不作赘述。
有机发光二极管(Organic Light Emitting Diode,OLED)、量子点发光二极管(Quantum Dot Light Emitting Diodes,QLED)、微型发光二极管(Micro Light Emitting Diode,Micro LED)等电致发光二极管具有自发光、低能耗等优点,在具体实施时,本公开实施例中的显示面板可以是电致发光显示面板。在本公开实施例中,子像素可以包括电致发光二极管以及用于驱动电致发光二极管发光的像素电路。其中,电致发光二极管包括层叠设置的阳极、发光层以及阴极。进一步地,电致发光二极管可以包括:OLED、QLED以及Micro LED中的至少一种。并且,一般像素电路可以包括驱动晶体管、开关晶体管等多个晶体管以及存储电容,其具体结构和工作原理可以与相关技术中的相同,在此不作赘述。
示例性地,在显示面板设置为电致发光显示面板时,显示区AA中还可 以设置:发光控制信号线、参考电压信号线,初始化信号线,第一电源线,第二电源线等信号线。其中,发光控制信号线可以用于传输发光控制信号,参考电压信号线可以用于传输固定电压值的参考电压信号,初始化信号线可以用于传输固定电压值的初始化信号,第一电源线可以用于传输固定电压值的高电压电源信号,第二电源线可以用于传输固定电压值的低电压电源信号。当然,其具体结构和工作原理可以与相关技术中的相同,在此不作赘述。
在具体实施时,在本公开实施例中,驱动信号线110可以包括数据线、第一电源线以及第二电源线中的至少一种。示例性地,驱动信号线110可以设置为数据线,这样可以通过上述绑定端子120向数据线传输信号。示例性地,驱动信号线110可以设置为第一电源线,这样可以通过上述绑定端子120向第一电源线传输高电压信号。示例性地,驱动信号线110可以设置为第二电源线,这样可以通过上述绑定端子120向第二电源线传输高电压信号。示例性地,驱动信号线110也可以设置为数据线、第一电源线以及第二电源线,这样可以通过上述绑定端子120向数据线、第一电源线以及第二电源线传输相应的信号。当然,在实际应用中,可以根据实际应用环境来设计确定,在此不作限定。
在具体实施时,在本公开实施例中,衬底基板100可以设置为玻璃基板、柔性基板、硅基板等,在此不作限定。其中,柔性基板可以包括PI(Polyimide,聚酰亚胺)基板。当然,在实际应用中,可以根据实际应用环境来设计确定,在此不作限定。
并且,由于玻璃基板的厚度较大,以及工艺条件的限制,在玻璃基板上制备过孔的难度较大,以及使得制备出的过孔通透性较差。因此,本公开实施例中,可以将衬底基板100设置为PI基板。由于PI基板的厚度较小以及材料的柔软性较高,在PI基板上形成贯穿过孔的工艺相比在玻璃基板上形成过孔的工艺难度较小,以及使形成的过孔的通透性较佳。
在具体实施时,在本公开实施例中,如图3与图4a所示,显示区AA还可以包括:位于衬底基板100背离驱动信号线110一侧的多个第一扇出线; 多个第一扇出线中的一个第一扇出线140与多个绑定端子120中的一个绑定端子120电连接;一个驱动信号线110通过基板过孔200与至少一个第一扇出线140对应电连接。示例性地,可以使一个驱动信号线110对应一个第一扇出线140,这样可以使一个驱动信号线110通过基板过孔200与一个第一扇出线140对应电连接。并且,可以使一个驱动信号线110对应一个基板过孔200,则一个驱动信号线110通过一个基板过孔200与一个第一扇出线140对应电连接。当然,也可以使一个驱动信号线110对应多个基板过孔200,则一个驱动信号线110可以通过多个基板过孔200与一个第一扇出线140对应电连接。
需要说明的是,在具体实施时,在本公开实施例中,在衬底基板100为柔性材料制成,如采用聚酰亚胺,则在制备上述显示面板时,如图4b所示,可以先提供一个刚性基板01,在该刚性基板01上制备绑定端子120,第一扇出线140,再制备PI层,即衬底基板100;之后再制备驱动信号线110,绑定微型LED,直至将显示面板中所需的各个膜层制备完之后,将刚性基板剥离掉。示例性地,可以采用刻蚀或者激光的方式将刚性基板剥离掉,以得到柔性显示面板。示例性地,刚性基板可以包括玻璃基板或硅基板。本公开实施例中,可以优先的使刚性基板采用玻璃基板,这样可以降低成本。
进一步地,在具体实施时,在本公开实施例中,如图6a与图7所示,显示区AA还可以包括:位于驱动信号线110所在层与衬底基板100之间的第一绝缘层710,位于第一绝缘层710与衬底基板100之间的多个第一辅助线610。其中,第一绝缘层710可以具有多个第一过孔711,一个驱动信号线110通过第一过孔711与一个第一辅助线610对应电连接,一个第一辅助线610通过基板过孔200与至少一个第一扇出线140对应电连接。可以理解的是,当一个驱动信号线110通过第一过孔711与一个第一辅助线610通过一个第一过孔711对应电连接时,第一辅助线610只起到转接电信号的作用;而如果一个驱动信号线110通过第一过孔711与一个第一辅助线610通过多个第一过孔711对应电连接时,驱动信号线110与第一辅助线610形成并联结构, 能够降低电信号在驱动信号线110上传输时产生的压降。
在具体实施时,在本公开实施例中,如图6a与图7所示,可以使驱动信号线110沿第一方向F1延伸,并且驱动信号线110沿第二方向F2排列。其中,第一方向F1和第二方向F2不同。例如,第一方向F1和第二方向F2垂直。示例性地,第一方向F1可以为子像素的列方向,第二方向F2可以为子像素的行方向。或者,第一方向F1可以为子像素的行方向,第二方向F2可以为子像素的列方向,在此不作限定。
示例性地,如图6a与图7所示,也可以使第一辅助线610沿第一方向F1延伸,并且第一辅助线610沿第二方向F2排列。在具体实施时,可以使相互对应的驱动信号线110和第一辅助线610在衬底基板100的正投影具有交叠区域,进一步地,可以使驱动信号线110在衬底基板100的正投影覆盖第一辅助线610在衬底基板100的正投影。示例性地,可以使相互对应的驱动信号线110和第一辅助线610在衬底基板100的正投影重叠,可以进一步降低第一辅助线610对显示效果的影响。当然,在一些实施例中,第一辅助线610的延伸长度也可以短于与之对应的驱动信号线110的长度。
示例性地,如图3与图6a所示,多个绑定端子相互间隔排列。例如,可以使绑定端子120沿第二方向F2依次排列。示例性地,可以使绑定端子120沿第二方向F2依次排列于同一直线上。示例性地,可以使相邻的绑定端子120之间的间距大致相同。这样可以统一设计绑定端子120,以使绑定端子120可以均匀设置。
示例性地,如图6a所示,可以以绑定端子120所在区域为界限,显示区AA可以被分为相对于绑定端子120的第一侧C1和第二侧C2;且第一侧C1和第二侧C2沿第一方向F1排列。例如,每个绑定端子120具有中心(例如几何中心),这样以多个绑定端子120的中心的连线为界限,从而显示区AA被分为相对于多个绑定端子120的第一侧C1和第二侧C2。当然,在实际应用中,也可以采用其他方式设置上述界限,在此不作限定。
示例性地,如图6a所示,可以使一个第一辅助线610对应一个第一扇出 线140,一个第一辅助线610对应一个基板过孔200,这样可以使一个第一辅助线610通过一个基板过孔200与一个第一扇出线140对应电连接。
示例性地,如图6a所示,可以使所有的基板过孔200位于绑定端子120所在区域的第一侧C1。当然,在实际应用中,也可以使所有的基板过孔200位于绑定端子120所在区域的第二侧C2,这可以根据实际应用环境来设计确定,在此不作限定。
示例性地,如图6b所示,也可以使一个第一辅助线610对应两个第一扇出线140,一个第一辅助线610对应两个基板过孔200,一个第一扇出线140对应一个基板过孔200,这样可以使一个第一辅助线610通过基板过孔200与两个第一扇出线140对应电连接。其中,可以使同一第一辅助线610对应的一个基板过孔200位于绑定端子120所在区域的第一侧C1,另一个基板过孔200位于绑定端子120所在区域的第二侧C2。这样可以使同一第一辅助线610对应的基板过孔200进行分散设置,并且使一个绑定端子120通过两条第一扇出线140分别电连接至驱动信号线110的不同位置,从而使驱动信号线110各处的电压等电位,进而可以改善由于信号线长度过长而产生的IR Droping。
进一步地,可以使第一过孔711在衬底基板100的正投影与基板过孔200在衬底基板100的正投影不交叠。一般采用刻蚀工艺制备过孔,最好使第一过孔711在衬底基板100的正投影与基板过孔200在衬底基板100的正投影至少部分不交叠,在一种实施例中,二者则可以完全不交叠,从而可以避免形成较深的贯通孔所可能影响后续电连接的稳定性。通常制备基板过孔200的工艺步骤早于制备第一过孔711的工艺步骤,这样可以避免采用刻蚀工艺制备第一过孔711时对基板过孔200造成影响。
示例性地,以显示面板为电致发光显示面板、驱动信号线110为数据线为例进行说明。如图8所示,像素电路中的晶体管132可以包括:栅极1321、与栅极1321绝缘设置的有源层1322、与栅极1321绝缘设置且与有源层1322电连接的源极1323与漏极1324。并且,在晶体管132的源极1323与漏极1324所在层和栅极1321所在层之间还设置有与源极1323和漏极1324均绝缘的金 属电极1325,且金属电极1325在衬底基板100的正投影与栅极1321在衬底基板100的正投影具有交叠区域,该交叠区域形成了像素电路中的存储电容。其中,有源层1322与衬底基板100之间设置有缓冲层311,栅极1321所在层与有源层1322之间设置有栅绝缘层312,栅极1321所在层与金属电极1325所在层之间设置有层间介质层313。金属电极1325所在层和源极1323与漏极1324所在层之间设置有层间绝缘层314。在实际应用中,晶体管的漏极1324与电致发光二极管的阳极通过过孔电连接,用于向阳极提供电压,同时,通过第二电源线向电致发光二极管的阴极加载电压,以使电致发光二极管发光,从而使显示面板实现显示功能。
在本公开的一种实施例中,在衬底基板100采用可挠性材料如塑料或聚酰亚胺的情况下时,在制作显示面板时,可以先提供一个刚性基板01,在该刚性基板01上依次制备绑定端子120,第一扇出线140;再涂覆可挠性材料如包括聚酰亚胺的溶液以形成PI基板100;接着制备第一辅助线610,缓冲层311,有源层1322,栅绝缘层312,栅极1321、栅线,层间介质层313,金属电极1325,层间绝缘层314,源极1323、漏极1324以及驱动信号线110等。当然,本公开实施例仅是以上述描述的制备方法为例进行说明的。本公开提高的显示面板还可以采用其他制备方法制备上述显示面板。
示例性地,结合图5与图8所示,栅线111可以与栅极1321同层同材质设置。这样可以采用同一构图工艺形成栅极1321与栅线111,从而可以降低工艺制备难度。
示例性地,结合图5与图8所示,数据线112可以和源极1323与漏极1324同层同材质设置。这样可以采用同一构图工艺形成数据线112、源极1323与漏极1324,从而可以降低工艺制备难度。进一步地,第一电源线和第二电源线中的至少一个也可以与数据线同层同材质设置。
示例性地,如图8所示,第一绝缘层710可以包括缓冲层311、栅绝缘层312、层间介质层313以及层间绝缘层314。进一步地,显示区AA还可以包括:多个第一连接部411、多个第二连接部412;其中,第一连接部411位于 栅绝缘层312与层间介质层313之间,第二连接部412位于层间介质层313与层间绝缘层314之间。一个数据线112对应至少一个第一连接部411、至少一个第二连接部412以及一个第一辅助线610,并且,该数据线112通过贯穿层间绝缘层314的过孔513与第二连接部412电连接,第二连接部412通过贯穿层间介质层313的过孔512与第一连接部411电连接,第一连接部411通过贯穿栅绝缘层312和缓冲层311的过孔511与第一辅助线610电连接,第一辅助线610通过基板过孔200与第一扇出线140电连接。这样可以实现数据线112与第一扇出线140电连接。这样可以使数据线112依次通过第二连接部412与第一连接部411与第一辅助线610实现电连接。若不设置第一连接部411和第二连接部412,则需要在第一绝缘层710中设置一个过孔,由于第一绝缘层710较厚,那么导致第一绝缘层710的过孔的较深,从而可能会出现数据线与第一辅助线610不能电连接的问题。
示例性地,第一过孔711可以包括:过孔511、过孔512以及过孔513。并且,过孔511在衬底基板100的正投影与过孔512在衬底基板100的正投影不交叠,过孔512在衬底基板100的正投影与过孔513在衬底基板100的正投影不交叠。过孔511在衬底基板100的正投影与基板过孔200在衬底基板100的正投影不交叠。这样可以使数据线112依次通过第二连接部412与第一连接部411与第一辅助线610实现电连接。若不设置第一连接部411和第二连接部412,则需要在第一绝缘层710中设置一个过孔,由于第一绝缘层710较厚,那么导致第一绝缘层710的过孔的较深,从而可能会出现数据线与第一辅助线610不能电连接的问题。
示例性地,如图6a所示,可以使一条数据线对应一个第一过孔711,则一条数据线可以对应一个第一连接部411、一个第二连接部412以及一个第一辅助线610。这样可以降低过孔的设置,提高显示面板的稳定性。
示例性地,如图6a所示,显示区AA可以具有沿第二方向F2的对称轴S0。也就是说,显示区AA可以关于该对称轴S0大致呈轴对称。并且,可以使基板过孔200位于对称轴S0至显示区AA的边缘的区域中。
示例性地,如图6a所示,可以使所有基板过孔200沿第二方向F2排列于一条直线L1上。这样可以降低基板过孔200的设计难度。示例性地,直线L1可以与对称轴S0平行。
示例性地,如图6a所示,可以使所有基板过孔200位于对称轴S0的同一侧且靠近显示区AA的边缘。在实际应用中,常规工艺要求绑定端子120距离显示面板的边缘不超过绑定设备的基台压头的有效移动范围(例如17mm以内),通过将基板过孔200均靠近显示区AA的边缘,这样可以采用常规工艺中的绑定设备即可进行柔性电路板绑定的操作,从而可以不用额外的设计绑定方式。
需要说明的是,由于工艺条件的限制或其他因素,上述各特征中的相同并不能完全相同,可能会有一种偏差,因此上述各特征之间的相同关系只要大致满足上述条件即可,均属于本公开的保护范围。例如,上述相同可以是在误差允许范围之内所允许的相同。
并且,由于工艺条件的限制或其他因素,也并不能使上述不同过孔完全沿第二方向F2排列于一条直线L1上,可能会有一种偏差,因此上述排列于一条直线L1上的关系只要大致满足上述条件即可,均属于本公开的保护范围。
本公开实施例又提供了一种显示面板,结构示意图如图9所示,其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处,其相同之处在此不作赘述。
在具体实施时,在本公开实施例中,如图9所示,可以使相互对应的驱动信号线110与第一辅助线610通过间隔的多个第一过孔711电连接。这样可以使一个驱动信号线110与一个第一辅助线610通过间隔的多个第一过孔711电连接,从而在驱动信号线110和第一辅助线610采用部分第一过孔711不能实现电连接的情况下,还可以使其采用其余第一过孔711实现电连接。
示例性地,第一过孔711可以设置为两个、四个或更多个,这可以根据实际应用环境来设计确定,在此不作限定,如此,驱动信号线110与第一辅助线610相当于并联,从而可以降低驱动信号线110的电阻,进而提高信号 的传输率。
示例性地,在具体实施时,在本公开实施例中,如图9所示,针对同一驱动信号线110对应的第一过孔711,可以使每相邻的两个第一过孔711之间的间距相同。这样可以使第一过孔711均匀设计,进一步提高显示面板的稳定性。
示例性地,在具体实施时,在本公开实施例中,如图9所示,可以使每相邻的驱动信号线110对应的第一过孔711沿第二方向F2排列于一条直线L1上,进一步提高显示面板的稳定性。
示例性地,在具体实施时,在本公开实施例中,也可以使每相邻的驱动信号线110对应的第一过孔711错位排列。这样可以进一步使第一过孔711均匀分散设计,进一步提高显示面板的稳定性。
本公开实施例又提供了一种显示面板,结构示意图如图10所示,其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处,其相同之处在此不作赘述。
示例性地,可以使一个驱动信号线110对应一个基板过孔200,在具体实施时,在本公开实施例中,如图10所示,可以使所有基板过孔200位于对称轴S0处。由于在制备显示面板时,需要对衬底基板100进行切割(例如激光切割或刀轮切割),在切割时会对过孔产生热影响或应力影响,从而导致基板过孔200出现不良,进而导致信号线之间的电连接出现不良问题。本公开通过将基板过孔200设置在对称轴S0处,则可以使基板过孔200位于显示区AA的中间行,可以避免切割造成的影响。
并且,由于基板过孔200设置在对称轴S0处,第一辅助线610相当于也关于对称轴S0呈大致对称图形,这样相当于第一扇出线140传输的信号到第一辅助线610的两端的电阻减少了一半,从而可以有效减小IR Drop(压降),提升显示的均一性。
本公开实施例又提供了一种显示面板,结构示意图如图11与图12所示,其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实 施例的区别之处,其相同之处在此不作赘述。
在具体实施时,在本公开实施例中,结合图11与图12所示,可以使各绑定端子120在衬底基板100的正投影与对应的基板过孔200在衬底基板100的正投影之间的距离大致相同。考虑到第一扇出线140的电阻的差异,通过将基板过孔200错落开孔,使较长的第一扇出线140对应的基板过孔200靠近绑定端子120所在区域对应的子像素行,使较短的第一扇出线140对应的基板过孔200远离绑定端子120所在区域对应的子像素行,以使绑定端子120输入的信号可以通过电阻大致相同的第一扇出线140,传输给每一个驱动信号线110,从而使传输到驱动信号线110上的电压大致相同,进而可以提高显示均一性。
在具体实施时,在本公开实施例中,如图11与图12所示,绑定端子120所在区域可以具有相对的第一侧C1和第二侧C2;且第一侧C1和第二侧C2沿第一方向F1排列。其中,可以使多个基板过孔200位于第一侧C1和第二侧C2中的至少一侧。示例性地,如图11所示,可以使所有基板过孔200位于第一侧C1。这样可以统一设置上述基板过孔200。
示例性地,在具体实施时,在本公开实施例中,如图12所示,也可以使多个基板过孔200中的部分基板过孔200位于第一侧C1,多个基板过孔200中的其余部分基板过孔200位于第二侧C2。这样可以将基板过孔200进一步分散,从而进一步提高显示面板的稳定性。
示例性地,在具体实施时,在本公开实施例中,如图12所示,沿第二方向F2上的第奇数个第一扇出线140对应的基板过孔200位于第一侧C1,第偶数个第一扇出线140对应的基板过孔200位于第二侧C2。这样可以进一步增大相邻的第一扇出线140对应的基板过孔200之间的距离,进一步提高显示面板的稳定性。
本公开实施例又提供了一种显示面板,结构示意图如图13至图16所示,其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处,其相同之处在此不作赘述。
在具体实施时,在本公开实施例中,如图13与图14所示,显示面板还可以包括:位于第一扇出线140所在层与衬底基板100之间第二绝缘层720,位于第二绝缘层720与衬底基板100之间的多个第二辅助线620。其中,第二绝缘层720具有多个第二过孔721,一个驱动信号线110通过基板过孔200与一个第二辅助线620对应电连接,以及,一个第二辅助线620通过第二过孔721与一个第一扇出线140对应电连接。
在具体实施时,在本公开实施例中,如图13与图15所示,相互对应的驱动信号线110和第二辅助线620在衬底基板100的正投影重叠。这样可以降低第二辅助信号线对显示效果的影响,提高显示效果。
示例性地,在具体实施时,在本公开实施例中,如图13所示,可以使一个第二辅助线620对应一个驱动信号线110,一个第二辅助线620对应一个基板过孔200,从而可以使相互对应的驱动信号线110与第二辅助线620通过一个基板过孔200电连接。这样可以使基板过孔200设置的较少,提高显示面板的稳定性。
示例性地,在具体实施时,在本公开实施例中,如图15所示,可以使一个第二辅助线620对应一个驱动信号线110,一个第二辅助线620对应多个基板过孔200,从而可以使相互对应的驱动信号线110与第二辅助线620通过间隔的多个基板过孔200电连接。这样可以使一个驱动信号线110与一个第二辅助线620通过间隔的多个基板过孔200电连接,从而在驱动信号线110和第二辅助线620采用部分基板过孔200不能实现电连接的情况下,还可以使其采用其余基板过孔200实现电连接。并且,这可以使驱动信号线110与第二辅助线620相当于并联,从而可以降低驱动信号线110的电阻,进而提高信号的传输率。
示例性地,基板过孔200可以设置为两个、四个或更多个,这可以根据实际应用环境来设计确定,在此不作限定。
示例性地,在具体实施时,在本公开实施例中,如图15所示,针对同一驱动信号线110对应的基板过孔200,可以使每相邻的两个基板过孔200之间 的间距相同。这样可以使基板过孔200均匀设计,可以进一步提高显示面板的稳定性。
示例性地,在具体实施时,在本公开实施例中,如图15所示,可以使每相邻的驱动信号线110对应的基板过孔200沿第二方向F2排列于一条直线L1上。这样可以使基板过孔200统一设计,进一步提高显示面板的稳定性。
示例性地,在具体实施时,在本公开实施例中,如图16所示,也可以使每相邻的驱动信号线110对应的基板过孔200错位排列。示例性地,以相邻的两个驱动信号线110对应的基板过孔200为例,一个驱动信号线110的过孔与另一个驱动信号端的过孔之间的间隙相对应。这样可以使基板过孔200进一步均匀分散设置,进一步提高显示面板的稳定性。
示例性地,可以使一个驱动信号线110对应一个第二过孔721,在具体实施时,在本公开实施例中,如图15所示,可以使所有第二过孔721位于对称轴S0。由于在制备显示面板时,需要对衬底基板100进行切割(例如激光切割或刀轮切割),在切割时会对过孔产生热影响或应力影响,从而导致第二过孔721出现不良,进而导致信号线之间的电连接出现不良问题。本公开通过将第二过孔721设置在对称轴S0处,则可以使第二过孔721位于显示区AA的中间行,可以避免切割造成的影响。
并且,由于第二过孔721设置在对称轴S0处,第二辅助线620相当于也关于对称轴S0呈大致对称图形,这样相当于第二扇出线150传输的信号到第二辅助线620的两端的电阻减少了一半,从而可以有效减小IR Drop(压降),提升显示的均一性。
本公开实施例又提供了一种显示面板,结构示意图如图17与图18所示,其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处,其相同之处在此不作赘述。
在具体实施时,在本公开实施例中,如图17与图18所示,显示区AA还可以包括:位于驱动信号线110所在层与衬底基板100之间的多个第二扇出线150,位于驱动信号线110所在层与第二扇出线150所在层之间的第三绝 缘层730。其中,第三绝缘层730具有多个第三过孔731;一个驱动信号线110可以对应一个第二扇出线150,一个第二扇出线150可以对应一个绑定端子120。也就是说,一个驱动信号线110通过第三过孔731与一个第二扇出线150对应电连接,一个第二扇出线150通过基板过孔200与一个绑定端子120电连接。
示例性地,在具体实施时,在本公开实施例中,如图17与图18所示,显示区AA还可以包括:位于第三绝缘层730与驱动信号线110所在层之间的多条第一辅助线610,以及位于第一辅助线610所在层与驱动信号线110所在层之间的第一绝缘层710。需要说明的是,第一辅助线610和第一绝缘层710的实施方式可以参见上述实施例,在此不作赘述。
示例性地,在具体实施时,在本公开实施例中,如图17与图18所示,一个驱动信号线110可以对应一个第一辅助线610,一个第一辅助线610对应一个第二扇出线150,也就是说,一个驱动信号线110通过第一过孔711与一个第一辅助线610对应电连接,一个第一辅助线610通过第三过孔731与一个第二扇出线150对应电连接,一个第二扇出线150通过基板过孔200与一个绑定端子120电连接。
示例性地,在具体实施时,在本公开实施例中,如图17与图18所示,可以使一个第一辅助线610对应一个第三过孔731。其中,可以使第三过孔731沿第二方向F2排列于一条直线L1上。或者,也可以使,第三过孔731分散设置,以提高衬底基板100的稳定性。
示例性地,在具体实施时,在本公开实施例中,也可以使基板过孔200在衬底基板100的正投影与第三过孔731在衬底基板100的正投影之间的距离大致相同,从而可以降低第二扇出线150的电阻差异性,降低输入到第一辅助线610的信号的延迟的差异性。
基于同一发明构思,本公开实施例还提供了一种显示装置,包括本公开实施例提供的上述显示面板。该显示装置解决问题的原理与前述显示面板相似,因此该显示装置的实施可以参见前述显示面板的实施,重复之处在此不 再赘述。
在具体实施时,在本公开实施例中,显示装置可以为:手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的,在此不做赘述,也不应作为对本公开的限制。
显然,本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样,倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内,则本公开也意图包含这些改动和变型在内。
Claims (23)
- 一种显示面板,包括:衬底基板,包括位于所述显示面板的显示区的多个基板过孔;多个驱动信号线和多个绑定端子,分别位于所述衬底基板的不同表面;所述多个驱动信号线中的至少一个通过所述基板过孔与所述多个绑定端子中的至少一个电连接。
- 如权利要求1所述的显示面板,其中,所述显示区还包括:多个第一扇出线,位于所述衬底基板背离所述驱动信号线一侧;所述多个第一扇出线中的一个所述第一扇出线与所述多个绑定端子中的一个绑定端子电连接;一个所述驱动信号线通过所述基板过孔与至少一个所述第一扇出线对应电连接。
- 如权利要求2所述的显示面板,其中,所述显示区还包括:第一绝缘层,位于所述驱动信号线所在层与所述衬底基板之间,且所述第一绝缘层具有多个第一过孔;多个第一辅助线,位于所述第一绝缘层与所述衬底基板之间;一个所述驱动信号线通过所述第一过孔与一个所述第一辅助线对应电连接,一个所述第一辅助线通过所述基板过孔与至少一个所述第一扇出线对应电连接。
- 如权利要求3所述的显示面板,其中,相互对应的驱动信号线和第一辅助线在衬底基板的正投影至少部分重叠,且相互对应的所述驱动信号线与所述第一辅助线通过间隔的多个所述第一过孔电连接。
- 如权利要求4所述的显示面板,其中,针对同一所述驱动信号线对应的第一过孔,每相邻的两个所述第一过孔之间的间距相同。
- 如权利要求5所述的显示面板,其中,所述多个绑定端子的每一个在所述衬底基板的正投影与对应的所述基板过孔在所述衬底基板的正投影之间 的距离大致相同。
- 如权利要求6所述的显示面板,其中,所述多个绑定端子沿第二方向依次间隔排列,以所述多个绑定端子所在区域为界限,所述显示区被所述多个绑定端子分为相对的第一侧和第二侧;且所述第一侧和所述第二侧沿所述第一方向排列;所述多个基板过孔位于所述第一侧和所述第二侧中的至少一侧。
- 如权利要求7所述的显示面板,其中,所述多个基板过孔中的部分基板过孔位于所述第一侧,所述多个基板过孔中的其余部分基板过孔位于所述第二侧。
- 如权利要求8所述的显示面板,其中,沿所述第二方向上的第奇数个第一扇出线对应的基板过孔位于所述第一侧,第偶数个第一扇出线对应的基板过孔位于所述第二侧。
- 如权利要求2-5任一项所述的显示面板,其中,一个所述第一扇出线对应一个所述基板过孔,一个所述第一辅助线通过所述基板过孔与两个所述第一扇出线对应电连接;同一所述第一辅助线对应的一个基板过孔位于所述多个绑定端子所在区域的第一侧,另一个基板过孔位于所述多个绑定端子所在区域的第二侧。
- 如权利要求2所述的显示面板,其中,所述显示面板还包括:第二绝缘层,位于所述第一扇出线所在层与所述衬底基板之间,且所述第二绝缘层具有多个第二过孔;多个第二辅助线,位于所述第二绝缘层与所述衬底基板之间;一个所述驱动信号线通过所述基板过孔与一个所述第二辅助线对应电连接;一个所述第二辅助线通过所述第二过孔与一个所述第一扇出线对应电连接。
- 如权利要求11所述的显示面板,其中,相互对应的驱动信号线和第二辅助线在衬底基板的正投影重叠,且相互对应的所述驱动信号线与所述第 二辅助线通过间隔的多个所述基板过孔电连接。
- 如权利要求12所述的显示面板,其中,针对同一所述驱动信号线对应的基板过孔,每相邻的两个所述基板过孔之间的间距相同。
- 如权利要求11-13任一项所述的显示面板,其中,每相邻的所述驱动信号线对应的基板过孔沿第二方向排列于一条直线上。
- 如权利要求11-13任一项所述的显示面板,其中,每相邻的所述驱动信号线对应的基板过孔错位排列。
- 如权利要求11-13任一项所述的显示面板,其中,所述驱动信号线沿第一方向延伸,所述显示区具有沿第二方向的对称轴;所述第一方向与所述第二方向不同;所有所述第二过孔位于所述显示区的对称轴。
- 如权利要求1所述的显示面板,其中,所述显示区还包括:多个第二扇出线,位于所述驱动信号线所在层与所述衬底基板之间;第三绝缘层,位于所述驱动信号线所在层与所述第二扇出线所在层之间,且所述第三绝缘层具有多个第三过孔;一个所述驱动信号线通过所述第三过孔与一个所述第二扇出线对应电连接,一个所述第二扇出线通过所述基板过孔与一个所述多个绑定端子中的一个电连接。
- 如权利要求2-5以及17任一项所述的显示面板,其中,所述驱动信号线沿第一方向延伸,所述显示区具有沿第二方向的对称轴;所述第一方向与所述第二方向不同;一个所述驱动信号线对应一个所述基板过孔,所述基板过孔位于所述对称轴至所述显示区的边缘的区域中。
- 如权利要求18所述的显示面板,其中,所有所述基板过孔沿所述第二方向排列于一条直线上。
- 如权利要求18或19所述的显示面板,其中,所有所述基板过孔位于所述对称轴的同一侧且靠近所述显示区的边缘。
- 如权利要求18或19所述的显示面板,其中,所有所述基板过孔位 于所述对称轴。
- 如权利要求1-21任一项所述的显示面板,其中,所述驱动信号线包括数据线、第一电源线以及第二电源线中的至少一种。
- 一种显示装置,其中,包括如权利要求1-22任一项所述的显示面板。
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PCT/CN2020/071545 WO2021138920A1 (zh) | 2020-01-10 | 2020-01-10 | 显示面板及显示装置 |
US17/281,709 US11537018B2 (en) | 2020-01-10 | 2020-01-10 | Display panel and display device |
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CN114049843A (zh) * | 2021-11-17 | 2022-02-15 | 合肥维信诺科技有限公司 | 显示模组及显示装置 |
CN114067694A (zh) * | 2021-12-08 | 2022-02-18 | Tcl华星光电技术有限公司 | 显示母板及其制备方法 |
WO2023159511A1 (zh) * | 2022-02-25 | 2023-08-31 | 京东方科技集团股份有限公司 | 显示基板及其制备方法、显示装置 |
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CN114171563B (zh) * | 2021-11-30 | 2023-07-04 | 武汉华星光电半导体显示技术有限公司 | 显示面板和显示装置 |
CN114188381B (zh) * | 2021-12-03 | 2023-05-09 | 武汉华星光电半导体显示技术有限公司 | 显示面板及显示装置 |
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US20230071948A1 (en) | 2023-03-09 |
EP4089733A1 (en) | 2022-11-16 |
US11537018B2 (en) | 2022-12-27 |
CN113454782A (zh) | 2021-09-28 |
EP4089733A4 (en) | 2022-12-28 |
US20230418122A1 (en) | 2023-12-28 |
US20220121072A1 (en) | 2022-04-21 |
US11796877B2 (en) | 2023-10-24 |
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