WO2020093442A1 - Procédé de fabrication de substrat de réseau et substrat de réseau - Google Patents

Procédé de fabrication de substrat de réseau et substrat de réseau Download PDF

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Publication number
WO2020093442A1
WO2020093442A1 PCT/CN2018/116043 CN2018116043W WO2020093442A1 WO 2020093442 A1 WO2020093442 A1 WO 2020093442A1 CN 2018116043 W CN2018116043 W CN 2018116043W WO 2020093442 A1 WO2020093442 A1 WO 2020093442A1
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WO
WIPO (PCT)
Prior art keywords
array substrate
photoresist
common electrode
transparent conductive
film
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PCT/CN2018/116043
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English (en)
Chinese (zh)
Inventor
朱茂霞
徐洪远
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Publication of WO2020093442A1 publication Critical patent/WO2020093442A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods

Definitions

  • the present invention relates to the field of display technology, and in particular, to an array substrate manufacturing method and an array substrate.
  • LCD liquid crystal displays
  • other flat display devices have been widely used in mobile phones, TVs, and individuals due to their advantages of high image quality, power saving, thin body, and wide application range.
  • Various consumer electronic products such as digital assistants, digital cameras, notebook computers, and desktop computers have become the mainstream in display devices.
  • liquid crystal display devices which include a liquid crystal display panel and a backlight module.
  • the working principle of the liquid crystal display panel is to place liquid crystal molecules in two parallel glass substrates. There are many vertical and horizontal small wires between the two glass substrates.
  • the liquid crystal molecules can be controlled to change the direction by turning on or off, and the light of the backlight module Refracted to produce a picture.
  • the liquid crystal display panel is composed of a color filter substrate (CF, Color), an array substrate (TFT, Thin Film Transistor), a liquid crystal (LC, Liquid) and a sealant frame (Sealant) sandwiched between the color filter substrate and the array substrate Composition
  • the molding process generally includes: the front-end array process (thin film, yellow light, etching and stripping), the middle-stage cell process (the TFT substrate is bonded to the CF substrate), and the rear-stage module assembly process ( The driver IC is pressed against the printed circuit board).
  • the front stage Array process is mainly to form a TFT substrate to facilitate the control of the movement of liquid crystal molecules;
  • the middle stage Cell process is mainly to add liquid crystal between the TFT substrate and the CF substrate;
  • the rear stage module assembly process is mainly to drive the IC pressing and printed circuit The integration of the board then drives the liquid crystal molecules to rotate and display images.
  • Existing array substrates generally include: a substrate substrate, a grid electrode arranged on the substrate substrate at intervals and an array substrate common electrode (Array Com, Acom), a common electrode provided on the substrate substrate, the gate electrode and the array substrate A gate insulating layer on the electrode, an active layer provided on the gate insulating layer on the gate, a source provided on the active layer and in contact with both ends of the active layer, and A drain, a passivation layer provided on the gate insulating layer, the active layer, the source and the drain, and a pixel electrode provided on the passivation layer and electrically connected to the drain, wherein
  • the gate and the common electrode of the array substrate are located on the same film layer and are made of opaque metal materials, and the aperture ratio is low.
  • the object of the present invention is to provide a method for manufacturing an array substrate, which can increase the pixel aperture ratio without increasing the number of photomasks.
  • the object of the present invention is also to provide an array substrate which can increase the pixel aperture ratio and improve the display effect.
  • the present invention provides a method for manufacturing an array substrate, including the following steps:
  • Step S1 Provide a base substrate on which a transparent conductive film and a metal film covering the transparent conductive film are formed;
  • Step S2 covering the metal film with a photoresist film
  • Step S3 patterning the photoresist film to remove the photoresist film except for the area where the gate and the common electrode of the array substrate are to be formed, to obtain the first photoresist segment on the area where the gate is to be formed Forming a second photoresist segment on the area of the common electrode of the array substrate, and the thickness of the first photoresist segment is greater than that of the second photoresist segment;
  • Step S4 Using the first photoresist section and the second photoresist section as shields, the transparent conductive film and the metal film are etched to remove the transparent conductive film and metal except for the area where the gate and the common electrode of the array substrate are to be formed film;
  • Step S5 Remove the second photoresist segment while thinning the first photoresist segment, etch the metal film with the remaining first photoresist segment as a shield, remove the metal film on the area where the common electrode of the array substrate is to be formed, to obtain an array substrate Common electrode
  • Step S6 Remove the remaining first photoresist segment to obtain the gate
  • Step S7 forming a gate insulating layer on the base electrode, the gate and the common electrode of the array substrate, forming an active layer on the gate insulating layer on the gate, and forming a separate layer on the active layer
  • a source electrode and a drain electrode located at both ends of the active layer are formed with a passivation layer on the gate insulating layer, the active layer, the source electrode and the drain electrode, and a pixel electrode is formed on the passivation layer.
  • the photoresist film is patterned by a half-tone mask or a gray-scale mask.
  • the process of etching the transparent conductive film and the metal film in step S4 includes:
  • the second etching is performed to remove the transparent conductive film except for the area where the gate and the common electrode of the array substrate are to be formed.
  • the metal film is etched with copper acid; in the second etching, the transparent conductive film is etched with oxalic acid.
  • the metal film is etched by using hydrogen peroxide copper acid to remove the metal film on the area where the common electrode of the array substrate is to be formed while retaining the transparent conductive film on the area where the common electrode of the array substrate is to be formed.
  • the second photoresist segment and the first photoresist segment are ashed through an oxygen plasma process to remove the second photoresist segment and thin the first photoresist segment at the same time.
  • step S6 a photoresist stripping solution is used to remove the remaining first photoresist segment.
  • the material of the transparent conductive film is indium tin oxide.
  • the invention also provides an array substrate, comprising: a base substrate, a grid electrode arranged on the base substrate at intervals and a common electrode of the array substrate, a common electrode arranged on the base substrate, the gate and the array substrate A gate insulating layer on the top, an active layer provided on the gate insulating layer on the gate, a source and a drain provided on the active layer and located at both ends of the active layer, A passivation layer provided on the gate insulating layer, active layer, source and drain, and a pixel electrode provided on the passivation layer;
  • the common electrode of the array substrate is a transparent electrode
  • the gate includes a transparent conductive portion provided on the same layer as the common electrode of the array substrate and a metal conductive portion laminated on the transparent conductive portion.
  • the material of the common electrode and the transparent conductive part of the array substrate is indium tin oxide.
  • the present invention provides a method for manufacturing an array substrate.
  • the method first forms a transparent conductive film and a metal film covering the transparent conductive film on a base substrate, and patterns the transparent through a mask
  • the conductive thin film and the metal thin film form the gate formed by the transparent conductive thin film and the metal thin film and the common electrode of the array substrate formed by the transparent conductive film.
  • the common electrode of the transparent array substrate can improve the pixel aperture ratio.
  • the display effect is improved, and the gate electrode and the common electrode of the array substrate are still made by one mask, without increasing the number of masks, and the manufacturing cost is low.
  • the invention also provides an array substrate, which can increase the pixel aperture ratio and improve the display effect.
  • step S1 is a schematic diagram of step S1 of the method for manufacturing an array substrate of the present invention
  • step S2 is a schematic diagram of step S2 of the method for manufacturing an array substrate of the present invention
  • step S3 is a schematic diagram of step S3 of the method for manufacturing an array substrate of the present invention.
  • step S4 is a schematic diagram of step S4 of the method for manufacturing an array substrate of the present invention.
  • step S5 of the method for manufacturing an array substrate of the present invention are schematic diagrams of step S5 of the method for manufacturing an array substrate of the present invention.
  • step S6 is a schematic diagram of step S6 of the method for manufacturing an array substrate of the present invention.
  • step S7 of the method for manufacturing an array substrate of the present invention are schematic diagrams of step S7 of the method for manufacturing an array substrate of the present invention.
  • FIG. 11 is a flowchart of a method for manufacturing an array substrate of the present invention.
  • the present invention provides a method for manufacturing an array substrate, including the following steps:
  • Step S1 As shown in FIG. 1, a base substrate 1 is provided, on which a transparent conductive film 101 and a metal film 102 covering the transparent conductive film 101 are formed.
  • the base substrate 1 is a transparent substrate, preferably a glass substrate.
  • the step S1 specifically includes first depositing a layer of transparent conductive film 101 on the base substrate 1, and then depositing a layer of metal film 102 on the transparent conductive film 101.
  • the material of the transparent conductive film 101 is indium tin oxide
  • the material of the metal film 102 is one or a combination of molybdenum, aluminum, titanium, and copper.
  • Step S2 As shown in FIG. 2, a photoresist film 103 is covered on the metal film 102.
  • the mask film 103 is formed on the metal film 102 by a coating process.
  • Step S3 pattern the photoresist film 103 to remove the photoresist film 103 except for the area where the gate electrode and the common electrode 3 of the array substrate are to be formed to obtain the area where the gate electrode is to be formed
  • the photoresist film 103 is patterned by a half tone mask (HTM) or a gray tone mask (GTM).
  • HTM half tone mask
  • GTM gray tone mask
  • the first photoresist segment 104 is formed by not exposing or completely exposing the photoresist film 103 on the area where the gate electrode is to be formed, and for the area where the common electrode of the array substrate is to be formed
  • the photoresist film 103 on the top is half-exposed to form a second photoresist segment 105, and the photoresist film 103 in the remaining area is completely exposed or not exposed to remove the photoresist film 103 in the remaining area after development.
  • Step S4 As shown in FIG. 4, using the first photoresist section 104 and the second photoresist section 105 as shields, the transparent conductive film 101 and the metal film 102 are etched, except for removing the common gate electrode and array substrate to be formed The transparent conductive film 101 and the metal film 102 outside the area of the electrode 3.
  • the process of etching the transparent conductive film 101 and the metal film 102 in the step S4 includes: performing the first etching to remove the metal film 102 except for the area where the gate and the common electrode 3 of the array substrate are to be formed ; Perform a second etching to remove the transparent conductive film 101 except for the area where the gate and the common electrode 3 of the array substrate are to be formed.
  • the metal film 102 is etched with copper acid; in the second etching, the transparent conductive film 101 is etched with oxalic acid.
  • Step S5 As shown in FIGS. 5 and 6, the second photoresist segment 105 is removed while the first photoresist segment 104 is thinned, and the metal thin film 102 is etched with the remaining first photoresist segment 104 as a shield to remove the to-be-formed
  • the metal thin film 102 on the area of the common electrode of the array substrate obtains the common electrode 3 of the array substrate.
  • the second photoresist segment 105 and the first photoresist segment 104 are ashed by an oxygen plasma process (O 2 Plasma) to remove the second photoresist segment 105 while thinning the first Photoresist section 104
  • O 2 Plasma oxygen plasma process
  • the metal film 102 is etched by using hydrogen peroxide copper acid to remove the metal film 102 on the area where the common electrode of the array substrate is to be formed while retaining the transparent conductive film 101 on the area where the common electrode of the array substrate is to be formed .
  • etching by the hydrogen peroxide copper acid can avoid etching the transparent conductive film 101 while etching the metal film 102, so as to retain the transparent conductive film 101 on the area where the common electrode of the array substrate is to be formed , For forming the common electrode 3 of the array substrate.
  • Step S6 As shown in FIG. 7, the remaining first photoresist segment 104 is removed to obtain the gate 2.
  • the step S6 uses a photoresist stripping solution to remove the remaining first photoresist segment 104.
  • Step S7 As shown in FIGS. 8 to 10, a gate insulating layer 4 is formed on the base substrate 1, the gate 2 and the common electrode 3 of the array substrate, and the gate insulating layer 4 on the gate 2 An active layer 5 is formed thereon, and a source electrode 6 and a drain electrode 7 located at both ends of the active layer 5 are formed on the active layer 5, and the gate insulating layer 4, the active layer 5, and the source A passivation layer 8 is formed on the electrode 6 and the drain 7, and a pixel electrode 9 is formed on the passivation layer 8.
  • step S7 specifically includes:
  • a gate insulating layer 4 is first deposited on the base substrate 1, the gate 2 and the common electrode 3 of the array substrate;
  • a semiconductor film is deposited on the gate insulating layer 4 and a metal film is deposited on the semiconductor film, and the semiconductor film and the metal film are simultaneously patterned through a mask to obtain Source layer 5, source electrode 6 and drain electrode 7.
  • the photomask patterning the semiconductor film and the metal film is a gray-scale photomask or a half-tone photomask.
  • a passivation layer 8 is then deposited on the gate insulating layer 4, the active layer 5, the source electrode 6 and the drain electrode 7, and the passivation layer 8 is patterned by a mask , A via 91 is formed through the passivation layer 8, the via 91 exposes a portion of the drain 7;
  • a transparent conductive film is finally formed on the passivation layer 8, and the transparent conductive film is patterned by a mask to form a pixel electrode 9, and the pixel electrode 9 passes through the via 91 is electrically connected to the drain 7.
  • the materials of the gate insulating layer 4 and the passivation layer 8 are one or a combination of silicon nitride and silicon oxide, and the material of the active layer 5 may be amorphous silicon or polysilicon Or a metal oxide semiconductor, the material of the source electrode 6 and the drain electrode 7 is a combination of one or more of molybdenum, aluminum, titanium, and copper, and the material of the pixel electrode 9 is indium tin oxide.
  • the manufacturing method of the present invention can make an array substrate through 4 masks, and the array substrate has a transparent array substrate common electrode, which can increase the pixel aperture ratio and improve the display effect, and the number of masks required for manufacturing is small, The production cost is lower.
  • the present invention also provides an array substrate, including: a base substrate 1, spaced-apart gates 2 provided on the base substrate 1 and a common electrode 3 of the array substrate, provided on the substrate The substrate 1, the gate 2 and the gate insulating layer 4 on the common electrode 3 of the array substrate, the active layer 5 provided on the gate insulating layer 4 on the gate 2, and the active layer 5 provided on the active layer 5 And the source electrode 6 and the drain electrode 7 located at both ends of the active layer 5, the passivation layer 8 provided on the gate insulating layer 4, the active layer 5, the source electrode 6 and the drain electrode 7, and the device The pixel electrode 9 on the passivation layer 8;
  • the array substrate common electrode 3 is a transparent electrode
  • the gate 2 includes a transparent conductive portion 21 provided in the same layer as the array substrate common electrode 3 and a metal conductive portion 22 stacked on the transparent conductive portion 21.
  • the materials of the array substrate common electrode 3 and the transparent conductive portion 21 are indium tin oxide.
  • a via hole 91 penetrating the passivation layer 8 and exposing a part of the drain 7 is formed on the passivation layer 8, and the pixel electrode 9 is electrically connected to the drain 7 through the via 91 Sexual connection.
  • the array substrate is made by four photomasks, wherein the array substrate common electrode 3 and the gate electrode 2 are made by a first photomask, and the active layer 5, the source electrode 6 and the drain electrode 7 It is made by a second mask, the via 91 is made by a third mask, and the pixel electrode 9 is made by a fourth mask.
  • the first mask and the second mask are both gray-scale masks or half-tone masks.
  • the materials of the gate insulating layer 4 and the passivation layer 8 are one or a combination of silicon nitride and silicon oxide, and the material of the active layer 5 may be amorphous silicon or polysilicon Or metal oxide semiconductor, the material of the metal conductive portion 22, the source electrode 6 and the drain electrode 7 is one or more combinations of molybdenum, aluminum, titanium and copper, the common electrode 3 of the array substrate, transparent conductive
  • the material of the portion 21 and the pixel electrode 9 is indium tin oxide.
  • the array substrate of the present invention has a transparent array substrate common electrode, which can increase the pixel aperture ratio and improve the display effect, and the number of masks required for manufacturing is small, and the manufacturing cost is low.
  • the present invention provides a method for manufacturing an array substrate.
  • the method first forms a transparent conductive film and a metal film covering the transparent conductive film on a base substrate, and patterns the transparent conductive film through a mask Thin film and metal film, forming the grid formed by the transparent conductive film and the metal film and the common electrode of the array substrate formed by the transparent conductive film.
  • the common electrode of the transparent array substrate can improve the pixel aperture ratio and improve Display effect, and the grid and the common electrode of the array substrate are still made by one mask, without increasing the number of masks, and the manufacturing cost is low.
  • the invention also provides an array substrate, which can increase the pixel aperture ratio and improve the display effect.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Liquid Crystal (AREA)

Abstract

La présente invention concerne un procédé de fabrication d'un substrat de réseau et un substrat de réseau. Le procédé de fabrication d'un substrat de réseau comprend les étapes consistant à : former en premier lieu, sur un substrat de base (1), un film mince conducteur transparent (101) et un film mince métallique (102) recouvrant le film mince conducteur transparent (101), et former des motifs, au moyen d'un photomasque, sur le film mince conducteur transparent (101) et le film mince métallique (102) pour former une électrode grille (2) formée par le film mince conducteur transparent (101) et le film mince métallique (102) et une électrode commune de substrat de réseau (3) formée par le film mince conducteur transparent (101). L'électrode commune de substrat de réseau transparent (3) peut augmenter le rapport d'ouverture de pixel et améliorer l'effet d'affichage, et l'électrode grille (2) et l'électrode commune de substrat de réseau (3) sont toujours uniquement fabriqués à partir d'un photomasque, sans augmenter la quantité de photomasques, et par conséquent, le coût de fabrication est relativement faible.
PCT/CN2018/116043 2018-11-07 2018-11-16 Procédé de fabrication de substrat de réseau et substrat de réseau WO2020093442A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201811320935.2 2018-11-07
CN201811320935.2A CN109616443A (zh) 2018-11-07 2018-11-07 阵列基板的制作方法及阵列基板

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WO2020093442A1 true WO2020093442A1 (fr) 2020-05-14

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CN111081737A (zh) * 2019-12-05 2020-04-28 深圳市华星光电半导体显示技术有限公司 一种阵列基板制备方法及阵列基板
CN115280231B (zh) * 2021-02-26 2023-11-03 京东方科技集团股份有限公司 阵列基板及其制备方法、显示面板、显示装置
CN113690181B (zh) * 2021-08-19 2024-03-12 昆山龙腾光电股份有限公司 Tft阵列基板及其制作方法
CN113725157B (zh) * 2021-08-27 2024-03-12 昆山龙腾光电股份有限公司 阵列基板及其制作方法

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US20040041954A1 (en) * 2002-09-03 2004-03-04 Toppoly Optoelectronics Corp. Method of fabricating liquid crystal display devices integrated with driving circuit
CN102544029A (zh) * 2012-02-07 2012-07-04 深圳市华星光电技术有限公司 一种薄膜晶体管阵列基板及其制作方法
CN102543864A (zh) * 2012-02-07 2012-07-04 深圳市华星光电技术有限公司 一种薄膜晶体管阵列基板及其制作方法
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US20040041954A1 (en) * 2002-09-03 2004-03-04 Toppoly Optoelectronics Corp. Method of fabricating liquid crystal display devices integrated with driving circuit
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CN102544029A (zh) * 2012-02-07 2012-07-04 深圳市华星光电技术有限公司 一种薄膜晶体管阵列基板及其制作方法
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