WO2017147974A1 - Procédé de fabrication de panneau de réseau et panneau de réseau ainsi fabriqué - Google Patents

Procédé de fabrication de panneau de réseau et panneau de réseau ainsi fabriqué Download PDF

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WO2017147974A1
WO2017147974A1 PCT/CN2016/078878 CN2016078878W WO2017147974A1 WO 2017147974 A1 WO2017147974 A1 WO 2017147974A1 CN 2016078878 W CN2016078878 W CN 2016078878W WO 2017147974 A1 WO2017147974 A1 WO 2017147974A1
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layer
hole
source
drain
passivation layer
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PCT/CN2016/078878
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English (en)
Chinese (zh)
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甘启明
王勐
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深圳市华星光电技术有限公司
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Priority to US15/105,582 priority Critical patent/US10103173B2/en
Publication of WO2017147974A1 publication Critical patent/WO2017147974A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13625—Patterning using multi-mask exposure

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating an array substrate and an array substrate obtained.
  • LCDs liquid crystal displays
  • Various consumer electronic products such as digital assistants, digital cameras, notebook computers, and desktop computers have become mainstream in display devices.
  • liquid crystal display devices which include a liquid crystal display panel and a backlight module.
  • the working principle of the liquid crystal display panel is to place liquid crystal molecules in two parallel glass substrates. There are many vertical and horizontal small wires between the two glass substrates, and the liquid crystal molecules are controlled to change direction by energizing or not, and the light of the backlight module is changed. Refracted to produce a picture.
  • the liquid crystal display panel comprises a CF (Color Filter) substrate, a Thin Film Transistor (TFT) array substrate, a liquid crystal (LC) sandwiched between the color filter substrate and the thin film transistor array substrate, and a sealant.
  • CF Color Filter
  • TFT Thin Film Transistor
  • LC liquid crystal sandwiched between the color filter substrate and the thin film transistor array substrate
  • sealant a sealant.
  • the composition of the box (Sealant).
  • FIG. 1 is a schematic diagram of a method for fabricating an array substrate according to the prior art.
  • the method for fabricating the array substrate includes the following steps:
  • Step 1 providing a base substrate 100, sequentially forming a gate (not shown), a gate insulating layer 200, an active layer (not shown), and a source/drain 300 on the base substrate 100;
  • Step 2 forming a first passivation layer 400 on the source/drain 300 and the gate insulating layer 200, and patterning the first passivation layer 400 to obtain a first passivation layer 400.
  • Step 3 forming a flat layer 500 on the first passivation layer 400, and patterning the flat layer 500 to obtain a second via hole 510 located in the first via hole 410; Annealing treatment;
  • Step 4 forming a common electrode 600 on the flat layer 500;
  • Step 5 forming a second passivation layer 700 on the common electrode 600 and the flat layer 500, and patterning the second passivation layer 700 to obtain a third via 710 located in the second via 510. ;
  • Step 6 forming a pixel electrode 800 on the second passivation layer 700 , and the pixel electrode 800 is in contact with the source/drain 300 via the third via 710 .
  • step 3 of the method for fabricating the above array substrate when the planarization layer 500 is annealed, the photoresist material of the planarization layer 500 located in the first via hole 410 reacts with the metal material of the source/drain electrodes 300 to generate no
  • the conductive complex 550 blocks the conduction of the pixel electrode 800 from the source/drain 300, resulting in the inability of the data signal to be transmitted to the pixel electrode 300, thereby having a fatal effect on the performance of the array substrate.
  • An object of the present invention is to provide a method for fabricating an array substrate, which effectively blocks the contact between the flat layer and the source/drain during the annealing process of each film layer, thereby preventing the two from reacting, reducing the number of masks, and reducing the processing time. reduce manufacturing cost.
  • the present invention provides a method for fabricating an array substrate, comprising the following steps:
  • Step 1 providing a substrate, sequentially forming a gate, a gate insulating layer, an active layer, and a source/drain on the substrate;
  • Step 2 forming a first passivation layer on the source/drain and gate insulating layers, forming a flat layer on the first passivation layer, and performing pattern processing on the flat layer to obtain a source corresponding to the source a first via above the drain;
  • Step 3 using the flat layer as a mask, etching the first passivation layer to form a second via hole corresponding to the first via hole;
  • Step 4 depositing a first transparent conductive layer on the flat layer, and patterning the first transparent conductive layer to form a common electrode and a conductive connection layer spaced apart from the common electrode, the conductive a connection layer covering the hole walls of the first through hole and the second through hole, and a source/drain exposed at the second through hole;
  • Step 5 forming a second passivation layer on the common electrode and the flat layer, and performing a hole treatment on a portion of the second passivation layer located in the first through hole and the second through hole to obtain a second a third via hole on the passivation layer, the third via hole exposing a portion of the conductive connection layer;
  • Step 6 depositing a second transparent conductive layer on the second passivation layer, and patterning the second transparent conductive layer to form a pixel electrode, wherein the pixel electrode and the conductive connection layer are via the third via hole In contact with each other, the conductive connection layer is in contact with the source/drain, thereby achieving conduction between the pixel electrode and the source/drain.
  • the step 2 further includes: annealing the flat layer after forming the first via hole on the flat layer.
  • the step 3 further includes: annealing the common electrode and the conductive connection layer; and the step 6 further comprises: annealing the pixel electrode.
  • the first passivation layer and the second passivation layer are a silicon oxide layer, a silicon nitride layer, or a composite layer formed by superposing a silicon oxide layer and a silicon nitride layer; the first passivation layer and the second passivation layer
  • the film thickness of the layer is
  • the size of the third through hole is smaller than the size of the first through hole and the second through hole.
  • the first through hole, the second through hole, and the third through hole are all circular holes, and the first through hole and the second through hole have a diameter of 7-12 ⁇ m, and the diameter of the third through hole is 3-5 ⁇ m.
  • the present invention also provides an array substrate including a substrate, a gate electrode disposed on the substrate, a gate insulating layer disposed on the gate and the substrate, and an active layer disposed on the gate insulating layer a source/drain provided on the active layer and the gate insulating layer, a first passivation layer disposed on the source/drain, the active layer, and the gate insulating layer, and disposed on the a flat layer on the first passivation layer, a common electrode and a conductive connection layer disposed on the flat layer, and a second passivation layer disposed on the common electrode, the conductive connection layer, and the flat layer, And a pixel electrode disposed on the second passivation layer;
  • a portion of the second passivation layer located in the first through hole and the second through hole is provided with a third through hole, the third through hole exposing a portion of the conductive connection layer;
  • the three-via hole is in contact with the conductive connection layer, and the conductive connection layer is in contact with the source/drain, thereby achieving conduction between the pixel electrode and the source/drain.
  • the first passivation layer and the second passivation layer are a silicon oxide layer, a silicon nitride layer, or a composite layer formed by superposing a silicon oxide layer and a silicon nitride layer; the first passivation layer and the second passivation layer
  • the film thickness of the layer is
  • the size of the third through hole is smaller than the size of the first through hole and the second through hole.
  • the first through hole, the second through hole, and the third through hole are all circular holes, and the first through hole and the second through hole have a diameter of 7-12 ⁇ m, and the diameter of the third through hole is 3-5 ⁇ m.
  • the present invention also provides an array substrate including a substrate, a gate electrode disposed on the substrate, a gate insulating layer disposed on the gate and the substrate, and an active layer disposed on the gate insulating layer a source/drain provided on the active layer and the gate insulating layer, a first passivation layer disposed on the source/drain, the active layer, and the gate insulating layer, and disposed on the a flat layer on the first passivation layer, a common electrode and a conductive connection layer disposed on the flat layer, and disposed on the common electrode and the conductive connection a bonding layer, a second passivation layer on the planar layer, and a pixel electrode disposed on the second passivation layer;
  • a portion of the second passivation layer located in the first through hole and the second through hole is provided with a third through hole, the third through hole exposing a portion of the conductive connection layer;
  • the three-via hole is in contact with the conductive connection layer, and the conductive connection layer is in contact with the source/drain, thereby achieving conduction between the pixel electrode and the source/drain;
  • the first passivation layer and the second passivation layer are a silicon oxide layer, a silicon nitride layer, or a composite layer formed by superposing a silicon oxide layer and a silicon nitride layer; the first passivation layer and the first passivation layer
  • the film thickness of the second passivation layer is
  • the size of the third through hole is smaller than the size of the first through hole and the second through hole.
  • the method for fabricating an array substrate provided by the present invention can realize the opening treatment of the flat layer and the first passivation layer by using a photomask, which can save a mask compared with the prior art. , saving production cost and reducing process time; forming a conductive connection layer covering the first via hole on the flat layer and the second via hole on the first passivation layer while forming the common electrode, thereby avoiding source/drain and The flat layer is exposed to the environment, which eliminates the possibility of reaction between the two, and is beneficial to improving the electrical performance of the array substrate and achieving signal conduction.
  • the array substrate prepared by the invention has smooth signal conduction and good electrical performance.
  • FIG. 1 is a schematic view showing a method of fabricating an array substrate of the prior art
  • FIG. 2 is a schematic view showing the first step of the method for fabricating the array substrate of the present invention
  • step 2 is a schematic diagram of step 2 of a method for fabricating an array substrate of the present invention
  • step 3 is a schematic diagram of step 3 of the method for fabricating an array substrate of the present invention.
  • step 4 is a schematic diagram of step 4 of the method for fabricating an array substrate of the present invention.
  • step 5 is a schematic diagram of step 5 of the method for fabricating an array substrate of the present invention.
  • FIG. 7 is a schematic view showing the step 6 of the method for fabricating the array substrate of the present invention and the invention is prepared Schematic diagram of the structure of the array substrate.
  • the present invention provides a method for fabricating an array substrate, including the following steps:
  • Step 1 as shown in FIG. 2, a substrate 10 is provided, and a gate electrode 15, a gate insulating layer 20, an active layer 25, and source/drain electrodes 30 are sequentially formed on the substrate 10.
  • the substrate 10 is a transparent substrate, preferably a glass substrate.
  • the material of the gate electrode 15 and the source/drain electrodes 30 is a stack combination of one or more of molybdenum (Mo), titanium (Ti), aluminum (Al), and copper (Cu).
  • Mo molybdenum
  • Ti titanium
  • Al aluminum
  • Cu copper
  • the material of the source/drain 30 is preferably copper.
  • the gate insulating layer 20 is a silicon oxide (SiO x ) layer, a silicon nitride (SiN x ) layer, or a composite layer composed of a silicon oxide layer and a silicon nitride layer.
  • the material of the active layer 25 is indium gallium zinc oxide (IGZO).
  • Step 2 As shown in FIG. 3, a first passivation layer 40 is formed on the source/drain 30 and the gate insulating layer 20, and a flat layer 50 is formed on the first passivation layer 40.
  • the flat layer 50 is exposed and developed by the cover to pattern the flat layer 50 to obtain a first through hole 51 corresponding to the upper side of the source/drain 30.
  • the material of the flat layer 50 is a positive photoresist.
  • the step 2 further includes: after the first through hole 51 is formed on the flat layer 50, the flat layer 50 is subjected to an annealing treatment to be heat-cured.
  • the flat layer 50 is annealed, since the first passivation layer 40 is provided between the flat layer 50 and the source/drain electrodes 30, it is impossible to contact, and thus no reaction occurs to form a complex.
  • Step 3 As shown in FIG. 4, the first passivation layer 40 is etched by using the flat layer 50 as a mask to form a second via hole 41 corresponding to the first via hole 51.
  • the etching process of the first passivation layer 40 is a dry etching process.
  • the step 2-3 only uses a mask to realize the opening treatment of the flat layer 50 and the first passivation layer 40. Compared with the prior art, the utility model can save a light mask, save production cost and reduce process time. . However, after the etching process of the step 2-3, the flat layer 50 and the source/drain 30 are exposed to the air at the first through hole 51 and the second through hole 41, respectively, and thus there is still a reaction. Possible.
  • Step 4 depositing a first transparent conductive layer on the flat layer 50, and collecting The first transparent conductive layer is patterned by a photolithography process to form a common electrode 60 and a conductive connection layer 65 spaced apart from the common electrode 60.
  • the conductive connection layer 65 covers the first The hole walls of the through hole 51 and the second through hole 41, and the source/drain 30 exposed at the second through hole 41, thereby preventing the source/drain 30 and the flat layer 50 from being exposed to the environment, eliminating the occurrence of both The possibility of reaction.
  • the material of the common electrode 60 and the conductive connection layer 65 is a transparent conductive metal oxide such as indium tin oxide (ITO) or the like.
  • the step 4 further comprises: annealing the common electrode 60 and the conductive connection layer 65 to heat-solidify and crystallize the transparent conductive metal oxide therein, thereby improving the film quality of the common electrode 60 and the conductive connection layer 65.
  • the structure reduces the sheet resistance, making the structure more stable and longer.
  • the first via hole 51 and the second via hole 41 are covered by the conductive connection layer 65, so that the source/drain 30 and the flat layer 50 cannot be exposed. In the environment, the possibility of a reaction between the two is eliminated.
  • Step 5 as shown in FIG. 6, a second passivation layer 70 is formed on the common electrode 60 and the flat layer 50, and the first pass hole 51 is located on the second passivation layer 70 by a photolithography process.
  • a portion of the second via hole 41 is subjected to an opening process to obtain a third via hole 71 on the second passivation layer 70, and the third via hole 71 exposes a portion of the conductive connection layer 65.
  • the etching process in the photolithography process of the second passivation layer 70 is a dry etching process.
  • the first passivation layer 40 and the second passivation layer 70 are a silicon oxide (SiO x ) layer, a silicon nitride (SiN x ) layer, or a composite layer composed of a silicon oxide layer and a silicon nitride layer.
  • SiO x silicon oxide
  • SiN x silicon nitride
  • Floor a composite layer composed of a silicon oxide layer and a silicon nitride layer.
  • the film thickness of the first passivation layer 40 and the second passivation layer 70 is the film thickness of the first passivation layer 40 and the second passivation layer 70.
  • the size of the third through hole 71 is smaller than the size of the first through hole 51 and the second through hole 41.
  • the first through hole 51, the second through hole 41, and the third through hole 71 are all circular holes, and the first through hole 51 and the second through hole 41 have a diameter of 7-12 ⁇ m.
  • the diameter of the third through hole 71 is 3-5 ⁇ m.
  • Step 6 depositing a second transparent conductive layer on the second passivation layer 70, and patterning the second transparent conductive layer by a photolithography process to form a pixel electrode 80.
  • the pixel electrode 80 is in contact with the conductive connection layer 65 via the third via 71, and the conductive connection layer 65 is in contact with the source/drain 30, thereby achieving conduction between the pixel electrode 80 and the source/drain 30.
  • the material of the pixel electrode 80 is a transparent conductive metal oxide such as indium tin oxide (ITO) or the like.
  • the step 6 further comprises: annealing the pixel electrode 80 to heat-solidify the transparent conductive metal oxide therein, thereby improving the film structure of the pixel electrode 80, reducing the sheet resistance, and making the structure more Stable and long lasting.
  • the present invention further provides an array substrate, comprising a substrate 10, a gate electrode 15 disposed on the substrate 10, a gate insulating layer 20 disposed on the gate electrode 15 and the substrate 10, and An active layer 25 on the gate insulating layer 20, a source/drain 30 provided on the active layer 25 and the gate insulating layer 20, and the source/drain 30 and the active layer 25 And a first passivation layer 40 on the gate insulating layer 20, a flat layer 50 disposed on the first passivation layer 40, and a common electrode 60 disposed on the flat layer 50 and spaced apart from each other and electrically connected a layer 65, a second passivation layer 70 disposed on the common electrode 60, the conductive connection layer 65, and the flat layer 50, and a pixel electrode 80 disposed on the second passivation layer 70;
  • a first via hole 51 and a second via hole 41 corresponding to the source/drain 30 are respectively formed on the flat layer 50 and the first passivation layer 40, and the conductive connection layer 65 covers the a hole wall of the first through hole 51 and the second through hole 41, and a source/drain 30 exposed at the second through hole 41;
  • a portion of the second passivation layer 70 in the first through hole 51 and the second through hole 41 is provided with a third through hole 71, the third through hole 71 exposes a portion of the conductive connection layer 65;
  • the pixel electrode 80 is in contact with the conductive connection layer 65 via the third via 71, and the conductive connection layer 65 is in contact with the source/drain 30, thereby achieving conduction between the pixel electrode 80 and the source/drain 30.
  • the substrate 10 is a transparent substrate, preferably a glass substrate.
  • the material of the gate electrode 15 and the source/drain electrodes 30 is a stack combination of one or more of molybdenum (Mo), titanium (Ti), aluminum (Al), and copper (Cu).
  • Mo molybdenum
  • Ti titanium
  • Al aluminum
  • Cu copper
  • the material of the source/drain 30 is preferably copper.
  • the gate insulating layer 20 is a silicon oxide (SiO x ) layer, a silicon nitride (SiN x ) layer, or a composite layer composed of a silicon oxide layer and a silicon nitride layer.
  • the material of the active layer 25 is indium gallium zinc oxide (IGZO).
  • the material of the flat layer 50 is a positive photoresist.
  • the material of the common electrode 60, the conductive connection layer 65, and the pixel electrode 80 is a transparent conductive metal oxide such as indium tin oxide (ITO) or the like.
  • the first passivation layer 40 and the second passivation layer 70 are a silicon oxide (SiO x ) layer, a silicon nitride (SiN x ) layer, or a composite layer composed of a silicon oxide layer and a silicon nitride layer.
  • SiO x silicon oxide
  • SiN x silicon nitride
  • Floor a composite layer composed of a silicon oxide layer and a silicon nitride layer.
  • the film thickness of the first passivation layer 40 and the second passivation layer 70 is the film thickness of the first passivation layer 40 and the second passivation layer 70.
  • the size of the third through hole 71 is smaller than the size of the first through hole 51 and the second through hole 41.
  • the first through hole 51, the second through hole 41, and the third through hole 71 are all circular holes, and the first through hole 51 and the second through hole 41 have a diameter of 7-12 ⁇ m.
  • the diameter of the third through hole 71 is 3-5 ⁇ m.
  • the method for fabricating an array substrate can realize the opening treatment of the flat layer and the first passivation layer by using a photomask, which can save a photomask compared with the prior art. Saving production cost and reducing process time; forming a conductive connection layer covering the first via hole on the flat layer and the second via hole on the first passivation layer while forming the common electrode, thereby avoiding source/drain and flatness
  • the layer is exposed to the environment, which eliminates the possibility of reaction between the two, and is beneficial to improving the electrical performance of the array substrate and achieving signal conduction.
  • the array substrate prepared by the invention has smooth signal conduction and good electrical performance.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Mathematical Physics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

L'invention concerne un procédé de fabrication d'un panneau de réseau et un panneau de réseau ainsi fabriqué qui utilisent un masque photographique pour mettre en œuvre une formation de trou sur une couche de planarisation (50) et une couche de passivation (40), permettant d'économiser un masque photographique, de réduire les coûts de fabrication et de réduire le temps de fabrication par rapport à l'état de la technique. Lors de la formation d'une électrode commune (60), une couche de connexion électroconductrice (45) entourant un premier trou traversant (51) sur la couche de planarisation et un second trou traversant (51) sur la couche de planarisation est simultanément formée, empêchant ainsi une source/un drain (30) et la couche de planarisation d'être exposés à l'environnement, éliminant la possibilité que les deux couches aient une réaction, facilitant une augmentation de la performance électrique du panneau de réseau, et mettant en œuvre une transmission de signal. Le panneau de réseau fabriqué selon l'invention permet une transmission de signal lisse et présente des performances électriques favorables.
PCT/CN2016/078878 2016-03-01 2016-04-08 Procédé de fabrication de panneau de réseau et panneau de réseau ainsi fabriqué WO2017147974A1 (fr)

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