WO2020077857A1 - 液晶显示器电路及显示器 - Google Patents

液晶显示器电路及显示器 Download PDF

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Publication number
WO2020077857A1
WO2020077857A1 PCT/CN2018/124229 CN2018124229W WO2020077857A1 WO 2020077857 A1 WO2020077857 A1 WO 2020077857A1 CN 2018124229 W CN2018124229 W CN 2018124229W WO 2020077857 A1 WO2020077857 A1 WO 2020077857A1
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WIPO (PCT)
Prior art keywords
isolation unit
isolation
unit
system chip
liquid crystal
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PCT/CN2018/124229
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English (en)
French (fr)
Inventor
李文芳
曹丹
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深圳市华星光电技术有限公司
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Publication of WO2020077857A1 publication Critical patent/WO2020077857A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers

Definitions

  • the present application relates to the field of liquid crystal display, in particular to a liquid crystal display circuit and a display.
  • Non-volatile memory the code is stored in the flash memory, by writing the code in the flash memory read by the panel driver board into the PMIC register, and in order to prevent errors in the process of reading the control bus.
  • the screen driver board will monitor during the blanking time of each frame, and will always occupy the control bus, and the system chip's charged erasable programmable read-only memory and tuner will also use the I2C bus, and the whole plant will need to adjust
  • the system bus and control bus of the system chip need to be connected together, but when the whole machine searches for a channel, the tuner bus will also act. At this time, the system bus and the control bus will conflict, causing unsuccessful search and abnormal screen.
  • the purpose of this application is to provide a liquid crystal display circuit and a display, which have the beneficial effect of preventing conflicts between the system chip bus and the control bus.
  • An embodiment of the present application provides a liquid crystal display circuit, which is applied to a display panel, and includes a system chip, a first isolation unit, a second isolation unit, a third isolation unit, a fourth isolation unit, a fifth isolation unit, and a system Chip bus and control bus;
  • the system chip is connected to the control terminal of the first isolation unit, and the input terminal of the first isolation unit is connected to a preset voltage and connected to the second isolation unit, the third isolation unit, the fourth isolation unit, and the third
  • the control terminals of the five isolation units are respectively connected, the input terminal of the second isolation unit is connected to the data line in the system chip bus, and the input terminal of the third isolation unit is connected to the data line of the control bus.
  • the second isolation unit and the output terminal of the third isolation unit are connected, the input terminal of the fourth isolation unit is connected to the clock signal line of the system chip bus, and the input terminal of the fifth isolation unit is connected to the The clock signal line of the control bus is connected, and the output ends of the fourth isolation unit and the fifth isolation unit are connected;
  • the first isolation unit is a MOS tube; the preset voltage connected to the input end of the first isolation unit is 5V.
  • the GPIO interface of the system chip is connected to the gate of the first isolation unit, and the first isolation unit is an NMOS tube.
  • the second isolation unit, the third isolation unit, the fourth isolation unit, and the fifth isolation unit are all MOS transistors.
  • the second isolation unit, the third isolation unit, the fourth isolation unit, and the fifth isolation unit are all NMOS transistors.
  • the first isolation unit when the GPIO interface is at a high level, the first isolation unit is turned on, and the common node of the first isolation unit and the second isolation unit is a low level, the second The isolation unit, the third isolation unit, the fourth isolation unit, and the fifth isolation unit are all cut off, and the system chip bus and the control bus are isolated.
  • the first isolation unit when the GPIO interface is at a low level, the first isolation unit is turned off, the common node of the first isolation unit and the second isolation unit is at a high level, and the second isolation
  • the unit, the third isolation unit, the fourth isolation unit, and the fifth isolation unit are all turned on, and the display panel I2C does not perform the reading action, and the system chip passes the second isolation unit, the third isolation unit, the fourth isolation unit,
  • the fifth isolation unit can control the control bus to perform common voltage regulation.
  • the liquid crystal display circuit of the present application further includes a resistor, one end of the resistor is connected to the preset voltage, and the other end of the resistor is connected to the first isolation unit and the second isolation unit. Common node connection.
  • An embodiment of the present application also provides a liquid crystal display circuit, which is applied to a display panel and includes: a system chip, a first isolation unit, a second isolation unit, a third isolation unit, a fourth isolation unit, a fifth isolation unit, and a system Chip bus and control bus;
  • the system chip is connected to the control terminal of the first isolation unit, and the input terminal of the first isolation unit is connected to a preset voltage and connected to the second isolation unit, the third isolation unit, the fourth isolation unit, and the third
  • the control terminals of the five isolation units are respectively connected, the input terminal of the second isolation unit is connected to the data line in the system chip bus, and the input terminal of the third isolation unit is connected to the data line of the control bus.
  • the second isolation unit and the output terminal of the third isolation unit are connected, the input terminal of the fourth isolation unit is connected to the clock signal line of the system chip bus, and the input terminal of the fifth isolation unit is connected to the The clock signal line of the control bus is connected, and the output ends of the fourth isolation unit and the fifth isolation unit are connected.
  • the first isolation unit is a MOS tube.
  • the GPIO interface of the system chip is connected to the gate of the first isolation unit, and the first isolation unit is an NMOS tube.
  • the second isolation unit, the third isolation unit, the fourth isolation unit, and the fifth isolation unit are all MOS transistors.
  • the second isolation unit, the third isolation unit, the fourth isolation unit, and the fifth isolation unit are all NMOS transistors.
  • the first isolation unit when the GPIO interface is at a high level, the first isolation unit is turned on, and the common node of the first isolation unit and the second isolation unit is a low level, the second The isolation unit, the third isolation unit, the fourth isolation unit, and the fifth isolation unit are all cut off, and the system chip bus and the control bus are isolated.
  • the first isolation unit when the GPIO interface is at a low level, the first isolation unit is turned off, the common node of the first isolation unit and the second isolation unit is at a high level, and the second isolation
  • the unit, the third isolation unit, the fourth isolation unit, and the fifth isolation unit are all turned on, and the display panel I2C does not perform the reading action, and the system chip passes the second isolation unit, the third isolation unit, the fourth isolation unit,
  • the fifth isolation unit can control the control bus to perform common voltage regulation.
  • the preset voltage connected to the input end of the first isolation unit is 5V.
  • the liquid crystal display circuit of the present application further includes a resistor, one end of the resistor is connected to the preset voltage, and the other end of the resistor is connected to the first isolation unit and the second isolation unit. Common node connection.
  • a display including a liquid crystal display circuit applied to a display panel which includes: a system chip, a first isolation unit, a second isolation unit, a third isolation unit, a fourth isolation unit, and a fifth isolation Unit, system chip bus and control bus;
  • the system chip is connected to the control terminal of the first isolation unit, and the input terminal of the first isolation unit is connected to a preset voltage and connected to the second isolation unit, the third isolation unit, the fourth isolation unit, and the third
  • the control terminals of the five isolation units are respectively connected, the input terminal of the second isolation unit is connected to the data line in the system chip bus, and the input terminal of the third isolation unit is connected to the data line of the control bus.
  • the second isolation unit and the output terminal of the third isolation unit are connected, the input terminal of the fourth isolation unit is connected to the clock signal line of the system chip bus, and the input terminal of the fifth isolation unit is connected to the The clock signal line of the control bus is connected, and the output ends of the fourth isolation unit and the fifth isolation unit are connected.
  • the first isolation unit is a MOS tube.
  • the GPIO interface of the system chip is connected to the gate of the first isolation unit, and the first isolation unit is an NMOS tube.
  • the preset voltage connected to the input end of the first isolation unit is 5V.
  • This application provides a liquid crystal display circuit, which is applied to a display panel and includes: a system chip, a first isolation unit, a second isolation unit, a third isolation unit, a fourth isolation unit, a fifth isolation unit, a system chip bus, and a control Bus; the system chip is connected to the control end of the first isolation unit, the input end of the first isolation unit is connected to a preset voltage and respectively connected to the second isolation unit, the third isolation unit, and the fourth isolation unit
  • the control terminals of the fifth isolation unit are connected respectively, the input terminal of the second isolation unit is connected to the data line in the system chip bus, and the input terminal of the third isolation unit is connected to the data line of the control bus ,
  • the output terminals of the second isolation unit and the third isolation unit are connected, and the input terminal of the fourth isolation unit is connected to the clock signal line of the system chip bus, which has the function of preventing conflicts between the system chip bus and the control bus Beneficial.
  • FIG. 1 is a schematic structural diagram of a liquid crystal display circuit in an embodiment of the present application.
  • first and second are used for description purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated.
  • the features defined as “first” and “second” may explicitly or implicitly include one or more of the features.
  • the meaning of “plurality” is two or more, unless otherwise specifically limited.
  • connection should be understood in a broad sense, for example, it can be fixed or detachable Connected, or integrally connected; it can be mechanical, electrical, or can communicate with each other; it can be directly connected, or it can be indirectly connected through an intermediary, it can be the connection between two elements or the interaction of two elements relationship.
  • the first feature “above” or “below” the second feature may include the direct contact of the first and second features, or may include the first and second features Contact not directly but through other features between them.
  • the first feature is “above”, “above” and “above” the second feature includes that the first feature is directly above and obliquely above the second feature, or simply means that the first feature is higher in level than the second feature.
  • the first feature is “below”, “below” and “below” the second feature includes that the first feature is directly below and obliquely below the second feature, or simply means that the first feature is less horizontal than the second feature.
  • FIG. 1 is a schematic structural diagram of a liquid crystal display circuit in an embodiment of the present application.
  • the liquid crystal display circuit which is applied to a display, includes: a system chip U1, a first isolation unit Q1, a second isolation unit Q2, The third isolation unit Q3, the fourth isolation unit Q4, the fifth isolation unit Q5, the system chip bus 100, and the control bus 200.
  • the system chip bus 100 has a data line SDA_S and a clock signal line SCL_S.
  • the data line SDA_S is used to transmit the data signal of the system chip
  • the clock signal line SCL_S is used to transmit the clock signal of the system chip.
  • the control bus 200 has a data line SDA_C and a clock signal line SCL_C.
  • the data line SDA_C is used to transmit the control signal of the display panel
  • the clock signal line SCL_C is used to obtain the clock signal from the system chip bus transmitting the clock signal line SCL_S of the display panel to provide to the control bus.
  • the data line SDA_C and the clock signal line SCL_C of the control bus 200 are connected to the driving circuit of the display panel.
  • the system chip U1 is connected to the control terminal of the first isolation unit Q1, the input terminal of the first isolation unit Q1 is connected to a preset voltage and connected to the second isolation unit Q2, the third isolation unit Q3,
  • the control terminals of the fourth isolation unit Q4 and the fifth isolation unit Q5 are respectively connected, the input terminal of the second isolation unit Q2 is connected to the data line SDA_S in the system chip bus, and the input terminal of the third isolation unit Q3 Connected to the data line SDA_C of the control bus, the output terminal of the second isolation unit Q2 is connected to the output terminal of the third isolation unit Q3, and the input terminal of the fourth isolation unit Q4 is connected to the system chip bus
  • the clock signal line SCL_S is connected, the input terminal of the fifth isolation unit Q5 is connected to the clock signal line SCL_C of the control bus, and the output terminals of the fourth isolation unit Q4 and the fifth isolation unit Q5 are connected.
  • the liquid crystal display circuit further includes a resistor R1, one end of the resistor R1 is connected to the preset voltage, the other end of the resistor R1 is connected to the first isolation unit Q1 and the second The common node of the isolation unit Q2 is connected.
  • the preset voltage connected to the input terminal of the first isolation unit is 5V.
  • the first isolation unit Q1, the second isolation unit Q2, the third isolation unit Q3, the fourth isolation unit Q4, and the fifth isolation unit Q5 are all MOS tubes, and are NMOS tubes.
  • the GPIO interface of the system chip is connected to the gate of the first isolation unit.
  • the first isolation unit is turned on, and the common node of the first isolation unit and the second isolation unit is low, the first The second isolation unit, the third isolation unit, the fourth isolation unit, and the fifth isolation unit are all cut off, and the system chip bus and the control bus are isolated, that is, the data line SDA_S of the system chip bus and the data line of the control bus SDA_C is isolated, and the clock signal line SCL_S of the system chip bus is isolated from the clock signal line SCL_C of the control bus.
  • the first isolation unit When the GPIO interface is at a low level, the first isolation unit is turned off, the common node of the first isolation unit and the second isolation unit is at a high level, and the second isolation unit, the third isolation unit, and the fourth isolation unit
  • the fifth isolation unit is turned on, and the driving chip of the display panel does not perform the reading operation without passing through the control bus.
  • the system chip passes through the system chip bus and passes through the second isolation unit, the third isolation unit, and the fourth isolation unit.
  • the fifth isolation unit can control the control bus to send a signal to the driving circuit of the display panel, so that the driving circuit performs common voltage adjustment.
  • the present application also provides a display including the liquid crystal display circuit described in any of the above embodiments.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种液晶显示器电路，包括：***芯片（U1）、第一隔离单元（Q1）、第二隔离单元（Q2）、第三隔离单元（Q3）、第四隔离单元（Q4）、第五隔离单元（Q5）、***芯片总线（100）以及控制总线（200）；***芯片（U1）与第一隔离单元（Q1）的控制端连接，第一隔离单元（Q1）的输入端接入预设电压并分别与第二隔离单元（Q2）、第三隔离单元（Q3）、第四隔离单元（Q4）、第五隔离单元（Q5）的控制端分别连接。该电路能防止***芯片总线（100）以及控制总线（200）冲突。

Description

液晶显示器电路及显示器 技术领域
本申请涉及液晶显示领域，具体涉及一种液晶显示器电路及显示器。
 背景技术
在现有技术中，PMIC(Power Management IC)电源管理集成电路为了节省空间尺寸，PMIC内部没有做NVM（Non-volatile memory）非易失存储器，代码存储在闪存里，通过将屏驱动板读取到的闪存里的代码写到PMIC的寄存器里面，且为了防止读取控制总线过程中出错。屏驱动板会在每一帧的消隐时间里去监测，会一直占用控制总线，而***芯片的带电可擦可编程只读存储器和调谐器也会使用I2C总线，而整机厂会需要调整***芯片的***总线和控制总线需要连通在一起，但是当整机搜台时，调谐器的总线也会动作，此时***总线和控制总线会冲突，引起搜台不成功和画面异常。
因此，现有技术存在缺陷，急需改进。
 技术问题
本申请的目的是提供一种液晶显示器电路及显示器，具有防止***芯片总线以及控制总线冲突的有益效果。
 技术解决方案
本申请实施例提供了一种液晶显示器电路，应用于显示器面板中，其包括：***芯片、第一隔离单元、第二隔离单元、第三隔离单元、第四隔离单元、第五隔离单元、***芯片总线以及控制总线；
所述***芯片与所述第一隔离单元的控制端连接，所述第一隔离单元的输入端接入预设电压并分别与该第二隔离单元、第三隔离单元、第四隔离单元、第五隔离单元的控制端分别连接，所述第二隔离单元的输入端与所述***芯片总线中的数据线连接，所述第三隔离单元的输入端与所述控制总线的数据线连接，所述第二隔离单元以及所述第三隔离单元的输出端连接，所述第四隔离单元的输入端与所述***芯片总线的时钟信号线连接，所述第五隔离单元的输入端与所述控制总线的时钟信号线连接，所述第四隔离单元以及所述第五隔离单元的输出端连接；
所述第一隔离单元为MOS管；所述第一隔离单元的输入端接入的预设电压为5V。
在本申请所述的液晶显示器电路中，所述***芯片的GPIO接口与所述第一隔离单元的栅极连接，所述第一隔离单元为NMOS管。
在本申请所述的液晶显示器电路中，所述第二隔离单元、第三隔离单元、第四隔离单元、第五隔离单元均为MOS管。
在本申请所述的液晶显示器电路中，所述第二隔离单元、第三隔离单元、第四隔离单元、第五隔离单元均为NMOS管。
在本申请所述的液晶显示器电路中，在所述GPIO 接口为高电平时，该第一隔离单元导通，该第一隔离单元与第二隔离单元的公共节点为低电平，该第二隔离单元、第三隔离单元、第四隔离单元、第五隔离单元均截止，***芯片总线以及控制总线进行了隔离。
在本申请所述的液晶显示器电路中，在所述GPIO 接口为低电平时，该第一隔离单元截止，该第一隔离单元与第二隔离单元的公共节点为高电平，该第二隔离单元、第三隔离单元、第四隔离单元、第五隔离单元均导通，显示板I2C不进行读取动作，***芯片此时通过该第二隔离单元、第三隔离单元、第四隔离单元、第五隔离单元可以控控制总线进行公共电压调节。
在本申请所述的液晶显示器电路中，还包括一电阻，所述电阻的一端接入所述预设电压，所述电阻的另一端与所述第一隔离单元以及所述第二隔离单元的公共节点连接。
本申请实施例还提供了一种液晶显示器电路，应用于显示器面板中，包括：***芯片、第一隔离单元、第二隔离单元、第三隔离单元、第四隔离单元、第五隔离单元、***芯片总线以及控制总线；
所述***芯片与所述第一隔离单元的控制端连接，所述第一隔离单元的输入端接入预设电压并分别与该第二隔离单元、第三隔离单元、第四隔离单元、第五隔离单元的控制端分别连接，所述第二隔离单元的输入端与所述***芯片总线中的数据线连接，所述第三隔离单元的输入端与所述控制总线的数据线连接，所述第二隔离单元以及所述第三隔离单元的输出端连接，所述第四隔离单元的输入端与所述***芯片总线的时钟信号线连接，所述第五隔离单元的输入端与所述控制总线的时钟信号线连接，所述第四隔离单元以及所述第五隔离单元的输出端连接。
在本申请所述的液晶显示器电路中，所述第一隔离单元为MOS管。
在本申请所述的液晶显示器电路中，所述***芯片的GPIO接口与所述第一隔离单元的栅极连接，所述第一隔离单元为NMOS管。
在本申请所述的液晶显示器电路中，所述第二隔离单元、第三隔离单元、第四隔离单元、第五隔离单元均为MOS管。
在本申请所述的液晶显示器电路中，所述第二隔离单元、第三隔离单元、第四隔离单元、第五隔离单元均为NMOS管。
在本申请所述的液晶显示器电路中，在所述GPIO 接口为高电平时，该第一隔离单元导通，该第一隔离单元与第二隔离单元的公共节点为低电平，该第二隔离单元、第三隔离单元、第四隔离单元、第五隔离单元均截止，***芯片总线以及控制总线进行了隔离。
在本申请所述的液晶显示器电路中，在所述GPIO 接口为低电平时，该第一隔离单元截止，该第一隔离单元与第二隔离单元的公共节点为高电平，该第二隔离单元、第三隔离单元、第四隔离单元、第五隔离单元均导通，显示板I2C不进行读取动作，***芯片此时通过该第二隔离单元、第三隔离单元、第四隔离单元、第五隔离单元可以控控制总线进行公共电压调节。
在本申请所述的液晶显示器电路中，所述第一隔离单元的输入端接入的预设电压为5V。
在本申请所述的液晶显示器电路中，还包括一电阻，所述电阻的一端接入所述预设电压，所述电阻的另一端与所述第一隔离单元以及所述第二隔离单元的公共节点连接。
一种显示器，其包括液晶显示器电路，所述液晶显示器电路应用于显示器面板中，其包括：***芯片、第一隔离单元、第二隔离单元、第三隔离单元、第四隔离单元、第五隔离单元、***芯片总线以及控制总线；
所述***芯片与所述第一隔离单元的控制端连接，所述第一隔离单元的输入端接入预设电压并分别与该第二隔离单元、第三隔离单元、第四隔离单元、第五隔离单元的控制端分别连接，所述第二隔离单元的输入端与所述***芯片总线中的数据线连接，所述第三隔离单元的输入端与所述控制总线的数据线连接，所述第二隔离单元以及所述第三隔离单元的输出端连接，所述第四隔离单元的输入端与所述***芯片总线的时钟信号线连接，所述第五隔离单元的输入端与所述控制总线的时钟信号线连接，所述第四隔离单元以及所述第五隔离单元的输出端连接。
在本申请所述的显示器中，所述第一隔离单元为MOS管。
在本申请所述的显示器中，所述***芯片的GPIO接口与所述第一隔离单元的栅极连接，所述第一隔离单元为NMOS管。
在本申请所述的显示器中，所述第一隔离单元的输入端接入的预设电压为5V。
 有益效果
本申请提供一种液晶显示器电路，应用于显示器面板中，包括：***芯片、第一隔离单元、第二隔离单元、第三隔离单元、第四隔离单元、第五隔离单元、***芯片总线以及控制总线；所述***芯片与所述第一隔离单元的控制端连接，所述第一隔离单元的输入端接入预设电压并分别与该第二隔离单元、第三隔离单元、第四隔离单元、第五隔离单元的控制端分别连接，所述第二隔离单元的输入端与所述***芯片总线中的数据线连接，所述第三隔离单元的输入端与所述控制总线的数据线连接，所述第二隔离单元以及所述第三隔离单元的输出端连接，所述第四隔离单元的输入端与所述***芯片总线的时钟信号线连接，具有防止***芯片总线以及控制总线冲突的有益效。
 附图说明
图1是本申请实施例中的液晶显示器电路的一种结构示意图。
 本发明的实施方式
下面详细描述本申请的实施方式，所述实施方式的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施方式是示例性的，仅用于解释本申请，而不能理解为对本申请的限制。
在本申请的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接或可以相互通讯；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
在本申请中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。
下文的公开提供了许多不同的实施方式或例子用来实现本申请的不同结构。为了简化本申请的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本申请。此外，本申请可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本申请提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
请参照图1，图1是本申请一实施例中的液晶显示器电路的结构示意图，该液晶显示器电路，应用于显示器中，包括：***芯片U1、第一隔离单元Q1、第二隔离单元Q2、第三隔离单元Q3、第四隔离单元Q4、第五隔离单元Q5、***芯片总线100以及控制总线200。
其中，该***芯片总线100具有数据线SDA_S以及时钟信号线SCL_S，该数据线SDA_S用于传输***芯片的数据信号，该时钟信号线SCL_S用于传输***芯片的时钟信号。
其中，该控制总线200具有数据线SDA_C以及时钟信号线SCL_C。该数据线SDA_C用于传输显示面板的控制信号，该时钟信号线SCL_C用于从***芯片总线的传输该显示面板的时钟信号线SCL_S获取时钟信号以提供给该控制总线使用。该控制总线200的数据线SDA_C以及时钟信号线SCL_C是与显示板的驱动电路连接的。
具体地，该***芯片U1与所述第一隔离单元Q1的控制端连接，所述第一隔离单元Q1的输入端接入预设电压并与该第二隔离单元Q2、第三隔离单元Q3、第四隔离单元Q4、第五隔离单元Q5的控制端分别连接，所述第二隔离单元Q2的输入端与所述***芯片总线中的数据线SDA_S连接，所述第三隔离单元Q3的输入端与所述控制总线的数据线SDA_C连接，所述第二隔离单元Q2的输出端与所述第三隔离单元Q3的输出端连接，所述第四隔离单元Q4的输入端与所述***芯片总线的时钟信号线SCL_S连接，所述第五隔离单元Q5的输入端与所述控制总线的时钟信号线SCL_C连接，所述第四隔离单元Q4以及所述第五隔离单元Q5的输出端连接。
在一些实施例中，该液晶显示器电路还包括一电阻R1，所述电阻R1的一端接入所述预设电压，所述电阻R1的另一端与所述第一隔离单元Q1以及所述第二隔离单元Q2的公共节点连接。第一隔离单元的输入端接入的预设电压为5V。
其中，第一隔离单元Q1、第二隔离单元Q2、第三隔离单元Q3、第四隔离单元Q4、第五隔离单元Q5均为MOS管，而且为NMOS管。***芯片的GPIO接口与所述第一隔离单元的栅极连接。
工作时，为了防止***芯片总线以及控制总线的冲突，在GPIO 接口为高电平时，该第一隔离单元导通，该第一隔离单元与第二隔离单元的公共节点为低电平，该第二隔离单元、第三隔离单元、第四隔离单元、第五隔离单元均截止，***芯片总线以及控制总线进行了隔离，也即是将该***芯片总线的数据线SDA_S与该控制总线的数据线SDA_C进行了隔离，以及将***芯片总线的时钟信号线SCL_S与控制总线的时钟信号线SCL_C进行隔离。在所述GPIO 接口为低电平时，该第一隔离单元截止，该第一隔离单元与第二隔离单元的公共节点为高电平，该第二隔离单元、第三隔离单元、第四隔离单元、第五隔离单元均导通，显示板的驱动芯片不通过该控制总线不进行读取动作，***芯片通过该***芯片总线以及通过该第二隔离单元、第三隔离单元、第四隔离单元、第五隔离单元可以控控制总线发送信号给显示板的驱动电路，使得驱动电路进行公共电压调节。
本申请还提供了一种显示器，包括上述任一实施例中的所述的液晶显示器电路。
在本说明书的描述中，参考术语“一个实施方式”、“某些实施方式”、“示意性实施方式”、“示例”、“具体示例”、或“一些示例”等的描述意指结合所述实施方式或示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施方式或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种液晶显示器电路，应用于显示器面板中，其包括：***芯片、第一隔离单元、第二隔离单元、第三隔离单元、第四隔离单元、第五隔离单元、***芯片总线以及控制总线；
    所述***芯片与所述第一隔离单元的控制端连接，所述第一隔离单元的输入端接入预设电压并分别与该第二隔离单元、第三隔离单元、第四隔离单元、第五隔离单元的控制端分别连接，所述第二隔离单元的输入端与所述***芯片总线中的数据线连接，所述第三隔离单元的输入端与所述控制总线的数据线连接，所述第二隔离单元以及所述第三隔离单元的输出端连接，所述第四隔离单元的输入端与所述***芯片总线的时钟信号线连接，所述第五隔离单元的输入端与所述控制总线的时钟信号线连接，所述第四隔离单元以及所述第五隔离单元的输出端连接；
    所述第一隔离单元为MOS管；所述第一隔离单元的输入端接入的预设电压为5V。
  2. 根据权利要求1所述的液晶显示器电路，其中，所述***芯片的GPIO接口与所述第一隔离单元的栅极连接，所述第一隔离单元为NMOS管。
  3. 根据权利要求2所述的液晶显示器电路，其中，所述第二隔离单元、第三隔离单元、第四隔离单元、第五隔离单元均为MOS管。
  4. 根据权利要求3所述的液晶显示器电路，其中，所述第二隔离单元、第三隔离单元、第四隔离单元、第五隔离单元均为NMOS管。
  5. 根据权利要求4所述的液晶显示器电路，其中，在所述GPIO 接口为高电平时，该第一隔离单元导通，该第一隔离单元与第二隔离单元的公共节点为低电平，该第二隔离单元、第三隔离单元、第四隔离单元、第五隔离单元均截止，***芯片总线以及控制总线进行了隔离。
  6. 根据权利要求5所述的液晶显示器电路，其中，在所述GPIO 接口为低电平时，该第一隔离单元截止，该第一隔离单元与第二隔离单元的公共节点为高电平，该第二隔离单元、第三隔离单元、第四隔离单元、第五隔离单元均导通，显示板I2C不进行读取动作，***芯片此时通过该第二隔离单元、第三隔离单元、第四隔离单元、第五隔离单元可以控控制总线进行公共电压调节。
  7. 根据权利要求1所述的液晶显示器电路，其中，还包括一电阻，所述电阻的一端接入所述预设电压，所述电阻的另一端与所述第一隔离单元以及所述第二隔离单元的公共节点连接。
  8. 一种液晶显示器电路，应用于显示器面板中，其包括：***芯片、第一隔离单元、第二隔离单元、第三隔离单元、第四隔离单元、第五隔离单元、***芯片总线以及控制总线；
    所述***芯片与所述第一隔离单元的控制端连接，所述第一隔离单元的输入端接入预设电压并分别与该第二隔离单元、第三隔离单元、第四隔离单元、第五隔离单元的控制端分别连接，所述第二隔离单元的输入端与所述***芯片总线中的数据线连接，所述第三隔离单元的输入端与所述控制总线的数据线连接，所述第二隔离单元以及所述第三隔离单元的输出端连接，所述第四隔离单元的输入端与所述***芯片总线的时钟信号线连接，所述第五隔离单元的输入端与所述控制总线的时钟信号线连接，所述第四隔离单元以及所述第五隔离单元的输出端连接。
  9. 根据权利要求8所述的液晶显示器电路，其中，所述第一隔离单元为MOS管。
  10. 根据权利要求9所述的液晶显示器电路，其中，所述***芯片的GPIO接口与所述第一隔离单元的栅极连接，所述第一隔离单元为NMOS管。
  11. 根据权利要求10所述的液晶显示器电路，其中，所述第二隔离单元、第三隔离单元、第四隔离单元、第五隔离单元均为MOS管。
  12. 根据权利要求11所述的液晶显示器电路，其中，所述第二隔离单元、第三隔离单元、第四隔离单元、第五隔离单元均为NMOS管。
  13. 根据权利要求12所述的液晶显示器电路，其中，在所述GPIO 接口为高电平时，该第一隔离单元导通，该第一隔离单元与第二隔离单元的公共节点为低电平，该第二隔离单元、第三隔离单元、第四隔离单元、第五隔离单元均截止，***芯片总线以及控制总线进行了隔离。
  14. 根据权利要求13所述的液晶显示器电路，其中，在所述GPIO 接口为低电平时，该第一隔离单元截止，该第一隔离单元与第二隔离单元的公共节点为高电平，该第二隔离单元、第三隔离单元、第四隔离单元、第五隔离单元均导通，显示板I2C不进行读取动作，***芯片此时通过该第二隔离单元、第三隔离单元、第四隔离单元、第五隔离单元可以控控制总线进行公共电压调节。
  15. 根据权利要求8所述的液晶显示器电路，其中，所述第一隔离单元的输入端接入的预设电压为5V。
  16. 根据权利要求8所述的液晶显示器电路，其中，还包括一电阻，所述电阻的一端接入所述预设电压，所述电阻的另一端与所述第一隔离单元以及所述第二隔离单元的公共节点连接。
  17. 一种显示器，其包括液晶显示器电路，所述液晶显示器电路应用于显示器面板中，其包括：***芯片、第一隔离单元、第二隔离单元、第三隔离单元、第四隔离单元、第五隔离单元、***芯片总线以及控制总线；
    所述***芯片与所述第一隔离单元的控制端连接，所述第一隔离单元的输入端接入预设电压并分别与该第二隔离单元、第三隔离单元、第四隔离单元、第五隔离单元的控制端分别连接，所述第二隔离单元的输入端与所述***芯片总线中的数据线连接，所述第三隔离单元的输入端与所述控制总线的数据线连接，所述第二隔离单元以及所述第三隔离单元的输出端连接，所述第四隔离单元的输入端与所述***芯片总线的时钟信号线连接，所述第五隔离单元的输入端与所述控制总线的时钟信号线连接，所述第四隔离单元以及所述第五隔离单元的输出端连接。
  18. 根据权利要求17所述的显示器，其中，所述第一隔离单元为MOS管。
  19. 根据权利要求18所述的显示器，其中，所述***芯片的GPIO接口与所述第一隔离单元的栅极连接，所述第一隔离单元为NMOS管。
  20. 根据权利要求17所述的显示器，其中，所述第一隔离单元的输入端接入的预设电压为5V。
PCT/CN2018/124229 2018-10-15 2018-12-27 液晶显示器电路及显示器 WO2020077857A1 (zh)

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