WO2020015642A1 - 移位寄存器单元、栅极驱动电路、显示装置及驱动方法 - Google Patents

移位寄存器单元、栅极驱动电路、显示装置及驱动方法 Download PDF

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Publication number
WO2020015642A1
WO2020015642A1 PCT/CN2019/096185 CN2019096185W WO2020015642A1 WO 2020015642 A1 WO2020015642 A1 WO 2020015642A1 CN 2019096185 W CN2019096185 W CN 2019096185W WO 2020015642 A1 WO2020015642 A1 WO 2020015642A1
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WIPO (PCT)
Prior art keywords
pull
transistor
node
signal
pole
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PCT/CN2019/096185
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English (en)
French (fr)
Inventor
冯雪欢
李永谦
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 合肥鑫晟光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP19837136.1A priority Critical patent/EP3825995A4/en
Priority to JP2019565273A priority patent/JP7396901B2/ja
Priority to US16/633,370 priority patent/US11069281B2/en
Publication of WO2020015642A1 publication Critical patent/WO2020015642A1/zh
Priority to US17/355,621 priority patent/US11403990B2/en
Priority to US17/838,419 priority patent/US11942041B2/en
Priority to US17/842,507 priority patent/US11727853B2/en
Priority to US18/173,190 priority patent/US12014668B2/en
Priority to US18/444,926 priority patent/US20240194149A1/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking

Definitions

  • Embodiments of the present disclosure relate to a shift register unit, a gate driving circuit, a display device, and a driving method.
  • the gate drive circuit is currently generally integrated in a GATE IC.
  • the area of the chip in the IC design is the main factor affecting the cost of the chip. How to effectively reduce the area of the chip is a technical developer's important consideration.
  • At least one embodiment of the present disclosure provides a shift register unit including a blanking unit, a first transmission circuit, a second transmission circuit, a first input-output unit, and a second input-output unit.
  • the blanking unit is configured to charge the pull-up control node and input the blanking pull-up signal to the blanking pull-up node in response to the compensation selection control signal;
  • the first input-output unit includes a first pull-up node and A first output terminal, the second input-output unit includes a second pull-up node and a second output terminal;
  • the first transmission circuit is electrically connected to the blanking pull-up node and the first pull-up node, and Configured to charge the first pull-up node using the blanking pull-up signal in response to a first transmission signal;
  • the second transmission circuit and the blanking pull-up node and the second pull-up node Electrically connected, and configured to charge the second pull-up node using the blanking pull-up signal in response to a second transmission signal
  • the blanking unit includes a blanking input circuit and a blanking pull-up circuit.
  • the blanking input circuit is configured to charge the pull-up control node and maintain the level of the pull-up control node in response to the compensation selection control signal;
  • the blanking pull-up circuit is configured to The blanking pull-up signal is input to the blanking pull-up node under the control of the level of the pull-up control node.
  • the blanking unit further includes a blanking coupling circuit.
  • the blanking coupling circuit is electrically connected to the pull-up control node, and is configured to couple and pull-up the level of the pull-up control node.
  • the blanking input circuit includes a first transistor and a first capacitor.
  • a gate of the first transistor is connected to a compensation selection control terminal to receive the compensation selection control signal, a first pole of the first transistor is connected to a blanking input signal terminal, and a second pole of the first transistor is connected to The pull-up control node is connected; and a first pole of the first capacitor is connected to the pull-up control node, and a second pole of the first capacitor is connected to a first voltage terminal.
  • the blanking pull-up circuit includes a second transistor.
  • the gate of the second transistor is connected to the pull-up control node, the first pole of the second transistor and the second voltage terminal are connected to receive a second voltage, and the second pole of the second transistor and the Blanking pull-up node connections.
  • the blanking coupling circuit includes a coupling capacitor and a third transistor.
  • a gate of the third transistor is connected to the pull-up control node, a first pole of the third transistor is connected to a second voltage terminal to receive a second voltage, and a second pole of the third transistor is connected to the A first pole of the coupling capacitor is connected, and a second pole of the coupling capacitor is connected to the pull-up control node.
  • the first transmission circuit includes a first transmission transistor.
  • the gate of the first transmission transistor is connected to a first transmission signal terminal to receive the first transmission signal, and the first pole of the first transmission transistor is connected to the blanking pull-up node to receive the blanking For a pull-up signal, the second pole of the first transmission transistor is connected to the first pull-up node.
  • the first transmission signal terminal includes a first clock signal terminal, and the first transmission signal includes a first clock received through the first clock signal terminal. signal.
  • the second transmission circuit includes a second transmission transistor.
  • the gate of the second transmission transistor is connected to a second transmission signal terminal to receive the second transmission signal, and the first pole of the second transmission transistor is connected to the blanking pull-up node to receive the blanking For a pull-up signal, a second pole of the second transmission transistor is connected to the second pull-up node.
  • the second transmission signal terminal includes a first clock signal terminal, and the second transmission signal includes a first clock received through the first clock signal terminal. signal.
  • the first input-output unit includes a display input circuit, an output circuit, a first pull-down control circuit, and a pull-down circuit.
  • the first output terminal includes a shift signal output terminal and a pixel scan signal output terminal, and the shift signal output terminal and the pixel scan signal output terminal output the composite output signal; and the display input circuit is configured to respond to Charging the first pull-up node under the first display input signal; the output circuit is configured to output the composite output signal to all of the signals under the control of the level of the first pull-up node;
  • the first output terminal; the first pull-down control circuit is configured to control the level of the pull-down node under the control of the level of the first pull-up node; the pull-down circuit is configured to Under the control of the level of the pull-down node, pull-down reset is performed on the first pull-up node, the shift signal output terminal, and the pixel scan signal output terminal.
  • the display input circuit includes a fourth transistor; a gate of the fourth transistor is connected to a display input signal terminal to receive the first display input signal, A first pole of the fourth transistor is connected to a second voltage terminal to receive a second voltage, and a second pole of the fourth transistor is connected to the first pull-up node;
  • the output circuit includes a fifth transistor and a sixth transistor; a gate of the fifth transistor is connected to the first pull-up node, and a first pole of the fifth transistor is connected to a second clock signal terminal to receive the first transistor.
  • Two clock signals and using the second clock signal as the composite output signal, the second pole of the fifth transistor is connected to the shift signal output terminal; the gate of the sixth transistor and the first transistor
  • the pull-up node is connected, the first pole of the sixth transistor and the second clock signal terminal are connected to receive the second clock signal and use the second clock signal as the composite output signal, the sixth
  • the second electrode of the transistor is connected to the pixel scanning signal output terminal;
  • the first pull-down control circuit includes a seventh transistor and a ninth transistor; a gate of the seventh transistor is connected to the first electrode and is configured to be connected to a third voltage terminal to receive a third voltage, and the seventh The second pole of the transistor is connected to the pull-down node; the gate of the ninth transistor is connected to the first pull-up node, the first pole of the ninth transistor is connected to the pull-down node, and the ninth The second electrode of the transistor and the fifth voltage terminal are connected to receive a fifth voltage;
  • the pull-down circuit includes a tenth transistor, an eleventh transistor, and a twelfth transistor; a gate of the tenth transistor is connected to the pull-down node, and a first pole of the tenth transistor and the first pull-up Node connection, the second pole of the tenth transistor and the fifth voltage terminal are connected to receive the fifth voltage; the gate of the eleventh transistor is connected to the pull-down node, the eleventh transistor The first pole of the transistor is connected to the shift signal output terminal, and the second pole of the eleventh transistor is connected to the fifth voltage terminal to receive the fifth voltage; the gate of the twelfth transistor and The pull-down node is connected, a first pole of the twelfth transistor is connected to the pixel scanning signal output terminal, and a second pole of the twelfth transistor is connected to a sixth voltage terminal to receive a sixth voltage.
  • the output circuit further includes a second capacitor, a first pole of the second capacitor is connected to the first pull-up node, and the second capacitor And the second pole of the fifth transistor is connected to the second pole of the fifth transistor.
  • the first pull-down control circuit further includes an eighth transistor, and a gate of the eighth transistor is connected to the first electrode and is configured to be connected to the fourth electrode.
  • the voltage terminal is connected to receive a fourth voltage
  • the second pole of the eighth transistor is connected to a second pull-down node different from the pull-down node.
  • the first input-output unit further includes a second pull-down control circuit and a third pull-down control circuit.
  • the second pull-down control circuit is configured to control the level of the pull-down node in response to a first clock signal;
  • the third pull-down control circuit is configured to control the pull-down in response to the first display input signal The level of the node is controlled.
  • the second pull-down control circuit includes a thirteenth transistor
  • the third pull-down control circuit includes a fourteenth transistor.
  • the gate of the thirteenth transistor is connected to a first clock signal terminal to receive the first clock signal
  • the first pole of the thirteenth transistor is connected to the pull-down node
  • the thirteenth transistor A second electrode and a fifth voltage terminal are connected to receive a fifth voltage
  • a gate of the fourteenth transistor is connected to a display input signal terminal to receive the first display input signal, and a first electrode of the fourteenth transistor and The pull-down node is connected
  • the second pole of the fourteenth transistor is connected to the fifth voltage terminal to receive the fifth voltage.
  • the second pull-down control circuit includes a thirteenth transistor and a seventeenth transistor
  • the third pull-down control circuit includes a fourteenth transistor.
  • the gate of the thirteenth transistor is connected to a first clock signal terminal to receive the first clock signal, the first pole of the thirteenth transistor is connected to the pull-down node, and the thirteenth transistor
  • a second pole is connected to a first pole of the seventeenth transistor
  • a gate of the seventeenth transistor is electrically connected to the pull-up control node, and a second pole of the seventeenth transistor is connected to a fifth voltage terminal
  • the gate of the fourteenth transistor is connected to a display input signal terminal to receive the first display input signal
  • the first pole of the fourteenth transistor is connected to the pull-down node
  • the The second pole of the fourteenth transistor is connected to the fifth voltage terminal to receive the fifth voltage.
  • the first input-output unit further includes a display reset circuit and a global reset circuit.
  • the display reset circuit is configured to reset the first pull-up node in response to a display reset signal;
  • the global reset signal is configured to reset the first pull-up node in response to a global reset signal.
  • the display reset circuit includes a fifteenth transistor
  • the global reset circuit includes a sixteenth transistor.
  • the gate of the fifteenth transistor is connected to a display reset signal terminal to receive the display reset signal, and the first pole of the fifteenth transistor is connected to the first pull-up node.
  • the second electrode and the fifth voltage terminal are connected to receive the fifth voltage;
  • the gate of the sixteenth transistor is connected to the global reset signal terminal to receive the global reset signal, and the first electrode of the sixteenth transistor and the The first pull-up node is connected, and the second pole of the sixteenth transistor is connected to the fifth voltage terminal to receive the fifth voltage.
  • a circuit structure of the second input-output unit is the same as a circuit structure of the first input-output unit.
  • the shift register unit provided by an embodiment of the present disclosure further includes at least one third transmission circuit and at least one third input-output unit electrically connected to the at least one third transmission circuit.
  • At least one embodiment of the present disclosure further provides a gate driving circuit, which includes a plurality of cascaded shift register units as provided in any one of the embodiments of the present disclosure.
  • At least one embodiment of the present disclosure also provides a display device including any gate driving circuit as provided in the embodiments of the present disclosure and a plurality of sub-pixel units arranged in an array, each of the gate driving circuits
  • the first output terminal and the second output terminal in the shift register unit are electrically connected to the sub-pixel units in different rows, respectively.
  • At least one embodiment of the present disclosure further provides a method for driving a shift register unit, including a display period and a blanking period for one frame, during which the blanking unit is responsive to the compensation selection control.
  • the timings of the first transmission signal and the second transmission signal are the same.
  • FIG. 1 is a schematic diagram of a shift register unit provided by at least one embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of another shift register unit provided by at least one embodiment of the present disclosure.
  • FIG. 3 is a schematic diagram of still another shift register unit provided by at least one embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of a first input-output unit in a shift register unit provided by at least one embodiment of the present disclosure
  • FIG. 5 is a circuit diagram including a blanking unit, a first transmission circuit, and a second transmission circuit according to at least one embodiment of the present disclosure
  • FIG. 6 is another circuit diagram including a blanking unit, a first transmission circuit, and a second transmission circuit provided by at least one embodiment of the present disclosure
  • FIG. 7 is another circuit diagram including a blanking unit, a first transmission circuit, and a second transmission circuit according to at least one embodiment of the present disclosure
  • FIG. 8 is a circuit diagram of a first input-output unit provided by at least one embodiment of the present disclosure.
  • FIG. 9 is a circuit diagram of another first input-output unit according to at least one embodiment of the present disclosure.
  • FIG. 10 is a circuit diagram of still another first input-output unit provided by at least one embodiment of the present disclosure.
  • FIG. 11 is a circuit diagram of still another first input-output unit provided by at least one embodiment of the present disclosure.
  • FIG. 12 is a circuit diagram of a shift register unit provided by at least one embodiment of the present disclosure.
  • FIG. 13 is a schematic diagram of a gate driving circuit provided by at least one embodiment of the present disclosure.
  • FIG. 14 is a schematic diagram of another gate driving circuit provided by at least one embodiment of the present disclosure.
  • FIG. 15 is a timing diagram of signals corresponding to the gate driving circuit shown in FIG. 14 during operation according to at least one embodiment of the present disclosure
  • 16 is a schematic diagram of a display device provided by at least one embodiment of the present disclosure.
  • FIG. 17 is a schematic diagram of a driving method of a shift register unit provided by at least one embodiment of the present disclosure.
  • pulse-up means charging a node or an electrode of a transistor so that the absolute level of the node or the electrode is The value increases to achieve the operation of the corresponding transistor (for example, turn on);
  • pulse-down means to discharge a node or an electrode of a transistor so that the absolute value of the level of the node or the electrode is reduced to achieve the corresponding Operation of the transistor (e.g. off).
  • pulse-up means discharging a node or an electrode of a transistor so that the absolute value of the level of the node or the electrode is reduced, thereby realizing the corresponding transistor.
  • Operation (such as turning on);
  • pulse-down means charging a node or an electrode of a transistor so that the absolute value of the level of the node or the electrode increases, thereby realizing the operation of the corresponding transistor (such as turning off) .
  • pulse-up and pulse-down will also be adjusted accordingly according to the specific type of transistor used, as long as the transistor can be controlled to achieve the corresponding switching function.
  • the gate drive circuit for OLED is usually composed of three sub-circuits, that is, a detection circuit, a display circuit, and a connection circuit (or gate circuit) that outputs a composite pulse of both.
  • a detection circuit a detection circuit
  • a display circuit a display circuit
  • a connection circuit or gate circuit
  • a gate drive circuit composed of a shift register unit needs to provide a driving signal for a scanning transistor and a sensing transistor to a sub-pixel unit in a display panel, for example, for a display period of one frame.
  • a sensing drive signal for the sensing transistor is provided in a blanking period of one frame.
  • the sensing driving signal output by the gate driving circuit is sequentially scanned line by line. For example, during the blanking period of the first frame, the sensing for the sub-pixel units of the first line in the display panel is output. Measure the driving signal, and output the sensing driving signal for the sub-pixel units in the second row of the display panel during the blanking period of the second frame, and so on, and output the frequency of the sensing driving signal corresponding to one row of the sub-pixel units in each frame.
  • Line-by-line sequential output that is, the line-by-line sequential compensation of the display panel is completed.
  • the following display problems may occur: one is that there is a scanning line that moves progressively during the scanning display of multiple frames of images; the second is due to the time for external compensation There are differences in points, which may cause a large difference in brightness in different areas of the display panel.
  • the sub-pixel units in the 10th row of the display panel are It has been compensated externally, but at this time, the luminous brightness of the sub-pixel unit in the tenth row may have changed, for example, the luminous brightness is reduced, which may cause uneven brightness in different areas of the display panel. This problem occurs in large-sized display panels. It will be more obvious.
  • the gate driving circuit when a gate driving circuit drives a display panel, if external compensation is to be achieved, the gate driving circuit is required to output not only a scan driving signal for a display period, but also a signal for a blanking period.
  • the sensing driving signal requires a blanking unit dedicated to a blanking period.
  • the area occupied by the gate driving circuit may be relatively large, so that the size of the frame of the display device using the gate driving circuit is larger.
  • a shift register unit which includes a blanking unit, a first transmission circuit, a second transmission circuit, a first input-output unit, and a second input-output unit.
  • the blanking unit is configured to charge the pull-up control node in response to the compensation selection control signal and input the blanking pull-up signal to the blanking pull-up node;
  • the first input-output unit includes a first pull-up node and a first output terminal.
  • the second input-output unit includes a second pull-up node and a second output terminal; the first transmission circuit is electrically connected to the blanking pull-up node and the first pull-up node, and is configured to utilize blanking in response to the first transmission signal.
  • the pull-up signal charges the first pull-up node;
  • the second transmission circuit is electrically connected to the blanking pull-up node and the second pull-up node, and is configured to respond to the second transmission signal by using the blanking pull-up signal to charge the second
  • the pull-up node performs charging;
  • the first input-output unit is configured to charge the first pull-up node in response to the first display input signal, and is configured to charge the composite output signal under the control of the level of the first pull-up node Output to the first output terminal;
  • the second input-output unit is configured to charge the second pull-up node in response to the second display input signal, and is configured to charge the second pull-up node; Under the control of the composite output signal to the second output terminal.
  • Embodiments of the present disclosure also provide a gate driving circuit, a display device, and a driving method corresponding to the above-mentioned shift register unit.
  • the shift register unit, the gate driving circuit, the display device and the driving method provided by the embodiments of the present disclosure can share a blanking unit, so that the display device using the shift register unit can reduce the frame size and cost;
  • the progressive order compensation such as the need for progressive order compensation in the shutdown detection
  • random compensation can also be implemented, which can avoid poor display such as scanning lines and uneven display brightness caused by progressive order compensation. problem.
  • random compensation refers to an external compensation method that is different from progressive compensation.
  • the use of random compensation can randomly output a blanking period in a frame corresponding to the display panel.
  • the sensing driving signals of the sub-pixel units in any row are the same in the following embodiments, and will not be described again.
  • the definition of "one frame”, “each frame”, or “a certain frame” includes a display period and a blanking period performed in sequence, such as gate driving in the display period.
  • the circuit outputs a display output signal.
  • the display output signal can drive the display panel to complete a complete scanning display of an image from the first line to the last line (ie, the scanning display of a frame of image).
  • the gate drive circuit outputs during the blanking period.
  • the blanking output signal can be used to drive a sensing transistor in a row of sub-pixel units in the display panel to complete external compensation of the row of sub-pixel units.
  • the shift register unit 10 includes a blanking unit 100, a first transmission circuit 210, a second transmission circuit 220, and a first input / output.
  • Unit 310 and second input-output unit 320 The first input-output unit 310 includes a first pull-up node Q1 and a first output terminal OP1, and the second input-output unit Q2 includes a second pull-up node Q2 and a second output terminal OP2.
  • a plurality of the shift register units 10 may be cascaded to construct a gate driving circuit provided by an embodiment of the present disclosure.
  • the blanking unit 100 is configured to charge the pull-up control node H and input a blanking pull-up signal to the blanking pull-up node N in response to the compensation selection control signal. For example, during a display period of one frame, the blanking unit 100 may charge the pull-up control node H in response to a compensation selection control signal; for example, during a display period or a blanking period of one frame, the blanking unit 100 will blank the pull-up control node H.
  • the hidden pull-up signal is input to the blanked pull-up node N.
  • the first transmission circuit 210 is electrically connected to the blanking pull-up node N and the first pull-up node Q1, and is configured to charge the first pull-up node Q1 by using the blanking pull-up signal in response to the first transmission signal.
  • the first transmission circuit 210 may be connected to the first transmission signal terminal TS1 to receive the first transmission signal.
  • the first transmission circuit 210 is turned on under the control of the first transmission signal, so that it can be obtained by using the blanking pull-up node N.
  • the blanking pull-up signal charges the first pull-up node Q1.
  • the first transmission signal terminal TS1 may be a first clock signal terminal CLKA, that is, the first transmission signal is a first clock signal received by the first clock signal terminal CLKA.
  • the second transmission circuit 220 is electrically connected to the blanking pull-up node N and the second pull-up node Q2, and is configured to charge the second pull-up node Q2 by using the blanking pull-up signal in response to the second transmission signal.
  • the second transmission circuit 220 may be connected to the second transmission signal terminal TS2 to receive the second transmission signal.
  • the second transmission circuit 220 is turned on under the control of the second transmission signal, so that it can be obtained by using the blanking pull-up node N.
  • the blanking pull-up signal charges the second pull-up node Q2.
  • the second transmission signal terminal TS2 may be a first clock signal terminal CLKA, that is, the second transmission signal is a first clock signal received by the first clock signal terminal CLKA.
  • charging a node indicates that, for example, the node is connected with a high-power
  • the flat voltage signal is electrically connected, so that the high-level voltage signal is used to raise the level of the node; discharging (or resetting) a node means, for example, electrically connecting the node to a low-level voltage signal, Thus, the low-level voltage signal is used to pull down the level of the node.
  • a capacitor electrically connected to the node can be set, and charging or discharging the node means charging or discharging the capacitor electrically connected to the node.
  • the first input-output unit 310 is configured to charge the first pull-up node Q1 in response to the first display input signal, and is configured to output a composite output signal to the first pull-up node Q1 under the control of the level of the first pull-up node Q1.
  • the first input-output unit 310 may output a scanning driving signal, and the scanning driving signal may drive a certain row of sub-pixel units in the display panel to perform scanning display.
  • the first input-output unit 310 may output a sensing driving signal, and the sensing driving signal may be used to drive a sensing transistor in a row of sub-pixel units in a display panel to complete External compensation for the sub-pixel units of the row.
  • the second input-output unit 320 is configured to charge the second pull-up node Q2 in response to the second display input signal, and is configured to output a composite output signal to the first pull-up node Q2 under the control of the level of the second pull-up node Q2.
  • the second input-output unit 320 may output a scanning driving signal, and the scanning driving signal may drive a certain row of sub-pixel units in the display panel for scanning display.
  • the second input-output unit 320 may output a sensing driving signal, and the sensing driving signal may be used to drive a sensing transistor in a row of sub-pixel units in a display panel to complete External compensation for the sub-pixel units of the row.
  • some embodiments of the present disclosure further provide a shift register unit 10.
  • the shift register unit 10 is different from the shift register unit 10 shown in FIG. 1 in that it further includes a third transmission.
  • the circuit 230 and a third input-output unit 330 electrically connected to the third transmission circuit 230.
  • the third transmission circuit 230 is electrically connected to the blanking pull-up node N and the third pull-up node Q3, and is configured to charge the third pull-up node Q3 by using the blanking pull-up signal in response to the third transmission signal.
  • the third input-output unit 330 is configured to charge the third pull-up node Q3 in response to the third display input signal, and is configured to output a composite output signal to the third pull-up node Q3 under the control of the level of the third pull-up node Q3.
  • the circuit structure can be simplified, so that the display device using the shift register unit 10 can reduce the frame size and reduce the cost.
  • FIG. 1 and FIG. 2 are only two examples of the present disclosure.
  • the shift register unit 10 provided by the embodiment of the present disclosure may further include more transmission circuits and input-output units, the transmission circuit and the input-output unit.
  • the number can be set according to the actual situation, which is not limited in the embodiments of the present disclosure.
  • the blanking unit 100 includes a blanking input circuit 110 and a blanking pull-up circuit 120.
  • the blanking input circuit 110 is configured to charge the pull-up control node H and maintain the level of the pull-up control node H in response to the compensation selection control signal.
  • the blanking input circuit 110 may be connected to the blanking input signal terminal STU1 and the compensation selection control terminal OE, so that under the control of the compensation selection control signal input by the compensation selection control terminal OE, the blanking may be used.
  • the blanking input signal input from the input signal terminal STU1 charges the pull-up control node H and maintains the level of the pull-up control node H.
  • the blanking input circuit 110 can charge the pull-up control node H in a display period of one frame, thereby pulling up the level of the pull-up control node H to a high level, and can pull up the high voltage of the pull-up control node H. The level is maintained until the blanking period of the frame.
  • the blanking pull-up circuit 120 is configured to input a blanking pull-up signal to the blanking pull-up node N under the control of the level of the pull-up control node H.
  • the blanking pull-up circuit 120 may be connected to the second voltage terminal VDD to receive a second voltage, and use the second voltage as a blanking pull-up signal; for another example, the blanking pull-up circuit 120 also It can be connected to the first clock signal terminal CLKA to receive the first clock signal, and use the first clock signal as a blanking pull-up signal.
  • the pull-up control node H is at a high level
  • the blanking pull-up circuit 120 is turned on, so that a blanking pull-up signal can be input to the blanking pull-up node N.
  • the second voltage terminal VDD may be configured to provide a DC high-level signal, that is, the second voltage is high.
  • the following embodiments are the same, and will not be described again.
  • the blanking unit 100 may further include a blanking coupling circuit 130.
  • the blanking coupling circuit 130 is electrically connected to the pull-up control node H, and is configured to couple and pull-up the pull-up control node H.
  • the blanking coupling circuit 130 may be connected to the second voltage terminal VDD to receive the second voltage; for another example, the blanking coupling circuit 130 may also be connected to the first clock signal terminal CLKA to receive the first clock signal.
  • the blanking coupling circuit may use the second voltage or the first clock signal to couple and pull-up the pull-up control node H, so as to avoid leakage of the pull-up control node H.
  • a blanking unit for example, a blanking input circuit, a blanking pull-up circuit, and a blanking coupling circuit
  • a blanking output signal can be output during the blanking period.
  • the “blanking” in the blanking input circuit, the blanking pull-up circuit, and the blanking coupling circuit merely indicates that these circuits are related to the blanking period, and does not limit these circuits to work only during the blanking period. The following embodiments The same is not repeated here.
  • the blanking input circuit 110 may be implemented to include a first transistor M1 and a first capacitor C1.
  • the gate of the first transistor M1 is connected to the compensation selection control terminal OE to receive the compensation selection control signal.
  • the first pole of the first transistor M1 is connected to the blanking input signal terminal STU1 to receive the blanking input signal.
  • the two poles are connected to the pull-up control node H.
  • the compensation selection control signal is a high-level on signal
  • the first transistor M1 is turned on, so that the blanking input signal can be used to charge the pull-up control node H.
  • the first pole of the first capacitor C1 is connected to the pull-up control node H, and the second pole of the first capacitor C1 is connected to the first voltage terminal VGL1.
  • the level of the pull-up control node H can be maintained. For example, in a display period of one frame, the blanking input circuit 110 charges the pull-up control node H to a high level, and the first capacitor C1 can set the pull-up control node H to a high level. Pull the control node H high to the blanking period of the frame.
  • the second pole of the first capacitor C1 may be connected to other voltage terminals in addition to the first voltage terminal VGL1, for example, the second pole of the first capacitor C1 is grounded. The embodiments of the present disclosure are not limited thereto.
  • the first voltage terminal VGL1 may be configured to provide a DC low-level signal, that is, the first voltage is a low level.
  • the following embodiments are the same, and are not described again.
  • the blanking pull-up circuit 120 may be implemented as the second transistor M2.
  • the gate of the second transistor M2 is connected to the pull-up control node H.
  • the first electrode of the second transistor M2 is connected to the second voltage terminal VDD to receive the second voltage and use the second voltage as a blanking pull-up signal.
  • the second transistor The second pole of M2 is connected to the blanking pull-up node N.
  • the second transistor M2 when the pull-up control node H is high, the second transistor M2 is turned on, so that a blanking pull-up signal can be input to the blanking pull-up node N.
  • the first pole of the second transistor M2 may also be connected to the first clock signal terminal CLKA to receive the first clock signal and use the first clock signal as a blanking pull-up. signal.
  • the blanking coupling circuit 130 may be implemented to include a coupling capacitor CST and a third transistor M3.
  • the gate of the third transistor M3 is connected to the pull-up control node H.
  • the first electrode of the third transistor M3 is connected to the second voltage terminal VDD to receive the second voltage.
  • the second electrode of the third transistor M3 is connected to the first terminal of the coupling capacitor CST.
  • One pole is connected, and the second pole of the coupling capacitor CST is connected to the pull-up control node H.
  • the third transistor M3 is turned on, so that the second voltage can be applied to the first pole of the coupling capacitor CST.
  • the high-level second voltage can be coupled and pulled up by the coupling capacitor CST to the level of the pull-up control node H, so that leakage of the pull-up control node H can be avoided.
  • the first pole of the third transistor M3 may also be connected to the first clock signal terminal CLKA to receive the first clock signal.
  • the third transistor M3 when the pull-up control node H is at a high level, the third transistor M3 is turned on, so that the first clock signal can be applied to the first pole of the coupling capacitor CST.
  • the first clock signal when the first clock signal is at a high level, the first clock signal can be coupled to pull-up the level of the pull-up control node H through the coupling capacitor CST, thereby avoiding leakage of the pull-up control node H.
  • the first transmission circuit 210 may be implemented as a first transmission transistor MT1.
  • the gate of the first transmission transistor MT1 is connected to the first transmission signal terminal TS1 to receive the first transmission signal.
  • the first pole of the first transmission transistor MT1 is connected to the blanking pull-up node N to receive the blanking pull-up signal.
  • the second pole of the transfer transistor MT1 is connected to the first pull-up node Q1. For example, when the first transmission signal is at a high level, the first transmission transistor MT1 is turned on, so that the first pull-up node Q1 can be charged by using the blanking pull-up signal.
  • the second transmission circuit 220 may be implemented as a second transmission transistor MT2.
  • the gate of the second transmission transistor MT2 is connected to the second transmission signal terminal TS2 to receive the second transmission signal
  • the first electrode of the second transmission transistor MT2 is connected to the blanking pull-up node N to receive the blanking pull-up signal
  • the second The second pole of the transfer transistor MT2 is connected to the second pull-up node Q2. For example, when the second transmission signal is at a high level, the second transmission transistor MT2 is turned on, so that the second pull-up node Q2 can be charged by using the blanking pull-up signal.
  • the gates of the first transmission transistor MT1 and the second transmission transistor MT2 may be connected to the first clock signal terminal CLKA to receive the same first clock signal.
  • the first clock signal is at a high level
  • the first transfer transistor MT1 and the second transfer transistor MT2 are turned on at the same time, so that the first pull-up node Q1 and the second pull-up node Q2 can be simultaneously performed by using the blanking pull-up signal. Charging.
  • the first input-output unit 310 includes a display input circuit 200, an output circuit 300, a first pull-down control circuit 400, and a pull-down circuit 500.
  • the first output terminal OP1 includes a shift signal output terminal CR and a pixel scanning signal output terminal OUT, and the shift signal output terminal CR and a pixel scanning signal output terminal OUT output a composite output signal.
  • the display input circuit 200 is configured to charge the first pull-up node Q1 in response to a first display input signal.
  • the display input circuit 200 may be connected to the display input signal terminal STU2 to receive the first display input signal, so that the display input circuit 200 is turned on under the control of the first display input signal.
  • the display input circuit 200 may also be connected to the second voltage terminal VDD to receive the second voltage. For example, during a display period of one frame, the display input circuit 200 is turned on under the control of the first display input signal, so that the second pull-up node Q1 can be charged with the second voltage.
  • the display input signal terminal STU2 of the input and output units at each level may be electrically connected to the output terminals of the first two input and output units.
  • the display input signal terminal STU2 of the input-output unit of this stage can be electrically connected to the shift signal output terminal CR of the input-output unit of the first two stages. connection.
  • the first two-stage input-output units means the second-stage input-output unit from the current-stage input-output unit
  • the last three-stage input-output units means the current-stage input-output unit from the back.
  • the third input-output unit where "front” and “rear” are relative. The following embodiments are the same and will not be described again.
  • the display input circuit 200 may also adopt other configurations, as long as the corresponding functions can be realized, and the embodiments of the present disclosure do not limit this.
  • the output circuit 300 is configured to output a composite output signal to the first output terminal OP1 under the control of the level of the first pull-up node Q1.
  • the output circuit 300 may be connected to the second clock signal terminal CLKB to receive the second clock signal, and use the second clock signal as a composite output signal.
  • the composite output signal may include a display output signal and a blanking output signal. During a display period of one frame, the output circuit 300 outputs the display output signal to the first output terminal under the control of the level of the first pull-up node Q1.
  • the first output terminal OP1 may include a shift signal output terminal CR and a pixel scanning signal output terminal OUT, and a display output signal output from the shift signal output terminal CR may be used for upper and lower shift register units.
  • the scanning output is shifted, and the display output signal output from the pixel scanning signal output terminal OUT can be used to drive a sub-pixel unit in the display panel for scanning display.
  • the output circuit 300 outputs a blanking output signal to the first output terminal OP1 under the control of the level of the first pull-up node Q1.
  • the blanking output signal can be used to drive the sensing transistor. .
  • the first pull-down control circuit 400 is configured to control the level of the pull-down node QB under the control of the level of the first pull-up node Q1.
  • the first pull-down control circuit 400 is connected to the third voltage terminal VDD_A and the fifth voltage terminal VGL2.
  • the fifth voltage terminal VGL2 may be configured to provide a fifth voltage, for example, the fifth voltage is a DC low-level signal. The following embodiments are the same, and are not repeated here. .
  • the first pull-down control circuit 400 may pull down the pull-down node QB to a low level through a fifth voltage of a low level provided by the fifth voltage terminal VGL2.
  • the first pull-down control circuit 500 may use a third voltage (for example, a high level) input from the third voltage terminal VDD_A to charge the pull-down node QB. To pull up the pull-down node QB to a high level.
  • the first pull-down control circuit 400 may also be connected to the fourth voltage terminal VDD_B to receive a fourth voltage (for example, a high level).
  • a fourth voltage for example, a high level
  • the third voltage terminal VDD_A and the fourth voltage terminal VDD_B may be It is configured to alternately input a high level, that is, when the third voltage terminal VDD_A inputs a high level, the fourth voltage terminal VDD_B inputs a low level, and when the third voltage terminal VDD_A inputs a low level, the fourth voltage terminal VDD_B inputs a high level.
  • the pull-down circuit 500 is configured to pull-down reset the first pull-up node Q1 and the first output terminal OP1 under the control of the level of the pull-down node QB.
  • the pull-down circuit 500 may perform a pull-down reset on the shift signal output terminal CR and the pixel scan signal output terminal OUT at the same time.
  • the pull-down circuit 500 when the pull-down circuit 500 is connected to the fifth voltage terminal VGL2, and when the pull-down circuit 500 is turned on under the control of the level of the pull-down node QB, the first voltage can be applied to the first through the low-level fifth voltage provided by the fifth voltage terminal VGL2
  • the pull-up node Q1, the shift signal output terminal CR, and the pixel scan signal output terminal OUT are pulled down to implement a reset.
  • the first input-output unit 310 may further include a second pull-down control circuit 600 configured to respond to the level of the pull-down node QB in response to the first clock signal. Take control.
  • the second pull-down control circuit 600 may be connected to the first clock signal terminal CLKA to receive a first clock signal, and at the same time connected to the fifth voltage terminal VGL2 to receive a fifth voltage of a low level.
  • the second pull-down control circuit 600 may be turned on in response to the first clock signal, so as to control the level of the pull-down node QB by using a fifth voltage of a low level, for example, The level of the pull-down node QB is pulled down.
  • the first input-output unit 310 may further include a third pull-down control circuit 700 configured to respond to the power of the pull-down node QB in response to the first display input signal. Ping for control.
  • the third pull-down control circuit 700 may be connected to the display input signal terminal STU2 to receive the first display input signal, and connected to the fifth voltage terminal VGL2 to receive the fifth voltage at a low level.
  • the third pull-down control circuit 700 may be turned on in response to the first display input signal, so as to control the level of the pull-down node QB by using a fifth voltage of a low level, for example, The level of the pull-down node QB is pulled down.
  • Pulling down the level of the pull-down node QB to a low level can avoid the influence of the level of the pull-down node QB on the level of the first pull-up node Q1, so that the display input circuit 200 can pull the first pull-up during the display period. Node Q1 is more fully charged.
  • the first input-output unit 310 may further include a display reset circuit 800 configured to reset the first pull-up node Q1 in response to a display reset signal.
  • the display reset circuit 800 may be connected to the display reset signal terminal STD to receive a display reset signal, and at the same time connected to the fifth voltage terminal VGL2 to receive a fifth voltage at a low level.
  • the display reset circuit 800 may be turned on in response to the display reset signal, so that the first pull-up node Q1 may be performed by the fifth low-level voltage provided by the fifth voltage terminal VGL2. Reset.
  • the display reset signal terminal STD of the I / O units of each level may be electrically connected to the output terminal (eg, the shift signal output terminal CR) of the last three I / O units.
  • the first input-output unit 310 may further include a global reset circuit 900 configured to reset the first pull-up node Q1 in response to a global reset signal.
  • the global reset circuit 900 is connected to the global reset signal terminal TRST to receive a global reset signal, and is simultaneously connected to the fifth voltage terminal VGL2 to receive a fifth voltage of a low level.
  • the global reset circuit 900 in the input-output units at all levels is turned on in response to the global reset signal, so that it can be provided through the fifth voltage terminal VGL2.
  • the low-level fifth voltage resets the first pull-up node Q1, thereby implementing a global reset of the input-output units at all levels.
  • first input-output unit 310 in FIG. 4 shows a first pull-down control circuit 400, a pull-down circuit 500, a second pull-down control circuit 600, a third pull-down control circuit 700, and a display reset circuit 800 and the global reset circuit 900
  • the above examples cannot limit the protection scope of the present disclosure.
  • those skilled in the art may choose to adopt or not adopt one or more of the above circuits according to the situation. Based on the various combinations and modifications of the foregoing circuits, the principles of the present disclosure are not deviated, and details are not described herein again.
  • the first input-output unit 310 shown in FIG. 4 may be implemented as the circuit structure shown in FIG. 8.
  • the first input-output unit 310 includes fourth to seventeenth transistors M4-M17 and a second capacitor C2.
  • the first output terminal OP1 includes a shift signal output terminal CR and a pixel scanning signal output terminal OUT. Both the shift signal output terminal CR and the pixel scanning signal output terminal OUT can output a composite output signal.
  • the transistors shown in FIG. 8 are all described by taking N-type transistors as an example.
  • the transistors shown in other drawings of the present disclosure are also described by taking N-type transistors as an example, and details are not described herein again.
  • the display input circuit 200 may be implemented as a fourth transistor M4.
  • the gate of the fourth transistor M4 is connected to the display input signal terminal STU2 to receive the first display input signal.
  • the two voltage terminals VDD are connected to receive the second voltage, and the second pole of the fourth transistor M4 is connected to the first pull-up node Q1.
  • the fourth transistor M4 is turned on under the control of the first display input signal, so that the second pull-up node Q1 can be charged with the second voltage.
  • the output circuit 300 may be implemented to include a fifth transistor M5, a sixth transistor M6, and a second capacitor C2.
  • the gate of the fifth transistor M5 is connected to the first pull-up node Q1.
  • the first pole of the fifth transistor M5 is connected to the second clock signal terminal CLKB to receive the second clock signal, and the second clock signal is used as a composite output signal.
  • the second pole of the fifth transistor M5 is connected to the shift signal output terminal CR; the gate of the sixth transistor M6 is connected to the first pull-up node Q1, and the first pole of the sixth transistor M6 is connected to the second clock signal terminal CLKB to Receive a second clock signal and use the second clock signal as a composite output signal.
  • the second pole of the sixth transistor M6 is connected to the pixel scanning signal output OUT; the first pole of the second capacitor C2 is connected to the first pull-up node Q1.
  • the second pole of the second capacitor C2 is connected to the second pole of the fifth transistor M5. For example, when the level of the first pull-up node Q1 is high, the fifth transistor M5 and the sixth transistor M6 are turned on, so that the second clock signal can be output to the shift signal output terminal CR as a composite output signal, respectively. And pixel scan signal output terminal OUT.
  • the first pull-down control circuit 400 may be implemented to include a seventh transistor M7, an eighth transistor M8, and a ninth transistor M9.
  • the gate of the seventh transistor M7 is connected to the first pole and is configured to be connected to the third voltage terminal VDD_A to receive the third voltage, and the second pole of the seventh transistor M7 is connected to the pull-down node QB;
  • the gate of the eighth transistor M8 Connected to the first pole and configured to be connected to the fourth voltage terminal VDD_B to receive the fourth voltage, the second pole of the eighth transistor M8 and the pull-down node QB are connected;
  • the gate of the ninth transistor M9 and the first pull-up node Q1 Connected, the first pole of the ninth transistor M9 and the pull-down node QB are connected, and the second pole of the ninth transistor M9 and the fifth voltage terminal VGL2 are connected to receive the fifth voltage.
  • the third voltage terminal VDD_A and the fourth voltage terminal VDD_B may be configured to alternately input a high level, that is, when the third voltage terminal VDD_A inputs a high level, the fourth voltage terminal VDD_B inputs a low level, and the third voltage terminal VDD_A
  • a low level is input
  • a high level is input to the fourth voltage terminal VDD_B, that is, only one of the seventh transistor M7 and the eighth transistor M8 is turned on, so that performance drift caused by the transistor being turned on for a long time can be avoided.
  • the seventh transistor M7 or the eighth transistor M8 When the seventh transistor M7 or the eighth transistor M8 is turned on, the third voltage or the fourth voltage can charge the pull-down node QB, thereby pulling up the level of the pull-down node QB to a high level.
  • the ninth transistor M9 When the level of the first pull-up node Q1 is high, the ninth transistor M9 is turned on.
  • the ninth transistor M9 and the seventh transistor M7 (or the eighth transistor M8) may be configured as (For example, the size ratio of the two, the threshold voltage, etc.)
  • the level of the pull-down node QB can be pulled down to a low level.
  • the low level can make the first The ten transistor M10, the eleventh transistor M11, and the twelfth transistor M12 are kept in an off state.
  • the pull-down circuit 500 may be implemented to include a tenth transistor M10, an eleventh transistor M11, and a twelfth transistor M12.
  • the gate of the tenth transistor M10 is connected to the pull-down node QB, the first pole of the tenth transistor M10 is connected to the first pull-up node Q1, and the second pole of the tenth transistor M10 is connected to the fifth voltage terminal VGL2 to receive the fifth voltage
  • the gate of the eleventh transistor M11 is connected to the pull-down node QB, the first pole of the eleventh transistor M11 is connected to the shift signal output terminal CR, and the second pole of the eleventh transistor M11 and the fifth voltage terminal VGL2 are connected to Receive a fifth voltage;
  • the gate of the twelfth transistor M12 is connected to the pull-down node QB, the first pole of the twelfth transistor M12 is connected to the pixel scanning signal output OUT, and the second pole of the twelfth transistor M12 and the sixth voltage
  • the tenth transistor M10, the eleventh transistor M11, and the twelfth transistor M12 are turned on, so that the fifth pull-up node at a low level can be used for the first pull-up node
  • the level of Q1 and the level of the shift signal output terminal CR are pulled down to reduce the operation, and the sixth level of the low level voltage may be used to pull down the level of the pixel scanning signal output OUT to reduce noise.
  • the low-level signals input to the first voltage terminal VGL1, the fifth voltage terminal VGL2, and the sixth voltage terminal VGL3 may be the same, that is, the three voltage terminals may be connected.
  • the three voltage terminals can be connected to different signal lines to receive different low-level signals respectively.
  • the embodiments of the present disclosure do not limit the manner of setting the first voltage terminal VGL1, the fifth voltage terminal VGL2, and the sixth voltage terminal VGL3.
  • the second pull-down control circuit 600 may be implemented as a thirteenth transistor M13.
  • the gate of the thirteenth transistor M13 is connected to the first clock signal terminal CLKA to receive the first clock signal
  • the first pole of the thirteenth transistor M13 is connected to the pull-down node QB
  • the voltage terminal VGL2 is connected to receive a fifth voltage.
  • the thirteenth transistor M13 is turned on, so that the pull-down node QB can be pulled down with a fifth voltage of a low level.
  • the second pull-down control circuit 600 may further include a seventeenth transistor M17.
  • the gate of the seventeenth transistor M17 is electrically connected to the pull-up control node H, the first pole of the seventeenth transistor M17 and the second pole of the thirteenth transistor M13 are connected, and the second pole of the seventeenth transistor M17 and the fifth
  • the voltage terminal VGL2 is connected to receive a fifth voltage.
  • the thirteenth transistor M13 and the seventeenth transistor M17 are turned on, so that the pull-down node QB is electrically connected to the fifth voltage terminal VGL2, so that the level of the pull-down node QB can be pulled down to a low level by using a fifth voltage of a low level.
  • the third pull-down control circuit 700 may be implemented as a fourteenth transistor M14.
  • the gate of the fourteenth transistor M14 is connected to the display input signal terminal STU2 to receive the first display input signal
  • the first pole of the fourteenth transistor M14 is connected to the pull-down node QB
  • the voltage terminal VGL2 is connected to receive a fifth voltage.
  • the fourteenth transistor M14 may be turned on in response to the first display input signal, so as to pull down the level of the pull-down node QB by using a fifth voltage of a low level.
  • Pulling down the level of the pull-down node QB to a low level can avoid the influence of the level of the pull-down node QB on the level of the pull-up node Q, thereby making the fourth transistor M4 charge the pull-up node Q more in the display period. full.
  • the display input signal terminal STU2 of each I / O unit may be electrically connected to the shift signal output terminal CR of the first two I / O units. That is, the first display input signal may be a signal output from the shift signal output terminal CR of the input and output units of the first two stages.
  • the display reset circuit 800 may be implemented as a fifteenth transistor M15.
  • the gate of the fifteenth transistor M15 is connected to the display reset signal terminal STD to receive the display reset signal.
  • the first pole of the fifteenth transistor M15 is connected to the first pull-up node Q1, and the second pole of the fifteenth transistor M15 is connected to the first
  • the five voltage terminal VGL2 is connected to receive a fifth voltage.
  • the fifteenth transistor M15 may be turned on in response to a display reset signal, so that the first pull-up node Q1 may be reset by using a fifth voltage of a low level.
  • the display reset signal terminal STD of the input and output units of each level can be electrically connected to the shift signal output terminal CR of the last three input and output units, that is, the display reset signal can be the last three The signal output from the shift signal output terminal CR of the input-output unit.
  • the global reset circuit 900 may be implemented as a sixteenth transistor M16.
  • the gate of the sixteenth transistor M16 is connected to the global reset signal terminal TRST to receive the global reset signal
  • the first pole of the sixteenth transistor M16 is connected to the first pull-up node Q1
  • the second pole of the sixteenth transistor M16 is connected to the first
  • the five voltage terminal VGL2 is connected to receive a fifth voltage.
  • the sixteenth transistor M16 in the input-output units at all levels is turned on in response to the global reset signal, and passes the low-level fifth voltage
  • the first pull-up node Q1 is reset, thereby implementing a global reset of the input and output units at all levels.
  • FIG. 9 other embodiments of the present disclosure further provide a first input-output unit 310.
  • the output circuit 300 further includes an eighteenth transistor M18 and a third capacitor C3, and accordingly, the pull-down circuit 500 further includes a nineteenth transistor M19.
  • the gate of the eighteenth transistor M18 is connected to the first pull-up node Q1, and the first pole of the eighteenth transistor M18 is connected to the third clock signal terminal CLKC to receive the third clock signal.
  • the second electrode of the transistor M18 is connected to another pixel scanning signal output terminal OUT2.
  • the first pole of the third capacitor C3 is connected to the first pull-up node Q1, and the second pole of the third capacitor C3 is connected to the second pole of the eighteenth transistor M18. For example, when the level of the first pull-up node Q1 is high, the eighteenth transistor M18 is turned on, so that the third clock signal is output to the pixel scanning signal output terminal OUT2.
  • the third clock signal input from the third clock signal terminal CLKC may be configured to be the same as the second clock signal input from the second clock signal terminal CLKB; for another example, in another example, the third clock signal It can also be configured to be different from the second clock signal, so that the two pixel scanning signal output terminals OUT and OUT2 can respectively output different signals, thereby improving the driving capability of the shift register unit and increasing the diversity of output signals.
  • the level holding capability of the first pull-up node Q1 can be improved by setting the third capacitor C3.
  • the third capacitor C3 may not be provided. Examples do not limit this.
  • the gate of the nineteenth transistor M19 is connected to the pull-down node QB, the first pole of the nineteenth transistor M19 is connected to the pixel scanning signal output OUT2, and the second pole of the nineteenth transistor M19 is connected to the sixth The voltage terminal VGL3 is connected.
  • the nineteenth transistor M19 is turned on, so that the level of the pixel scanning signal output terminal OUT2 can be pulled down and reset by using a low-level sixth voltage.
  • the second pole of the nineteenth transistor M19 can also be configured to be connected to other signal terminals, as long as the pixel scanning signal output terminal OUT2 can be pulled down and reset, which is not limited in the embodiments of the present disclosure.
  • the first capacitor C1 can be used to maintain the level at the pull-up control node H
  • the second capacitor C2 can be used to maintain the level at the first pull-up node Q1.
  • the first capacitor C1 and / or the second capacitor C2 may be a capacitive device manufactured by a process, for example, a capacitive device is realized by manufacturing a special capacitor electrode, and each electrode of the capacitor may be a metal layer or a semiconductor layer (for example, doped polysilicon). ), Or in some examples, by designing circuit wiring parameters so that the first capacitor C1 and / or the second capacitor C2 can also be implemented by parasitic capacitance between various devices.
  • connection method of the first capacitor C1 and / or the second capacitor C2 is not limited to the method described above, and may also be other suitable connection methods, as long as it can be stored in the pull-up control node H or the first pull-up node Q1. Level.
  • the level of the first pull-up node Q1 and / or the pull-up control node H is maintained at a high level, there are some transistors (for example, the first transistor M1, the tenth transistor M10, the fifteenth transistor M15, and the sixteenth transistor M16). And the first pole of the first transfer transistor TM1) is connected to the first pull-up node Q1 or the pull-up control node H, and the second pole is connected to the low-level signal. Even in the case where a non-conducting signal is input to the gates of these transistors, leakage may occur due to a voltage difference between the first and second poles of the transistors. The effect of the level maintenance of the pull-up node Q1 and / or the pull-up control node H becomes worse.
  • the pull-up control node H is taken as an example.
  • the first pole of the first transistor M1 is connected to the blanking input signal terminal STU1, and the second pole is connected to the pull-up control node H.
  • the pull-up control node H may leak electricity through the first transistor M1.
  • some embodiments of the present disclosure also provide a circuit structure having a leakage prevention structure.
  • the transistors M1_b, MT1_b, MT2_b, M10_b, M15_b, M16_b, M20, and M21 are added.
  • the working principle of leakage prevention will be described using the transistor M1_b as an example.
  • the gate of the transistor M1_b is connected to the gate of the first transistor M1, the first pole of the transistor M1_b is connected to the second pole of the transistor M20, and the second pole of the transistor M1_b is connected to the pull-up control node H.
  • the gate of the transistor M20 is connected to the pull-up control node H, and the first pole of the transistor M20 and the seventh voltage terminal VB are connected to receive a seventh voltage of a high level.
  • the transistor M20 When the pull-up control node H is at a high level, the transistor M20 is turned on under the control of the level of the pull-up control node H, so that the seventh high-level voltage input from the seventh voltage terminal VB can be input to the transistor M1_b
  • the first pole of the transistor M1_b causes the first and second poles of the transistor M1_b to be at a high level, thereby preventing the pull-up control node H from leaking electricity through the transistor M1_b.
  • the gate of the transistor M1_b since the gate of the transistor M1_b is connected to the gate of the first transistor M1, the combination of the first transistor M1 and the transistor M1_b can achieve the same effect as the aforementioned first transistor M1, and also has the effect of preventing leakage.
  • a transistor MT1_b and a transistor MT2_b may be respectively provided to implement a leakage prevention structure.
  • the gates of the transistors MT1_b and MT2_b are connected to the first clock signal terminal CLKA to receive the first clock signal.
  • the second pole of the first transmission transistor MT1 and the first pole of the transistor MT1_b are connected to the first leakage prevention node OF1. As shown in FIG. 7, corresponding to the first transfer transistor MT1 and the second transfer transistor MT2, a transistor MT1_b and a transistor MT2_b may be respectively provided to implement a leakage prevention structure.
  • the gates of the transistors MT1_b and MT2_b are connected to the first clock signal terminal CLKA to receive the first clock signal.
  • the second pole of the first transmission transistor MT1 and the first pole of the transistor MT1_b are connected to the first leakage prevention node OF1. As shown in FIG.
  • the first leakage prevention node OF1 is electrically connected to the transistor M21 in the first input-output unit 310; the second pole of the second transmission transistor MT2 and the first pole of the transistor MT2_b are connected to the second leakage prevention node OF2.
  • the second leakage prevention node OF2 may be electrically connected to a transistor in the second input-output unit 320 to implement a leakage prevention function, for example. Setting the transistor MT1_b can prevent leakage of the first pull-up node Q1, and setting the transistor MT2_b can prevent leakage of the second pull-up node Q2.
  • the transistors M10_b, M15_b, and M16_b can be respectively combined with the transistor M21 to implement a leakage prevention structure, thereby preventing leakage of the first pull-up node Q1.
  • the first pole of the transistor M21 and the eighth voltage terminal VC are connected to receive a high-level eighth voltage.
  • the working principle of preventing the leakage of the first pull-up node Q1 is the same as the above-mentioned working principle of preventing the leakage of the pull-up control node H, which is not repeated here.
  • FIG. 11 other embodiments of the present disclosure further provide a first input-output unit 310.
  • the second pull-down node QB2 is added; in order to work with the second pull-down node QB2, the transistors M22, M22_b, M9_b, M13_b, M17_b, M14_b, M11_b, M12_b, and M19_b are added accordingly.
  • the second pole of the eighth transistor M8 is no longer connected to the pull-down node QB, but is connected to the second pull-down node QB2; the transistor M22_b is an anti-leakage transistor provided to prevent leakage of the first pull-up node Q1 .
  • the working principles of the transistors M22, M22_b, and M9_b are similar to those of the transistors M10, M10_b, and M9; the working principles of the transistors M13_b, M17_b, and M14_b are respectively the same as those of the transistors M13, M17, and M14 Similar; the transistors M11_b, M12_b, and M19_b work similarly to the transistors M11, M12, and M19, respectively, and are not repeated here.
  • the performance of the shift register unit 10 can be further improved.
  • the level of the pull-down node QB and the level of the second pull-down node QB2 can be better at a low level, thereby not affecting the power of the first pull-up node Q1.
  • the noise of the first pull-up node Q1 and the output terminals (CR, OUT, OUT2) can be further reduced to avoid output abnormality.
  • FIG. 12 shows a shift register unit 10 according to an embodiment of the present disclosure.
  • the first transfer transistor MT1 is connected to the first input-output unit 310 through a first pull-up node Q1, and the second transfer transistor MT2 is connected through a second The pull node Q2 is connected to the second input-output unit 320.
  • the first input-output unit 310 in FIG. 12 may use any one of the first input-output units provided by the embodiments of the present disclosure.
  • the first input-output unit 310 may use FIG. 8, FIG. 9, FIG. 10, and FIG. 11. Any circuit structure shown in.
  • circuit structure of the first input / output unit 310 is described in the embodiment of the present disclosure, and the circuit structure of the second input / output unit 320 may be the same as the circuit structure of the first input / output unit 310.
  • the embodiments of the present disclosure include but are not limited to this.
  • the circuit structure of the second input / output unit 320 may be different from the circuit structure of the first input / output unit 310 as long as corresponding functions can be implemented.
  • the transistors used in the embodiments of the present disclosure may all be thin film transistors or field effect transistors or other switching devices with the same characteristics.
  • the thin film transistors are used as an example for description.
  • the source and drain of the transistor used here can be symmetrical in structure, so there can be no difference in structure of the source and drain of the transistor.
  • one pole is directly described as the first pole and the other pole is the second pole.
  • transistors can be classified into N-type and P-type transistors according to the characteristics of the transistors.
  • the turn-on voltage is a low-level voltage (for example, 0V, -5V, -10V, or other suitable voltage), and the turn-off voltage is a high-level voltage (for example, 5V, 10V, or other suitable voltage) );
  • the turn-on voltage is a high-level voltage (for example, 5V, 10V, or other suitable voltage)
  • the turn-off voltage is a low-level voltage (for example, 0V, -5V, -10V, or other suitable voltage) Voltage).
  • the transistors used in the shift register unit 10 provided in the embodiments of the present disclosure are all described by taking N-type transistors as examples.
  • the embodiments of the present disclosure include, but are not limited to, for example, shifting. At least a part of the transistors in the register unit 10 may also be a P-type transistor.
  • At least one embodiment of the present disclosure further provides a gate driving circuit 20, as shown in FIG. 13, the gate driving circuit 20 includes a plurality of cascaded shift register units 10, wherein any one or more shift registers
  • the unit 10 may adopt the structure of the shift register unit 10 provided by the embodiment of the present disclosure or a modification thereof.
  • A1, A2, A3, and A4 in FIG. 13 represent input / output units.
  • the four input / output units can all adopt the circuit structure in FIG. 9.
  • the cascade of the shift register unit 10 means that the input and output units in the shift register unit 10 are cascaded, and the cancellation in different shift register units 10 Hidden units are not cascaded.
  • each shift register unit 10 includes two input-output units.
  • the gate driving circuit 20 When the gate driving circuit 20 is used to drive a display panel, the output terminal of each input-output unit may be separately connected to the display panel.
  • One row of the sub-pixel units is electrically connected.
  • the input-output units A1, A2, A3, and A4 may be electrically connected to the first, second, third, and fourth sub-pixel units, respectively.
  • the two input-output units in the shift register unit 10 are adjacent, that is, the sub-pixel units for driving adjacent rows in the display panel.
  • Embodiments of the present disclosure include, but are not limited to, for example, one of the shift register units 10 may include an input-output unit A1 and an input-output unit A3, and the other shift register unit 10 includes an input-output unit A2 and an input-output unit A4. That is, the two input-output units included in the shift register unit 10 may be non-adjacent.
  • the shift register unit 10 may further include four input-output units (A1, A2, A3, and A4), and the four input-output units pass through the first transmission circuit, respectively.
  • the second transmission circuit 220, the third transmission circuit 230, and the fourth transmission circuit 240 are electrically connected to the blanking unit 100.
  • the gate driving circuit provided by the embodiment of the present disclosure can share the blanking unit, so that the display device using the gate driving circuit can reduce the frame size and reduce the cost.
  • the following uses the gate driving circuit 20 shown in FIG. 14 as an example to describe the signal lines in the gate driving circuit 20.
  • the gate driving circuit 20 further includes a first sub-clock signal line CLK_1, a second sub-clock signal line CLK_2, a third sub-clock signal line CLK_3, and a fourth sub-clock signal line CLK_4.
  • the 4n-3th-level input / output unit is connected to the first sub-clock signal line CLK_1 to receive the second clock signal.
  • the 4n-3th-level input-output unit is connected to the first sub-clock signal line CLK_1 through the second clock signal terminal CLKB.
  • the 4n-2 stage input / output unit is connected to the second sub-clock signal line CLK_2 to receive the second clock signal, for example, the 4n-2 stage input / output unit is connected to the second sub-clock signal line CLK_2 through the second clock signal terminal CLKB Connection; the 4n-1 level input / output unit and the third sub clock signal line CLK_3 are connected to receive the second clock signal, for example, the 4n-1 level input / output unit passes the second clock signal terminal CLKB and the third sub clock signal line CLK_3 connection; the 4n-level input and output unit is connected to the fourth sub-clock signal line CLK_4 to receive the second clock signal, for example, the 4n-level input and output unit is connected to the fourth sub-clock signal line CLK_4 through the second clock signal terminal CLKB; n is an integer greater than zero.
  • the gate driving circuit provided by the embodiment of the present disclosure may use a 4 CLK clock signal, so that the signal waveforms output by adjacent input / output units in the gate driving circuit may overlap, thereby, for example, increasing Pre-charge time.
  • the embodiment of the present disclosure does not limit the type of the clock signal used. For example, clock signals such as 6CLK, 8CLK, etc. may also be used.
  • the gate driving circuit 20 may further include an eighth sub clock signal line CLK_8, a ninth sub clock signal line CLK_9, a tenth sub clock signal line CLK_10, and an eleventh sub clock signal line CLK_11.
  • the 4n-3 stage input-output unit is connected to the eighth sub-clock signal line CLK_8 to receive the third clock signal, for example, the 4n-3 stage input-output unit
  • the third clock signal terminal CLKC is connected to the eighth sub-clock signal line CLK_8;
  • the 4n-2 stage input and output unit is connected to the ninth sub-clock signal line CLK_9 to receive the third clock signal, for example, the 4n-2 stage input and output
  • the unit is connected through the third clock signal terminal CLKC and the ninth sub-clock signal line CLK_9;
  • the 4n-1 stage input / output unit is connected with the tenth sub-clock signal line CLK_10 to receive the third clock signal, for example, the 4n-1
  • the gate driving circuit 20 may further include a fifth sub-clock signal line CLK_5, a sixth sub-clock signal line CLK_6, and a seventh sub-clock signal line CLK_7.
  • Each of the blanking units 100 in the gate driving circuit 20 is connected to the fifth sub-clock signal line CLK_5 to receive the compensation selection control signal.
  • each of the blanking units 100 in the gate driving circuit 20 uses the compensation selection control terminal OE.
  • each stage input and output unit is connected to the sixth sub-clock signal line CLK_6 to receive the global reset signal, for example, each stage input-output unit passes the global reset signal terminal TRST and the sixth sub-clock
  • the signal line CLK_6 is connected; each stage of the input / output unit is connected to the seventh sub-clock signal line CLK_7 to receive the first clock signal. connection.
  • the display input signal terminal STU2 of the input and output units at each level is connected to the shift signal output terminal CR of the first two input and output units, and the display reset signal terminal STD of the input and output units at each level and the last three input and output The shift signal output terminal CR of the unit is connected.
  • cascading relationship shown in FIG. 14 is only an example. According to the description of the present disclosure, other cascading methods may also be adopted according to the actual situation.
  • the input / output unit in the gate driving circuit 20 shown in FIG. 14 adopts the circuit structure shown in FIG. 9, and the blanking unit 100 in the gate driving circuit 20 adopts shown in FIG. 6.
  • FIG. 15 shows a timing diagram of signals when the gate driving circuit 20 shown in FIG. 14 operates.
  • H ⁇ 5> represents the pull-up control nodes H, Q ⁇ 1>, Q ⁇ 5>, and Q ⁇ in the blanking unit 100 that are electrically connected to the fifth-stage input-output unit in the gate driving circuit 20.
  • 6>, Q ⁇ 7>, and Q ⁇ 8> represent the pull-up nodes Q (i.e., the first, fifth, sixth, seventh, and eighth input / output units in the gate drive circuit 20)
  • OUT ⁇ 1> (CR ⁇ 1>), OUT ⁇ 7> (CR ⁇ 7>), and OUT ⁇ 8> (CR ⁇ 8>) represent the first, seventh, and third stages in the gate drive circuit 20, respectively.
  • the pixel scanning signal output terminal OUT (shift signal output terminal CR) in the eight-stage input-output unit, OUT2 ⁇ 7> and OUT2 ⁇ 8> represent the seventh-stage and eighth-stage input-output units in the gate driving circuit 20, respectively.
  • the pixel scan signal output terminal OUT2 in. 1F represents the first frame
  • DS represents the display period in the first frame
  • BL represents the blanking period in the first frame.
  • STU2 in FIG. 15 represents a display input signal terminal in the first-stage input-output unit.
  • the third voltage terminal VDD_A is input to a low level and the fourth voltage terminal VDD_B is input to a high level as an example, but the embodiment of the present disclosure is not limited thereto.
  • the signal levels in the signal timing diagram shown in Figure 15 are only schematic and do not represent true level values.
  • the fifth sub-clock signal line CLK_5 and the sixth sub-clock signal line CLK_6 provide a high level, because the compensation selection control terminal OE of each blanking unit 100 and the fifth sub-clock signal line CLK_5 Connected, so that the first transistor M1 in each blanking unit 100 is turned on, because the blanking input signal terminal STU1 is connected to a low level at this time, the pull-up in each blanking unit 100 can be pulled up
  • the control node H is reset; since the global reset signal terminal TRST of each stage input and output unit is connected to the sixth sub-clock signal line CLK_6, the sixteenth transistor M16 in the stage input and output unit is turned on, so that The pull-up node Q in each stage of the input-output unit is reset.
  • the eighth transistor M8 is turned on, so that the level of the pull-down node QB is charged to a high level.
  • the high level of the pull-down node QB causes the tenth transistor M10 to be turned on, so that the level of the pull-up node Q can be further pulled down to a low level.
  • the display input signal terminal STU2 of the first-stage input-output unit inputs a high level, and the fourth transistor M4 is turned on. Therefore, the high level input from the second voltage terminal VDD can be matched by the fourth transistor M4.
  • the pull-up node Q ⁇ 1> is charged, so that the level of the pull-up node Q ⁇ 1> is pulled up to a high level, and the high-level of the pull-up node Q ⁇ 1> can be held by the second capacitor C2.
  • the fifth transistor M5 and the sixth transistor M6 are turned on under the control of the level of the pull-up node Q ⁇ 1>, but since the second clock signal terminal CLKB (connected to the first sub-clock signal line CLK1) is in the first stage P1 inputs a low-level signal, so both the shift signal output terminal CR ⁇ 1> and the pixel scanning signal output terminal OUT ⁇ 1> output the low-level signal. In the first stage P1, pre-charging of the pull-up node Q ⁇ 1> is completed.
  • the second clock signal terminal CLKB inputs a high-level signal, and the level of the pull-up node Q ⁇ 1> is further pulled up due to the bootstrap effect, so the fifth transistor M5 and the sixth transistor M6 are held The conducting state, so that both the shift signal output terminal CR ⁇ 1> and the pixel scanning signal output terminal OUT ⁇ 1> output the high-level signal.
  • the high-level signal output from the shift signal output terminal CR ⁇ 1> can be used for the scan shift of the upper and lower shift register units (input and output units), while the output from the pixel scan signal output terminal OUT ⁇ 1>
  • the high-level signal can be used to drive a sub-pixel unit in a display panel for display.
  • the second clock signal terminal CLKB inputs a low-level signal. Since the pull-up node Q ⁇ 1> is maintained at a high level at this time, the fifth transistor M5 and the sixth transistor M6 continue to be turned on. As a result, both the shift signal output terminal CR ⁇ 1> and the pixel scanning signal output terminal OUT ⁇ 1> output the low-level signal. Due to the bootstrapping effect of the second capacitor C2, the level of the pull-up node Q ⁇ 1> will also drop.
  • the shift-signal output terminal of the fourth-stage input-output unit outputs High level, so the display reset signal terminal STD of the first input / output unit inputs high level, the fifteenth transistor M15 is turned on, and the level of the pull-up node Q ⁇ 1> is pulled down to a low level, thereby completing Reset of pull-up node Q ⁇ 1>.
  • the ninth transistor M9 is turned off, and the high level input from the fourth voltage terminal VDD_B can charge the pull-down node QB, and the pull-down node QB is charged to a high level , So that the tenth transistor M10 is turned on, so that the level of the pull-up node Q ⁇ 1> can be further reset.
  • the eleventh transistor M11 and the twelfth transistor M12 are also turned on, so that the level of the shift signal output terminal CR ⁇ 1> and the pixel scan signal output terminal OUT ⁇ 1> can be further pulled down and reset.
  • the analogy is repeated, and the second-level and third-level input-output units drive the sub-pixel units in the display panel line by line to complete the display drive of one frame. . So far, the display period DS of the first frame 1F ends.
  • the pull-up control node H is also charged in the display period DS of the first frame 1F.
  • the display period of the first frame 1F DS also performs the following operations.
  • the fifth sub-clock signal line CLK_5 is provided with the same signal as the shift signal output terminal of the fifth-stage input-output unit.
  • the shift signal output terminal of the fifth-stage input-output unit outputs high voltage
  • the compensation selection control terminal OE of the blanking unit 100 is input to a high level, and the first transistor M1 is turned on (as shown in FIG. 6).
  • the blanking input signal terminal STU1 and the shift of the fifth-stage input and output unit can be shifted.
  • the bit signal output terminal is connected, so that the high level input from the blanking input signal terminal STU1 charges the pull-up control node H ⁇ 5>, thereby pulling the level of the pull-up control node H ⁇ 5> to a high level.
  • the above-mentioned charging process for the pull-up control node H ⁇ 5> is only an example, and the embodiments of the present disclosure include but are not limited thereto.
  • the blanking input signal terminal STU1 of the blanking unit 100 may also be connected to the shift signal output terminal of the third or fourth stage input and output unit, and at the same time, the signal provided to the fifth sub-clock signal line CLK_5 and to The signal timing of the blanking input signal terminal STU1 may be the same.
  • the high level of the pull-up control node H ⁇ 5> can be maintained until the blanking period BL of the first frame 1F.
  • the seventh row of sub-pixel units needs to be compensated in the first frame 1F, the following operations are performed in the blanking period BL of the first frame 1F.
  • the seventh sub-clock signal line CLK_7 provides a high level. Since the first clock signal terminal CLKA is connected to the seventh sub-clock signal line CLK_7, the first clock signal is high at this stage, so The four transmission circuits in FIG. 14 are all turned on, so that the high-level second voltage can charge the pull-up nodes Q ⁇ 5>, Q ⁇ 6>, Q ⁇ 7>, and Q ⁇ 8> at the same time, so that The pull-up nodes Q ⁇ 5>, Q ⁇ 6>, Q ⁇ 7>, and Q ⁇ 8> are pulled up to a high level.
  • only the transmission circuit with the seventh-stage input-output unit may be turned on, so that only the level of the pull-up node Q ⁇ 7> is pulled up to a high level.
  • the second clock signal terminal CLKB (connected to the third sub-clock signal line CLK_3) in the seventh-stage input-output unit inputs a high-level signal.
  • the level of the pull-up node Q ⁇ 7> is This function is further pulled up.
  • the fifth transistor M5 and the sixth transistor M6 in the seventh-stage input-output unit are turned on.
  • the high-level signal input from the second clock signal terminal CLKB in the seventh-stage input-output unit can be turned on. Output to the shift signal output terminal CR ⁇ 7> and the pixel scan signal output terminal OUT ⁇ 7>.
  • the signal output from the pixel scanning signal output terminal OUT ⁇ 7> can be used to drive a sensing transistor in a sub-pixel unit in a display panel to achieve external compensation.
  • the signal input from the third clock signal terminal CLKC can be output to the pixel scanning signal output terminal OUT2 ⁇ 7>.
  • the signal of OUT2 ⁇ 7> can be different from OUT ⁇ 7>, thereby improving the gate driving circuit. Drive capabilities to meet diverse needs.
  • the level of the signal input from the second clock signal terminal CLKB (connected to the third sub-clock signal line CLK_3) in the seventh-stage input-output unit changes from a high level to a low level, and is pulled up
  • the level of node Q ⁇ 7> is pulled down due to the bootstrap effect.
  • the fifth sub-clock signal line CLK_5 and the sixth sub-clock signal line CLK_6 provide a high level. Since the compensation selection control terminal OE of each blanking unit 100 is connected to the fifth sub-clock signal line CLK_5
  • the global reset signal terminal TRST of each stage input and output unit is connected to the sixth sub clock signal line CLK_6, so the level of the pull-up control node H in each blanking unit 100 and the input and output unit of each stage can be controlled.
  • the level of the pull-up node Q is reset.
  • the driving signal corresponding to the seventh row of sub-pixel units of the display panel is output as an example during the blanking period of the first frame.
  • the n-th input and output units in the output unit need to be input during the blanking period of the frame. Pull the level of the node Q to a high level, and during the blanking period of the frame, input a high-level signal through the second clock signal terminal CLKB or the third clock signal terminal CLKC in the n-th input and output unit.
  • n is an integer greater than zero.
  • the same timing of two signals refers to time synchronization at a high level, and it is not required that the amplitudes of the two signals are the same.
  • the display device 1 includes a gate driving circuit 20 and a plurality of sub-pixel units 410 arranged in an array.
  • the display device 1 further includes a display panel 40, and a pixel array composed of a plurality of sub-pixel units 410 is disposed in the display panel 40.
  • the first output terminal OP1 and the second output terminal OP2 in each of the shift register units 10 in the gate driving circuit 20 are respectively electrically connected to the sub-pixel units 410 in different rows.
  • the gate driving circuit 20 passes through the gate line GL It is electrically connected to the sub-pixel unit 410.
  • the gate driving circuit 20 is used to provide a driving signal to the pixel array.
  • the driving signal can drive the scanning transistor and the sensing transistor in the sub-pixel unit 410.
  • the display device 1 may further include a data driving circuit 30 for providing a data signal to the pixel array.
  • the data driving circuit 30 is electrically connected to the sub-pixel unit 410 through a data line DL.
  • the display device 1 in this embodiment may be any of: a liquid crystal panel, a liquid crystal television, a display, an OLED panel, an OLED television, an electronic paper display device, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigator, etc. Products or parts with display capabilities.
  • At least one embodiment of the present disclosure also provides a driving method that can be used to drive the shift register unit 10 provided by the embodiment of the present disclosure.
  • a plurality of the shift register units 10 can be cascaded to construct a gate of an embodiment of the present disclosure.
  • the driving method includes a display period and a blanking period for one frame. As shown in FIG. 17, the driving method includes the following operation steps.
  • Step S100 During the display period, make the blanking unit charge the pull-up control node in response to the compensation selection control signal;
  • Step S200 During the blanking period, make the first transmission circuit use the blanking pull-up signal to charge the first pull-up node in response to the first transmission signal, and make the second transmission circuit use the blanking The pull signal charges the second pull-up node.
  • the timings of the first transmission signal and the second transmission signal are the same.

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Abstract

一种移位寄存器单元（10）、栅极驱动电路（20）、显示装置（1）及驱动方法。移位寄存器单元（10）包括消隐单元（100）、第一传输电路（210）、第二传输电路（220）、第一输入输出单元（310）和第二输入输出单元（320）。消隐单元（100）被配置为响应于补偿选择控制信号对上拉控制节点（H）进行充电并将消隐上拉信号输入到消隐上拉节点（N）；第一传输电路（210）和消隐上拉节点（N）以及第一上拉节点（Q1）电连接，且被配置为响应于第一传输信号利用消隐上拉信号对第一上拉节点（Q1）进行充电。移位寄存器单元（10）可以共用消隐单元（100），从而使得采用该移位寄存器单元（10）的显示装置（1）可以减小边框尺寸。

Description

移位寄存器单元、栅极驱动电路、显示装置及驱动方法
本申请要求于2018年7月18日递交的中国专利申请第201810792891.7号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种移位寄存器单元、栅极驱动电路、显示装置及驱动方法。
背景技术
在显示领域特别是OLED(Organic Light-Emitting Diode，有机发光二极管)显示面板中，栅极驱动电路目前一般集成在GATE IC中。IC设计中芯片的面积是影响芯片成本的主要因素，如何有效地降低芯片面积是技术开发人员需要着重考虑的。
发明内容
本公开至少一实施例提供一种移位寄存器单元，包括消隐单元、第一传输电路、第二传输电路、第一输入输出单元和第二输入输出单元。所述消隐单元被配置为响应于补偿选择控制信号对上拉控制节点进行充电并将消隐上拉信号输入到消隐上拉节点；所述第一输入输出单元包括第一上拉节点和第一输出端，所述第二输入输出单元包括第二上拉节点和第二输出端；所述第一传输电路和所述消隐上拉节点以及所述第一上拉节点电连接，且被配置为响应于第一传输信号利用所述消隐上拉信号对所述第一上拉节点进行充电；所述第二传输电路和所述消隐上拉节点以及所述第二上拉节点电连接，且被配置为响应于第二传输信号利用所述消隐上拉信号对所述第二上拉节点进行充电；所述第一输入输出单元被配置为响应于第一显示输入信号对所述第一上拉节点进行充电，并且被配置为在所述第一上拉节点的电平的控制下将复合输出信号输出至第一输出端；所述第二输入输出单元被配置为响应于第二显示输入信号对所述第二上拉节点进行充电，并 且被配置为在所述第二上拉节点的电平的控制下将复合输出信号输出至第二输出端。
例如，在本公开一实施例提供的移位寄存器单元中，所述消隐单元包括消隐输入电路和消隐上拉电路。所述消隐输入电路被配置为响应于所述补偿选择控制信号对所述上拉控制节点进行充电并保持所述上拉控制节点的电平；所述消隐上拉电路被配置为在所述上拉控制节点的电平的控制下将所述消隐上拉信号输入到所述消隐上拉节点。
例如，在本公开一实施例提供的移位寄存器单元中，所述消隐单元还包括消隐耦合电路。所述消隐耦合电路与所述上拉控制节点电连接，且被配置为对所述上拉控制节点的电平进行耦合上拉。
例如，在本公开一实施例提供的移位寄存器单元中，所述消隐输入电路包括第一晶体管和第一电容。所述第一晶体管的栅极和补偿选择控制端连接以接收所述补偿选择控制信号，所述第一晶体管的第一极和消隐输入信号端连接，所述第一晶体管的第二极和所述上拉控制节点连接；以及所述第一电容的第一极和所述上拉控制节点连接，所述第一电容的第二极和第一电压端连接。
例如，在本公开一实施例提供的移位寄存器单元中，所述消隐上拉电路包括第二晶体管。所述第二晶体管的栅极和所述上拉控制节点连接，所述第二晶体管的第一极和第二电压端连接以接收第二电压，所述第二晶体管的第二极和所述消隐上拉节点连接。
例如，在本公开一实施例提供的移位寄存器单元中，消隐耦合电路包括耦合电容和第三晶体管。所述第三晶体管的栅极和所述上拉控制节点连接，所述第三晶体管的第一极和第二电压端连接以接收第二电压，所述第三晶体管的第二极和所述耦合电容的第一极连接，所述耦合电容的第二极和所述上拉控制节点连接。
例如，在本公开一实施例提供的移位寄存器单元中，所述第一传输电路包括第一传输晶体管。所述第一传输晶体管的栅极和第一传输信号端连接以接收所述第一传输信号，所述第一传输晶体管的第一极和所述消隐上拉节点连接以接收所述消隐上拉信号，所述第一传输晶体管的第二极和所述第一上拉节点连接。
例如，在本公开一实施例提供的移位寄存器单元中，所述第一传输信 号端包括第一时钟信号端，所述第一传输信号包括通过所述第一时钟信号端接收的第一时钟信号。
例如，在本公开一实施例提供的移位寄存器单元中，所述第二传输电路包括第二传输晶体管。所述第二传输晶体管的栅极和第二传输信号端连接以接收所述第二传输信号，所述第二传输晶体管的第一极和所述消隐上拉节点连接以接收所述消隐上拉信号，所述第二传输晶体管的第二极和所述第二上拉节点连接。
例如，在本公开一实施例提供的移位寄存器单元中，所述第二传输信号端包括第一时钟信号端，所述第二传输信号包括通过所述第一时钟信号端接收的第一时钟信号。
例如，在本公开一实施例提供的移位寄存器单元中，所述第一输入输出单元包括显示输入电路、输出电路、第一下拉控制电路和下拉电路。所述第一输出端包括移位信号输出端和像素扫描信号输出端，所述移位信号输出端和所述像素扫描信号输出端输出所述复合输出信号；所述显示输入电路被配置为响应于所述第一显示输入信号对所述第一上拉节点进行充电；所述输出电路被配置为在所述第一上拉节点的电平的控制下，将所述复合输出信号输出至所述第一输出端；所述第一下拉控制电路被配置为在所述第一上拉节点的电平的控制下，对下拉节点的电平进行控制；所述下拉电路被配置为在所述下拉节点的电平的控制下，对所述第一上拉节点、所述移位信号输出端和所述像素扫描信号输出端进行下拉复位。
例如，在本公开一实施例提供的移位寄存器单元中，所述显示输入电路包括第四晶体管；所述第四晶体管的栅极和显示输入信号端连接以接收所述第一显示输入信号，所述第四晶体管的第一极和第二电压端连接以接收第二电压，所述第四晶体管的第二极和所述第一上拉节点连接；
所述输出电路包括第五晶体管和第六晶体管；所述第五晶体管的栅极和所述第一上拉节点连接，所述第五晶体管的第一极和第二时钟信号端连接以接收第二时钟信号并将所述第二时钟信号作为所述复合输出信号，所述第五晶体管的第二极和所述移位信号输出端连接；所述第六晶体管的栅极和所述第一上拉节点连接，所述第六晶体管的第一极和所述第二时钟信号端连接以接收所述第二时钟信号并将所述第二时钟信号作为所述复合输出信号，所述第六晶体管的第二极和所述像素扫描信号输出端连接；
所述第一下拉控制电路包括第七晶体管和第九晶体管；所述第七晶体管的栅极和第一极连接且被配置为和第三电压端连接以接收第三电压，所述第七晶体管的第二极和所述下拉节点连接；所述第九晶体管的栅极和所述第一上拉节点连接，所述第九晶体管的第一极和所述下拉节点连接，所述第九晶体管的第二极和第五电压端连接以接收第五电压；
所述下拉电路包括第十晶体管、第十一晶体管和第十二晶体管；所述第十晶体管的栅极和所述下拉节点连接，所述第十晶体管的第一极和所述第一上拉节点连接，所述第十晶体管的第二极和所述第五电压端连接以接收所述第五电压；所述第十一晶体管的栅极和所述下拉节点连接，所述第十一晶体管的第一极和所述移位信号输出端连接，所述第十一晶体管的第二极和所述第五电压端连接以接收所述第五电压；所述第十二晶体管的栅极和所述下拉节点连接，所述第十二晶体管的第一极和所述像素扫描信号输出端连接，所述第十二晶体管的第二极和第六电压端连接以接收第六电压。
例如，在本公开一实施例提供的移位寄存器单元中，所述输出电路还包括第二电容，所述第二电容的第一极和所述第一上拉节点连接，所述第二电容的第二极和所述第五晶体管的第二极连接。
例如，在本公开一实施例提供的移位寄存器单元中，所述第一下拉控制电路还包括第八晶体管，所述第八晶体管的栅极和第一极连接且被配置为和第四电压端连接以接收第四电压，所述第八晶体管的第二极和不同于所述下拉节点的第二下拉节点连接。
例如，在本公开一实施例提供的移位寄存器单元中，所述第一输入输出单元还包括第二下拉控制电路和第三下拉控制电路。所述第二下拉控制电路被配置为响应于第一时钟信号对所述下拉节点的电平进行控制；所述第三下拉控制电路被配置为响应于所述第一显示输入信号对所述下拉节点的电平进行控制。
例如，在本公开一实施例提供的移位寄存器单元中，所述第二下拉控制电路包括第十三晶体管，所述第三下拉控制电路包括第十四晶体管。所述第十三晶体管的栅极和第一时钟信号端连接以接收所述第一时钟信号，所述第十三晶体管的第一极和所述下拉节点连接，所述第十三晶体管的第二极和第五电压端连接以接收第五电压；所述第十四晶体管的栅极和显示 输入信号端连接以接收所述第一显示输入信号，所述第十四晶体管的第一极和所述下拉节点连接，所述第十四晶体管的第二极和所述第五电压端连接以接收所述第五电压。
例如，在本公开一实施例提供的移位寄存器单元中，所述第二下拉控制电路包括第十三晶体管和第十七晶体管，所述第三下拉控制电路包括第十四晶体管。所述第十三晶体管的栅极和第一时钟信号端连接以接收所述第一时钟信号，所述第十三晶体管的第一极和所述下拉节点连接，所述第十三晶体管的第二极和所述第十七晶体管的第一极连接；所述第十七晶体管的栅极和所述上拉控制节点电连接，所述第十七晶体管的第二极和第五电压端连接以接收第五电压；所述第十四晶体管的栅极和显示输入信号端连接以接收所述第一显示输入信号，所述第十四晶体管的第一极和所述下拉节点连接，所述第十四晶体管的第二极和所述第五电压端连接以接收所述第五电压。
例如，在本公开一实施例提供的移位寄存器单元中，所述第一输入输出单元还包括显示复位电路和全局复位电路。所述显示复位电路被配置为响应于显示复位信号对所述第一上拉节点进行复位；所述全局复位信号被配置为响应于全局复位信号对所述第一上拉节点进行复位。
例如，在本公开一实施例提供的移位寄存器单元中，所述显示复位电路包括第十五晶体管，所述全局复位电路包括第十六晶体管。所述第十五晶体管的栅极和显示复位信号端连接以接收所述显示复位信号，所述第十五晶体管的第一极和所述第一上拉节点连接，所述第十五晶体管的第二极和第五电压端连接以接收第五电压；所述第十六晶体管的栅极和全局复位信号端连接以接收所述全局复位信号，所述第十六晶体管的第一极和所述第一上拉节点连接，所述第十六晶体管的第二极和所述第五电压端连接以接收所述第五电压。
例如，在本公开一实施例提供的移位寄存器单元中，所述第二输入输出单元的电路结构和所述第一输入输出单元的电路结构相同。
例如，本公开一实施例提供的移位寄存器单元还包括至少一个第三传输电路和与所述至少一个第三传输电路电连接的至少一个第三输入输出单元。
本公开至少一实施例还提供一种栅极驱动电路，包括多个级联的如本 公开的实施例提供的任一移位寄存器单元。
本公开至少一实施例还提供一种显示装置，包括如本公开的实施例提供的任一栅极驱动电路以及多个呈阵列排布的子像素单元，所述栅极驱动电路中的每一个移位寄存器单元中的所述第一输出端和所述第二输出端分别和不同行的子像素单元电连接。
本公开至少一实施例还提供一种移位寄存器单元的驱动方法，包括用于一帧的显示时段和消隐时段，在所述显示时段，使得所述消隐单元响应于所述补偿选择控制信号对所述上拉控制节点进行充电；在所述消隐时段，使得所述第一传输电路响应于所述第一传输信号利用所述消隐上拉信号对所述第一上拉节点进行充电，以及使得所述第二传输电路响应于所述第二传输信号利用所述消隐上拉信号对所述第二上拉节点进行充电。
例如，在本公开一实施例提供的驱动方法中，所述第一传输信号和所述第二传输信号的时序相同。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为本公开至少一实施例提供的一种移位寄存器单元的示意图；
图2为本公开至少一实施例提供的另一种移位寄存器单元的示意图；
图3为本公开至少一实施例提供的又一种移位寄存器单元的示意图；
图4为本公开至少一实施例提供的一种移位寄存器单元中的第一输入输出单元的示意图；
图5为本公开至少一实施例提供的一种包括消隐单元、第一传输电路和第二传输电路的电路图；
图6为本公开至少一实施例提供的另一种包括消隐单元、第一传输电路和第二传输电路的电路图；
图7为本公开至少一实施例提供的又一种包括消隐单元、第一传输电路和第二传输电路的电路图；
图8为本公开至少一实施例提供的一种第一输入输出单元的电路图；
图9为本公开至少一实施例提供的另一种第一输入输出单元的电路 图；
图10为本公开至少一实施例提供的又一种第一输入输出单元的电路图；
图11为本公开至少一实施例提供的再一种第一输入输出单元的电路图；
图12为本公开至少一实施例提供的一种移位寄存器单元的电路图；
图13为本公开至少一实施例提供的一种栅极驱动电路的示意图；
图14为本公开至少一实施例提供的另一种栅极驱动电路的示意图；
图15为本公开至少一实施例提供的一种对应于图14所示的栅极驱动电路工作时的信号时序图；
图16为本公开至少一实施例提供的一种显示装置的示意图；以及
图17为本公开至少一实施例提供的一种移位寄存器单元的驱动方法的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在本公开的实施例中，例如，当各个电路实现为N型晶体管时，术语“上 拉”表示对一个节点或一个晶体管的一个电极进行充电，以使得该节点或该电极的电平的绝对值升高，从而实现相应晶体管的操作(例如导通)；“下拉”表示对一个节点或一个晶体管的一个电极进行放电，以使得该节点或该电极的电平的绝对值降低，从而实现相应晶体管的操作(例如截止)。
又例如，当各个电路实现为P型晶体管时，术语“上拉”表示对一个节点或一个晶体管的一个电极进行放电，以使得该节点或该电极的电平的绝对值降低，从而实现相应晶体管的操作(例如导通)；“下拉”表示对一个节点或一个晶体管的一个电极进行充电，以使得该节点或该电极的电平的绝对值升高，从而实现相应晶体管的操作(例如截止)。
并且，术语“上拉”、“下拉”的具体含义也将根据所采用的晶体管的具体类型而相应调整，只要能实现对于晶体管的控制以实现相应的开关功能。
目前用于OLED的栅极驱动电路通常要用三个子电路组合而成，即检测电路、显示电路和输出两者复合脉冲的连接电路(或门电路)，这样的电路结构非常复杂，无法满足高分辨率窄边框的要求。
在对OLED显示面板中的子像素单元进行补偿时，除了在子像素单元中设置像素补偿电路进行内部补偿外，还可以通过设置感测晶体管进行外部补偿。在进行外部补偿时，由移位寄存器单元构成的栅极驱动电路需要向显示面板中的子像素单元分别提供用于扫描晶体管和感测晶体管的驱动信号，例如，在一帧的显示时段提供用于扫描晶体管的扫描驱动信号，在一帧的消隐时段提供用于感测晶体管的感测驱动信号。
在一种外部补偿方法中，栅极驱动电路输出的感测驱动信号是逐行顺序扫描的，例如，在第一帧的消隐时段输出用于显示面板中第一行的子像素单元的感测驱动信号，在第二帧的消隐时段输出用于显示面板中第二行的子像素单元的感测驱动信号，依次类推，以每帧输出对应一行子像素单元的感测驱动信号的频率逐行顺序输出，即完成对显示面板的逐行顺序补偿。
但是，在采用上述逐行顺序补偿的方法时，可能会产生以下显示不良问题：一是在进行多帧图像的扫描显示过程中有一条逐行移动的扫描线；二是由于进行外部补偿的时间点存在差异，从而可能会造成显示面板不同区域的亮度差异比较大，例如，在对显示面板的第100行的子像素单元进行外部补偿时，显示面板的第10行的子像素单元虽然已经进行过外部补偿了，但此时第10行的子像素单元的发光亮度可能已经发生变化，例如发光亮度降低， 从而会造成显示面板不同区域的亮度不均匀，在大尺寸的显示面板中这种问题会更加明显。
如上所述，在栅极驱动电路驱动一个显示面板时，如果要实现外部补偿，则需要该栅极驱动电路不仅可以输出用于显示时段的扫描驱动信号，同时还需要输出用于消隐时段的感测驱动信号，即需要专门用于消隐时段的消隐单元。在这种情形下，栅极驱动电路所占用的面积可能会比较大，从而使得采用该栅极驱动电路的显示装置的边框的尺寸较大。
针对上述问题，本公开的至少一实施例提供一种移位寄存器单元，该移位寄存器单元包括消隐单元、第一传输电路、第二传输电路、第一输入输出单元和第二输入输出单元。消隐单元被配置为响应于补偿选择控制信号对上拉控制节点进行充电并将消隐上拉信号输入到消隐上拉节点；第一输入输出单元包括第一上拉节点和第一输出端，第二输入输出单元包括第二上拉节点和第二输出端；第一传输电路和消隐上拉节点以及第一上拉节点电连接，且被配置为响应于第一传输信号利用消隐上拉信号对第一上拉节点进行充电；第二传输电路和消隐上拉节点以及第二上拉节点电连接，且被配置为响应于第二传输信号利用消隐上拉信号对第二上拉节点进行充电；第一输入输出单元被配置为响应于第一显示输入信号对第一上拉节点进行充电，并且被配置为在第一上拉节点的电平的控制下将复合输出信号输出至第一输出端；第二输入输出单元被配置为响应于第二显示输入信号对第二上拉节点进行充电，并且被配置为在第二上拉节点的电平的控制下将复合输出信号输出至第二输出端。
本公开的实施例还提供对应于上述移位寄存器单元的栅极驱动电路、显示装置及驱动方法。
本公开的实施例提供的移位寄存器单元、栅极驱动电路、显示装置及驱动方法，可以共用消隐单元，从而使得采用该移位寄存器单元的显示装置可以减小边框尺寸，降低成本；同时，在兼顾逐行顺序补偿(例如在关机检测中需要进行逐行顺序补偿)的前提下，还可以实现随机补偿，从而可以避免由于逐行顺序补偿造成的扫描线以及显示亮度不均匀等显示不良问题。
需要说明的是，在本公开的实施例中，随机补偿指的是区别于逐行顺序补偿的一种外部补偿方法，采用随机补偿可以在某一帧的消隐时段随机输出对应于显示面板中任意一行的子像素单元的感测驱动信号，以下各实施例与 此相同，不再赘述。
另外，在本公开的实施例中，为了说明的目的，定义“一帧”、“每帧”或“某一帧”包括依次进行的显示时段和消隐时段，例如在显示时段中栅极驱动电路输出显示输出信号，该显示输出信号可以驱动显示面板从第一行到最后一行完成完整的一幅图像的扫描显示(即一帧图像的扫描显示)，在消隐时段中栅极驱动电路输出消隐输出信号，该消隐输出信号可以用于驱动显示面板中的某一行子像素单元中的感测晶体管，以完成该行子像素单元的外部补偿。
下面结合附图对本公开的实施例及其示例进行详细说明。
本公开的至少一个实施例提供一种移位寄存器单元10，如图1所示，该移位寄存器单元10包括消隐单元100、第一传输电路210、第二传输电路220、第一输入输出单元310和第二输入输出单元320。第一输入输出单元310包括第一上拉节点Q1和第一输出端OP1，第二输入输出单元Q2包括第二上拉节点Q2和第二输出端OP2。多个该移位寄存器单元10可以级联构建本公开一实施例提供的栅极驱动电路。
消隐单元100被配置为响应于补偿选择控制信号对上拉控制节点H进行充电并将消隐上拉信号输入到消隐上拉节点N。例如，在一帧的显示时段，该消隐单元100可以响应于补偿选择控制信号对上拉控制节点H进行充电；例如，在一帧的显示时段或消隐时段，该消隐单元100将消隐上拉信号输入到消隐上拉节点N。
第一传输电路210和消隐上拉节点N以及第一上拉节点Q1电连接，且被配置为响应于第一传输信号利用消隐上拉信号对第一上拉节点Q1进行充电。例如，第一传输电路210可以和第一传输信号端TS1连接以接收第一传输信号，第一传输电路210在第一传输信号的控制下而导通，从而可以利用消隐上拉节点N获得的消隐上拉信号对第一上拉节点Q1进行充电。例如，在一些实施例中，第一传输信号端TS1可以为第一时钟信号端CLKA，即第一传输信号为第一时钟信号端CLKA接收的第一时钟信号。
第二传输电路220和消隐上拉节点N以及第二上拉节点Q2电连接，且被配置为响应于第二传输信号利用消隐上拉信号对第二上拉节点Q2进行充电。例如，第二传输电路220可以和第二传输信号端TS2连接以接收第二传输信号，第二传输电路220在第二传输信号的控制下而导通，从而可以利用 消隐上拉节点N获得的消隐上拉信号对第二上拉节点Q2进行充电。例如，在一些实施例中，第二传输信号端TS2可以为第一时钟信号端CLKA，即第二传输信号为第一时钟信号端CLKA接收的第一时钟信号。
需要说明的是，在本公开的实施例中，对一个节点(例如上拉控制节点H、第一上拉节点Q1、第二上拉节点Q2等)进行充电表示例如将该节点与一个高电平的电压信号电连接，从而利用该高电平的电压信号以拉高该节点的电平；对一个节点进行放电(或复位)表示例如将该节点与一个低电平的电压信号电连接，从而利用该低电平的电压信号以拉低该节点的电平。例如，可以设置一个与该节点电连接的电容，对该节点进行充电或放电即表示对与该节点电连接的电容进行充电或放电。
第一输入输出单元310被配置为响应于第一显示输入信号对第一上拉节点Q1进行充电，并且被配置为在第一上拉节点Q1的电平的控制下将复合输出信号输出至第一输出端OP1。例如，在一帧的显示时段，第一输入输出单元310可以输出扫描驱动信号，该扫描驱动信号可以驱动显示面板中的某一行子像素单元进行扫描显示。又例如，在一帧的消隐时段，第一输入输出单元310可以输出感测驱动信号，该感测驱动信号可以用于驱动显示面板中的某一行子像素单元中的感测晶体管，以完成该行子像素单元的外部补偿。
第二输入输出单元320被配置为响应于第二显示输入信号对第二上拉节点Q2进行充电，并且被配置为在第二上拉节点Q2的电平的控制下将复合输出信号输出至第二输出端OP2。例如，在一帧的显示时段，第二输入输出单元320可以输出扫描驱动信号，该扫描驱动信号可以驱动显示面板中的某一行子像素单元进行扫描显示。又例如，在一帧的消隐时段，第二输入输出单元320可以输出感测驱动信号，该感测驱动信号可以用于驱动显示面板中的某一行子像素单元中的感测晶体管，以完成该行子像素单元的外部补偿。
例如，本公开的一些实施例还提供一种移位寄存器单元10，如图2所示，该移位寄存器单元10与图1中所示的移位寄存器单元10的区别在于还包括第三传输电路230以及与第三传输电路230电连接的第三输入输出单元330。
例如，第三传输电路230和消隐上拉节点N以及第三上拉节点Q3电连接，且被配置为响应于第三传输信号利用消隐上拉信号对第三上拉节点Q3进行充电。第三输入输出单元330被配置为响应于第三显示输入信号对第三上拉节点Q3进行充电，并且被配置为在第三上拉节点Q3的电平的控制下 将复合输出信号输出至第三输出端OP3。
本公开的一些实施例提供的移位寄存器单元10中的多个输入输出单元(第一输入输出单元310、第二输入输出单元320和第三输入输出单元330等)可以共用一个消隐单元100，从而可以简化电路结构，从而使得采用该移位寄存器单元10的显示装置可以减小边框尺寸，降低成本。
需要说明的是，图1和图2仅是本公开的两个示例，本公开的实施例提供的移位寄存器单元10还可以包括更多个传输电路以及输入输出单元，传输电路和输入输出单元的个数可以根据实际情况进行设置，本公开的实施例对此不作限定。
如图3所示，在本公开的一些实施例中，消隐单元100包括消隐输入电路110和消隐上拉电路120。
该消隐输入电路110被配置为响应于补偿选择控制信号对上拉控制节点H进行充电并保持上拉控制节点H的电平。例如，在一些实施例中，消隐输入电路110可以和消隐输入信号端STU1以及补偿选择控制端OE连接，从而可以在补偿选择控制端OE输入的补偿选择控制信号的控制下，利用消隐输入信号端STU1输入的消隐输入信号对上拉控制节点H进行充电，并保持上拉控制节点H的电平。例如，消隐输入电路110可以在一帧的显示时段对上拉控制节点H进行充电，从而将上拉控制节点H的电平上拉至高电平，并可以将上拉控制节点H的高电平保持至该帧的消隐时段。
该消隐上拉电路120被配置为在上拉控制节点H的电平的控制下将消隐上拉信号输入到消隐上拉节点N。例如，在一些实施例中，消隐上拉电路120可以和第二电压端VDD连接以接收第二电压，并将第二电压作为消隐上拉信号；又例如，消隐上拉电路120还可以和第一时钟信号端CLKA连接以接收第一时钟信号，并将第一时钟信号作为消隐上拉信号。例如，在上拉控制节点H为高电平时，消隐上拉电路120导通，从而可以将消隐上拉信号输入到消隐上拉节点N。
需要说明的是，在本公开的实施例中第二电压端VDD例如可以被配置为提供直流高电平信号，即第二电压为高电平，以下各实施例与此相同，不再赘述。
如图3所示，消隐单元100还可以包括消隐耦合电路130。该消隐耦合电路130与上拉控制节点H电连接，且被配置为对上拉控制节点H进行耦 合上拉。例如，在一些实施例中，消隐耦合电路130可以和第二电压端VDD连接以接收第二电压；又例如，消隐耦合电路130还可以和第一时钟信号端CLKA连接以接收第一时钟信号。例如，当上拉控制节点H为高电平时，该消隐耦合电路可以利用第二电压或第一时钟信号对上拉控制节点H耦合上拉，从而可以避免上拉控制节点H发生漏电。
需要说明的是，在本公开的实施例中，在移位寄存器单元中设置消隐单元(例如包括消隐输入电路、消隐上拉电路以及消隐耦合电路)是为了实现在一帧的消隐时段中可以输出消隐输出信号。消隐输入电路、消隐上拉电路以及消隐耦合电路中的“消隐”仅是表示这些电路和消隐时段有关，而并不限定这些电路仅工作在消隐时段中，以下各实施例与此相同，不再赘述。
如图5和图6所示，在一些实施例中，消隐输入电路110可以实现为包括第一晶体管M1和第一电容C1。第一晶体管M1的栅极和补偿选择控制端OE连接以接收补偿选择控制信号，第一晶体管M1的第一极和消隐输入信号端STU1连接以接收消隐输入信号，第一晶体管M1的第二极和上拉控制节点H连接。例如，当补偿选择控制信号为高电平的导通信号时，第一晶体管M1被导通，从而可以利用消隐输入信号对上拉控制节点H进行充电。
第一电容C1的第一极和上拉控制节点H连接，第一电容C1的第二极和第一电压端VGL1连接。通过设置第一电容C1可以保持上拉控制节点H的电平，例如，在一帧的显示时段中，消隐输入电路110将上拉控制节点H充电至高电平，第一电容C1可以将上拉控制节点H的高电平保持至该帧的消隐时段。需要说明的是，在本公开的实施例中，第一电容C1的第二极除了可以和第一电压端VGL1连接外，还可以与其他电压端连接，例如第一电容C1的第二极接地，本公开的实施例对此不作限定。
需要说明的是，在本公开的实施例中第一电压端VGL1例如可以被配置为提供直流低电平信号，即第一电压为低电平，以下各实施例与此相同，不再赘述。
如图5和图6所示，在一些实施例中，消隐上拉电路120可以实现为第二晶体管M2。第二晶体管M2的栅极和上拉控制节点H连接，第二晶体管M2的第一极和第二电压端VDD连接以接收第二电压并将第二电压作为消隐上拉信号，第二晶体管M2的第二极和消隐上拉节点N连接。
例如，当上拉控制节点H为高电平时，第二晶体管M2被导通，从而可 以将消隐上拉信号输入到消隐上拉节点N。例如，如图7所示，在其他一些实施例中，第二晶体管M2的第一极还可以和第一时钟信号端CLKA连接以接收第一时钟信号并将第一时钟信号作为消隐上拉信号。
如图5和图6所示，在一些实施例中，消隐耦合电路130可以实现为包括耦合电容CST和第三晶体管M3。第三晶体管M3的栅极和上拉控制节点H连接，第三晶体管M3的第一极和第二电压端VDD连接以接收第二电压，第三晶体管M3的第二极和耦合电容CST的第一极连接，耦合电容CST的第二极和上拉控制节点H连接。例如，当上拉控制节点H为高电平时，第三晶体管M3被导通，从而第二电压可以施加至耦合电容CST的第一极。高电平的第二电压可以通过耦合电容CST对上拉控制节点H的电平进行耦合上拉，从而可以避免上拉控制节点H发生漏电。
例如，如图7所示，在另一些实施例中，第三晶体管M3的第一极还可以和第一时钟信号端CLKA连接以接收第一时钟信号。例如，当上拉控制节点H为高电平时，第三晶体管M3被导通，从而第一时钟信号可以施加至耦合电容CST的第一极。当第一时钟信号为高电平时，第一时钟信号可以通过耦合电容CST对上拉控制节点H的电平进行耦合上拉，从而可以避免上拉控制节点H发生漏电。
如图5所示，在本公开的一些实施例中，第一传输电路210可以实现为第一传输晶体管MT1。第一传输晶体管MT1的栅极和第一传输信号端TS1连接以接收第一传输信号，第一传输晶体管MT1的第一极和消隐上拉节点N连接以接收消隐上拉信号，第一传输晶体管MT1的第二极和第一上拉节点Q1连接。例如，当第一传输信号为高电平时，第一传输晶体管MT1导通，从而可以利用消隐上拉信号对第一上拉节点Q1进行充电。
如图5所示，在本公开的一些实施例中，第二传输电路220可以实现为第二传输晶体管MT2。第二传输晶体管MT2的栅极和第二传输信号端TS2连接以接收第二传输信号，第二传输晶体管MT2的第一极和消隐上拉节点N连接以接收消隐上拉信号，第二传输晶体管MT2的第二极和第二上拉节点Q2连接。例如，当第二传输信号为高电平时，第二传输晶体管MT2导通，从而可以利用消隐上拉信号对第二上拉节点Q2进行充电。
例如，如图6所示，在一些实施例中，第一传输晶体管MT1和第二传输晶体管MT2的栅极均可以和第一时钟信号端CLKA连接以接收相同的第 一时钟信号。当第一时钟信号为高电平时，第一传输晶体管MT1和第二传输晶体管MT2同时被导通，从而可以利用消隐上拉信号同时对第一上拉节点Q1和第二上拉节点Q2进行充电。
如图4所示，在本公开的实施例提供的移位寄存器单元10中，第一输入输出单元310包括显示输入电路200、输出电路300、第一下拉控制电路400和下拉电路500。
第一输出端OP1包括移位信号输出端CR和像素扫描信号输出端OUT，移位信号输出端CR和像素扫描信号输出端OUT输出复合输出信号。
该显示输入电路200被配置为响应于第一显示输入信号对第一上拉节点Q1进行充电。例如，在一些实施例中，显示输入电路200可以和显示输入信号端STU2连接以接收第一显示输入信号，从而使得显示输入电路200在第一显示输入信号的控制下被导通。例如，显示输入电路200还可以和第二电压端VDD连接以接收第二电压。例如，在一帧的显示时段中，显示输入电路200在第一显示输入信号的控制下被导通，从而可以利用第二电压对第一上拉节点Q1进行充电。
例如，在多个输入输出单元级联时，各级输入输出单元的显示输入信号端STU2可以和前两级输入输出单元的输出端电连接。例如，在输出端包括移位信号输出端CR和像素扫描信号输出端OUT的情形下，本级输入输出单元的显示输入信号端STU2可以和前两级输入输出单元的移位信号输出端CR电连接。
另外，在本公开的实施例中，“前两级输入输出单元”表示本级输入输出单元往前数第二个输入输出单元，“后三级输入输出单元”表示本级输入输出单元往后数第三个输入输出单元，这里的“前”和“后”是相对的。以下各实施例与此相同，不再赘述。
需要说明的是，在本公开的实施例中，显示输入电路200还可以采用其他配置方式，只要可以实现相应的功能即可，本公开的实施例对此不作限定。
该输出电路300被配置为在第一上拉节点Q1的电平的控制下，将复合输出信号输出至第一输出端OP1。例如，在一些实施例中，输出电路300可以和第二时钟信号端CLKB连接以接收第二时钟信号，并将第二时钟信号作为复合输出信号。例如，复合输出信号可以包括显示输出信号和消隐输出信号，在一帧的显示时段中，输出电路300在第一上拉节点Q1的电平的控制 下将显示输出信号输出至第一输出端OP1，例如在一些实施例中，第一输出端OP1可以包括移位信号输出端CR和像素扫描信号输出端OUT，移位信号输出端CR输出的显示输出信号可以用于上下级移位寄存器单元的扫描移位，而像素扫描信号输出端OUT输出的显示输出信号可以用于驱动显示面板中的子像素单元进行扫描显示。在一帧的消隐时段中，输出电路300在第一上拉节点Q1的电平的控制下将消隐输出信号输出至第一输出端OP1，该消隐输出信号可以用于驱动感测晶体管。
第一下拉控制电路400被配置为在第一上拉节点Q1的电平的控制下，对下拉节点QB的电平进行控制。例如，在一个示例中，第一下拉控制电路400和第三电压端VDD_A以及第五电压端VGL2连接。需要说明的是，在本公开的实施例中第五电压端VGL2例如可以被配置为提供第五电压，例如该第五电压为直流低电平信号，以下各实施例与此相同，不再赘述。
例如，当第一上拉节点Q1处于高电平时，第一下拉控制电路400可以通过第五电压端VGL2提供的低电平的第五电压将下拉节点QB下拉至低电平。又例如，当第一上拉节点Q1的电平处于低电平时，第一下拉控制电路500可以利用第三电压端VDD_A输入的第三电压(例如为高电平)对下拉节点QB进行充电，以将下拉节点QB上拉至高电平。
在另一些示例中，第一下拉控制电路400还可以和第四电压端VDD_B连接以接收第四电压(例如为高电平)，例如，第三电压端VDD_A和第四电压端VDD_B可以被配置为交替输入高电平，即第三电压端VDD_A输入高电平时，第四电压端VDD_B输入低电平，而第三电压端VDD_A输入低电平时，第四电压端VDD_B输入高电平。
下拉电路500被配置为在下拉节点QB的电平的控制下，对第一上拉节点Q1和第一输出端OP1进行下拉复位。例如在第一输出端OP1包括移位信号输出端CR和像素扫描信号输出端OUT的情形下，下拉电路500可以对移位信号输出端CR和像素扫描信号输出端OUT同时进行下拉复位。
例如，下拉电路500和第五电压端VGL2连接，下拉电路500在下拉节点QB的电平的控制下被导通时，可以通过第五电压端VGL2提供的低电平的第五电压对第一上拉节点Q1、移位信号输出端CR以及像素扫描信号输出端OUT进行下拉，从而实现复位。
在一些实施例中，如图4所示，第一输入输出单元310还可以包括第二 下拉控制电路600，第二下拉控制电路600被配置为响应于第一时钟信号对下拉节点QB的电平进行控制。例如，在一个示例中，第二下拉控制电路600可以和第一时钟信号端CLKA连接以接收第一时钟信号，同时和第五电压端VGL2连接以接收低电平的第五电压。例如，在一帧的消隐时段中，第二下拉控制电路600可以响应于第一时钟信号而被导通，从而利用低电平的第五电压对下拉节点QB的电平进行控制，例如对下拉节点QB的电平进行下拉。
在一些实施例中，如图4所示，第一输入输出单元310还可以包括第三下拉控制电路700，第三下拉控制电路700被配置为响应于第一显示输入信号对下拉节点QB的电平进行控制。例如，第三下拉控制电路700可以和显示输入信号端STU2连接以接收第一显示输入信号，同时和第五电压端VGL2连接以接收低电平的第五电压。例如，在一帧的显示时段中，第三下拉控制电路700可以响应于第一显示输入信号而被导通，从而利用低电平的第五电压对下拉节点QB的电平进行控制，例如对下拉节点QB的电平进行下拉。将下拉节点QB的电平下拉至低电平，可以避免下拉节点QB的电平对第一上拉节点Q1的电平的影响，从而在显示时段中可以使得显示输入电路200对第一上拉节点Q1的充电更充分。
在一些实施例中，如图4所示，第一输入输出单元310还可以包括显示复位电路800，显示复位电路800被配置为响应于显示复位信号对第一上拉节点Q1进行复位。例如，在一个示例中，显示复位电路800可以和显示复位信号端STD连接以接收显示复位信号，同时和第五电压端VGL2连接以接收低电平的第五电压。例如，在一帧的显示时段中，显示复位电路800可以响应于显示复位信号而被导通，从而可以通过第五电压端VGL2提供的低电平的第五电压对第一上拉节点Q1进行复位。例如，在多个输入输出单元级联时，各级输入输出单元的显示复位信号端STD可以和后三级输入输出单元的输出端(例如移位信号输出端CR)电连接。
在一些实施例中，如图4所示，第一输入输出单元310还可以包括全局复位电路900，全局复位电路900被配置为响应于全局复位信号对第一上拉节点Q1进行复位。例如，在一个示例中，全局复位电路900和全局复位信号端TRST连接以接收全局复位信号，同时和第五电压端VGL2连接以接收低电平的第五电压。例如，在多个输入输出单元级联时，在一帧的显示时段前，各级输入输出单元中的全局复位电路900响应于全局复位信号而被导通， 从而可以通过第五电压端VGL2提供的低电平的第五电压对第一上拉节点Q1进行复位，从而实现对各级输入输出单元的全局复位。
本领域技术人员可以理解，尽管图4中的第一输入输出单元310示出了第一下拉控制电路400、下拉电路500、第二下拉控制电路600、第三下拉控制电路700、显示复位电路800以及全局复位电路900，然而上述示例并不能限制本公开的保护范围。在实际应用中，本领域技术人员可以根据情况选择采用或不采用上述各电路中的一个或多个，基于前述各电路的各种组合变型均不脱离本公开的原理，对此不再赘述。
在本公开的至少一个实施例中，图4中所示的第一输入输出单元310可以实现为图8所示的电路结构。如图8所示，该第一输入输出单元310包括：第四至第十七晶体管M4-M17以及第二电容C2。第一输出端OP1包括移位信号输出端CR和像素扫描信号输出端OUT，移位信号输出端CR和像素扫描信号输出端OUT均可以输出复合输出信号。需要说明的是，在图8中所示的晶体管均以N型晶体管为例进行说明。另外，在本公开的其它附图中所示的晶体管也是以N型晶体管为例进行说明的，对此不再赘述。
如图8所示，显示输入电路200可以实现为第四晶体管M4，第四晶体管M4的栅极和显示输入信号端STU2连接以接收第一显示输入信号，第四晶体管M4的第一极和第二电压端VDD连接以接收第二电压，第四晶体管M4的第二极和第一上拉节点Q1连接。例如，在一帧的显示时段中，第四晶体管M4在第一显示输入信号的控制下被导通，从而可以利用第二电压对第一上拉节点Q1进行充电。
如图8所示，输出电路300可以实现为包括第五晶体管M5、第六晶体管M6和第二电容C2。第五晶体管M5的栅极和第一上拉节点Q1连接，第五晶体管M5的第一极和第二时钟信号端CLKB连接以接收第二时钟信号，并将第二时钟信号作为复合输出信号，第五晶体管M5的第二极和移位信号输出端CR连接；第六晶体管M6的栅极和第一上拉节点Q1连接，第六晶体管M6的第一极和第二时钟信号端CLKB连接以接收第二时钟信号，并将第二时钟信号作为复合输出信号，第六晶体管M6的第二极和像素扫描信号输出端OUT连接；第二电容C2的第一极和第一上拉节点Q1连接，第二电容C2的第二极和第五晶体管M5的第二极连接。例如，在第一上拉节点Q1的电平为高电平时，第五晶体管M5和第六晶体管M6被导通，从而可以将 第二时钟信号作为复合输出信号分别输出至移位信号输出端CR和像素扫描信号输出端OUT。
如图8所示，第一下拉控制电路400可以实现为包括第七晶体管M7、第八晶体管M8和第九晶体管M9。第七晶体管M7的栅极和第一极连接且被配置为和第三电压端VDD_A连接以接收第三电压，第七晶体管M7的第二极和下拉节点QB连接；第八晶体管M8的栅极和第一极连接且被配置为和第四电压端VDD_B连接以接收第四电压，第八晶体管M8的第二极和下拉节点QB连接；第九晶体管M9的栅极和第一上拉节点Q1连接，第九晶体管M9的第一极和下拉节点QB连接，第九晶体管M9的第二极和第五电压端VGL2连接以接收第五电压。
例如，第三电压端VDD_A和第四电压端VDD_B可以被配置为交替输入高电平，即第三电压端VDD_A输入高电平时，第四电压端VDD_B输入低电平，而第三电压端VDD_A输入低电平时，第四电压端VDD_B输入高电平，即第七晶体管M7和第八晶体管M8中只有一个晶体管处于被导通状态，这样可以避免由于晶体管长期被导通而引起的性能漂移。当第七晶体管M7或第八晶体管M8导通时，第三电压或第四电压可以对下拉节点QB进行充电，从而将下拉节点QB的电平上拉至高电平。当第一上拉节点Q1的电平为高电平时，第九晶体管M9被导通，例如在晶体管的设计上，可以将第九晶体管M9与第七晶体管M7(或第八晶体管M8)配置为(例如对二者的尺寸比、阈值电压等配置)在M9和M7(M8)均被导通时，下拉节点QB的电平可以被下拉至低电平，例如，该低电平可以使得第十晶体管M10、第十一晶体管M11以及第十二晶体管M12保持截止状态。
如图8所示，下拉电路500可以实现为包括第十晶体管M10、第十一晶体管M11和第十二晶体管M12。第十晶体管M10的栅极和下拉节点QB连接，第十晶体管M10的第一极和第一上拉节点Q1连接，第十晶体管M10的第二极和第五电压端VGL2连接以接收第五电压；第十一晶体管M11的栅极和下拉节点QB连接，第十一晶体管M11的第一极和移位信号输出端CR连接，第十一晶体管M11的第二极和第五电压端VGL2连接以接收第五电压；第十二晶体管M12的栅极和下拉节点QB连接，第十二晶体管M12的第一极和像素扫描信号输出端OUT连接，第十二晶体管M12的第二极和第六电压端VGL3连接以接收第六电压。需要说明的是，在本公开的实施例中的第 六电压端VGL3例如可以被配置为提供直流低电平信号，即第六电压为低电平，以下各实施例与此相同，不再赘述。
例如，当下拉节点QB的电平为高电平时，第十晶体管M10、第十一晶体管M11以及第十二晶体管M12被导通，从而可以利用低电平的第五电压对第一上拉节点Q1的电平和移位信号输出端CR的电平进行下拉以降低操作，并且可以利用低电平的第六电压对像素扫描信号输出端OUT的电平进行下拉以降低噪声。
需要说明的是，在本公开的实施例中，例如，第一电压端VGL1、第五电压端VGL2以及第六电压端VGL3输入的低电平信号可以相同，即可以将上述三个电压端连接到同一根信号线以接收相同的低电平信号；又例如，上述三个电压端可以分别连接到不同的信号线以分别接收不同的低电平信号。本公开的实施例对第一电压端VGL1、第五电压端VGL2以及第六电压端VGL3的设置方式不作限定。
如图8所示，第二下拉控制电路600可以实现为第十三晶体管M13。第十三晶体管M13的栅极和第一时钟信号端CLKA连接以接收第一时钟信号，第十三晶体管M13的第一极和下拉节点QB连接，第十三晶体管M13的第二极和第五电压端VGL2连接以接收第五电压。例如，在一帧的消隐时段中，当第一时钟信号为高电平时，第十三晶体管M13被导通，从而可以利用低电平的第五电压对下拉节点QB进行下拉。
例如，在另一些示例中，如图8所示，第二下拉控制电路600还可以包括第十七晶体管M17。第十七晶体管M17的栅极和上拉控制节点H电连接，第十七晶体管M17的第一极和第十三晶体管M13的第二极连接，第十七晶体管M17的第二极和第五电压端VGL2连接以接收第五电压。
例如，在一帧的消隐时段，当第一时钟信号的电平和上拉控制节点H的电平均为高电平时，第十三晶体管M13和第十七晶体管M17均被导通，使下拉节点QB与第五电压端VGL2电连接，从而可以利用低电平的第五电压将下拉节点QB的电平下拉为低电平。
如图8所示，第三下拉控制电路700可以实现为第十四晶体管M14。第十四晶体管M14的栅极和显示输入信号端STU2连接以接收第一显示输入信号，第十四晶体管M14的第一极和下拉节点QB连接，第十四晶体管M14的第二极和第五电压端VGL2连接以接收第五电压。例如，在一帧的显示时 段中，第十四晶体管M14可以响应于第一显示输入信号而被导通，从而利用低电平的第五电压对下拉节点QB的电平进行下拉。将下拉节点QB的电平下拉至低电平，可以避免下拉节点QB的电平对上拉节点Q的电平的影响，从而在显示时段中使得第四晶体管M4对上拉节点Q的充电更充分。
例如，在多个输入输出单元级联时，各级输入输出单元的显示输入信号端STU2可以和前两级输入输出单元的移位信号输出端CR电连接。即，第一显示输入信号可以为前两级输入输出单元的移位信号输出端CR输出的信号。
如图8所示，显示复位电路800可以实现为第十五晶体管M15。第十五晶体管M15的栅极和显示复位信号端STD连接以接收显示复位信号，第十五晶体管M15的第一极和第一上拉节点Q1连接，第十五晶体管M15的第二极和第五电压端VGL2连接以接收第五电压。例如，在一帧的显示时段中，第十五晶体管M15可以响应于显示复位信号而被导通，从而可以利用低电平的第五电压对第一上拉节点Q1进行复位。例如，在多个输入输出单元级联时，各级输入输出单元的显示复位信号端STD可以和后三级输入输出单元的移位信号输出端CR电连接，即显示复位信号可以为后三级输入输出单元的移位信号输出端CR输出的信号。
如图8所示，全局复位电路900可以实现为第十六晶体管M16。第十六晶体管M16的栅极和全局复位信号端TRST连接以接收全局复位信号，第十六晶体管M16的第一极和第一上拉节点Q1连接，第十六晶体管M16的第二极和第五电压端VGL2连接以接收第五电压。例如，在多个输入输出单元级联时，在一帧的显示时段前，各级输入输出单元中的第十六晶体管M16响应于全局复位信号而被导通，通过低电平的第五电压对第一上拉节点Q1进行复位，从而实现对各级输入输出单元的全局复位。
如图9所示，本公开的另一些实施例还提供一种第一输入输出单元310，图9中所示的第一输入输出单元310和图8中所示的第一输入输出单元310相比，输出电路300还包括第十八晶体管M18和第三电容C3，相应地，下拉电路500还包括第十九晶体管M19。
如图9所示，第十八晶体管M18的栅极和第一上拉节点Q1连接，第十八晶体管M18的第一极和第三时钟信号端CLKC连接以接收第三时钟信号，第十八晶体管M18的第二极和另一个像素扫描信号输出端OUT2连接。第 三电容C3的第一极和第一上拉节点Q1连接，第三电容C3的第二极和第十八晶体管M18的第二极连接。例如，当第一上拉节点Q1的电平为高电平时，第十八晶体管M18被导通，从而将第三时钟信号输出至像素扫描信号输出端OUT2。例如，在一个示例中，第三时钟信号端CLKC输入的第三时钟信号可以配置为和第二时钟信号端CLKB输入的第二时钟信号相同；又例如，在另一个示例中，第三时钟信号还可以被配置为与第二时钟信号不同，从而使得两个像素扫描信号输出端OUT和OUT2分别可以输出不同的信号，从而可以提高移位寄存器单元的驱动能力以及增加输出信号的多样性。
需要说明的是，在图9所示的示例中，通过设置第三电容C3可以提高第一上拉节点Q1的电平的保持能力，当然，也可以不设置第三电容C3，本公开的实施例对此不作限定。
如图9所示，第十九晶体管M19的栅极和下拉节点QB连接，第十九晶体管M19的第一极和像素扫描信号输出端OUT2连接，第十九晶体管M19的第二极和第六电压端VGL3连接。例如，当下拉节点QB的电平为高电平时，第十九晶体管M19被导通，从而可以利用低电平的第六电压对像素扫描信号输出端OUT2的电平进行下拉复位。需要说明的是，第十九晶体管M19的第二极还可以被配置为和其它信号端连接，只要可以实现对像素扫描信号输出端OUT2下拉复位即可，本公开的实施例对此不作限定。
如前所述，在本公开的实施例提供的移位寄存器单元10中，可以利用第一电容C1维持上拉控制节点H处的电平，利用第二电容C2维持第一上拉节点Q1处的电平。第一电容C1和/或第二电容C2可以是通过工艺制程制作的电容器件，例如通过制作专门的电容电极来实现电容器件，该电容的各个电极可以通过金属层、半导体层(例如掺杂多晶硅)等实现，或者在一些示例中，通过设计电路布线参数使得第一电容C1和/或第二电容C2也可以通过各个器件之间的寄生电容实现。第一电容C1和/或第二电容C2的连接方式不局限于上面描述的方式，也可以为其他适用的连接方式，只要能存储写入到上拉控制节点H或第一上拉节点Q1的电平即可。
当第一上拉节点Q1和/或上拉控制节点H的电平维持在高电平时，存在一些晶体管(例如第一晶体管M1、第十晶体管M10、第十五晶体管M15、第十六晶体管M16以及第一传输晶体管TM1)的第一极连接第一上拉节点Q1或上拉控制节点H，而第二极连接低电平信号。即使在这些晶体管的栅 极输入的是非导通信号的情况下，由于其第一极和第二极之间存在电压差，也可能出现漏电的情况，从而使得移位寄存器单元10中对于第一上拉节点Q1和/或上拉控制节点H的电平维持的效果变差。
例如，如图5所示，以上拉控制节点H为例，第一晶体管M1的第一极和消隐输入信号端STU1连接，第二极和上拉控制节点H连接。当上拉控制节点H的电平处于高电平，而消隐输入信号端STU1输入的信号为低电平时，上拉控制节点H可能会通过第一晶体管M1漏电。
针对上述问题，如图7和图10所示，本公开的一些实施例还提供一种具有防漏电结构的电路结构。如图7和图10所示，增加了晶体管M1_b、MT1_b、MT2_b、M10_b、M15_b、M16_b、M20以及M21。下面以晶体管M1_b为例对防漏电的工作原理进行说明。
晶体管M1_b的栅极和第一晶体管M1的栅极连接，晶体管M1_b的第一极和晶体管M20的第二极连接，晶体管M1_b的第二极和上拉控制节点H连接。晶体管M20的栅极和上拉控制节点H连接，晶体管M20的第一极和第七电压端VB连接以接收高电平的第七电压。当上拉控制节点H为高电平时，晶体管M20在上拉控制节点H的电平的控制下被导通，从而可以将第七电压端VB输入的高电平的第七电压输入到晶体管M1_b的第一极，使得晶体管M1_b的第一极和第二极都处于高电平，从而可以防止上拉控制节点H通过晶体管M1_b漏电。此时，由于晶体管M1_b的栅极和第一晶体管M1的栅极连接，所以第一晶体管M1和晶体管M1_b的结合可以实现与前述第一晶体管M1相同的效果，同时还具有防漏电的效果。
类似地，如图7所示，对应于第一传输晶体管MT1和第二传输晶体管MT2，还可以分别设置晶体管MT1_b和晶体管MT2_b以实现防漏电结构。晶体管MT1_b以及晶体管MT2_b的栅极都和第一时钟信号端CLKA连接以接收第一时钟信号，第一传输晶体管MT1的第二极以及晶体管MT1_b的第一极和第一防漏电节点OF1连接，如图10所示，第一防漏电节点OF1和第一输入输出单元310中的晶体管M21电连接；第二传输晶体管MT2的第二极以及晶体管MT2_b的第一极和第二防漏电节点OF2连接，第二防漏电节点OF2例如可以和第二输入输出单元320中的晶体管电连接以实现防漏电功能。通过设置晶体管MT1_b可以防止第一上拉节点Q1发生漏电，设置晶体管MT2_b可以防止第二上拉节点Q2发生漏电。
类似地，如图10所示，晶体管M10_b、M15_b以及M16_b可以分别结合晶体管M21实现防漏电结构，从而可以防止第一上拉节点Q1发生漏电。例如，晶体管M21的第一极和第八电压端VC连接以接收高电平的第八电压。防止第一上拉节点Q1发生漏电的工作原理和上述防止上拉控制节点H发生漏电的工作原理相同，这里不再赘述。
如图11所示，本公开的另一些实施例还提供一种第一输入输出单元310，图11中所示的第一输入输出单元310和图10中所示的第一输入输出单元310相比，增加了第二下拉节点QB2；为了和第二下拉节点QB2配合工作，相应地增加了晶体管M22、M22_b、M9_b、M13_b、M17_b、M14_b、M11_b、M12_b以及M19_b。需要说明的是，第八晶体管M8的第二极不再和下拉节点QB连接，而是和第二下拉节点QB2连接；晶体管M22_b是为了防止第一上拉节点Q1发生漏电而设置的防漏电晶体管。
在图11所示的第一输入输出单元310中，晶体管M22、M22_b以及M9_b分别和晶体管M10、M10_b以及M9的工作原理类似；晶体管M13_b、M17_b以及M14_b分别和晶体管M13、M17以及M14的工作原理类似；晶体管M11_b、M12_b以及M19_b分别和晶体管M11、M12以及M19的工作原理类似，这里不再赘述。
在本公开的实施例提供的移位寄存器单元10中，通过设置第二下拉节点QB2以及相应的晶体管，可以进一步提高该移位寄存器单元10的性能。例如，在对第一上拉节点Q1进行充电时，可以使得下拉节点QB的电平和第二下拉节点QB2的电平更好地处于低电平，从而不会影响第一上拉节点Q1的电平，使得对第一上拉节点Q1的充电更充分。又例如，在移位寄存器单元10不需要输出时，可以进一步降低第一上拉节点Q1和输出端(CR、OUT、OUT2)的噪声，避免发生输出异常。
图12示出了一种本公开的实施例提供的移位寄存器单元10，第一传输晶体管MT1通过第一上拉节点Q1和第一输入输出单元310连接，第二传输晶体管MT2通过第二上拉节点Q2和第二输入输出单元320连接。例如，图12中的第一输入输出单元310可以采用本公开的实施例提供的任意一个第一输入输出单元，例如该第一输入输出单元310可以采用图8、图9、图10以及图11中所示的任一电路结构。需要说明的是，在本公开的实施例中对第一输入输出单元310的电路结构进行了描述，第二输入输出单元320的电路 结构可以和第一输入输出单元310的电路结构相同。本公开的实施例包括但不限于此，例如，第二输入输出单元320的电路结构也可以和第一输入输出单元310的电路结构不同，只要可以实现相应的功能即可。
本公开的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。此外，按照晶体管的特性区分可以将晶体管分为N型和P型晶体管。当晶体管为P型晶体管时，开启电压为低电平电压(例如，0V、-5V、-10V或其他合适的电压)，关闭电压为高电平电压(例如，5V、10V或其他合适的电压)；当晶体管为N型晶体管时，开启电压为高电平电压(例如，5V、10V或其他合适的电压)，关闭电压为低电平电压(例如，0V、-5V、-10V或其他合适的电压)。
另外，需要说明的是，本公开的实施例中提供的移位寄存器单元10中采用的晶体管均是以N型晶体管为例进行说明的，本公开的实施例包括但不限于此，例如移位寄存器单元10中的至少部分晶体管也可以采用P型晶体管。
本公开的至少一个实施例还提供一种栅极驱动电路20，如图13所示，该栅极驱动电路20包括多个级联的移位寄存器单元10，其中任意一个或多个移位寄存器单元10可以采用本公开的实施例提供的移位寄存器单元10的结构或其变型。图13中的A1、A2、A3和A4表示输入输出单元，例如这四个输入输出单元均可以采用图9中的电路结构。需要说明的是，在本公开的实施例中，移位寄存器单元10的级联均表示移位寄存器单元10中的输入输出单元之间进行级联，而不同的移位寄存器单元10中的消隐单元之间不进行级联。
例如，如图13所示，每个移位寄存器单元10包括两个输入输出单元，当该栅极驱动电路20用于驱动一显示面板时，每个输入输出单元的输出端可以分别和显示面板中的一行子像素单元电连接。例如，输入输出单元A1、A2、A3以及A4可以分别和第一行、第二行、第三行以及第四行子像素单元电连接。
需要说明的是，在图13所示的栅极驱动电路20中，移位寄存器单元10中的两个输入输出单元是相邻的，即用于驱动显示面板中相邻行的子像素单元。本公开的实施例包括但不限于此，例如其中一个移位寄存器单元10可以包括输入输出单元A1和输入输出单元A3，而另一个移位寄存器单元10包括输入输出单元A2和输入输出单元A4，即移位寄存器单元10中包括的两个输入输出单元可以是不相邻的。
例如，在另一些实施例中，如图14所示，移位寄存器单元10还可以包括四个输入输出单元(A1、A2、A3和A4)，该四个输入输出单元分别通过第一传输电路210、第二传输电路220、第三传输电路230以及第四传输电路240和消隐单元100电连接。
本公开的实施例提供的栅极驱动电路可以共用消隐单元，从而使得采用该栅极驱动电路的显示装置可以减小边框尺寸，降低成本。
下面以图14所示的栅极驱动电路20为例，对栅极驱动电路20中的信号线进行说明。
如图14所示，栅极驱动电路20还包括第一子时钟信号线CLK_1、第二子时钟信号线CLK_2、第三子时钟信号线CLK_3和第四子时钟信号线CLK_4。第4n-3级输入输出单元和第一子时钟信号线CLK_1连接以接收第二时钟信号，例如，第4n-3级输入输出单元通过第二时钟信号端CLKB和第一子时钟信号线CLK_1连接；第4n-2级输入输出单元和第二子时钟信号线CLK_2连接以接收第二时钟信号，例如，第4n-2级输入输出单元通过第二时钟信号端CLKB和第二子时钟信号线CLK_2连接；第4n-1级输入输出单元和第三子时钟信号线CLK_3连接以接收第二时钟信号，例如，第4n-1级输入输出单元通过第二时钟信号端CLKB和第三子时钟信号线CLK_3连接；第4n级输入输出单元和第四子时钟信号线CLK_4连接以接收第二时钟信号，例如，第4n级输入输出单元通过第二时钟信号端CLKB和第四子时钟信号线CLK_4连接；n为大于零的整数。
如上所述，本公开的实施例提供的栅极驱动电路可以采用4CLK的时钟信号，这样可以使得该栅极驱动电路中相邻的输入输出单元输出的信号波形有交叠，从而例如，可以增加预充电时间。本公开的实施例对采用的时钟信号的类型不作限定，例如还可以采用6CLK、8CLK等时钟信号。
如图14所示，栅极驱动电路20还可以包括第八子时钟信号线CLK_8、 第九子时钟信号线CLK_9、第十子时钟信号线CLK_10和第十一子时钟信号线CLK_11。在输入输出单元和第三时钟信号端CLKC连接的情形下，第4n-3级输入输出单元和第八子时钟信号线CLK_8连接以接收第三时钟信号，例如，第4n-3级输入输出单元通过第三时钟信号端CLKC和第八子时钟信号线CLK_8连接；第4n-2级输入输出单元和第九子时钟信号线CLK_9连接以接收第三时钟信号，例如，第4n-2级输入输出单元通过第三时钟信号端CLKC和第九子时钟信号线CLK_9连接；第4n-1级输入输出单元和第十子时钟信号线CLK_10连接以接收第三时钟信号，例如，第4n-1级输入输出单元通过第三时钟信号端CLKC和第十子时钟信号线CLK_10连接；第4n级输入输出单元和第十一子时钟信号线CLK_11连接以接收第三时钟信号，例如，第4n级输入输出单元通过第三时钟信号端CLKC和第十一子时钟信号线CLK_11连接；n为大于零的整数。
如图14所示，栅极驱动电路20还可以包括第五子时钟信号线CLK_5、第六子时钟信号线CLK_6和第七子时钟信号线CLK_7。栅极驱动电路20中的每一个消隐单元100和第五子时钟信号线CLK_5连接以接收补偿选择控制信号，例如，栅极驱动电路20中的每一个消隐单元100通过补偿选择控制端OE和第五子时钟信号线CLK_5连接；每一级输入输出单元和第六子时钟信号线CLK_6连接以接收全局复位信号，例如，每一级输入输出单元通过全局复位信号端TRST和第六子时钟信号线CLK_6连接；每一级输入输出单元和第七子时钟信号线CLK_7连接以接收第一时钟信号，例如，每一级输入输出单元通过第一时钟信号端CLKA和第七子时钟信号端CLK_7连接。
如图14所示，各级输入输出单元的显示输入信号端STU2和前两级输入输出单元的移位信号输出端CR连接，各级输入输出单元的显示复位信号端STD和后三级输入输出单元的移位信号输出端CR连接。
需要说明的是，图14中所示的级联关系仅是一种示例，根据本公开的描述，还可以根据实际情况采用其它级联方式。
例如，在一些实施例中，图14所示的栅极驱动电路20中的输入输出单元采用图9中所示的电路结构，栅极驱动电路20中的消隐单元100采用图6中所示的电路结构，在这种情形下，图15示出了图14所示的栅极驱动电路20工作时的信号时序图。
在图15中，H<5>表示栅极驱动电路20中和第五级输入输出单元电连接的消隐单元100中的上拉控制节点H，Q<1>、Q<5>、Q<6>、Q<7>以及Q<8>分别表示栅极驱动电路20中第一级、第五级、第六级、第七级以及第八级输入输出单元中的上拉节点Q(即图9中所示的第一上拉节点Q1)。OUT<1>(CR<1>)、OUT<7>(CR<7>)和OUT<8>(CR<8>)分别表示栅极驱动电路20中的第一级、第七级以及第八级输入输出单元中的像素扫描信号输出端OUT(移位信号输出端CR)，OUT2<7>和OUT2<8>分别表示栅极驱动电路20中的第七级和第八级输入输出单元中的像素扫描信号输出端OUT2。1F表示第一帧，DS表示第一帧中的显示时段，BL表示第一帧中的消隐时段。需要说明的是，图15中的STU2表示第一级输入输出单元中的显示输入信号端。
另外，需要说明的是，在图15中是以第三电压端VDD_A输入低电平而第四电压端VDD_B输入高电平为例进行示意的，但本公开的实施例不限于此。图15所示的信号时序图中的信号电平只是示意性的，不代表真实电平值。
下面结合图15中的信号时序图，对图14中所示的栅极驱动电路20的工作原理进行说明。
在第一帧1F开始前，第五子时钟信号线CLK_5和第六子时钟信号线CLK_6提供高电平，由于每一个消隐单元100的补偿选择控制端OE均和第五子时钟信号线CLK_5连接，所以使得每一个消隐单元100中的第一晶体管M1被导通，由于此时消隐输入信号端STU1接入的为低电平，从而可以对每一个消隐单元100中的上拉控制节点H进行复位；由于每一级输入输出单元的全局复位信号端TRST均和第六子时钟信号线CLK_6连接，所以使得每一级输入输出单元中的第十六晶体管M16导通，从而可以对每一级输入输出单元中的上拉节点Q进行复位。
由于第四电压端VDD_B输入高电平，第八晶体管M8被导通，使得下拉节点QB的电平被充电至高电平。下拉节点QB的高电平使得第十晶体管M10被导通，从而可以进一步将上拉节点Q的电平下拉至低电平。
在第一帧1F的显示时段DS中，对第一级输入输出单元的工作过程描述如下。
在第一阶段P1中，第一级输入输出单元的显示输入信号端STU2输入 高电平，第四晶体管M4被导通，所以第二电压端VDD输入的高电平可以通过第四晶体管M4对上拉节点Q<1>进行充电，从而使得上拉节点Q<1>的电平被上拉至高电平，并且上拉节点Q<1>的高电平可以被第二电容C2保持。第五晶体管M5和第六晶体管M6在上拉节点Q<1>的电平的控制下被导通，但由于第二时钟信号端CLKB(与第一子时钟信号线CLK1连接)在第一阶段P1输入低电平信号，所以移位信号输出端CR<1>和像素扫描信号输出端OUT<1>均输出该低电平信号。在第一阶段P1，完成对上拉节点Q<1>的预充电。
在第二阶段P2中，第二时钟信号端CLKB输入高电平信号，上拉节点Q<1>的电平由于自举效应而进一步被拉高，所以第五晶体管M5和第六晶体管M6保持导通状态，从而移位信号输出端CR<1>和像素扫描信号输出端OUT<1>均输出该高电平信号。例如，从移位信号输出端CR<1>输出的高电平信号可以用于上下级移位寄存器单元(输入输出单元)的扫描移位，而从像素扫描信号输出端OUT<1>输出的高电平信号可以用于驱动显示面板中的子像素单元进行显示。
在第三阶段P3中，第二时钟信号端CLKB输入低电平信号，由于此时上拉节点Q<1>保持高电平，所以第五晶体管M5和第六晶体管M6继续保持导通状态，从而使得移位信号输出端CR<1>和像素扫描信号输出端OUT<1>均输出该低电平信号。由于第二电容C2的自举作用，所以上拉节点Q<1>的电平也会下降。
在第四阶段P4中，由于第一级输入输出单元的显示复位信号端STD和第四级输入输出单元的移位信号输出端连接，此时第四级输入输出单元的移位信号输出端输出高电平，所以第一极输入输出单元的显示复位信号端STD输入高电平，第十五晶体管M15被导通，上拉节点Q<1>的电平被下拉至低电平，从而完成对上拉节点Q<1>的复位。由于上拉节点Q<1>的电平为低电平，第九晶体管M9被截止，同时第四电压端VDD_B输入的高电平可以对下拉节点QB进行充电，下拉节点QB被充电至高电平，从而使得第十晶体管M10被导通，从而可以进一步对上拉节点Q<1>的电平进行复位。同时第十一晶体管M11和第十二晶体管M12也被导通，从而可以对移位信号输出端CR<1>的电平和像素扫描信号输出端OUT<1>的电平进一步下拉复位。
第一级输入输出单元驱动显示面板中的第一行子像素完成显示后，依次 类推，第二级、第三级等输入输出单元逐行驱动显示面板中的子像素单元完成一帧的显示驱动。至此，第一帧1F的显示时段DS结束。
同时在第一帧1F的显示时段DS中还对上拉控制节点H进行充电，例如，当第一帧1F中需要对第七行子像素单元进行补偿时，则在第一帧1F的显示时段DS中还进行如下操作。
在第五阶段P5中，使得第五子时钟信号线CLK_5提供和第五级输入输出单元的移位信号输出端相同的信号，则当第五级输入输出单元的移位信号输出端输出高电平时，消隐单元100的补偿选择控制端OE输入高电平，第一晶体管M1被导通(如图6所示)；同时可以使消隐输入信号端STU1和第五级输入输出单元的移位信号输出端连接，从而使得消隐输入信号端STU1输入的高电平对上拉控制节点H<5>进行充电，从而将上拉控制节点H<5>的电平上拉至高电平。
需要说明的是，上述对上拉控制节点H<5>的充电过程仅是一种示例，本公开的实施例包括但不限于此。例如，消隐单元100的消隐输入信号端STU1还可以和第三级或第四级输入输出单元的移位信号输出端连接，同时使得提供至第五子时钟信号线CLK_5的信号和提供至消隐输入信号端STU1的信号时序相同即可。
上拉控制节点H<5>的高电平可以一直保持到第一帧1F的消隐时段BL中。当第一帧1F中需要对第七行子像素单元进行补偿时，则在第一帧1F的消隐时段BL中进行如下操作。
在第六阶段P6中，第七子时钟信号线CLK_7提供高电平，由于第一时钟信号端CLKA和第七子时钟信号线CLK_7连接，所以在此阶段第一时钟信号为高电平，所以图14中的四个传输电路均导通，从而高电平的第二电压可以同时对上拉节点Q<5>、Q<6>、Q<7>以及Q<8>进行充电，以将上拉节点Q<5>、Q<6>、Q<7>以及Q<8>的电平上拉至高电平。
需要说明的是，在第六阶段中，也可以仅使得和第七级输入输出单元的传输电路导通，从而仅将上拉节点Q<7>的电平上拉至高电平。
在第七阶段P7中，第七级输入输出单元中的第二时钟信号端CLKB(与第三子时钟信号线CLK_3连接)输入高电平信号，上拉节点Q<7>的电平由于自举作用而进一步被拉高，第七级输入输出单元中的第五晶体管M5和第六晶体管M6被导通，第七级输入输出单元中的第二时钟信号端CLKB输入 的高电平信号可以输出至移位信号输出端CR<7>和像素扫描信号输出端OUT<7>。例如，像素扫描信号输出端OUT<7>输出的信号可以用于驱动显示面板中的子像素单元中的感测晶体管，以实现外部补偿。同时第三时钟信号端CLKC输入的信号可以输出至像素扫描信号输出端OUT2<7>，如图15所示，OUT2<7>的信号可以和OUT<7>不同，从而可以提高栅极驱动电路的驱动能力，满足多样化的需求。
在第八阶段P8中，第七级输入输出单元中的第二时钟信号端CLKB(与第三子时钟信号线CLK_3连接)输入的信号的电平从高电平变为低电平，上拉节点Q<7>的电平由于自举作用而被下拉。
在第九阶段P9中，第五子时钟信号线CLK_5和第六子时钟信号线CLK_6提供高电平，由于每一个消隐单元100的补偿选择控制端OE均和第五子时钟信号线CLK_5连接，每一级输入输出单元的全局复位信号端TRST均和第六子时钟信号线CLK_6连接，所以可以对每一个消隐单元100中的上拉控制节点H的电平以及每一级输入输出单元中的上拉节点Q的电平进行复位。
至此，第一帧的驱动时序结束。后续在第二帧、第三帧等更多阶段中对栅极驱动电路的驱动可以参考上述描述，这里不再赘述。
需要说明是，在上述对随机补偿的工作原理进行描述时，是以第一帧的消隐时段输出对应于显示面板的第七行子像素单元的驱动信号为例进行说明的，本公开对此不作限定。例如，当在某一帧的消隐时段中需要输出对应于显示面板的第n行子像素单元的驱动信号时，则需要在该帧的消隐时段中将第n级输入输出单元中的上拉节点Q的电平上拉至高电平，同时在该帧的消隐时段中，通过第n级输入输出单元中的第二时钟信号端CLKB或第三时钟信号端CLKC输入高电平信号，n为大于零的整数。
另外，在本公开的实施例中，两个信号时序相同指的是位于高电平的时间同步，而不要求两个信号的幅值相同。
本公开的至少一个实施例还提供一种显示装置1，如图16所示，该显示装置1包括本公开实施例提供的栅极驱动电路20以及多个呈阵列排布的子像素单元410。例如，该显示装置1还包括显示面板40，多个子像素单元410构成的像素阵列设置在显示面板40中。
栅极驱动电路20中的每一个移位寄存器单元10中的第一输出端OP1和 第二输出端OP2分别和不同行的子像素单元410电连接，例如，栅极驱动电路20通过栅线GL与子像素单元410电连接。栅极驱动电路20用于提供驱动信号至像素阵列，例如该驱动信号可以驱动子像素单元410中的扫描晶体管和感测晶体管。
例如，该显示装置1还可以包括数据驱动电路30，该数据驱动电路30用于提供数据信号至像素阵列。例如，数据驱动电路30通过数据线DL与子像素单元410电连接。
需要说明的是，本实施例中的显示装置1可以为：液晶面板、液晶电视、显示器、OLED面板、OLED电视、电子纸显示装置、手机、平板电脑、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开的实施例提供的显示装置1的技术效果可以参考上述实施例中关于栅极驱动电路20的相应描述，这里不再赘述。
本公开的至少一个实施例还提供一种驱动方法，可以用于驱动本公开的实施例提供的移位寄存器单元10，多个该移位寄存器单元10可以级联构建本公开一实施例的栅极驱动电路，该栅极驱动电路用于驱动显示面板显示至少一帧画面。该驱动方法包括用于一帧的显示时段和消隐时段。如图17所示，该驱动方法包括以下操作步骤。
步骤S100：在显示时段，使得消隐单元响应于补偿选择控制信号对上拉控制节点进行充电；
步骤S200：在消隐时段，使得第一传输电路响应于第一传输信号利用消隐上拉信号对第一上拉节点进行充电，以及使得第二传输电路响应于第二传输信号利用消隐上拉信号对第二上拉节点进行充电。
在另一些实施例提供的驱动方法中，第一传输信号和第二传输信号的时序相同。
需要说明的是，关于本公开的实施例提供的驱动方法的详细描述和技术效果可以参考本公开的实施例中对于移位寄存器单元10和栅极驱动电路20的工作原理的描述，这里不再赘述。
以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以权利要求的保护范围为准。

Claims (25)

  1. 一种移位寄存器单元，包括消隐单元、第一传输电路、第二传输电路、第一输入输出单元和第二输入输出单元；其中，
    所述消隐单元被配置为响应于补偿选择控制信号对上拉控制节点进行充电并将消隐上拉信号输入到消隐上拉节点；
    所述第一输入输出单元包括第一上拉节点和第一输出端，所述第二输入输出单元包括第二上拉节点和第二输出端；
    所述第一传输电路和所述消隐上拉节点以及所述第一上拉节点电连接，且被配置为响应于第一传输信号利用所述消隐上拉信号对所述第一上拉节点进行充电；
    所述第二传输电路和所述消隐上拉节点以及所述第二上拉节点电连接，且被配置为响应于第二传输信号利用所述消隐上拉信号对所述第二上拉节点进行充电；
    所述第一输入输出单元被配置为响应于第一显示输入信号对所述第一上拉节点进行充电，并且被配置为在所述第一上拉节点的电平的控制下将复合输出信号输出至第一输出端；
    所述第二输入输出单元被配置为响应于第二显示输入信号对所述第二上拉节点进行充电，并且被配置为在所述第二上拉节点的电平的控制下将复合输出信号输出至第二输出端。
  2. 根据权利要求1所述的移位寄存器单元，其中，所述消隐单元包括消隐输入电路和消隐上拉电路；
    所述消隐输入电路被配置为响应于所述补偿选择控制信号对所述上拉控制节点进行充电并保持所述上拉控制节点的电平；
    所述消隐上拉电路被配置为在所述上拉控制节点的电平的控制下将所述消隐上拉信号输入到所述消隐上拉节点。
  3. 根据权利要求2所述的移位寄存器单元，其中，所述消隐单元还包括消隐耦合电路；
    所述消隐耦合电路与所述上拉控制节点电连接，且被配置为对所述上拉控制节点的电平进行耦合上拉。
  4. 根据权利要求2或3所述的移位寄存器单元，其中，所述消隐输 入电路包括第一晶体管和第一电容；
    所述第一晶体管的栅极和补偿选择控制端连接以接收所述补偿选择控制信号，所述第一晶体管的第一极和消隐输入信号端连接，所述第一晶体管的第二极和所述上拉控制节点连接；以及
    所述第一电容的第一极和所述上拉控制节点连接，所述第一电容的第二极和第一电压端连接。
  5. 根据权利要求2-4任一项所述的移位寄存器单元，其中，所述消隐上拉电路包括第二晶体管；
    所述第二晶体管的栅极和所述上拉控制节点连接，所述第二晶体管的第一极和第二电压端连接以接收第二电压，所述第二晶体管的第二极和所述消隐上拉节点连接。
  6. 根据权利要求3所述的移位寄存器单元，其中，消隐耦合电路包括耦合电容和第三晶体管；
    所述第三晶体管的栅极和所述上拉控制节点连接，所述第三晶体管的第一极和第二电压端连接以接收第二电压，所述第三晶体管的第二极和所述耦合电容的第一极连接，所述耦合电容的第二极和所述上拉控制节点连接。
  7. 根据权利要求1-6任一所述的移位寄存器单元，其中，所述第一传输电路包括第一传输晶体管；
    所述第一传输晶体管的栅极和第一传输信号端连接以接收所述第一传输信号，所述第一传输晶体管的第一极和所述消隐上拉节点连接以接收所述消隐上拉信号，所述第一传输晶体管的第二极和所述第一上拉节点连接。
  8. 根据权利要求7所述的移位晶体管单元，其中，所述第一传输信号端包括第一时钟信号端，所述第一传输信号包括通过所述第一时钟信号端接收的第一时钟信号。
  9. 根据权利要求1-8任一所述的移位寄存器单元，其中，所述第二传输电路包括第二传输晶体管；
    所述第二传输晶体管的栅极和第二传输信号端连接以接收所述第二传输信号，所述第二传输晶体管的第一极和所述消隐上拉节点连接以接收所述消隐上拉信号，所述第二传输晶体管的第二极和所述第二上拉节点连 接。
  10. 根据权利要求9所述的移位晶体管单元，其中，所述第二传输信号端包括第一时钟信号端，所述第二传输信号包括通过所述第一时钟信号端接收的第一时钟信号。
  11. 根据权利要求1-10任一项所述的移位寄存器单元，其中，所述第一输入输出单元包括显示输入电路、输出电路、第一下拉控制电路和下拉电路；
    所述第一输出端包括移位信号输出端和像素扫描信号输出端，所述移位信号输出端和所述像素扫描信号输出端输出所述复合输出信号；
    所述显示输入电路被配置为响应于所述第一显示输入信号对所述第一上拉节点进行充电；
    所述输出电路被配置为在所述第一上拉节点的电平的控制下，将所述复合输出信号输出至所述第一输出端；
    所述第一下拉控制电路被配置为在所述第一上拉节点的电平的控制下，对下拉节点的电平进行控制；
    所述下拉电路被配置为在所述下拉节点的电平的控制下，对所述第一上拉节点、所述移位信号输出端和所述像素扫描信号输出端进行下拉复位。
  12. 根据权利要求11所述的移位寄存器单元，其中，
    所述显示输入电路包括第四晶体管；所述第四晶体管的栅极和显示输入信号端连接以接收所述第一显示输入信号，所述第四晶体管的第一极和第二电压端连接以接收第二电压，所述第四晶体管的第二极和所述第一上拉节点连接；
    所述输出电路包括第五晶体管和第六晶体管；所述第五晶体管的栅极和所述第一上拉节点连接，所述第五晶体管的第一极和第二时钟信号端连接以接收第二时钟信号并将所述第二时钟信号作为所述复合输出信号，所述第五晶体管的第二极和所述移位信号输出端连接；所述第六晶体管的栅极和所述第一上拉节点连接，所述第六晶体管的第一极和所述第二时钟信号端连接以接收所述第二时钟信号并将所述第二时钟信号作为所述复合输出信号，所述第六晶体管的第二极和所述像素扫描信号输出端连接；
    所述第一下拉控制电路包括第七晶体管和第九晶体管；所述第七晶体管的栅极和第一极连接且被配置为和第三电压端连接以接收第三电压，所 述第七晶体管的第二极和所述下拉节点连接；所述第九晶体管的栅极和所述第一上拉节点连接，所述第九晶体管的第一极和所述下拉节点连接，所述第九晶体管的第二极和第五电压端连接以接收第五电压；
    所述下拉电路包括第十晶体管、第十一晶体管和第十二晶体管；所述第十晶体管的栅极和所述下拉节点连接，所述第十晶体管的第一极和所述第一上拉节点连接，所述第十晶体管的第二极和所述第五电压端连接以接收所述第五电压；所述第十一晶体管的栅极和所述下拉节点连接，所述第十一晶体管的第一极和所述移位信号输出端连接，所述第十一晶体管的第二极和所述第五电压端连接以接收所述第五电压；所述第十二晶体管的栅极和所述下拉节点连接，所述第十二晶体管的第一极和所述像素扫描信号输出端连接，所述第十二晶体管的第二极和第六电压端连接以接收第六电压。
  13. 根据权利要求12所述的移位寄存器单元，其中，所述输出电路还包括第二电容，
    所述第二电容的第一极和所述第一上拉节点连接，所述第二电容的第二极和所述第五晶体管的第二极连接。
  14. 根据权利要求12或13所述的移位寄存器单元，其中，所述第一下拉控制电路还包括第八晶体管，
    所述第八晶体管的栅极和第一极连接且被配置为和第四电压端连接以接收第四电压，所述第八晶体管的第二极和不同于所述下拉节点的第二下拉节点连接。
  15. 根据权利要求11-14任一项所述的移位寄存器单元，其中，所述第一输入输出单元还包括第二下拉控制电路和第三下拉控制电路；其中，
    所述第二下拉控制电路被配置为响应于第一时钟信号对所述下拉节点的电平进行控制；
    所述第三下拉控制电路被配置为响应于所述第一显示输入信号对所述下拉节点的电平进行控制。
  16. 根据权利要求15所述的移位寄存器单元，其中，所述第二下拉控制电路包括第十三晶体管，所述第三下拉控制电路包括第十四晶体管；
    所述第十三晶体管的栅极和第一时钟信号端连接以接收所述第一时钟信号，所述第十三晶体管的第一极和所述下拉节点连接，所述第十三晶 体管的第二极和第五电压端连接以接收第五电压；
    所述第十四晶体管的栅极和显示输入信号端连接以接收所述第一显示输入信号，所述第十四晶体管的第一极和所述下拉节点连接，所述第十四晶体管的第二极和所述第五电压端连接以接收所述第五电压。
  17. 根据权利要求15所述的移位寄存器单元，其中，所述第二下拉控制电路包括第十三晶体管和第十七晶体管，所述第三下拉控制电路包括第十四晶体管；
    所述第十三晶体管的栅极和第一时钟信号端连接以接收所述第一时钟信号，所述第十三晶体管的第一极和所述下拉节点连接，所述第十三晶体管的第二极和所述第十七晶体管的第一极连接；所述第十七晶体管的栅极和所述上拉控制节点电连接，所述第十七晶体管的第二极和第五电压端连接以接收第五电压；
    所述第十四晶体管的栅极和显示输入信号端连接以接收所述第一显示输入信号，所述第十四晶体管的第一极和所述下拉节点连接，所述第十四晶体管的第二极和所述第五电压端连接以接收所述第五电压。
  18. 根据权利要求11-17任一项所述的移位寄存器单元，其中，所述第一输入输出单元还包括显示复位电路和全局复位电路，其中，
    所述显示复位电路被配置为响应于显示复位信号对所述第一上拉节点进行复位；所述全局复位信号被配置为响应于全局复位信号对所述第一上拉节点进行复位。
  19. 根据权利要求18所述的移位寄存器单元，其中，所述显示复位电路包括第十五晶体管，所述全局复位电路包括第十六晶体管；
    所述第十五晶体管的栅极和显示复位信号端连接以接收所述显示复位信号，所述第十五晶体管的第一极和所述第一上拉节点连接，所述第十五晶体管的第二极和第五电压端连接以接收第五电压；
    所述第十六晶体管的栅极和全局复位信号端连接以接收所述全局复位信号，所述第十六晶体管的第一极和所述第一上拉节点连接，所述第十六晶体管的第二极和所述第五电压端连接以接收所述第五电压。
  20. 根据权利要求11-19任一所述的移位寄存器单元，其中，所述第二输入输出单元的电路结构和所述第一输入输出单元的电路结构相同。
  21. 根据权利要求1所述的移位寄存器单元，还包括至少一个第三传 输电路和与所述至少一个第三传输电路电连接的至少一个第三输入输出单元。
  22. 一种栅极驱动电路，包括多个级联的如权利要求1-21任一项所述的移位寄存器单元。
  23. 一种显示装置，包括如权利要求22所述的栅极驱动电路以及多个呈阵列排布的子像素单元，其中，
    所述栅极驱动电路中的每一个移位寄存器单元中的所述第一输出端和所述第二输出端分别和不同行的子像素单元电连接。
  24. 一种如权利要求1-21任一项所述的移位寄存器单元的驱动方法，包括用于一帧的显示时段和消隐时段，其中，
    在所述显示时段，使得所述消隐单元响应于所述补偿选择控制信号对所述上拉控制节点进行充电；
    在所述消隐时段，使得所述第一传输电路响应于所述第一传输信号利用所述消隐上拉信号对所述第一上拉节点进行充电，以及使得所述第二传输电路响应于所述第二传输信号利用所述消隐上拉信号对所述第二上拉节点进行充电。
  25. 根据权利要求24所述的驱动方法，其中，所述第一传输信号和所述第二传输信号的时序相同。
PCT/CN2019/096185 2018-07-18 2019-07-16 移位寄存器单元、栅极驱动电路、显示装置及驱动方法 WO2020015642A1 (zh)

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CN109935199A (zh) 2019-06-25
JP2021530722A (ja) 2021-11-11
JP7396901B2 (ja) 2023-12-12
EP3825995A4 (en) 2022-06-15
EP3825995A1 (en) 2021-05-26
US11069281B2 (en) 2021-07-20
CN109935199B (zh) 2021-01-26

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