WO2019114287A1 - 阵列基板及其制备方法、触控显示面板 - Google Patents

阵列基板及其制备方法、触控显示面板 Download PDF

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Publication number
WO2019114287A1
WO2019114287A1 PCT/CN2018/098998 CN2018098998W WO2019114287A1 WO 2019114287 A1 WO2019114287 A1 WO 2019114287A1 CN 2018098998 W CN2018098998 W CN 2018098998W WO 2019114287 A1 WO2019114287 A1 WO 2019114287A1
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Prior art keywords
electrode
layer
touch
substrate
forming
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PCT/CN2018/098998
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English (en)
French (fr)
Inventor
武新国
王凤国
史大为
刘弘
王子峰
李峰
马波
郭志轩
李元博
赵晶
段岑鸿
梁海琴
Original Assignee
京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Priority to US16/631,524 priority Critical patent/US11222908B2/en
Publication of WO2019114287A1 publication Critical patent/WO2019114287A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0448—Details of the electrode shape, e.g. for enhancing the detection of touches, for generating specific electric field shapes, for enhancing display quality
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/047—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means using sets of wires, e.g. crossed wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04103—Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices

Definitions

  • Embodiments of the present disclosure relate to an array substrate, a method of fabricating the same, and a touch display panel.
  • the touch panel can be classified into an Add on Mode, an On-Cell, an In-Cell, and the like according to the composition.
  • the in-cell touch panel embeds the touch electrodes of the touch module in the display module, and combines the display and the touch into one, which not only greatly reduces the overall thickness of the module, but also makes the product thinner and lighter. Reduced production costs.
  • the self-capacitive touch panel has gradually become the mainstream touch panel.
  • the self-capacitive touch panel directly adds a touch electrode and a touch line on a thin film transistor (TFT) array substrate, and adopts a time-division driving operation mode, and one frame effective time is divided into a display time period (Display Time). And the touch time (Touch Time), the driving signals of the two time periods are processed separately.
  • the touch electrodes are multiplexed into a common electrode
  • the touch lines are multiplexed into a common electrode line
  • the touch lines provide a common voltage signal to the touch electrodes, and the touch signals are not scanned, but during the touch period, The touch signal is scanned through the touch line, and the two work independently in time sharing.
  • the self-capacitive touch panel has the advantages of simple structure, easy implementation, and the like, there are also defects in which the aperture ratio is low.
  • high-brightness display has gradually become the main development trend of touch panels, and the low aperture ratio of self-capacitive touch panels seriously restricts the brightness enhancement of touch panels.
  • At least one embodiment of the present disclosure provides an array substrate including a substrate and a first electrode and a second electrode formed on the substrate and configured to transmit a display signal, and a touch line configured to transmit a touch signal.
  • the first electrode and the touch line are respectively disposed in different layers, and an orthographic projection of the first electrode on the substrate at least partially overlaps with an orthographic projection of the touch line on the substrate.
  • the orthographic projection of the touch line on the substrate is located within an orthographic projection of the first electrode on the substrate, or the orthographic projection of the first electrode on the substrate is located The touch line is within an orthographic projection on the substrate.
  • the second electrode and the touch line are disposed in the same layer.
  • the touch line is further configured to transmit a common voltage signal.
  • the first electrode is disposed on the substrate, and the buffer layer covers the first electrode
  • the active layer is disposed on the buffer layer, and is connected to the first electrode through a via hole formed in the buffer layer, the gate insulating layer covers the active layer, and the gate electrode is disposed at On the gate insulating layer, the interlayer insulating layer covers the gate electrode, the second electrode and the touch line are disposed on the interlayer insulating layer, and the second electrode passes through the interlayer insulating layer
  • the via hole opened above is connected to the active layer.
  • a light shielding layer is further included, and the light shielding layer and the first electrode are disposed in the same layer.
  • the method further includes a flat layer, a touch electrode, a passivation layer, and a pixel electrode; the second electrode and the touch line cover the flat layer, and the touch electrode is disposed in the a passivation layer is formed on the passivation layer, and the pixel electrode is disposed on the passivation layer, and the through hole is formed on the flat layer.
  • the via holes of the passivation layer and the planarization layer are connected to the second electrode; or the second electrode and the touch line cover the passivation layer, and the pixel electrode is disposed on the passivation layer, Connected to the second electrode through a via hole formed in the passivation layer, the flat layer covers the pixel electrode, and the touch electrode is disposed on the flat layer, through the flat layer and blunt The via of the layer is connected to the touch line.
  • At least one embodiment of the present disclosure also provides a touch display panel including the above array substrate.
  • At least one embodiment of the present disclosure provides a method of fabricating an array substrate, including:
  • first electrode and a second electrode configured to transmit a display signal
  • a touch line configured to transmit a touch signal
  • the first electrode and the touch line are respectively formed in different layers
  • An orthographic projection of the first electrode on the substrate at least partially overlaps an orthographic projection of the touch line on the substrate.
  • an orthographic projection of the touch line on the substrate is located within an orthographic projection of the first electrode on the substrate, or the first electrode is on the substrate The orthographic projection is located within the orthographic projection of the touch line on the substrate.
  • the second electrode and the touch line are disposed in the same layer.
  • the touch line is further configured to transmit a common voltage signal.
  • a first electrode and a second electrode configured to transmit a display signal, and a touch line configured to transmit a touch signal are respectively formed on the substrate, including:
  • the first electrode is formed on the substrate while a light shielding layer is further formed.
  • forming the active layer on the buffer layer includes forming a low temperature polysilicon active layer on the buffer layer.
  • the method further includes:
  • a passivation layer covering the second electrode and the touch line and having a fourth via
  • a pixel electrode is formed on the passivation layer, and the pixel electrode passes through the fourth via and the second electrode
  • Connecting forming a flat layer covering the pixel electrode, and forming a third electrode penetrating the flat layer and the passivation layer, forming a touch electrode on the flat layer, wherein the touch electrode passes the third pass
  • the hole is connected to the touch wire.
  • FIG. 1 is a schematic structural view of a self-capacitive touch array substrate known to the inventors
  • FIG. 2 is a schematic structural view of an array substrate according to an embodiment of the present disclosure
  • FIG. 3 is a schematic structural view of a first electrode and a light shielding layer pattern formed according to an embodiment of the present disclosure
  • Figure 4 is a cross-sectional view taken along line A-A of Figure 3;
  • FIG. 5 is a schematic structural view of forming a buffer layer pattern with a first via hole according to an embodiment of the present disclosure
  • Figure 6 is a cross-sectional view taken along line A-A of Figure 5;
  • FIG. 7 is a schematic structural view of forming an LTPS active layer pattern according to an embodiment of the present disclosure.
  • Figure 8 is a cross-sectional view taken along line A-A of Figure 7;
  • FIG. 9 is a schematic structural view of a gate insulating layer and a gate electrode pattern formed according to an embodiment of the present disclosure.
  • Figure 10 is a cross-sectional view taken along line A-A of Figure 9;
  • FIG. 11 is a schematic structural view of forming an interlayer insulating layer pattern with a second via hole according to an embodiment of the present disclosure
  • Figure 12 is a cross-sectional view taken along line A-A of Figure 11;
  • FIG. 13 is a schematic structural diagram of forming a second electrode and a touch line pattern according to an embodiment of the present disclosure
  • Figure 14 is a cross-sectional view taken along line A-A of Figure 13;
  • FIG. 15 is a schematic structural view of forming a flat layer pattern with a third via hole according to an embodiment of the present disclosure
  • Figure 16 is a cross-sectional view taken along line A-A of Figure 15;
  • FIG. 17 is a schematic structural diagram of forming a touch electrode pattern according to an embodiment of the present disclosure.
  • Figure 18 is a cross-sectional view taken along line A-A of Figure 17;
  • FIG. 19 is a schematic structural view of forming a passivation layer pattern with a fourth via hole according to an embodiment of the present disclosure
  • Figure 20 is a cross-sectional view taken along line A-A of Figure 19;
  • 21 is a schematic structural view of a pixel electrode pattern formed according to an embodiment of the present disclosure.
  • Figure 22 is a cross-sectional view taken along line A-A of Figure 21;
  • FIG. 23 is a schematic structural view of an array substrate according to another embodiment of the present disclosure.
  • 13 LTPS active layer
  • 14 gate insulating layer
  • 15 gate electrode
  • installation In the description of the embodiments of the present invention, it should be noted that the terms “installation”, “connected”, and “connected” are to be understood broadly, and may be, for example, a fixed connection or a Removable connection, or integral connection; may be mechanical connection or electrical connection; may be directly connected, or may be indirectly connected through an intermediate medium, and may be internal communication between the two elements.
  • the specific meaning of the above terms in the present invention can be understood in a specific case by those skilled in the art.
  • the array substrate is a low temperature poly-Silicon (LTPS) thin film transistor structure.
  • the array substrate includes a substrate 10, a light shielding layer 11 disposed on the substrate, a buffer layer 12 covering the light shielding layer 11, an LTPS active layer 13 disposed on the buffer layer 12, and an LTPS active layer 13 a gate insulating layer 14, a gate electrode 15 disposed on the gate insulating layer 14, an interlayer insulating layer 16 covering the gate electrode 15, a first electrode 17, a second electrode 18, and a touch provided on the interlayer insulating layer 16.
  • LTPS low temperature poly-Silicon
  • the line 19, the first electrode 17 and the second electrode 18 are a source electrode and a drain electrode, respectively, and the first electrode 17 and the second electrode 18 are respectively activated by a via hole formed in the gate insulating layer 14 and the interlayer insulating layer 16 and the LTPS.
  • the layer 13 is connected to cover the flat layer 20 of the first electrode 17, the second electrode 18 and the touch line 19, the touch electrode 21 disposed on the flat layer 20, and the touch electrode 21 passes through the via hole formed in the flat layer 20.
  • the touch line 19 is connected to cover the passivation layer 22 of the touch electrode 21, the pixel electrode 23 disposed on the passivation layer 22, and the pixel electrode 23 passes through the passivation layer 22 and the via hole and the second electrode formed on the flat layer 20. 18 connections.
  • the touch pattern metal (TPM) and the touch electrode are connected through the flat layer via hole to realize time-division driving of the common voltage and the touch scan.
  • the reason why the aperture ratio of the structure is low as shown in FIG. 1 is that the structure adopts a parallel dual source structure, and the source electrode, the drain electrode and the touch line are disposed in parallel and in parallel. Since the touch line is disposed in the display area in parallel with the source electrode and the drain electrode, the opaque wiring area is large, and the light transmission area is reduced, thereby resulting in a low aperture ratio, and the aperture ratio is only about 50%, which seriously restricts The brightness is increased.
  • Embodiments of the present disclosure provide an array substrate, a method for fabricating the same, and a touch display panel to overcome the defects of low aperture ratio of the prior art structure.
  • the touch line and the source electrode are disposed on different layers and overlapped, that is, the orthographic projection of the touch line on the substrate overlaps with the orthographic projection of the source electrode on the substrate to reduce the touch line pair light.
  • the occlusion increases the light transmission area.
  • An array substrate according to an embodiment of the present disclosure includes a first electrode and a second electrode configured to transmit a display signal, and a touch line configured to transmit a touch signal, wherein the first electrode and the touch line are respectively Provided in different layers, and the orthographic projection of the first electrode on the substrate at least partially overlaps the orthographic projection of the touch line on the substrate.
  • a first electrode 17 as a source electrode is disposed on and in contact with the substrate 10
  • the touch line 19 is disposed in another layer above the first electrode 17, unlike the first electrode 17.
  • the layer arrangement, the orthographic projection of the touch line 19 on the substrate 10 at least partially overlaps the orthographic projection of the first electrode 17 on the substrate 10.
  • the second electrode 18 as a drain electrode is disposed in the same layer as the touch line 19, and the second electrode 18 and the touch line 19 may be formed by one patterning process, and the array substrate further includes a buffer layer 12
  • the active layer 13, the gate insulating layer 14, the gate electrode 15 and the interlayer insulating layer 16, the layer of the active layer 13 is located between the layer where the first electrode 17 is located and the layer where the second electrode 18 is located, and is respectively connected to the first electrode 17 is connected to the second electrode 18.
  • the orthographic projection of the touch line 19 on the substrate may be located within an orthographic projection of the first electrode 17 on the substrate, ie, the first electrode 17 is in the The width of the orthographic projection on the substrate is greater than the width of the orthographic projection of the touch line 19 on the substrate 10, and the orthographic projection of the touch line 19 on the substrate 10 is located at the first electrode 17 Within the orthographic projection on the substrate 10.
  • the orthographic projection of the first electrode 17 on the substrate 10 may be located within the orthographic projection of the touch line 19 on the substrate 10, that is, the touch line 19 is The width of the orthographic projection on the substrate 10 is greater than the width of the orthographic projection of the first electrode 17 on the substrate 10.
  • the orthographic projection of the first electrode 17 on the substrate 10 may be located at the touch.
  • Line 19 is within the orthographic projection on the substrate 10.
  • At least one embodiment of the present disclosure provides an array substrate by separating a first electrode and a touch line in different layers and causing an orthographic projection of the first electrode on the substrate with the touch line
  • the orthographic projections on the substrate at least partially overlap, reducing the opaque wiring area, increasing the light transmission area, maximizing the aperture ratio, and thereby increasing the brightness.
  • the technical solution of the present disclosure will be described below by taking an LTPS thin film transistor array substrate of a double gate structure as an example.
  • 3 to 22 are schematic views showing the structure of an array substrate according to an embodiment of the present disclosure.
  • the "patterning process" in the present embodiment includes a process of depositing a film layer, coating a photoresist, mask exposure, development, etching, stripping photoresist, etc., and is a mature preparation process.
  • the deposition may be carried out by a mature process such as sputtering, evaporation, chemical vapor deposition, etc., and the coating may adopt a mature coating process, and the etching may adopt a mature method, and is not specifically limited herein.
  • a first electrode and a light shielding layer pattern are formed on the substrate.
  • Forming the light shielding layer and the first electrode pattern includes: depositing a first metal film on the substrate 10, coating a photoresist on the first metal film, exposing and developing the photoresist by using a monotone mask, The first electrode and the light shielding layer pattern are formed to form an unexposed area, a photoresist is left, a completely exposed area is formed at other positions, the photoresist is removed, the first metal film of the fully exposed area is etched and the remaining light is stripped.
  • the glue is formed to form a pattern of the light shielding layer 11 and the first electrode 17, as shown in FIGS. 3 and 4, wherein the first electrode 17 is a source electrode.
  • the pattern of the light shielding layer and the first electrode is formed by one patterning process, and the light shielding layer is made of the same metal material as that of the first electrode.
  • the substrate may be a glass substrate or a quartz substrate, and the first metal film may be one of a metal such as platinum Pt, ruthenium Ru, gold Au, silver Ag, molybdenum Mo, chromium Cr, aluminum Al, tantalum Ta, titanium Ti, tungsten W or the like. Or a variety, or composite layer structure, such as Ti / Al / Ti or Mo / Al / Mo.
  • a buffer pattern layer having a first via hole is formed on the substrate on which the light shielding layer and the first electrode pattern are formed.
  • Forming the buffer layer pattern with the first via hole includes: depositing a buffer layer film on the substrate on which the light shielding layer 11 and the first electrode 17 pattern are formed, and coating a buffer layer on the buffer layer film, using a single The mask is exposed and developed by the tone mask to form a fully exposed area at the first via location, the photoresist is removed, an unexposed area is formed at other locations, a photoresist is retained, and the fully exposed area is buffered.
  • the layer film is etched and the remaining photoresist is stripped to form a pattern of the buffer layer 12 with the first via a, the first via a is located at the position of the first electrode 17, and the buffer film in the via is removed.
  • the surface of the first electrode 17 is exposed as shown in FIGS. 5 and 6.
  • the buffer layer may be silicon nitride SiNx, silicon oxide SiOx or silicon oxynitride Si(ON)x, which may be a single layer, a double layer or a multilayer structure, and the buffer layer prevents metal ions in the substrate from diffusing to the active layer.
  • a suitable buffer layer can improve the quality of the interface on the back side of the polysilicon layer (ie, the side of the polysilicon layer facing the substrate), prevent leakage current from occurring at the back surface of the polysilicon layer, and further reduce Heat conduction slows down the cooling rate of silicon heated by the laser.
  • Forming the LTPS active layer pattern includes: depositing an amorphous silicon film on the substrate on which the foregoing pattern is formed, treating the amorphous silicon film with a laser, crystallizing the amorphous silicon film into a polysilicon film, and then coating the polysilicon film A layer of photoresist, exposed and developed by a single-tone mask, forming an unexposed area at the LTPS active layer pattern location, retaining photoresist, forming a fully exposed area at other locations, photoresist It is removed, the polysilicon film in the fully exposed region is etched and the remaining photoresist is stripped to form a pattern of the LTPS active layer 13, as shown in FIGS.
  • the LTPS active layer 13 is U-shaped, the first end is disposed on the first electrode 17, and is connected to the first electrode 17 through the first via a on the buffer layer, and the second end is disposed in the light shielding Above layer 11.
  • a gate insulating layer and a gate electrode pattern are formed on the substrate on which the aforementioned pattern is formed.
  • Forming the gate insulating layer and the gate electrode pattern includes: sequentially depositing a gate insulating film and a second metal film on the substrate on which the foregoing pattern is formed, patterning the second metal film by a patterning process, and forming the gate insulating layer 14 and the gate electrode 15 The pattern, the gate insulating layer 14 covers the LTPS active layer 13, and the gate electrode 15 is disposed on the gate insulating layer 14, as shown in FIGS. 9 and 10. Since the LTPS active layer of the present embodiment is U-shaped, the LTPS active layer and the gate line form a double gate structure.
  • the gate insulating film may be silicon nitride SiNx, silicon oxide SiOx or silicon oxynitride Si(ON)x, and may be a single layer, a double layer or a multilayer structure, and the second metal film may be a platinum Pt, a ruthenium or a ruthenium.
  • the second metal film may be a platinum Pt, a ruthenium or a ruthenium.
  • Au gold
  • An interlayer insulating layer pattern having a second via hole is formed on the substrate on which the aforementioned pattern is formed.
  • Forming the interlayer insulating layer pattern with the second via hole includes: depositing an interlayer insulating film on the substrate on which the foregoing pattern is formed, and patterning the interlayer insulating film by a patterning process to form a second via hole b
  • the interlayer insulating layer 16 is patterned, the second via hole b is located at the second end of the U-shaped LTPS active layer 13, and the interlayer insulating layer 16 and the gate insulating layer 14 in the hole are etched away to expose the LTPS active layer.
  • As the interlayer insulating film a composite film of silicon nitride SiNx, silicon oxide SiOx or SiNx/SiOx may be used.
  • a second electrode and a touch line pattern are formed on the substrate on which the aforementioned pattern is formed.
  • Forming the drain electrode and the touch line pattern includes: depositing a third metal film on the substrate on which the pattern is formed, patterning the third metal film by a patterning process, forming a pattern of the second electrode 18 and the touch line 19,
  • the second electrode 18 is connected to the second end of the LTPS active layer 13 through the second via b on the interlayer insulating layer 16.
  • the touch line 19 is located above the first electrode 17, and the front projection of the touch line 19 on the substrate Located within the orthographic projection of the first electrode 17 on the substrate, as shown in Figures 13 and 14.
  • the second electrode 18 is a drain electrode.
  • the third metal film may be one or more of platinum Pt, ruthenium Ru, gold Au, silver Ag, molybdenum Mo, chromium Cr, aluminum Al, tantalum Ta, titanium Ti, tungsten W, or the like, or a composite layer structure. Such as Ti/Al/Ti or Mo/Al/Mo.
  • a flat layer pattern having a third via hole is formed on the substrate on which the aforementioned pattern is formed.
  • Forming the flat layer pattern with the third via hole includes: depositing a flat film on the substrate on which the foregoing pattern is formed, exposing and developing the flat film using a mask to form a flat layer having the third via hole c
  • the pattern of 20, the third via c is located at the position of the touch line 19, and the flat film in the hole is removed to expose the surface of the touch line 19, as shown in FIGS. 15 and 16.
  • the flat film can be made of an organic material such as acrylic.
  • a touch electrode pattern is formed on the substrate on which the aforementioned pattern is formed.
  • Forming the touch electrode pattern includes: depositing a first transparent film on the substrate on which the pattern is formed, patterning the first transparent film by a patterning process, forming a pattern of the touch electrode 21, and the touch electrode 21 passes through the flat layer 20
  • the opened third via c is connected to the touch line 19 as shown in FIGS. 17 and 18.
  • the first transparent film may be indium tin oxide ITO or indium zinc oxide IZO.
  • a passivation layer pattern with a fourth via hole is formed on the substrate on which the aforementioned pattern is formed.
  • Forming the passivation layer pattern with the fourth via hole includes: depositing a passivation film on the substrate on which the foregoing pattern is formed, patterning the passivation film by a patterning process, and forming a passivation with the fourth via hole d
  • the layer 22 is patterned, the fourth via d is located at the position of the second electrode 18, and the passivation layer 22 and the flat layer 20 in the hole are etched away to expose the surface of the second electrode 18, as shown in FIGS. 19 and 20.
  • the passivation film may be a composite film of silicon nitride SiNx, silicon oxide SiOx or SiNx/SiOx.
  • a pixel electrode pattern is formed on the substrate on which the aforementioned pattern is formed.
  • Forming the pixel electrode pattern includes: depositing a second transparent film on the substrate on which the pattern is formed, patterning the second transparent film by a patterning process, forming a pattern of the pixel electrode 23, and the pixel electrode 23 is opened through the passivation layer 22.
  • the fourth via d is connected to the second electrode 18 as shown in FIGS. 21 and 22.
  • the second transparent film may be indium tin oxide ITO or indium zinc oxide IZO.
  • the source electrode and the touch line are respectively disposed in different layers, compared with the structure in which the source electrode and the touch line are disposed in parallel.
  • the rate which in turn increases the brightness.
  • the embodiment of the present disclosure utilizes the source electrode as the light-shielding structure, which reduces the area of the light-shielding layer, not only further increases the light-transmitting area, but also effectively avoids display defects caused by factors such as alignment accuracy in preparation, and improves the yield.
  • the overlapping of the front projection of the first electrode and the touch line on the substrate means that the first electrode is disposed in one structural layer, and the touch line is disposed in another structural layer, and the touch line is on the substrate.
  • the upper orthographic projection coincides with the orthographic projection of the first electrode on the substrate.
  • the orthographic projection of the touch line on the substrate is located within the orthographic projection of the first electrode on the substrate, wherein the width of the touch line being orthographically projected on the substrate is equal to or smaller than the width of the first electrode being orthographically projected on the substrate, and the touch
  • the contour of the orthographic projection of the line on the substrate is surrounded by the contour of the orthographic projection of the first electrode on the substrate.
  • the orthographic projection of the first electrode on the substrate is located within the orthographic projection of the touch line on the substrate, wherein the width of the first electrode being orthographically projected on the substrate is equal to or smaller than the width of the touch line being orthographically projected on the substrate, first
  • the contour of the orthographic projection of the electrode on the substrate is surrounded by the contour of the orthographic projection of the touch line on the substrate.
  • the width and shape of the touch line and the position of the via of the touch line and the touch electrode can be designed according to actual needs, and the touch line can also be configured to transmit the touch signal and the common voltage signal. Not limited.
  • the array substrate of this embodiment includes:
  • the light shielding layer 11 and the first electrode 17 are disposed on the substrate 10;
  • a buffer layer 12 covering the light shielding layer 11 and the first electrode 17, and a first via hole for connecting the first electrode 17 and the LTPS active layer 13 is opened thereon;
  • a U-shaped LTPS active layer 13 disposed on the buffer layer 12, the first end of which is connected to the first electrode 17 through the first via hole;
  • a gate electrode 15 disposed on the gate insulating layer 14;
  • the interlayer insulating layer 16, covering the gate electrode 15, is provided with a second via hole for connecting the second electrode 18 and the LTPS active layer 13, the second via hole penetrating the interlayer insulating layer 16 and the gate insulating layer 14;
  • the second electrode 18 and the touch line 19 are disposed on the interlayer insulating layer 16, and the second electrode 18 is connected to the second end of the LTPS active layer 13 through the second via hole;
  • the flat layer 20 covers the second electrode 18 and the touch line 19, and has a third via hole for connecting the touch line 19 and the touch electrode 21;
  • the touch electrode 21 is disposed on the flat layer 20 and connected to the touch line 19 through the third via hole;
  • the passivation layer 22 covers the touch electrode 21, and has a fourth via hole for connecting the second electrode 18 and the pixel electrode 23, and the fourth via hole penetrates the passivation layer 22 and the flat layer 20;
  • the pixel electrode 23 is disposed on the passivation layer 22 and connected to the second electrode 18 through the fourth via hole.
  • the first electrode serves as a source electrode
  • the second electrode serves as a drain electrode
  • the source electrode and the data line are integrated
  • the gate electrode and the gate line are integrated.
  • the light shielding layer 11 and the first electrode 17 are disposed on the substrate 10, which means that the light shielding layer 11 and the first electrode 17 may be directly disposed on the substrate 10 and in contact with the substrate 10, or may be disposed by the light shielding layer 11 and the first electrode 17. On the substrate 10, but not in direct contact with the substrate 10, other structures are provided therebetween.
  • the array substrate of the present embodiment includes: a substrate 10, a light shielding layer 11, a first electrode 17, a buffer layer 12, a U-shaped LTPS active layer 13, a gate insulating layer 14, a gate electrode 15, and interlayer insulation.
  • the structure of the layer 16, the second electrode 18 and the touch line 19 is the same as that of the previous embodiment, except that the passivation layer 22 covers the second electrode 18 and the touch line 19, and the second electrode 18 is opened thereon.
  • a fourth via connected to the pixel electrode 23 the pixel electrode 23 is disposed on the passivation layer 22, connected to the second electrode 18 through the fourth via, and the flat layer 20 covers the pixel electrode 23, and the touch line is opened thereon.
  • the third via hole connected to the touch electrode 21 is disposed on the flat layer 20 and connected to the touch line 19 through the third via hole.
  • the first electrode and the touch line are separated into different layers, and the orthographic projection of the touch line on the substrate is located within the orthographic projection of the source electrode on the substrate, thereby improving the opening. rate.
  • embodiments of the present disclosure may also employ a single gate structure LTPS thin film transistor array substrate.
  • the U-shaped LTPS active layer in the foregoing embodiment may be modified into an L shape, and the vertical end of the L-shaped active layer is disposed on the source electrode (data line) to form a cross with the gate electrode (gate line).
  • the horizontal end is parallel to the gate line and does not intersect the gate line to form a single gate structure LTPS thin film transistor array substrate.
  • the source electrode can function as a shield, so that no light shielding layer can be provided.
  • array substrates of other structures may also be used in the embodiments of the present disclosure.
  • the LTPS active layer can be replaced with a metal oxide material to form an Oxide thin film transistor array substrate.
  • the metal oxide material may be indium gallium zinc oxide IGZO or indium tin zinc oxide ITZO.
  • At least one embodiment of the present disclosure further provides a method for preparing an array substrate.
  • the preparation method comprises:
  • first electrode and a second electrode for transmitting a display signal on the substrate, and a touch line for transmitting the touch signal, wherein the first electrode and the touch line are respectively formed in different layers and on the substrate
  • the orthographic projections at least partially overlap.
  • an orthographic projection of the touch line on the substrate may be located in an orthographic projection of the first electrode on the substrate, or an orthographic projection of the first electrode on the substrate may be located on the substrate Within the orthographic projection.
  • the second electrode and the touch line are disposed in the same layer and formed by one patterning process. In another embodiment, the second electrode and the first electrode are disposed in the same layer and are formed by one patterning process.
  • the method for preparing the array substrate includes:
  • a touch electrode is formed on the flat layer, and the touch electrode is connected to the touch line through the third via hole;
  • a light shielding layer is simultaneously formed.
  • a method of fabricating an array substrate includes:
  • the first electrode serves as a source electrode
  • the second electrode serves as a drain electrode
  • the source electrode and the data line are integrated.
  • At least one embodiment of the present disclosure further provides a touch display panel including the array substrate using the foregoing embodiments.
  • the touch display panel can be any product or component having a display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.

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Abstract

一种阵列基板，包括基底(10)、设置在所述基底(10)上的第一电极(17)和第二电极(18)以及触控线(19)，所述第一电极(17)和所述第二电极(18)均被配置为传输显示信号，所述触控线(19)配置为传输触控信号，其中，所述第一电极(17)和所述触控线(19)分别设置在不同层中，所述第一电极(17)在所述基底(10)上的正投影与所述触控线(19)在所述基底(10)上的正投影至少部分重叠。还提供了一种制备阵列基板的方法及触摸显示面板。

Description

阵列基板及其制备方法、触控显示面板
本申请要求于2017年12月15日递交的中国专利申请第201711352621.6号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种阵列基板及其制备方法、触控显示面板。
背景技术
随着显示技术的飞速发展，触摸面板(Touch Panel)已经逐渐遍及人们的生活中。触摸面板按照组成结构可以分为外挂式(Add on Mode)、覆盖表面式(On-Cell)、内嵌式(In-Cell)等。其中，内嵌式触摸面板是将触摸模组的触控电极内嵌在显示模组内部，将显示与触控合二为一，不仅大大减小了模组整体厚度，产品更轻薄，而且大大降低了制作成本。目前，内嵌式触控面板中，自电容式触控面板已逐渐成为主流的触控面板。
自电容式触摸面板是在薄膜晶体管(Thin Film Transistor，TFT)阵列基板上直接增加触控电极和触控线，采用分时驱动的工作方式，一帧有效时间被划分为显示时段(Display Time)和触控时段(Touch Time)，两个时段的驱动信号分开处理。在显示时段内，触控电极复用为公共电极，触控线复用为公共电极线，触控线向触控电极提供公共电压信号，不进行触控信号扫描，而在触控时段内，通过触控线进行触控信号扫描，两者分时独立工作。
虽然自电容式触摸面板具有结构简单、易于实现等优点，但也存在开口率较低的缺陷。近年来，高亮度显示逐渐成为触摸面板的主要发展趋势，而自电容式触摸面板较低的开口率，严重制约了触摸面板的亮度提升。
发明内容
本公开的至少一个实施例提供了一种阵列基板，包括基底和形成在所述基底上的配置为传输显示信号的第一电极和第二电极以及配置为传输触控信 号的触控线，所述第一电极和所述触控线分别设置在不同层中，所述第一电极在所述基底上的正投影与所述触控线在所述基底上的正投影至少部分重叠。
在本公开的一个实施例中，所述触控线在所述基底上的正投影位于所述第一电极在基底上的正投影之内，或者所述第一电极在基底上的正投影位于所述触控线在基底上的正投影之内。
在本公开的一个实施例中，所述第二电极和触控线同层设置。
在本公开的一个实施例中，所述触控线还用于传输公共电压信号。
在本公开的一个实施例中，还包括缓冲层、有源层、栅绝缘层、栅电极和层间绝缘层；所述第一电极设置在基底上，所述缓冲层覆盖所述第一电极，所述有源层设置在所述缓冲层上，通过所述缓冲层上开设的过孔与所述第一电极连接，所述栅绝缘层覆盖所述有源层，所述栅电极设置在所述栅绝缘层上，所述层间绝缘层覆盖所述栅电极，所述第二电极和触控线设置在所述层间绝缘层上，所述第二电极通过所述层间绝缘层上开设的过孔与所述有源层连接。
在本公开的一个实施例中，还包括遮光层，所述遮光层和第一电极同层设置。
在本公开的一个实施例中，还包括平坦层、触控电极、钝化层和像素电极；所述第二电极和触控线上覆盖所述平坦层，所述触控电极设置在所述平坦层上，通过所述平坦层上开设的过孔与所述触控线连接，所述钝化层覆盖所述触控电极，所述像素电极设置在所述钝化层上，通过贯穿所述钝化层和平坦层的过孔与所述第二电极连接；或者，所述第二电极和触控线上覆盖所述钝化层，所述像素电极设置在所述钝化层上，通过所述钝化层上开设的过孔与所述第二电极连接，所述平坦层覆盖所述像素电极，所述触控电极设置在所述平坦层上，通过贯穿所述平坦层和钝化层的过孔与所述触控线连接。
本公开的至少一个实施例还提供了一种触控显示面板，包括上述阵列基板。
本公开的至少一个实施例提供了一种阵列基板的制备方法，包括：
在基底上形成配置为传输显示信号的第一电极和第二电极以及配置为传输触控信号的触控线，所述第一电极和所述触控线分别在不同层中形成，且 所述第一电极在所述基底上的正投影与所述触控线在所述基底上的正投影至少部分重叠。
在本公开的一个实施例中，所述触控线在所述基底上的正投影位于所述第一电极在所述基底上的正投影之内，或者所述第一电极在所述基底上的正投影位于所述触控线在所述基底上的正投影之内。
在本公开的一个实施例中，所述第二电极和触控线同层设置。
在本公开的一个实施例中，所述触控线还配置为传输公共电压信号。
在本公开的一个实施例中，在所述基底上分别形成配置为传输显示信号的第一电极和第二电极，以及配置为传输触控信号的触控线，包括：
在所述基底上形成所述第一电极；
形成覆盖所述第一电极且具有第一过孔的缓冲层；
在所述缓冲层上形成有源层，所述有源层通过所述第一过孔与所述第一电极连接；
形成覆盖所述有源层的栅绝缘层，在所述栅绝缘层上形成栅电极；
形成覆盖所述栅电极且具有第二过孔的层间绝缘层；以及
在所述层间绝缘层上形成所述第二电极和触控线，所述第二电极通过所述第二过孔与所述有源层连接。
在本公开的一个实施例中，在基底上形成所述第一电极的同时还形成有遮光层。
在本公开的一个实施例中，在所述缓冲层上形成所述有源层包括：在所述缓冲层上形成低温多晶硅有源层。
在本公开的一个实施例中，还包括：
形成覆盖所述第二电极和所述触控线且具有第三过孔的平坦层，在所述平坦层上形成触控电极，所述触控电极通过所述第三过孔与所述触控线连接，形成覆盖所述触控电极的钝化层，并形成贯穿所述钝化层和平坦层的第四过孔，在所述钝化层上形成像素电极，所述像素电极通过第四过孔与所述第二电极连接；或者，
形成覆盖所述第二电极和触控线且具有第四过孔的钝化层，在所述钝化层上形成像素电极，所述像素电极通过所述第四过孔与所述第二电极连接，形成覆盖所述像素电极的平坦层，并形成贯穿所述平坦层和钝化层的第三电 极，在所述平坦层上形成触控电极，所述触控电极通过所述第三过孔与触控线连接。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为发明人已知的一种自电容式触摸阵列基板的结构示意图；
图2为根据本公开的一个实施例的阵列基板的结构示意图；
图3为根据本公开的一个实施例的形成第一电极和遮光层图案后的结构示意图；
图4为图3中A-A向剖视图；
图5为根据本公开的一个实施例形成带有第一过孔的缓冲层图案后的结构示意图；
图6为图5中A-A向剖视图；
图7为根据本公开的一个实施例的形成LTPS有源层图案后的结构示意图；
图8为图7中A-A向剖视图；
图9为根据本公开的一个实施例形成栅绝缘层和栅电极图案后的结构示意图；
图10为图9中A-A向剖视图；
图11为根据本公开的一个实施例形成带有第二过孔的层间绝缘层图案后的结构示意图；
图12为图11中A-A向剖视图；
图13为根据本公开的一个实施例形成第二电极和触控线图案后的结构示意图；
图14为图13中A-A向剖视图；
图15为根据本公开的一个实施例的形成带有第三过孔的平坦层图案后的结构示意图；
图16为图15中A-A向剖视图；
图17为根据本公开的一个实施例的形成触控电极图案后的结构示意图；
图18为图17中A-A向剖视图；
图19为根据本公开的一个实施例形成带有第四过孔的钝化层图案后的结构示意图；
图20为图19中A-A向剖视图；
图21为根据本公开的一个实施例形成像素电极图案后的结构示意图；
图22为图21中A-A向剖视图；以及
图23为根据本公开的另一个实施例的阵列基板的结构示意图。
附图标记说明:
10—基底；             11—遮光层；           12—缓冲层；
13—LTPS有源层；       14—栅绝缘层；         15—栅电极；
16—层间绝缘层；       17—第一电极；         18—第二电极；
19—触控线；           20—平坦层；           21—触控电极；
22—钝化层；           23—像素电极。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
在本发明实施例的描述中，需要理解的是，术语“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。
在本发明实施例的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本发明中的具体含义。
图1为发明人已知的一种自电容式触摸阵列基板的结构示意图，阵列基板为低温多晶硅(Low Temperature Poly-Silicon，LTPS)薄膜晶体管结构。如图1所示，该阵列基板包括基底10，设置在基底上的遮光层11，覆盖遮光层11的缓冲层12，设置在缓冲层12上的LTPS有源层13，覆盖LTPS有源层13的栅绝缘层14，设置在栅绝缘层14上的栅电极15，覆盖栅电极15的层间绝缘层16，设置在层间绝缘层16上的第一电极17、第二电极18和触控线19，第一电极17和第二电极18分别为源电极和漏电极，第一电极17和第二电极18分别通过栅绝缘层14和层间绝缘层16上开设的过孔与LTPS有源层13连接，覆盖第一电极17、第二电极18和触控线19的平坦层20，设置在平坦层20上的触控电极21，触控电极21通过平坦层20上开设的过孔与触控线19连接，覆盖触控电极21的钝化层22，设置在钝化层22上的像素电极23，像素电极23通过钝化层22和平坦层20上开设的过孔与第二电极18连接。其中，触控线(Touch Pattern Metal，TPM)与触控电极通过平坦层过孔连接，实现对公共电压及触控扫描的分时驱动。
本公开的发明人发现，如图1所示结构开口率较低的原因，是该结构采用并行的双源(Dual Source)结构，源电极、漏电极和触控线同层且平行设置。由于触控线与源电极和漏电极并行设置在显示区域，使不透光的布线面积较大，减小了透光区域，因此导致开口率较低，开口率仅为50％左右，严重制约了亮度提升。
本公开的实施例提供了一种阵列基板及其制备方法、触控显示面板，以克服现有结构开口率较低的缺陷。在本公开中，将触控线与源电极设置在不同层并使其重叠，即触控线在基底上的正投影与源电极在基底上的正投影存在重叠，以减少触控线对光线的遮挡，增加透光区域。
图2为根据本公开的一个实施例的阵列基板的结构示意图。根据本公开的实施例的阵列基板包括配置为传输显示信号的第一电极和第二电极，以及配置为传输触控信号的触控线，其中，所述第一电极和所述触控线分别设置在不同层中，且所述第一电极在所述基底上的正投影与所述触控线在所述基底上的正投影至少部分重叠。如图2所示，作为源电极的第一电极17设置在基底10上并与所述基底接触，而触控线19设置在第一电极17之上的其它层中，与第一电极17不同层设置，所述触控线19在所述基底10上的正投影与 所述第一电极17在所述基底10上的正投影至少部分重叠。
在一个实施例中，作为漏电极的第二电极18与触控线19同层设置，所述第二电极18和所述触控线19可以通过一次构图工艺形成，阵列基板还包括缓冲层12、有源层13、栅绝缘层14、栅电极15和层间绝缘层16，有源层13所在层位于第一电极17所在层与第二电极18所在层之间，并分别与第一电极17和第二电极18连接。
在一个实施例中，所述触控线19在所述基底上的正投影可以位于所述第一电极17在所述基底上的正投影之内，即，所述第一电极17在所述基底上的正投影的宽度大于所述触控线19在所述基底10上的正投影的宽度，所述触控线19在所述基底10上的正投影位于所述第一电极17在所述基底10上的正投影内。在另一个实施例中，所述第一电极17在所述基底10上的正投影可以位于所述触控线19在所述基底10上的正投影之内，即所述触控线19在所述基底10上的正投影的宽度大于所述第一电极17在所述基底10上的正投影的宽度，所述第一电极17在所述基底10上的正投影可以位于所述触控线19在所述基底10上的正投影内。
本公开的至少一个实施例提供了一种阵列基板，通过将第一电极和触控线分设在不同层中且使所述第一电极在所述基底上的正投影与所述触控线在所述基底上的正投影至少部分重叠，减小了不透光的布线面积，增加了透光区域，最大限度地提高了开口率，进而提升了亮度。
下面通过具体实施例详细说明本公开的技术方案。
以下以双栅结构的LTPS薄膜晶体管阵列基板为例来说明本公开的技术方案。图3～22为根据本公开的一个实施例制备阵列基板的结构示意图。其中，本实施例中所说的“构图工艺”包括沉积膜层、涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，是成熟的制备工艺。沉积可采用溅射、蒸镀、化学气相沉积等成熟工艺，涂覆可采用成熟的涂覆工艺，刻蚀可采用成熟的方法，在此不做具体的限定。
(1)在基底上形成第一电极和遮光层图案。形成遮光层和第一电极图案包括：在基底10上沉积第一金属薄膜，在第一金属薄膜上涂覆一层光刻胶，采用单色调掩膜版对光刻胶进行曝光并显影，在第一电极和遮光层图案位置形成未曝光区域，保留有光刻胶，在其它位置形成完全曝光区域，光刻胶被 去除，对完全曝光区域的第一金属薄膜进行刻蚀并剥离剩余的光刻胶，形成遮光层11和第一电极17图案，如图3和图4所示，其中，第一电极17为源电极。通过上述工艺，通过一次构图工艺形成遮光层和第一电极的图案，遮光层由与第一电极的材料相同的金属材料制成。基底可以采用玻璃基底或石英基底，第一金属薄膜可以采用铂Pt、钌Ru、金Au、银Ag、钼Mo、铬Cr、铝Al、钽Ta、钛Ti、钨W等金属中的一种或多种，或复合层结构，如Ti/Al/Ti或Mo/Al/Mo。
(2)在形成有遮光层和第一电极图案的基底上，形成带有第一过孔的缓冲图案层。形成带有第一过孔的缓冲层图案包括：在形成有遮光层11和第一电极17图案的基底上，沉积一缓冲层薄膜，在缓冲层薄膜上涂覆一层光刻胶，采用单色调掩膜版对光刻胶进行曝光并显影，在第一过孔位置形成完全曝光区域，光刻胶被去除，在其它位置形成未曝光区域，保留有光刻胶，对完全曝光区域的缓冲层薄膜进行刻蚀并剥离剩余的光刻胶，形成带有第一过孔a的缓冲层12图案，第一过孔a位于第一电极17所在位置，过孔内的缓冲层薄膜被去除，暴露出第一电极17的表面，如图5和图6所示。其中，缓冲层可以采用氮化硅SiNx、氧化硅SiOx或氮氧化硅Si(ON)x，可以为单层、双层或者多层结构，缓冲层可以防止基底中的金属离子扩散至有源层，防止对阈值电压和漏电流等特性产生影响，合适的缓冲层可以改善多晶硅层背面(即多晶硅层面向基底的一面)界面的质量，防止在多晶硅层背面界面出产生漏电流，进一步还可以降低热传导，减缓被激光加热的硅的冷却速率。
(3)在形成有前述图案的基底上，形成LTPS有源层图案。形成LTPS有源层图案包括：在形成有前述图案的基底上，沉积非晶硅薄膜，采用激光对非晶硅薄膜进行处理，使非晶硅薄膜结晶成多晶硅薄膜，随后在多晶硅薄膜上涂覆一层光刻胶，采用单色调掩膜版对光刻胶进行曝光并显影，在LTPS有源层图案位置形成未曝光区域，保留有光刻胶，在其它位置形成完全曝光区域，光刻胶被去除，对完全曝光区域的多晶硅薄膜进行刻蚀并剥离剩余的光刻胶，形成LTPS有源层13图案，如图7和图8所示。本实施例中，LTPS有源层13为U形状，第一端设置在第一电极17上，并通过缓冲层上的第一过孔a与第一电极17连接，第二端跨设在遮光层11之上。
(4)在形成有前述图案的基底上，形成栅绝缘层和栅电极图案。形成栅 绝缘层和栅电极图案包括：在形成有前述图案的基底上，依次沉积栅绝缘薄膜和第二金属薄膜，通过构图工艺对第二金属薄膜进行构图，形成栅绝缘层14和栅电极15图案，栅绝缘层14覆盖LTPS有源层13，栅电极15设置在栅绝缘层14上，如图9和图10所示。由于本实施例LTPS有源层为U形状，因此LTPS有源层与栅线形成双栅结构。其中，栅绝缘薄膜可以采用氮化硅SiNx、氧化硅SiOx或氮氧化硅Si(ON)x，可以为单层、双层或者多层结构，第二金属薄膜可以采用铂Pt、钌Ru、金Au、银Ag、钼Mo、铬Cr、铝Al、钽Ta、钛Ti、钨W等金属中的一种或多种，或复合层结构，如Ti/Al/Ti或Mo/Al/Mo。
(5)在形成有前述图案的基底上，形成带有第二过孔的层间绝缘层图案。形成带有第二过孔的层间绝缘层图案包括：在形成有前述图案的基底上，沉积一层间绝缘薄膜，通过构图工艺对层间绝缘薄膜进行构图，形成带有第二过孔b的层间绝缘层16图案，第二过孔b位于U形LTPS有源层13的第二端，孔内的层间绝缘层16和栅绝缘层14被刻蚀掉，暴露出LTPS有源层13的表面，如图11和图12所示。层间绝缘薄膜可以采用氮化硅SiNx、氧化硅SiOx或SiNx/SiOx的复合薄膜。
(6)在形成有前述图案的基底上，形成第二电极和触控线图案。形成漏电极和触控线图案包括：在形成有前述图案的基底上，沉积一第三金属薄膜，通过构图工艺对第三金属薄膜进行构图，形成第二电极18和触控线19图案，第二电极18通过层间绝缘层16上的第二过孔b与LTPS有源层13的第二端连接，触控线19位于第一电极17之上，触控线19在基底上的正投影位于第一电极17在基底上的正投影之内，如图13和图14所示。第二电极18为漏电极。第三金属薄膜可以采用铂Pt、钌Ru、金Au、银Ag、钼Mo、铬Cr、铝Al、钽Ta、钛Ti、钨W等金属中的一种或多种，或复合层结构，如Ti/Al/Ti或Mo/Al/Mo。
(7)在形成有前述图案的基底上，形成带有第三过孔的平坦层图案。形成带有第三过孔的平坦层图案包括：在形成有前述图案的基底上，沉积一平坦薄膜，采用掩膜版对平坦薄膜进行曝光并显影，形成带有第三过孔c的平坦层20图案，第三过孔c位于触控线19所在位置，孔内的平坦薄膜被去掉，暴露出触控线19的表面，如图15和图16所示。平坦薄膜可以采用有机材料， 如亚克力等。
(8)在形成有前述图案的基底上，形成触控电极图案。形成触控电极图案包括：在形成有前述图案的基底上，沉积一第一透明薄膜，通过构图工艺对第一透明薄膜进行构图，形成触控电极21图案，触控电极21通过平坦层20上开设的第三过孔c与触控线19连接，如图17和图18所示。第一透明薄膜可以采用氧化铟锡ITO或氧化铟锌IZO。
(9)在形成有前述图案的基底上，形成带有第四过孔的钝化层图案。形成带有第四过孔的钝化层图案包括：在形成有前述图案的基底上，沉积一钝化薄膜，通过构图工艺对钝化薄膜进行构图，形成带有第四过孔d的钝化层22图案，第四过孔d位于第二电极18所在位置，孔内的钝化层22和平坦层20被刻蚀掉，暴露出第二电极18的表面，如图19和图20所示。钝化薄膜可以采用氮化硅SiNx、氧化硅SiOx或SiNx/SiOx的复合薄膜。
(10)在形成有前述图案的基底上，形成像素电极图案。形成像素电极图案包括：在形成有前述图案的基底上，沉积一第二透明薄膜，通过构图工艺对第二透明薄膜进行构图，形成像素电极23图案，像素电极23通过钝化层22上开设的第四过孔d与第二电极18连接，如图21和图22所示。第二透明薄膜可以采用氧化铟锡ITO或氧化铟锌IZO。
通过图3～图22所示的制备阵列基板过程可以看出，与源电极和触控线并行设置的结构相比，本实施例通过将源电极和触控线分设在不同层中，且第一电极和触控线在基底上的投影存在重叠，减小或取消了触控线在显示区域的遮挡，减小了不透光的布线面积，增加了透光区域，最大限度地提高了开口率，进而提升了亮度。同时，本公开实施例利用源电极作为遮光结构，减少了遮光层的面积，不仅进一步增加了透光区域，而且有效避免了制备中对位精度等因素造成的显示不良，提高了良品率。
本实施例中，第一电极和触控线在基底上的正投影存在重叠是指，第一电极设置在一结构层中，而触控线设置在另一结构层中，触控线在基底上的正投影与第一电极在基底上的正投影有重合。触控线在基底上的正投影位于第一电极在基底上的正投影之内是指，触控线在基底上正投影的宽度等于或小于第一电极在基底上正投影的宽度，触控线在基底上的正投影的轮廓被第一电极在基底上的正投影的轮廓包围。第一电极在基底上的正投影位于触控 线在基底上的正投影之内是指，第一电极在基底上正投影的宽度等于或小于触控线在基底上正投影的宽度，第一电极在基底上的正投影的轮廓被触控线在基底上的正投影的轮廓包围。实际实施时，触控线的宽度、形状以及触控线与触控电极连接的过孔位置等可以根据实际需要进行设计，触控线还可以配置为传输触控信号和公共电压信号，本公开不做限定。
基于前述阵列基板制备过程，如图21和图22所示，本实施例阵列基板包括：
基底10，
遮光层11和第一电极17，设置在基底10上；
缓冲层12，覆盖遮光层11和第一电极17，其上开设有用于使第一电极17与LTPS有源层13连接的第一过孔；
U形的LTPS有源层13，设置在缓冲层12上，其第一端通过第一过孔与第一电极17连接；
栅绝缘层14，覆盖LTPS有源层13；
栅电极15，设置在栅绝缘层14上；
层间绝缘层16，覆盖栅电极15，其上开设有用于使第二电极18与LTPS有源层13连接的第二过孔，第二过孔贯穿层间绝缘层16和栅绝缘层14；
第二电极18和触控线19，设置在层间绝缘层16上，第二电极18通过第二过孔与LTPS有源层13的第二端连接；
平坦层20，覆盖第二电极18和触控线19，其上开设有用于使触控线19与触控电极21连接的第三过孔；
触控电极21，设置在平坦层20上，通过第三过孔与触控线19连接；
钝化层22，覆盖触控电极21，其上开设有用于使第二电极18与像素电极23连接的第四过孔，第四过孔贯穿钝化层22和平坦层20；
像素电极23，设置在钝化层22上，通过第四过孔与第二电极18连接。
本实施例中，第一电极作为源电极，第二电极作为漏电极，源电极与数据线为一体结构，栅电极与栅线为一体结构。
遮光层11和第一电极17设置在基底10上，指的是遮光层11和第一电极17可以直接设置在基底10上并与基底10接触，也可以是遮光层11和第一电极17设置在基底10上，但不与基底10直接接触，其间设置有其他的结 构。
图23为根据本公开另一个实施例的阵列基板的结构示意图。该实施例是前述实施例的变形，其中，将触控电极设置在像素电极的上方。如图23所示，本实施例阵列基板包括：基底10、遮光层11、第一电极17、缓冲层12、U形的LTPS有源层13、栅绝缘层14、栅电极15、层间绝缘层16、第二电极18和触控线19的结构与前述实施例相同，所不同的是，钝化层22覆盖第二电极18和触控线19，其上开设有用于使第二电极18与像素电极23连接的第四过孔，像素电极23设置在钝化层22上，通过第四过孔与第二电极18连接，平坦层20覆盖像素电极23，其上开设有用于触控线19与触控电极21连接的第三过孔，触控电极21设置在平坦层20上，通过第三过孔与触控线19连接。
与前述实施例相同，本实施例中通过将第一电极和触控线分设在不同层中，且触控线在基底上的正投影位于源电极在基底上的正投影之内，提高了开口率。
虽然前述实施例是基于双栅结构的LTPS薄膜晶体管阵列基板，但基于相同的技术构思，本公开的实施例也可以采用单栅结构的LTPS薄膜晶体管阵列基板。例如，可以将前述实施例中的U形LTPS有源层修改为L形，L形有源层的竖直端设置在源电极(数据线)上，与栅电极(栅线)形成交叉，而水平端平行于栅线，与栅线无交叉，形成单栅结构的LTPS薄膜晶体管阵列基板。源电极可以起到遮挡作用，因此可以不设置遮光层。
此外，本公开实施例中也可以采用其它结构的阵列基板。例如，LTPS有源层可以替换为金属氧化物材料，形成Oxide薄膜晶体管阵列基板。金属氧化物材料可以是铟镓锌氧化物IGZO或铟锡锌氧化物ITZO。
在上述实施例的技术方案基础上，本公开的至少一个实施例还提供了一种阵列基板的制备方法。所述制备方法包括：
在基底上分别形成用于传输显示信号的第一电极和第二电极，以及用于传输触控信号的触控线，所述第一电极和触控线分别在不同层中形成且在基底上的正投影至少部分重叠。
例如，所述触控线在基底上的正投影可以位于所述第一电极在基底上的正投影内，或者所述第一电极在基底上的正投影可以位于所述触控线在基底 上的正投影之内。
在一个实施例中，所述第二电极和触控线同层设置且通过一次构图工艺形成。在另一个实施例中，所述第二电极和第一电极同层设置且通过一次构图工艺形成。
在一个实施例中，阵列基板的制备方法包括：
S11、在基底上形成第一电极；
S12、形成覆盖所述第一电极且具有第一过孔的缓冲层，所述第一过孔用于使第一电极与LTPS有源层连接；
S13、在所述缓冲层上形成LTPS有源层，所述LTPS有源层通过所述第一过孔与所述第一电极连接；
S14、形成覆盖所述LTPS有源层的栅绝缘层，在所述栅绝缘层上形成栅电极；
S15、形成覆盖所述栅电极且具有第二过孔的层间绝缘层，所述第二过孔用于使所述LTPS有源层与所述第二电极连接；
S16、在所述层间绝缘层上形成第二电极和触控线，所述第二电极通过所述第二过孔与所述LTPS有源层连接；
S17、形成覆盖所述第二电极和触控线且具有第三过孔的平坦层，所述第三过孔用于使触控线与触控电极连接；
S18、在所述平坦层上形成触控电极，所述触控电极通过所述第三过孔与所述触控线连接；
S19、形成覆盖所述触控电极的钝化层，并形成贯穿所述钝化层和平坦层的第四过孔；
S110、在所述钝化层上形成像素电极，所述像素电极通过所述第四过孔与所述第二电极连接。
其中，形成所述第一电极时，还同时形成有遮光层。
在另一个实施例中，阵列基板的制备方法包括：
S21～S26、同前述S11～S16；
S27、形成覆盖所述第二电极和触控线且具有第四过孔的钝化层，所述第四过孔用于使第二电极与像素电极连接；
S28、在所述钝化层上形成像素电极，所述像素电极通过所述第四过孔 与所述第二电极连接；
S29、形成覆盖所述像素电极的平坦层，并形成贯穿所述平坦层和钝化层的第三过孔；
S210、在所述平坦层上形成触控电极，所述触控电极通过所述第三过孔与所述触控线连接。
在本实施例中，第一电极作为源电极，第二电极作为漏电极，源电极与数据线为一体结构。
基于本公开的发明构思，本公开的至少一个实施例还提供了一种触控显示面板，该触控显示面板包括采用前述实施例的阵列基板。触控显示面板可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (15)

  1. 一种阵列基板，包括基底、设置在所述基底上的第一电极和第二电极以及触控线，所述第一电极和所述第二电极均被配置为传输显示信号，所述触控线配置为传输触控信号，其中，所述第一电极和所述触控线分别设置在不同层中，所述第一电极在所述基底上的正投影与所述触控线在所述基底上的正投影至少部分重叠。
  2. 根据权利要求1所述的阵列基板，其中，所述触控线在所述基底上的正投影位于所述第一电极在所述基底上的正投影内，或者所述第一电极在所述基底上的正投影位于所述触控线在所述基底上的正投影内。
  3. 根据权利要求1或2所述的阵列基板，其中，所述第二电极和触控线同层设置。
  4. 根据权利要求1至3中任何一项所述的阵列基板，其中，所述触控线还配置为传输公共电压信号。
  5. 根据权利要求1至4中任何一项所述的阵列基板，其还包括缓冲层、有源层、栅绝缘层、栅电极和层间绝缘层；
    所述缓冲层覆盖所述第一电极，所述有源层设置在所述缓冲层上，通过所述缓冲层上开设的过孔与所述第一电极连接，所述栅绝缘层覆盖所述有源层，所述栅电极设置在所述栅绝缘层上，所述层间绝缘层覆盖所述栅电极，所述第二电极和触控线设置在所述层间绝缘层上，且所述第二电极通过所述层间绝缘层上开设的过孔与所述有源层连接。
  6. 根据权利要求1至5中任何一项所述的阵列基板，其还包括遮光层，所述遮光层和所述第一电极同层设置。
  7. 根据权利要求1至6中任何一项所述的阵列基板，其还包括平坦层、 触控电极、钝化层和像素电极；
    所述第二电极和触控线上覆盖所述平坦层，所述触控电极设置在所述平坦层上，通过所述平坦层上开设的过孔与所述触控线连接，所述钝化层覆盖所述触控电极，所述像素电极设置在所述钝化层上，并通过贯穿所述钝化层和平坦层的过孔与所述第二电极连接；
    或者，
    所述第二电极和触控线上覆盖所述钝化层，所述像素电极设置在所述钝化层上，通过所述钝化层上开设的过孔与所述第二电极连接，所述平坦层覆盖所述像素电极，所述触控电极设置在所述平坦层上，并通过贯穿所述平坦层和钝化层过孔与所述触控线连接。
  8. 一种触控显示面板，其包括如权利要求1至7中任何一项所述的阵列基板。
  9. 一种阵列基板的制备方法，其包括：
    在基底上形成配置为传输显示信号的第一电极和第二电极以及配置为传输触控信号的触控线，所述第一电极和所述触控线分别形成在不同层中，所述第一电极在所述基底上的正投影与所述触控线在所述基底上的正投影至少部分重叠。
  10. 根据权利要求9所述的制备方法，其中，所述触控线在基底上的正投影位于所述第一电极在基底上的正投影之内，或者所述第一电极在基底上的正投影位于所述触控线在基底上的正投影之内。
  11. 根据权利要求9或10所述的制备方法，其中，所述第二电极和触控线同层设置。
  12. 根据权利要求9所述的制备方法，其中，所述触控线还配置为传输公共电压信号。
  13. 根据权利要求9至12中任何一项所述的制备方法，其中，在所述基底上形成配置为传输显示信号的所述第一电极和所述第二电极以及配置为传输触控信号的所述触控线包括：
    在基底上形成所述第一电极；
    形成覆盖所述第一电极且具有第一过孔的缓冲层；
    在所述缓冲层上形成有源层，所述有源层通过所述第一过孔与所述第一电极连接；
    形成覆盖所述有源层的栅绝缘层，在所述栅绝缘层上形成栅电极；
    形成覆盖所述栅电极且具有第二过孔的层间绝缘层；
    在所述层间绝缘层上形成所述第二电极和触控线，所述第二电极通过所述第二过孔与所述有源层连接。
  14. 根据权利要求13所述的制备方法，其中，在基底上形成所述第一电极的同时形成有遮光层。
  15. 根据权利要求9～12所述的制备方法，其包括：
    形成覆盖所述第二电极和触控线且具有第三过孔的平坦层，
    在所述平坦层上形成触控电极，所述触控电极通过所述第三过孔与所述触控线连接，
    形成覆盖所述触控电极的钝化层，并形成贯穿所述钝化层和所述平坦层的第四过孔；
    在所述钝化层上形成像素电极，所述像素电极通过所述第四过孔与所述第二电极连接；或者，
    形成覆盖所述第二电极和触控线且具有第四过孔的钝化层，
    在所述钝化层上形成像素电极，所述像素电极通过所述第四过孔与第二电极连接，
    形成覆盖所述像素电极的平坦层，并形成贯穿所述平坦层和钝化层的第三过孔，
    在所述平坦层上形成触控电极，所述触控电极通过所述第三过孔与所述触控线连接。
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