WO2019007076A1 - 阵列基板及制备方法、液晶显示面板、显示装置 - Google Patents
阵列基板及制备方法、液晶显示面板、显示装置 Download PDFInfo
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- WO2019007076A1 WO2019007076A1 PCT/CN2018/076470 CN2018076470W WO2019007076A1 WO 2019007076 A1 WO2019007076 A1 WO 2019007076A1 CN 2018076470 W CN2018076470 W CN 2018076470W WO 2019007076 A1 WO2019007076 A1 WO 2019007076A1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
- G02F1/133553—Reflecting elements
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/133345—Insulating layers
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
- G02F1/133509—Filters, e.g. light shielding masks
- G02F1/133512—Light shielding layers, e.g. black matrix
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
- G02F1/133504—Diffusing, scattering, diffracting elements
- G02F1/133507—Films for enhancing the luminance
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
- G02F1/136295—Materials; Compositions; Manufacture processes
Definitions
- the present disclosure relates to the field of display technologies, and in particular, to an array substrate and a method for fabricating the same, a liquid crystal display panel, and a display device.
- TFT-LCD Thin Film Transistor Liquid Crystal Display
- the liquid crystal display generally includes a liquid crystal display panel and a backlight for providing a light source to the liquid crystal display panel.
- the liquid crystal display panel is divided into a display area and a non-display area, and the liquid crystal display panel comprises: an array substrate, an opposite substrate with the array substrate, and a counter substrate; a liquid crystal layer disposed between the array substrate and the opposite substrate; in order to prevent light leakage in the non-display area, a black matrix layer is generally formed in the non-display area of the opposite substrate, so that the light in the non-display area is not utilized, thereby causing Backlight light utilization and panel transmittance are low.
- Embodiments of the present disclosure provide an array substrate and a preparation method thereof, a liquid crystal display panel, and a display device.
- An array substrate provided by an embodiment of the present disclosure includes: a first substrate; a signal line disposed above a region of the first substrate corresponding to a non-display area of the array substrate; an insulating layer An insulating layer is disposed between the signal line and the first substrate, wherein a groove is disposed in the insulating layer, and the signal line is disposed on an inner wall of the groove, and an inner wall of the groove The direction is set such that at least a portion of the light incident on the signal line from a side of the first substrate that faces away from the signal line is reflected to a display area of the array substrate.
- the signal line is a scan line or a data line.
- the signal line includes a scan line and a data line, the scan line and the data line are arranged to cross over a region of the first substrate corresponding to a non-display area of the array substrate;
- the insulating layer includes: a first insulating layer disposed between the scan line and the first substrate, wherein the first insulating layer is provided with a first groove, and the scan line is disposed On an inner wall of the first groove, a direction of an inner wall of the first groove is disposed such that at least a portion of the light incident on the scan line from a side of the first substrate facing away from the scan line Reflecting to a display area of the array substrate; and a second insulating layer disposed between the data line and the first substrate, wherein the second insulating layer is provided with a second recess a groove, the data line is disposed on an inner wall of the second groove, and an inner wall of the second groove is disposed in a direction such that the light is incident from a side of the first substrate facing away from the data line
- the signal line fills the inner wall of the recess.
- the signal line covers a portion of the inner wall of the recess.
- the inner wall of the groove is two intersecting planes or curved surfaces.
- the groove has a cross section that is an isosceles triangle.
- the inner wall of the first groove or the second groove is a curved surface or two intersecting planes.
- the cross section of the first groove or the second groove is an isosceles triangle.
- the embodiment of the present disclosure further provides a liquid crystal display panel, comprising: an array substrate provided by any embodiment of the present disclosure; an opposite substrate to the array substrate; and an array substrate and the opposite substrate The liquid crystal layer between.
- the opposite substrate includes: a second substrate, a black matrix layer disposed on the second substrate and corresponding to the non-display area of the array substrate and facing one side of the array substrate;
- the cross section of the groove is an isosceles triangle, and the apex angle of the isosceles triangle is ⁇ 1 , and ⁇ 1 satisfies the following conditions:
- L 1min is the distance from the vertex of the apex angle of the isosceles triangle to the proximal end of the adjacent pixel unit
- L 1max is the vertex of a base angle of the isosceles triangle to the adjacent pixel on the same side as the vertex The distance from the distal end of the unit
- d 1min is the distance from the vertex of the base angle of the isosceles triangle to the black matrix layer
- d 1max is the distance from the vertex of the apex angle of the isosceles triangle to the black matrix layer.
- the opposite substrate includes: a second substrate, a black matrix layer disposed on the second substrate and corresponding to the non-display area of the array substrate and facing one side of the array substrate;
- the cross section of the groove is an isosceles triangle, and the apex angle ⁇ 1 of the isosceles triangle satisfies the following conditions:
- L' 1min is the distance from the vertex of a base angle of the isosceles triangle to the proximal end of the adjacent pixel unit on the same side of the vertex;
- L' 1max is the vertex of the apex angle of the isosceles triangle to the phase The distance from the distal end of the adjacent pixel unit;
- d 1min is the distance from the vertex of a base angle of the isosceles triangle to the black matrix layer;
- d 1max is the distance from the vertex of the apex angle of the isosceles triangle to the black matrix layer.
- the embodiment of the present disclosure further provides a display device including the liquid crystal display panel provided by any embodiment of the present disclosure.
- the embodiment of the present disclosure further provides a method for preparing an array substrate, including the following steps:
- the signal line is a scan line or a data line.
- the signal line includes a scan line and a data line
- the insulating layer includes a first insulating layer and a second insulating layer
- the preparation method includes the following steps:
- the insulating layer is formed on one side of the first substrate, and the recess is formed in a portion of the insulating layer corresponding to the non-display area of the array substrate, including:
- the negative photoresist is exposed and developed by a halftone mask to form an insulating layer, and a groove is formed in a portion of the insulating layer corresponding to the non-display region of the array substrate.
- the first insulating layer is formed on one side of the first substrate, and the first recess is formed in a portion of the first insulating layer corresponding to the non-display area of the array substrate, including:
- the second insulating layer is formed on one side of the first insulating layer, and the second recess is formed in a portion of the second insulating layer corresponding to the non-display area of the array substrate include:
- FIG. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure
- FIG. 2 is a perspective view of the array substrate provided by an embodiment of the present disclosure
- FIG. 3 is a top plan view of the array substrate according to an embodiment of the present disclosure.
- FIG. 4 is a schematic structural diagram of another array substrate according to an embodiment of the present disclosure.
- FIG. 5 is a perspective view of the other array substrate according to an embodiment of the present disclosure.
- FIG. 6 is a perspective view of still another array substrate according to an embodiment of the present disclosure.
- FIG. 7 is a schematic flow chart of a method for fabricating an array substrate according to an embodiment of the present disclosure.
- FIGS. 8(a) to 8(i) are schematic diagrams showing a process flow for preparing an array substrate according to an embodiment of the present disclosure
- FIGS. 9 and 10 are schematic structural diagrams of a liquid crystal display panel according to an embodiment of the present disclosure.
- FIG 11 and 12 are schematic structural diagrams of another liquid crystal display panel according to an embodiment of the present disclosure.
- cross-arrangement of scan lines and data lines refers to the intersection of scan lines and data lines on the substrate on which they are placed, especially perpendicular to each other, and does not mean that the scan lines and the data lines themselves intersect.
- a signal line eg, a scan line or a data line "overfills" the inner wall of the groove means that the inner wall of the groove is completely or substantially covered by the signal line such that the light incident on the signal line is completely Or basically reflected. In this case, the inside of the groove is not necessarily completely filled with the signal line.
- the inner wall of the groove may be two intersecting planes or curved surfaces.
- the inner wall of the groove may be substantially "V" shaped or "U” shaped.
- the curved surface may be a curved surface or other curved surface, such as a paraboloid.
- the arc or paraboloid here refers to a curved surface formed by a circular arc or a parabola.
- the two curved surfaces may form a single curved surface with no significant boundaries at the intersection.
- cross section of the groove refers to a section perpendicular to the direction in which the length of the groove extends.
- the distance from the vertex of the apex angle of the isosceles triangle to the "proximal end of the adjacent pixel unit" refers to the projection of the vertex and the proximal end of the adjacent pixel electrode in a plane parallel to the array substrate. the distance between.
- the distance from the vertex of a base angle of the isosceles triangle to the "distal end of the adjacent pixel unit" on the same side of the vertex means that the vertex is parallel to the distal end of the ipsilateral adjacent pixel electrode. The distance between projections in the plane of the array substrate.
- Embodiments of the present disclosure provide an array substrate and a preparation method thereof, a liquid crystal display panel, and a display device for at least partially improving backlight light utilization rate and panel transmittance.
- an array substrate provided by an embodiment of the present disclosure includes: a first substrate 11 , scan lines 12 and data arranged across the area of the first substrate 11 corresponding to the non-display area of the array substrate
- a first insulating layer 14 is disposed between the scan line 12 and the first substrate 11.
- the first insulating layer 14 is provided with a first recess 15 having an inner wall inclined, and the scan line 12 is disposed on the inner wall of the first recess 15. At least a part of the light incident on the scanning line 12 from the side of the first substrate 11 facing away from the scanning line 12 (shown by a line with an arrow in the figure) is reflected to the display area of the array substrate.
- the inner wall of the first groove 15 is inclined toward the middle, for example, substantially V-shaped or U-shaped.
- the scan line 12 can reflect at least part of the light incident from the side of the first substrate 11 facing away from the scan line 12 to the display area of the array substrate, the backlight light utilization rate and the panel transparency can be improved to some extent. Over rate.
- the scan line 12 may be disposed to fill the first concave surface.
- the scan line 12 may also partially cover the inner wall of the first recess 15.
- the inner wall of the first groove 15 may be two intersecting planes.
- the inner wall of the first groove 15 may be a curved surface.
- the inner wall of the first recess 15 may be such that the scanning line 12 disposed thereon can reflect at least part of the light incident thereon to the display area of the array substrate.
- the embodiment of the present disclosure It is not limited and can be set according to actual needs.
- the first groove 15 has an isosceles triangle in cross section.
- the cross section of the first groove 15 is not limited to an isosceles triangle, and may be, for example, other triangles, semicircles, semi-ellipses, parabolas, and the like.
- the array substrate further includes: a thin film transistor; the scan line 12 is disposed in the same layer as the gate of the thin film transistor.
- the array substrate further includes: a passivation layer 16 disposed on the thin film transistor, and a pixel electrode 17 disposed on the passivation layer 16; the pixel electrode 17 and the film
- the drains of the transistors are electrically connected, and the pixel electrodes 17 are located in the display area of the array substrate.
- the adjacent two scanning lines 12 and the adjacent two data lines 13 define one pixel unit, and the pixel electrode 17 is disposed in the pixel unit as shown in FIG.
- the embodiment of the present disclosure is described by taking the data line 13 on the scan line 12 as an example.
- the embodiment of the present disclosure is not limited thereto, and the data line 13 may also be located under the scan line 12, and the embodiment of the present disclosure.
- the structure of the thin film transistor in the above array substrate is not limited, and thin film transistors of various structures are suitable.
- the array substrate of the embodiment of the present disclosure shown in FIG. 4 and FIG. 5 is similar to the array substrate of the embodiment of the present disclosure shown in FIG. 1-3, and the same portions are not described herein again, and only the different portions will be described below.
- the arrangement of the scan lines 12 in the array substrate provided by the embodiment of the present disclosure may be disposed as needed, but a second insulating layer 18 is disposed between the data lines 13 and the first substrate 11, and the second insulating layer 18 is disposed.
- a second recess 19 having an inner wall inclined is provided, and the data line 13 is disposed on the inner wall of the second recess 19 such that at least a portion of the light incident on the data line 13 from the side of the first substrate 11 facing away from the data line 13 Reflected to the display area of the array substrate.
- the data line 13 can reflect at least a portion of the light incident thereon to the display area of the array substrate, the backlight light utilization rate and the panel transmittance can be improved to some extent.
- the data line 13 may be disposed to fill the second concave.
- the data line 13 may also partially cover the inner wall of the second recess 19.
- the inner wall of the second groove 19 can be two intersecting planes.
- the inner wall of the second groove 19 may be a curved surface.
- the inner wall of the second recess 19 may be such that the data line 13 disposed thereon can reflect at least a portion of the light incident thereon to the display area of the array substrate.
- the embodiment of the present disclosure It is not limited and can be set according to actual needs.
- the second groove 19 has an isosceles triangle in cross section.
- the cross section of the second groove 19 is not limited to an isosceles triangle, and may be, for example, other triangles, semicircles, semi-ellipses, parabolas, and the like.
- the data line 13 is disposed in the same layer as the source and drain of the thin film transistor.
- the array substrate of the embodiment of the present disclosure shown in FIG. 6 is similar to the array substrate of the embodiment of the present disclosure shown in FIG. 4 and FIG. 5, and the same portions are not described herein again. Only the different portions will be described below.
- the data line 13 in the array substrate provided by the embodiment of the present disclosure adopts the structure of the data line 13 in the array substrate provided by the embodiment of the present disclosure shown in FIG. 4 and FIG. 5 and is disposed on the inner wall of the second groove 19 .
- the scan line 12 adopts the structure of the scan line 12 in the array substrate provided by the embodiment of the present disclosure shown in FIG. 1-2, wherein the scan line 12 is disposed on the inner wall of the first recess.
- an embodiment of the present disclosure further provides a method for preparing an array substrate, including the following steps:
- the method for preparing the array substrate includes steps S101 and S102. If the array substrate shown in FIG. 4 and FIG. 5 is fabricated, the method for preparing the array substrate includes the steps. S103 and S104; If an array substrate as shown in FIG. 6 is fabricated, the method for preparing the array substrate includes steps S101, S102, S103, and S104.
- steps S101 and S102 and the steps S103 and S104 are related to the structure of the fabricated array substrate. If the data lines are located above the scan lines, steps S103 and S104 are performed after steps S101 and S102. The line is below the scan line, and steps S103 and S104 are before steps S101 and S102.
- a first insulating layer is formed on one side of the first substrate in step S101, and a first concave in which the inner wall is inclined is formed in a portion of the first insulating layer corresponding to the non-display area of the array substrate.
- the steps of the slot may include:
- the light transmittance of the shielding portion of the halftone mask can be set to gradually decrease from the both sides to the middle, and the shape of the first groove can be controlled by controlling the light transmittance of the shielding portion of the halftone mask.
- a second insulating layer is formed on one side of the first insulating layer in step S103, and an inner wall is inclined in a portion of the second insulating layer corresponding to the non-display area of the array substrate.
- the step of the second groove may include:
- the negative photoresist is exposed and developed by a halftone mask (if necessary, etching or the like may also be selected) to form a second insulating layer, and corresponding to the second insulating layer A second groove in which the inner wall is inclined is formed in a portion of the non-display area of the array substrate.
- the light transmittance of the shielding portion of the halftone mask can be set to gradually decrease from the both sides to the middle, and the shape of the second groove can be controlled by controlling the light transmittance of the shielding portion of the halftone mask.
- Step 1 refer to FIG. 8 (a), the first negative photoresist 82 is coated on the first substrate 81;
- Step 2 referring to Figures 8(b) and 8(c), the first negative photoresist 82 is exposed and developed by the first halftone mask 83 to form the first insulating layer 84, and at the first a first groove 85 of the insulating layer 84 corresponding to the non-display area of the array substrate, wherein the inner wall is inclined and the cross section is an isosceles triangle;
- Step 3 referring to FIG. 8(d), a scan line 86 is formed on the inner wall of the first recess 85, and the scan line is incident on the scan line 86 from the side of the first substrate 81 facing away from the scan line 86. At least part of the light is reflected to the display area of the array substrate;
- Step 4 on the first substrate 81 formed with the scan line 86 is coated with a second negative photoresist 87;
- Step 5 referring to Figures 8(f) and 8(g), the second negative photoresist 87 is exposed and developed by the second halftone mask 88 to form a second insulating layer 89, and in the second a second groove 90 of the insulating layer 89 corresponding to the non-display area of the array substrate, wherein the inner wall is inclined and the cross section is an isosceles triangle;
- Step 6 referring to FIG. 8(h), a data line 91 is formed on the inner wall of the second recess 90, and the data line is incident on the data line 91 from the side of the first substrate 81 facing away from the data line 91. At least part of the light is reflected to the display area of the array substrate;
- the scan line 86 and the data line 91 are arranged in a cross arrangement.
- Step 7 a passivation layer 92 and a pixel electrode 93 are sequentially formed on the first substrate 81 on which the data lines 91 are formed.
- the step of preparing the thin film transistor is further included, and the preparation step of the thin film transistor can be selected according to requirements, and details are not described herein again, and the thin film transistor can be prepared while preparing the scan line 86.
- the gate electrode prepares the source and drain of the thin film transistor while preparing the data line 91.
- the first insulating layer and the second insulating layer are formed by the negative photoresist itself, or the materials are the same.
- the method of forming the first or second insulating layer and forming the first or second recess thereon is not limited to the above steps, for example, by first forming a layer of insulating material on one side of the first substrate, A photoresist is coated on the insulating material layer, and the first groove or the second groove is formed as needed at a desired position of the insulating layer material by a process such as exposure, development, and etching.
- the insulating material layer and the photoresist are made of different materials.
- an embodiment of the present disclosure further provides a liquid crystal display panel, including: the array substrate 21 provided by any embodiment of the present disclosure, the opposite substrate 22 opposite to the array substrate 21 , and The liquid crystal layer 23 is disposed between the array substrate 21 and the opposite substrate 22.
- the liquid crystal display panel may be any mode liquid crystal display panel, for example, a twisted nematic (TN) mode liquid crystal display panel, an In Plane Switching (IPS) mode liquid crystal display panel, and an advanced superdimensional field switch (Advanced). Super Dimension Switch, ADS) mode LCD panel, etc.
- TN twisted nematic
- IPS In Plane Switching
- Advanced Advanced superdimensional field switch
- ADS Advanced superdimensional field switch
- the opposite substrate 22 includes: a second substrate 221, a non-display area disposed on the second substrate 221 and corresponding to the array substrate, and facing the array substrate 21 The black matrix layer 222 on.
- the first groove 211 of the array substrate 21 has an isosceles triangle cross section, and the apex angle of the isosceles triangle is ⁇ 1 , and ⁇ 1 satisfies the following conditions:
- L 1min is the distance from the vertex of the apex angle of the isosceles triangle to the proximal end of the adjacent pixel unit
- L 1max is the vertex of a base angle of the isosceles triangle to the adjacent pixel on the same side as the vertex The distance from the distal end of the unit
- d 1min is the distance from the vertex of a base angle of the isosceles triangle to the black matrix layer 222
- d 1max is the distance from the vertex of the apex angle of the isosceles triangle to the black matrix layer 222.
- ⁇ 1 in order to reflect as much light incident on the scanning line as possible to the display area of the array substrate, ⁇ 1 may be set to satisfy the following conditions:
- L' 1min is the distance from the vertex of a base angle of the isosceles triangle to the proximal end of the adjacent pixel unit on the same side of the vertex;
- L' 1max is the vertex of the apex angle of the isosceles triangle to the phase The distance from the far end of the adjacent pixel unit.
- the cross section of the second groove 212 of the array substrate 21 is an isosceles triangle, and the apex angle of the isosceles triangle is ⁇ 2 , and ⁇ 2 satisfies the following conditions:
- L 2min is the distance from the vertex of the apex angle of the isosceles triangle to the proximal end of the adjacent pixel unit
- L 2max is the vertex of a base angle of the isosceles triangle to the adjacent pixel on the same side as the vertex The distance from the distal end of the unit
- d 2min is the distance from the vertex of a base angle of the isosceles triangle to the black matrix layer 222
- d 2max is the distance from the vertex of the apex angle of the isosceles triangle to the black matrix layer 222.
- ⁇ 2 in order to reflect as much light incident on the data line as possible to the display area of the array substrate, ⁇ 2 may be set to satisfy the following conditions:
- L' 2min is the distance from the vertex of a base angle of the isosceles triangle to the proximal end of the adjacent pixel unit on the same side of the vertex;
- L' 2max is the vertex of the apex angle of the isosceles triangle to the phase The distance from the far end of the adjacent pixel unit.
- an embodiment of the present disclosure further provides a display device, including the liquid crystal display panel provided by any embodiment of the present disclosure.
- the display device can be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
- the array substrate includes: a first substrate; a signal line, where the signal line is above the area of the first substrate corresponding to the non-display area of the array substrate Arranging; an insulating layer disposed between the signal line and the first substrate, wherein the insulating layer is provided with a groove, and the signal line is disposed on an inner wall of the groove, The direction of the inner wall of the groove is set such that at least a portion of the light incident on the signal line from a side of the first substrate facing away from the signal line is reflected to a display area of the array substrate. Since the signal line can reflect at least a portion of the light incident thereon to the display area of the array substrate, the backlight light utilization rate and the panel transmittance can be improved to some extent.
- the signal line fills the inner wall of the recess. In this way, on the one hand, the light incident on the signal line can be reflected as much as possible to the display area of the array substrate, thereby improving the backlight light utilization rate and the panel transmittance as much as possible, and on the other hand, can be increased to some extent.
- the effective line width of the signal line thereby reducing the line resistance of the signal line.
- a liquid crystal display panel includes the above array substrate, and the array substrate includes: a first substrate; a signal line, wherein the signal line corresponds to the array substrate on the first substrate Arranging above the region of the non-display area; an insulating layer disposed between the signal line and the first substrate, wherein the insulating layer is provided with a groove, and the signal line is disposed at the The inner wall of the groove is disposed such that an inner wall of the groove is disposed such that at least a portion of light incident on the signal line from a side of the first substrate facing away from the signal line is reflected to the array substrate Display area. Since the signal line can reflect at least a portion of the light incident thereon to the display area of the array substrate, the backlight light utilization rate and panel transmittance can be at least partially improved.
- the array substrate prepared by the method of the present disclosure includes: a first substrate; a signal line disposed above the region of the first substrate corresponding to the non-display area of the array substrate; a layer, the insulating layer is disposed between the signal line and the first substrate, wherein a groove is disposed in the insulating layer, and the signal line is disposed on an inner wall of the groove, the groove
- the direction of the inner wall is set such that at least a portion of the light incident on the signal line from a side of the first substrate that faces away from the signal line is reflected to a display area of the array substrate. Since the signal line can reflect at least a portion of the light incident thereon to the display area of the array substrate, the backlight light utilization rate and panel transmittance can be at least partially improved.
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Abstract
一种阵列基板(21)及制备方法、液晶显示面板、显示装置,阵列基板(21)包括:第一基板(11);信号线(12,13),信号线(12,13)在第一基板(11)对应于阵列基板(21)的非显示区的区域的上方布置;绝缘层(14),绝缘层(14)设置在信号线(12,13)与第一基板(11)之间,其中绝缘层(14)中设有凹槽,信号线(12,13)设置在凹槽的内壁上,凹槽的内壁的方向设置成使得从第一基板(11)的背离信号线(12,13)的一侧入射到信号线(12,13)上的至少部分光线反射到阵列基板(21)的显示区。
Description
本公开要求2017年7月7日递交的、申请号为201710552949.6、发明名称为“一种阵列基板及制备方法、液晶显示面板、显示装置”的中国专利申请的优先权,其全部内容通过引用并入本申请中。
本公开涉及显示技术领域,特别是涉及一种阵列基板及制备方法、液晶显示面板、显示装置。
薄膜晶体管液晶显示器(Thin Film Transistor Liquid Crystal Display,TFT-LCD)具有体积小、功耗低、无辐射等特点,在当前的平板显示器市场中占据了主导地位。
液晶显示器一般包括液晶显示面板和给该液晶显示面板提供光源的背光源,液晶显示面板分为显示区和非显示区,液晶显示面板包括:阵列基板、与阵列基板对盒的对向基板,以及设置在阵列基板与对向基板之间的液晶层;为了防止非显示区漏光,一般会在对向基板的非显示区形成黑矩阵层,这样非显示区的光线就得不到利用,从而造成背光源光利用率和面板透过率较低。
发明内容
本公开实施例提供了一种阵列基板及制备方法、液晶显示面板、显示装置。
本公开实施例提供的一种阵列基板,包括:第一基板;信号线,所述信号线在所述第一基板对应于所述阵列基板的非显示区的区域的上方布置;绝缘层,所述绝缘层设置在所述信号线与所述第一基板之间,其中所述绝缘层中设有凹槽,所述信号线设置在所述凹槽的内壁上,所述凹槽的内壁的方向设置成使得从所述第一基板的背离所述信号线的一侧入射到所述信号线上的至少部分光线反射到所述阵列基板的显示区。
在一个实施例中,所述信号线为扫描线或数据线。
在一个实施例中,所述信号线包括扫描线和数据线,所述扫描线和数据线在所述第一基板对应于所述阵列基板的非显示区的区域的上方交叉布置;其中所述绝缘层包括:第一绝缘层,所述第一绝缘层设置在所述扫描线与所述第一基板之间,其中所述 第一绝缘层中设有第一凹槽,所述扫描线设置在所述第一凹槽的内壁上,所述第一凹槽的内壁的方向设置成使得从所述第一基板的背离所述扫描线的一侧入射到所述扫描线上的至少部分光线反射到所述阵列基板的显示区;和第二绝缘层,所述第二绝缘层设置在所述数据线与所述第一基板之间,其中所述第二绝缘层中设有第二凹槽,所述数据线设置在所述第二凹槽的内壁上,所述第二凹槽的内壁的方向设置成使得从所述第一基板的背离所述数据线的一侧入射到所述数据线上的至少部分光线反射到所述阵列基板的显示区。
在一个实施例中,所述信号线布满所述凹槽的内壁。
在一个实施例中,所述信号线覆盖所述凹槽的内壁的一部分。
在一个实施例中,所述凹槽的内壁为两个相交的平面或曲面。
在一个实施例中,所述凹槽的横截面为等腰三角形。
在一个实施例中,所述第一凹槽或所述第二凹槽的内壁为曲面或两个相交的平面。
在一个实施例中,所述第一凹槽或所述第二凹槽的横截面为等腰三角形。
本公开实施例还提供了一种液晶显示面板,包括:本公开任意实施例提供的阵列基板;与所述阵列基板对盒的对向基板;和设置在所述阵列基板与所述对向基板之间的液晶层。
在一个实施例中,所述对向基板包括:第二基板、设置在所述第二基板上且对应于所述阵列基板的非显示区且朝向所述阵列基板一面上的黑矩阵层;所述凹槽的横截面为等腰三角形,该等腰三角形的顶角为θ
1,θ
1满足如下条件:
L
1min/d
1max<tanθ
1<L
1max/d
1min
其中,L
1min为该等腰三角形的顶角所在的顶点到相邻像素单元的近端的距离;L
1max为该等腰三角形的一底角所在的顶点到与该顶点同侧的相邻像素单元的远端的距离;d
1min为该等腰三角形的一底角所在的顶点到黑矩阵层的距离;d
1max为该等腰三角形的顶角所在的顶点到黑矩阵层的距离。
在一个实施例中,所述对向基板包括:第二基板、设置在所述第二基板上且对应于所述阵列基板的非显示区且朝向所述阵列基板一面上的黑矩阵层;所述凹槽的横截面为等腰三角形,该等腰三角形的顶角θ
1满足如下条件:
L′
1min/d
1min<tanθ
1<L′
1max/d
1max
其中,L’
1min为该等腰三角形的一底角所在的顶点到与该顶点同侧的相邻像素单元的近端的距离;L’
1max为该等腰三角形的顶角所在的顶点到相邻像素单元的远端的距离;d
1min为该等腰三角形的一底角所在的顶点到黑矩阵层的距离;d
1max为该等腰三角形的顶角所在的顶点到黑矩阵层的距离。
本公开实施例还提供了一种显示装置,包括本公开任意实施例提供的液晶显示面板。
本公开实施例还提供了一种阵列基板的制备方法,包括如下步骤:
在第一基板一侧形成绝缘层,并在所述绝缘层的对应于阵列基板的非显示区的部分中形成凹槽;
在所述凹槽的内壁上形成信号线,所述凹槽的内壁的方向设置成使得从所述第一基板的背离所述信号线的一侧入射到所述信号线上的至少部分光线反射到所述阵列基板的显示区。
在一个实施例中,所述信号线为扫描线或数据线。
在一个实施例中,所述信号线包括扫描线和数据线,所述绝缘层包括第一绝缘层和第二绝缘层;并且所述制备方法包括如下步骤:
在第一基板一侧形成第一绝缘层,并在所述第一绝缘层的对应于阵列基板的非显示区的部分中形成第一凹槽;
在所述第一凹槽的内壁上形成扫描线,所述第一凹槽的内壁的方向设置成使得从所述第一基板的背离所述扫描线的一侧入射到所述扫描线上的至少部分光线反射到所述阵列基板的显示区;
在所述第一绝缘层一侧形成第二绝缘层,并在所述第二绝缘层的对应于阵列基板的非显示区的部分中形成第二凹槽;并且
在所述第二凹槽的内壁上形成数据线,所述第二凹槽的内壁的方向设置成使得从所述第一基板的背离所述数据线的一侧入射到所述数据线上的至少部分光线反射到所述阵列基板的显示区;其中,在所述阵列基板中所述扫描线与所述数据线呈交叉布置。
在一个实施例中,在第一基板一侧形成绝缘层,并在所述绝缘层的对应于所述阵列基板的非显示区的部分中形成凹槽的步骤包括:
在第一基板一侧涂覆负性光刻胶;
通过半色调掩膜板对所述负性光刻胶进行曝光并显影,以形成绝缘层,并在所述 绝缘层的对应于所述阵列基板的非显示区的部分中形成凹槽。
在一个实施例中,在第一基板一侧形成第一绝缘层,并在所述第一绝缘层的对应于所述阵列基板的非显示区的部分中形成第一凹槽的步骤包括:
在第一基板一侧涂覆负性光刻胶;
通过半色调掩膜板对所述负性光刻胶进行曝光并显影,以形成第一绝缘层,并在所述第一绝缘层的对应于所述阵列基板的非显示区的部分中形成第一凹槽。
在一个实施例中,在所述第一绝缘层一侧形成第二绝缘层,并在所述第二绝缘层的对应于所述阵列基板的非显示区的部分中形成第二凹槽的步骤包括:
在所述第一绝缘层一侧涂覆负性光刻胶;
通过半色调掩膜板对所述负性光刻胶进行曝光并显影,以形成第二绝缘层,并在所述第二绝缘层的对应于所述阵列基板的非显示区的部分中形成第二凹槽。
图1为本公开的实施例提供的一种阵列基板的结构示意图;
图2为本公开的实施例提供的所述阵列基板的透视图;
图3为本公开的实施例提供的所述阵列基板的俯视图;
图4为本公开的实施例提供的另一种阵列基板的结构示意图;
图5为本公开的实施例提供的所述另一种阵列基板的透视图;
图6为本公开的实施例提供的又一种阵列基板的透视图;
图7为本公开的实施例提供的阵列基板的制备方法的流程示意图;
图8(a)~图8(i)为本公开的实施例提供的阵列基板的制备工艺流程示意图;
图9和10为本公开的实施例提供的一种液晶显示面板的结构示意图;
图11和12为本公开的实施例提供的另一种液晶显示面板的结构示意图。
除非另外定义,本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的技术人员所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性,而只是用来区分不同的组成部分。在本公开中所采用的术语“竖直”或“水平”具有相对的含义而不是绝对的含义,例如“竖直”可以理解为表示第一方向,“水平”可以理解为表示与第一方向大致垂直的 第二方向。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同,而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接,而是可以包括电性的连接,不管是直接的还是间接的。“上”、“下”、“上方”、“下方”、“左”、“右”等仅用于表示相对位置关系,当被描述对象的绝对位置改变后,则该相对位置关系也可能相应地改变。
除非另作定义,本公开实施例以及附图中,同一标号代表同一含义。并且,本公开实施例附图中,只呈现出本公开实施例涉及到的结构,其他结构可参考通常设计。为了清晰起见,在用于描述本公开的实施例的附图中,层或区域的厚度被放大。可以理解,当诸如层、膜、区域或衬底基板之类的元件被称作位于另一元件“上”或“下”时,该元件可以“直接”位于另一元件“上”或“下”,或者可以存在中间元件。
在本公开中,扫描线和数据线“交叉布置”指的是扫描线和数据线在其所在的基板上的投影发生交叉,尤其是相互垂直,而不意味着扫描线和数据线本身相交。
在本公开中,信号线(例如扫描线或数据线)“布满”凹槽的内壁指的是凹槽的内壁完全或基本上被信号线覆盖,使得入射到所述信号线上的光线完全或基本上被反射。在这种情况下,凹槽内部不一定完全被信号线填满。
在本公开中,凹槽的内壁可以为两个相交的平面或曲面。换言之,凹槽的内壁可以大致为“V”形或“U”形。在凹槽的内壁为两个相交的曲面的情况下,所述曲面可以为弧面或者其它曲面,例如抛物面。这里的弧面或者抛物面是指一段圆弧或者抛物线通过平移而形成的曲面。在凹槽的内壁为两个相交的曲面的情况下,这两个曲面可以形成在相交处没有明显分界的单个曲面。
在本公开中,凹槽的“横截面”指的是与凹槽的长度延伸方向垂直的截面。
在本公开中,等腰三角形的顶角所在的顶点到“相邻像素单元的近端”的距离指的是所述顶点与相邻像素电极的近端在平行于阵列基板的平面内的投影之间的距离。同理,等腰三角形的一底角所在的顶点到与该顶点同侧的“相邻像素单元的远端”的距离指的是所述顶点与同侧相邻像素电极的远端在平行于阵列基板的平面内的投影之间的距离。
本公开实施例提供了一种阵列基板及制备方法、液晶显示面板、显示装置,用以至少部分地提高背光源光利用率和面板透过率。
下面将结合本公开实施例中的附图,对本公开实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。基于本公开中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本公开保护的范围。
需要说明的是,本公开附图中各层的厚度和形状不反映真实比例,目的只是示意说明本公开内容。
参见图1、图2,本公开的实施例提供的一种阵列基板包括:第一基板11、在第一基板11对应于阵列基板的非显示区的区域的上方交叉布置的扫描线12和数据线13,扫描线12与第一基板11之间设有第一绝缘层14,第一绝缘层14中设有内壁倾斜的第一凹槽15,扫描线12设置在第一凹槽15的内壁上,使得从第一基板11的背离所述扫描线12的一侧入射到扫描线12上的至少部分光线(如图中带箭头的线所示)反射到阵列基板的显示区。在一个示例中,所述第一凹槽15的内壁朝向中间倾斜,例如大致呈V字形或U形。
由于扫描线12可以使得从第一基板11的背离扫描线12的一侧入射到其上的至少部分光线反射到阵列基板的显示区,因此可以在一定程度上提高背光源光利用率和面板透过率。
在一个实施例中,为了尽可能地提高背光源光利用率和面板透过率,以及减小扫描线的线阻,如图1、图2所示,可以设置扫描线12布满第一凹槽15的内壁。作为替代,扫描线12也可以部分地覆盖第一凹槽15的内壁。
在一个实施例中,第一凹槽15的内壁可以为两个相交的平面。
在另一个实施例中,第一凹槽15的内壁可以为曲面。
需要指出的是,第一凹槽15的内壁只要使得设置在其上的扫描线12可以将至少部分入射到其上的光线反射到阵列基板的显示区即可,至于具体形状,本公开实施例并不对其进行限定,可以根据实际需要进行设定。
在一个实施例中,如图2所示,第一凹槽15的横截面为等腰三角形。当然,第一凹槽15的横截面并不限于等腰三角形,例如:还可以为其它三角形、半圆形、半椭圆形、抛物线形等。
在一个实施例中,上述阵列基板还包括:薄膜晶体管;扫描线12与该薄膜晶体管的栅极同层设置。
在一个实施例中,如图1、图2所示,上述阵列基板还包括:设置在薄膜晶体管 上的钝化层16,以及设置在钝化层16上的像素电极17;像素电极17与薄膜晶体管的漏极电连接,像素电极17位于阵列基板的显示区。相邻的两条扫描线12和相邻的两条数据线13定义一个像素单元,像素电极17设置在像素单元内,如图3所示。
需要说明的是,本公开实施例以数据线13位于扫描线12之上为例进行说明,但本公开实施例并不限于此,数据线13也可位于扫描线12之下,本公开实施例对上述阵列基板中的薄膜晶体管的结构并不进行限定,各种结构的薄膜晶体管都适用。
图4、图5所示的本公开实施例的阵列基板与图1-3所显示的本公开实施例的阵列基板相似,相同的部分在此不再赘述,下面只说明不同的部分。
参见图4、图5,本公开实施例提供的阵列基板中扫描线12的设置可以根据需要设置,但数据线13与第一基板11之间设有第二绝缘层18,第二绝缘层18中设有内壁倾斜的第二凹槽19,数据线13设置在第二凹槽19的内壁上,使得从第一基板11的背离数据线13的一侧入射到数据线13上的至少部分光线反射到阵列基板的显示区。
由于数据线13可以使得至少部分入射到其上的光线反射到阵列基板的显示区,因此可以在一定程度上提高背光源光利用率和面板透过率。
在一个实施例中,为了尽可能地提高背光源光利用率和面板透过率,以及减小数据线的线阻,如图4、图5所示,可以设置数据线13布满第二凹槽19的内壁。作为替代,数据线13也可以部分地覆盖第二凹槽19的内壁。
在一个实施例中,第二凹槽19的内壁可以为两个相交的平面。
在另一个实施例中,第二凹槽19的内壁可以为曲面。
需要指出的是,第二凹槽19的内壁只要使得设置在其上的数据线13可以将至少部分入射到其上的光线反射到阵列基板的显示区即可,至于具体形状,本公开实施例并不对其进行限定,可以根据实际需要进行设定。
在一个实施例中,如图4所示,第二凹槽19的横截面为等腰三角形。当然,第二凹槽19的横截面并不限于等腰三角形,例如:还可以为其它三角形、半圆形、半椭圆形、抛物线形等。
在一个实施例中,数据线13与薄膜晶体管的源漏极同层设置。
图6所示的本公开实施例的阵列基板与图4、图5所示的本公开实施例的阵列基板相似,相同的部分在此不再赘述,下面只说明不同的部分。
参见图6,本公开实施例提供的阵列基板中数据线13采用了图4、图5所示的本 公开实施例提供的阵列基板中数据线13的结构并且设置在第二凹槽19的内壁上,所述扫描线12采用了图1-2中显示的本公开实施例提供的阵列基板中的扫描线12的结构,其中该扫描线12设置在第一凹槽的内壁上。
基于同一构思,参见图7,本公开实施例还提供了一种阵列基板的制备方法,包括如下步骤:
S101、在第一基板一侧形成第一绝缘层,并在所述第一绝缘层的对应于所述阵列基板的非显示区的部分中形成内壁倾斜的第一凹槽;
S102、在所述第一凹槽的内壁上形成扫描线,所述扫描线使得从所述第一基板的背离所述扫描线的一侧入射到所述扫描线上的至少部分光线反射到所述阵列基板的显示区;和/或
S103、在所述第一绝缘层一侧形成第二绝缘层,并在所述第二绝缘层的对应于所述阵列基板的非显示区的部分中形成内壁倾斜的第二凹槽;
S104、在所述第二凹槽的内壁上形成数据线,所述数据线使得从所述第一基板的背离所述数据线的一侧入射到所述数据线上的至少部分光线反射到所述阵列基板的显示区;其中,所述扫描线与所述数据线呈交叉布置。
若制作如图1、图2所示的阵列基板,则该阵列基板的制备方法包括步骤S101和S102;若制作如图4、图5所示的阵列基板,则该阵列基板的制备方法包括步骤S103和S104;若制作如图6所示的阵列基板,则该阵列基板的制备方法包括步骤S101、S102、S103和S104。
需要指出的是,步骤S101和S102与步骤S103和S104的制作先后顺序与制作的阵列基板的结构有关,若数据线位于扫描线之上,则步骤S103和S104在步骤S101和S102之后,若数据线位于扫描线之下,则步骤S103和S104在步骤S101和S102之前。
在一个实施例中,步骤S101中在第一基板一侧形成第一绝缘层,并在所述第一绝缘层的对应于所述阵列基板的非显示区的部分中形成内壁倾斜的第一凹槽的步骤可以包括:
在第一基板一侧涂覆负性光刻胶;
通过半色调掩膜板对所述负性光刻胶进行曝光和显影(如果需要时,也可以选用蚀刻等工艺),以形成第一绝缘层,并在所述第一绝缘层的对应于所述阵列基板的非显示区的部分中形成内壁倾斜的第一凹槽。
其中,半色调掩膜板的遮挡部位的透光率可以设置成从两侧向中间逐渐减小,通过控制半色调掩膜板的遮挡部位的透光率,可以控制第一凹槽的形状。
在一个实施例中,步骤S103中在所述第一绝缘层一侧形成第二绝缘层,并在所述第二绝缘层的对应于所述阵列基板的非显示区的部分中形成内壁倾斜的第二凹槽的步骤可以包括:
在所述第一绝缘层一侧涂覆负性光刻胶;
通过半色调掩膜板对所述负性光刻胶进行曝光并显影(如果需要时,也可以选用蚀刻等工艺),以形成第二绝缘层,并在所述第二绝缘层的对应于所述阵列基板的非显示区的部分中形成内壁倾斜的第二凹槽。
其中,半色调掩膜板的遮挡部位的透光率可以设置成从两侧向中间逐渐减小,通过控制半色调掩膜板的遮挡部位的透光率,可以控制第二凹槽的形状。
下面以图6所示的阵列基板的制备为例,结合附图8(a)~8(i)来具体说明本公开实施例提供的阵列基板的制备工艺流程。
步骤一、参见图8(a),在第一基板81上涂覆第一负性光刻胶82;
步骤二、参见图8(b)和8(c),通过第一半色调掩膜板83对第一负性光刻胶82进行曝光并显影,以形成第一绝缘层84,并在第一绝缘层84的对应于所述阵列基板的非显示区的部分中形成内壁倾斜且横截面为等腰三角形的第一凹槽85;
步骤三、参见图8(d),在第一凹槽85的内壁上形成扫描线86,所述扫描线使得从第一基板81的背离所述扫描线86的一侧入射到扫描线86上的至少部分光线反射到阵列基板的显示区;
步骤四、参见图8(e),在形成有扫描线86的第一基板81上涂覆第二负性光刻胶87;
步骤五、参见图8(f)和8(g),通过第二半色调掩膜板88对第二负性光刻胶87进行曝光并显影,以形成第二绝缘层89,并在第二绝缘层89的对应于所述阵列基板的非显示区的部分中形成内壁倾斜且横截面为等腰三角形的第二凹槽90;
步骤六、参见图8(h),在第二凹槽90的内壁上形成数据线91,所述数据线使得从第一基板81的背离所述数据线91的一侧入射到数据线91上的至少部分光线反射到阵列基板的显示区;
其中,扫描线86与数据线91呈交叉布置。
步骤七、参见图8(i),在形成有数据线91的第一基板81上依次形成钝化层92 和像素电极93。
需要说明的是,在上述制备阵列基板的过程中还包括制备薄膜晶体管的步骤,薄膜晶体管的制备步骤可以根据需要选择,在此不再赘述,并且可以在制备扫描线86的同时制备薄膜晶体管的栅极,在制备数据线91的同时制备薄膜晶体管的源漏极。另外,在以上涉及形成绝缘层的步骤二和步骤五中,第一绝缘层和第二绝缘层由负性光刻胶本身形成,或者说两者材质相同。但是,形成第一或第二绝缘层并在其上形成第一或第二凹槽的方法不限于上述步骤,例如也可以通过如下方法:首先在第一基板一侧形成一层绝缘材料层,在该绝缘材料层上涂覆光刻胶,通过曝光、显影以及蚀刻等工艺在该绝缘层材料的期望位置处根据需要形成上述的第一凹槽或第二凹槽。在这种情况下绝缘材料层和光刻胶的材质不同。
基于同一构思,参见图9至图12,本公开实施例还提供了一种液晶显示面板,包括:本公开任意实施例提供的阵列基板21、与阵列基板21对盒的对向基板22,以及设置在阵列基板21与对向基板22之间的液晶层23。
上述液晶显示面板可以为任意模式的液晶显示面板,例如:扭曲向列(Twist Nematic,TN)模式液晶显示面板、平面转换(In Plane Switching,IPS)模式液晶显示面板、高级超维场开关(Advanced Super Dimension Switch,ADS)模式液晶显示面板等。
在一个实施例中,如图9至图12所示,对向基板22包括:第二基板221、设置在第二基板221上且对应于所述阵列基板的非显示区且朝向阵列基板21一面上的黑矩阵层222。
在一个实施例中,如图9所示,阵列基板21的第一凹槽211横截面为等腰三角形,该等腰三角形的顶角为θ
1,θ
1满足如下条件:
L
1min/d
1max<tanθ
1<L
1max/d
1min
其中,L
1min为该等腰三角形的顶角所在的顶点到相邻像素单元的近端的距离;L
1max为该等腰三角形的一底角所在的顶点到与该顶点同侧的相邻像素单元的远端的距离;d
1min为该等腰三角形的一底角所在的顶点到黑矩阵层222的距离;d
1max为该等腰三角形的顶角所在的顶点到黑矩阵层222的距离。
在一个实施例中,如图10所示,为了尽可能多地将入射到扫描线上的光线反射到阵列基板的显示区,θ
1可以设置成满足如下条件:
L′
1min/d
1min<tanθ
1<L′
1max/d
1max
其中,L’
1min为该等腰三角形的一底角所在的顶点到与该顶点同侧的相邻像素单元的近端的距离;L’
1max为该等腰三角形的顶角所在的顶点到相邻像素单元的远端的距离。
在一个实施例中,如图11所示,阵列基板21的第二凹槽212的横截面为等腰三角形,该等腰三角形的顶角为θ
2,θ
2满足如下条件:
L
2min/d
2max<tanθ
2<L
2max/d
2min
其中,L
2min为该等腰三角形的顶角所在的顶点到相邻像素单元的近端的距离;L
2max为该等腰三角形的一底角所在的顶点到与该顶点同侧的相邻像素单元的远端的距离;d
2min为该等腰三角形的一底角所在的顶点到黑矩阵层222的距离;d
2max为该等腰三角形的顶角所在的顶点到黑矩阵层222的距离。
在一个实施例,如图12所示,为了尽可能多地将入射到数据线上的光线反射到阵列基板的显示区,θ
2可以设置成满足如下条件:
L′
2min/d
2min<tanθ
2<L′
2max/d
2max
其中,L’
2min为该等腰三角形的一底角所在的顶点到与该顶点同侧的相邻像素单元的近端的距离;L’
2max为该等腰三角形的顶角所在的顶点到相邻像素单元的远端的距离。
基于同一构思,本公开实施例还提供了一种显示装置,包括本公开任意实施例提供的液晶显示面板。该显示装置可以为:手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
综上所述,本公开实施例提供的技术方案中,阵列基板包括:第一基板;信号线,所述信号线在所述第一基板对应于所述阵列基板的非显示区的区域的上方布置;绝缘层,所述绝缘层设置在所述信号线与所述第一基板之间,其中所述绝缘层中设有凹槽,所述信号线设置在所述凹槽的内壁上,所述凹槽的内壁的方向设置成使得从所述第一基板的背离所述信号线的一侧入射到所述信号线上的至少部分光线反射到所述阵列基板的显示区。由于信号线可以使得至少部分入射到其上的光线反射到阵列基板的显示区,因此可以在一定程度上提高背光源光利用率和面板透过率。
在一个实施例中,所述信号线布满所述凹槽的内壁。这样,一方面可以尽可能多地将入射到信号线上的光线反射到阵列基板的显示区,从而尽可能地提高背光源光利 用率和面板透过率,另一方面可以在一定程度上增加信号线的有效线宽,从而减小信号线的线阻。
根据本公开的一个实施例提供的一种液晶显示面板包括上述的阵列基板,而上述的阵列基板包括:第一基板;信号线,所述信号线在所述第一基板对应于所述阵列基板的非显示区的区域的上方布置;绝缘层,所述绝缘层设置在所述信号线与所述第一基板之间,其中所述绝缘层中设有凹槽,所述信号线设置在所述凹槽的内壁上,所述凹槽的内壁的方向设置成使得从所述第一基板的背离所述信号线的一侧入射到所述信号线上的至少部分光线反射到所述阵列基板的显示区。由于信号线可以使得至少部分入射到其上的光线反射到阵列基板的显示区,因此可以至少部分地提高背光源光利用率和面板透过率。
在一个实施例中,采用本公开方法制备的阵列基板包括:第一基板;信号线,所述信号线在所述第一基板对应于所述阵列基板的非显示区的区域的上方布置;绝缘层,所述绝缘层设置在所述信号线与所述第一基板之间,其中所述绝缘层中设有凹槽,所述信号线设置在所述凹槽的内壁上,所述凹槽的内壁的方向设置成使得从所述第一基板的背离所述信号线的一侧入射到所述信号线上的至少部分光线反射到所述阵列基板的显示区。由于信号线可以使得至少部分入射到其上的光线反射到阵列基板的显示区,因此可以至少部分地提高背光源光利用率和面板透过率。
显然,本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样,倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内,则本公开也意图包含这些改动和变型在内。
Claims (19)
- 一种阵列基板,包括:第一基板;信号线,所述信号线在所述第一基板对应于所述阵列基板的非显示区的区域的上方布置;和绝缘层,所述绝缘层设置在所述信号线与所述第一基板之间,其中所述绝缘层中设有凹槽,所述信号线设置在所述凹槽的内壁上,所述凹槽的内壁的方向设置成使得从所述第一基板的背离所述信号线的一侧入射到所述信号线上的至少部分光线反射到所述阵列基板的显示区。
- 根据权利要求1所述的阵列基板,其中所述信号线为扫描线或数据线。
- 根据权利要求1所述的阵列基板,其中所述信号线包括扫描线和数据线,所述扫描线和数据线在所述第一基板对应于所述阵列基板的非显示区的区域的上方交叉布置;其中所述绝缘层包括:第一绝缘层,所述第一绝缘层设置在所述扫描线与所述第一基板之间,其中所述第一绝缘层中设有第一凹槽,所述扫描线设置在所述第一凹槽的内壁上,所述第一凹槽的内壁的方向设置成使得从所述第一基板的背离所述扫描线的一侧入射到所述扫描线上的至少部分光线反射到所述阵列基板的显示区;和第二绝缘层,所述第二绝缘层设置在所述数据线与所述第一基板之间,其中所述第二绝缘层中设有第二凹槽,所述数据线设置在所述第二凹槽的内壁上,所述第二凹槽的内壁的方向设置成使得从所述第一基板的背离所述数据线的一侧入射到所述数据线上的至少部分光线反射到所述阵列基板的显示区。
- 根据权利要求1所述的阵列基板,其中所述信号线布满所述凹槽的内壁。
- 根据权利要求1所述的阵列基板,其中所述信号线覆盖所述凹槽的内壁的一部分。
- 根据权利要求1所述的阵列基板,其中所述凹槽的内壁为曲面或两个相交的平面。
- 根据权利要求6所述的阵列基板,其中所述凹槽的横截面为等腰三角形。
- 根据权利要求3所述的阵列基板,其中所述第一凹槽或所述第二凹槽的内壁为曲面或两个相交的平面。
- 根据权利要求8所述的阵列基板,其中所述第一凹槽或所述第二凹槽的横截面为等腰三角形。
- 一种液晶显示面板,包括:如权利要求1-9中任一项所述的阵列基板;与所述阵列基板对盒的对向基板;和设置在所述阵列基板与所述对向基板之间的液晶层。
- 根据权利要求10所述的液晶显示面板,其中所述对向基板包括:第二基板、设置在所述第二基板上且对应于所述阵列基板的非显示区且朝向所述阵列基板一面上的黑矩阵层;所述凹槽的横截面为等腰三角形,该等腰三角形的顶角为θ 1,θ 1满足如下条件:L 1min/d 1max<tanθ 1<L 1max/d 1min其中,L 1min为该等腰三角形的顶角所在的顶点到相邻像素单元的近端的距离;L 1max为该等腰三角形的一底角所在的顶点到与该顶点同侧的相邻像素单元的远端的距离;d 1min为该等腰三角形的一底角所在的顶点到黑矩阵层的距离;d 1max为该等腰三角形的顶角所在的顶点到黑矩阵层的距离。
- 根据权利要求10所述的液晶显示面板,其中所述对向基板包括:第二基板、设置在所述第二基板上且对应于所述阵列基板的非显示区且朝向所述阵列基板一面上的黑矩阵层;所述凹槽的横截面为等腰三角形,该等腰三角形的顶角θ 1满足如下条件:L′ 1min/d 1min<tanθ 1<L′ 1max/d 1max其中,L’ 1min为该等腰三角形的一底角所在的顶点到与该顶点同侧的相邻像素单元的近端的距离;L’ 1max为该等腰三角形的顶角所在的顶点到相邻像素单元的远端的距离;d 1min为该等腰三角形的一底角所在的顶点到黑矩阵层的距离;d 1max为该等腰三角形的顶角所在的顶点到黑矩阵层的距离。
- 一种显示装置,包括如权利要求10-12中任一项所述的液晶显示面板。
- 一种阵列基板的制备方法,包括如下步骤:在第一基板一侧形成绝缘层,并在所述绝缘层的对应于阵列基板的非显示区的部分中形成凹槽;在所述凹槽的内壁上形成信号线,所述凹槽的内壁的方向设置成使得从所述第一 基板的背离所述信号线的一侧入射到所述信号线上的至少部分光线反射到所述阵列基板的显示区。
- 根据权利要求14所述的制备方法,其中所述信号线为扫描线或数据线。
- 根据权利要求14所述的制备方法,其中所述信号线包括扫描线和数据线,所述绝缘层包括第一绝缘层和第二绝缘层;并且所述方法包括如下步骤:在第一基板一侧形成第一绝缘层,并在所述第一绝缘层的对应于阵列基板的非显示区的部分中形成第一凹槽;在所述第一凹槽的内壁上形成扫描线,所述第一凹槽的内壁的方向设置成使得从所述第一基板的背离所述扫描线的一侧入射到所述扫描线上的至少部分光线反射到所述阵列基板的显示区;在所述第一绝缘层一侧形成第二绝缘层,并在所述第二绝缘层的对应于阵列基板的非显示区的部分中形成第二凹槽;并且在所述第二凹槽的内壁上形成数据线,所述第二凹槽的内壁的方向设置成使得从所述第一基板的背离所述数据线的一侧入射到所述数据线上的至少部分光线反射到所述阵列基板的显示区;其中,在所述阵列基板中所述扫描线与所述数据线呈交叉布置。
- 根据权利要求14所述的制备方法,其中在第一基板一侧形成绝缘层,并在所述绝缘层的对应于所述阵列基板的非显示区的部分中形成凹槽的步骤包括:在第一基板一侧涂覆负性光刻胶;通过半色调掩膜板对所述负性光刻胶进行曝光并显影,以形成绝缘层,并在所述绝缘层的对应于所述阵列基板的非显示区的部分中形成凹槽。
- 根据权利要求16所述的制备方法,其中在第一基板一侧形成第一绝缘层,并在所述第一绝缘层的对应于所述阵列基板的非显示区的部分中形成第一凹槽的步骤包括:在第一基板一侧涂覆负性光刻胶;通过半色调掩膜板对所述负性光刻胶进行曝光并显影,以形成第一绝缘层,并在所述第一绝缘层的对应于所述阵列基板的非显示区的部分中形成第一凹槽。
- 根据权利要求16或18所述的制备方法,其中在所述第一绝缘层一侧形成第二绝缘层,并在所述第二绝缘层的对应于所述阵列基板的非显示区的部分中形成第二 凹槽的步骤包括:在所述第一绝缘层一侧涂覆负性光刻胶;通过半色调掩膜板对所述负性光刻胶进行曝光并显影,以形成第二绝缘层,并在所述第二绝缘层的对应于所述阵列基板的非显示区的部分中形成第二凹槽。
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CN109188814A (zh) * | 2018-10-15 | 2019-01-11 | 京东方科技集团股份有限公司 | 一种显示基板、显示装置及显示基板的制作方法 |
CN109860207B (zh) | 2019-02-27 | 2022-07-19 | 合肥鑫晟光电科技有限公司 | 一种阵列基板、其制作方法、显示面板及显示装置 |
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CN114137754B (zh) * | 2021-11-30 | 2022-10-21 | 绵阳惠科光电科技有限公司 | 曲面屏及显示装置 |
CN114740665B (zh) * | 2022-04-29 | 2023-08-01 | 广州华星光电半导体显示技术有限公司 | 一种显示面板及显示装置 |
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