WO2018209599A1 - 阵列基板及其制造方法 - Google Patents

阵列基板及其制造方法 Download PDF

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Publication number
WO2018209599A1
WO2018209599A1 PCT/CN2017/084720 CN2017084720W WO2018209599A1 WO 2018209599 A1 WO2018209599 A1 WO 2018209599A1 CN 2017084720 W CN2017084720 W CN 2017084720W WO 2018209599 A1 WO2018209599 A1 WO 2018209599A1
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Prior art keywords
metal
layer
protective layer
conductive layer
metal conductive
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PCT/CN2017/084720
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English (en)
French (fr)
Inventor
钱俊
叶江波
肖禄
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深圳市柔宇科技有限公司
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Priority to CN201780004625.7A priority Critical patent/CN108701695A/zh
Priority to PCT/CN2017/084720 priority patent/WO2018209599A1/zh
Publication of WO2018209599A1 publication Critical patent/WO2018209599A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs

Definitions

  • the present application relates to the field of display technologies, and in particular, to an array substrate and a method of fabricating the same.
  • a molybdenum (Mo)-aluminum (Al)-molybdenum (Mo) structure is generally used in the array substrate as the source and drain layer 10 of the array substrate (as shown in FIG. 1a).
  • an electric field is formed between the side surface of the first molybdenum layer 11 and the upper surface of the aluminum layer 12 (as shown in FIG. 1b), thereby causing electrochemical corrosion, resulting in the first molybdenum layer.
  • the etching rate of 11 is lowered while the etching rate of the aluminum layer 12 is increased.
  • a large recess 14 is formed on the side of the aluminum layer 12 (as shown in FIG. 1c), and the subsequent film structure cannot completely cover the inner surface of the recess 14, resulting in abnormal quality of the array substrate.
  • the purpose of the present application is to provide an array substrate and a manufacturing method thereof, which can reduce the depression formed on the metal conductive layer during the manufacturing process and improve the quality of the array substrate.
  • the application provides a method for manufacturing an array substrate, comprising the following steps:
  • the third metal protective layer is etched through the photoresist pattern layer to the first metal protective layer to form a channel.
  • the present application also provides an array substrate including a substrate substrate and sequentially stacked on the substrate substrate a first metal protective layer, a first metal conductive layer, a second metal protective layer, and a second metal conductive layer stacked over the second metal protective layer and a third metal covering the surface of the second metal conductive layer
  • the protective layer is formed with through holes communicating with each other from the third metal protective layer to the first metal protective layer to form a channel.
  • the method for fabricating the array substrate of the present application by forming a plurality of metal conductive layers on the base substrate, and protecting the outer surface of the metal conductive layer by a metal protective layer, by increasing the number of layers of the metal conductive layer, the single layer is reduced.
  • the thickness of the metal conductive layer further reduces the depth of the recess formed on the sidewall of the metal conductive layer during the etching process, reduces the quality abnormality in the subsequent process, and improves the product yield of the array substrate.
  • FIG. 1 is a schematic view showing a manufacturing process of a prior art array substrate.
  • FIG. 2 is a schematic flow chart of a method for fabricating an array substrate according to a first embodiment of the present application.
  • 3 to 7 are schematic views showing the process of manufacturing the array substrate according to the first embodiment of the present application.
  • FIG. 8 is a schematic flow chart of a method for fabricating an array substrate according to a second embodiment of the present application.
  • FIG. 9 to FIG. 11 are schematic diagrams showing the process of manufacturing the array substrate according to the second embodiment of the present application.
  • FIG. 12 is a schematic flow chart of a method for fabricating an array substrate according to a third embodiment of the present application.
  • FIG. 2 is a schematic flow chart of a method for manufacturing an array substrate according to a first embodiment of the present application.
  • the manufacturing method of the array substrate of the present application mainly includes the following steps:
  • Step S101 providing a base substrate on which a first metal protective layer, a first metal conductive layer and a second metal protective layer are sequentially formed.
  • the first metal protective layer 202 and the first metal conductive layer 203 and the second metal protective layer 204 may be sequentially formed on the base substrate 201 by sputtering or thermal evaporation.
  • the functions of the first metal protection layer 202 and the second metal protection layer 204 are to prevent the metal in the first metal conductive layer 203 from diffusing into other layer structures on the substrate substrate 201, so as not to reduce the array substrate. performance. It can be understood that the metal mobility of the first metal conductive layer 203 is greater than the metal mobility of the first metal conductive layer 203 and the second metal protective layer 204.
  • the materials of the first metal protective layer 202 and the second metal protective layer 204 may be the same or different.
  • the materials of the first metal protection layer 202 and the second metal protection layer 204 may both be molybdenum (Mo), and the material of the first metal conductive layer 203 may be aluminum. (Al). It is to be understood that, in other embodiments of the present application, the first metal protection layer 202, the second metal protection layer 204, and the first metal conductive layer 203 are not limited to the above metal materials.
  • Step S102 Laying a second metal conductive layer 205 over the second metal protection layer 204.
  • a second metal conductive layer 205 may be deposited over the second metal cap layer 204 by sputtering or thermal evaporation.
  • the second metal conductive layer 205 covers the second metal protection layer 204.
  • the material of the second metal conductive layer 205 may be the same as the material of the first metal conductive layer 203.
  • the depression formed on the sidewalls of the second metal conductive layer 205 and the second metal conductive layer 205 during etching is also greater.
  • the thickness of the first metal conductive layer 203 and the second metal conductive layer 205 are both less than 3000A.
  • the first metal conductive layer 203 and the second metal conductive layer 205 have a thickness of between 1000A and 3000A. The purpose of the arrangement is to prevent large depressions from being formed on the sidewalls of the first metal conductive layer 203 and the second metal conductive layer 205 during the subsequent etching process.
  • Step S103 covering the surface of the second metal conductive layer 205 with the third metal protective layer 206.
  • the third metal protective layer 206 may be the same material as the first metal protective layer 202 and the second metal protective layer 204. That is, the second metal conductive layer 205 is interposed between the second metal protective layer 204 and the third metal protective layer 206. The second metal protective layer 204 and the third metal protective layer 206 together prevent diffusion of the third metal conductive layer to other layer structures of the array substrate. It can be understood that the surface of the present application is a face of each layer structure away from the base substrate 201.
  • Step S104 covering the surface of the third metal protective layer 206 with a photoresist pattern layer.
  • a photoresist may be coated on the third metal protective layer 206, and then the photoresist pattern layer 207 may be formed by a mask etching process. It can be understood that the photoresist pattern layer 207 includes a pattern region and a hollow region 208.
  • Step S105 etching the third metal protective layer 206 to the first metal protective layer 202 through the photoresist pattern layer 207 to form the channel 210.
  • the array substrate can be etched using wet etching.
  • An etchant is sprayed on the photoresist pattern layer 207, and the etchant sequentially etches the third metal protective layer 206, the second metal conductive layer 205, and the second metal protective layer 204 via the hollow regions on the photoresist pattern layer 207.
  • the channel is formed together in the above layer structure. It will be appreciated that the channel is used for electron transfer.
  • the thickness of the first metal conductive layer 203 / the second metal conductive layer 205 corresponding to the large hollow region should be reduced. That is, the larger the area of the photoresist pattern layer 207 hollowed out region 208, the smaller the thickness of the first metal conductive layer 203 and the second metal conductive layer 205.
  • the area of the photoresist pattern layer 207 corresponding to the substantially intermediate region of the array is larger than the area of the corresponding photoresist pattern layer 207 hollow region 208 on the peripheral region. That is to say, in the peripheral line region, the peripheral line region during the etching process has a large recess after the wet etching. Therefore, it is also possible to reduce the thickness of the single-layer metal conductive layer in the peripheral region, and to reduce the adverse effects caused by the depression.
  • the etching solution used in the wet etching may include H 2 O 2 , a metal chelating agent or an organic acid.
  • the process of forming the trench further includes removing the photoresist pattern layer 207. Further specifically, the photoresist pattern layer 207 may be removed by a wet etching method to form The array substrate shown in FIG.
  • the method for fabricating an array substrate according to the first embodiment of the present application by forming two metal conductive layers on the base substrate, and protecting the outer surface of the metal conductive layer by a metal protective layer, by increasing the number of layers of the metal conductive layer, Thereby, the thickness of the single-layer metal conductive layer is reduced, thereby reducing the depth of the recess formed on the sidewall of the metal conductive layer during the etching process, reducing the quality abnormality in the subsequent process, and improving the product yield of the array substrate.
  • FIG. 8 is a schematic flow chart of a method for manufacturing an array substrate according to a second embodiment of the present application.
  • the manufacturing method of the array substrate of the present application mainly includes the following steps:
  • Step S201 providing a base substrate on which a first metal protective layer, a first metal conductive layer and a second metal protective layer are sequentially formed.
  • Step S202 laminating a second metal conductive layer over the second metal protection layer.
  • step S202 includes:
  • Step S2021 covering the surface of the second metal protective layer with the third metal conductive layer.
  • Step S2022 covering the surface of the third metal conductive layer with a fourth metal protective layer.
  • Step S2023 covering the surface of the fourth metal conductive layer with the second metal conductive layer.
  • the first metal protective layer 202, the first metal conductive layer 203, the second metal protective layer 204, the third metal conductive layer 211, the fourth metal protective layer 212, and the The second metal conductive layer 205 is sequentially stacked on the base substrate 201.
  • a third metal conductive layer 211 and a fourth metal protective layer 212 are stacked between the second metal protective layer 204 and the second metal conductive layer 205.
  • Step S203 covering the surface of the second metal conductive layer 205 with the third metal protective layer 206.
  • the third metal protection layer 206 may be the same material as the first metal protection layer 202 and the second metal protection layer 204 and the fourth metal protection layer 212.
  • the materials of the first metal conductive layer 203, the second metal conductive layer 205, and the third metal conductive layer 211 may be the same.
  • Step S204 covering the surface of the third metal protection layer 206 with a photoresist pattern layer.
  • a photoresist may be coated on the third metal protective layer 206, and then the photoresist pattern layer 207 may be formed by a mask etching process. It can be understood that the photoresist pattern layer includes a pattern region and a hollow region 208.
  • Step S205 etching the third metal protective layer 206 to the first metal protective layer 202 through the photoresist pattern layer to form a channel.
  • the array substrate can be etched using wet etching. Spraying an etchant on the photoresist pattern layer, and etching the third metal protective layer 206, the second metal conductive layer 205, the fourth metal protective layer 212, and the etchant sequentially through the hollow regions on the photoresist pattern layer.
  • the channel 210 is formed in common on the above layer structure. It will be appreciated that the channel 210 is used for electron transfer.
  • the etching solution used in the wet etching may include H 2 O 2 , a metal chelating agent or an organic acid.
  • the process of forming the trench further includes removing the photoresist pattern layer 207. More specifically, the photoresist pattern layer may be removed by a wet etching method to form an array substrate as shown in FIG.
  • the method for fabricating an array substrate according to the first embodiment of the present application by forming a three-layer metal conductive layer on the base substrate, and protecting the outer surface of the metal conductive layer by a metal protective layer, by increasing the number of layers of the metal conductive layer, Thereby, the thickness of the single-layer metal conductive layer is reduced, thereby reducing the depth of the recess formed on the sidewall of the metal conductive layer during the etching process, reducing the quality abnormality in the subsequent process, and improving the product yield of the array substrate.
  • FIG. 12 is a schematic flow chart of a method for manufacturing an array substrate according to a third embodiment of the present application.
  • the manufacturing method of the array substrate of the present application mainly includes the following steps:
  • Step S301 providing a substrate on which a first metal protective layer, a first metal conductive layer and a second metal protective layer are sequentially formed.
  • Step S302 Laying a second metal conductive layer on top of the second metal protective layer.
  • Step S3021 covering the surface of the second metal protective layer with a spacer layer, wherein the spacer layer comprises a plurality of spaced apart third metal conductive layers and a fourth metal protective layer, and the third metal conductive layer located at the bottom A layer covers the second metal protective layer.
  • the number of the third metal conductive layers is the same as the number of the fourth metal protective layers.
  • the number of the third metal conductive layer and the fourth metal protective layer 212 may be 1, 2, 3, 4, 6, . It can be understood that the third metal guide is not increased in order to increase the overall thickness of the array substrate. The more the number of the electric layer and the fourth metal protective layer, the smaller the thickness of the self-contained layer, and the smaller the depression formed on each of the metal conductive layers.
  • Step S3022 covering the second metal conductive layer on the surface of the fourth metal protective layer at the top.
  • Step S303 covering a surface of the second metal conductive layer with a third metal protective layer.
  • the third metal protective layer may be the same material as the first metal protective layer and the second metal protective layer and the fourth metal protective layer.
  • the materials of the first metal conductive layer, the second metal conductive layer, and the third metal conductive layer may be the same.
  • Step S304 covering the surface of the third metal protective layer with a photoresist pattern layer.
  • a photoresist may be coated on the third metal protective layer, and then the photoresist pattern layer is formed by a mask etching process. It can be understood that the photoresist pattern layer includes a pattern area and a hollow area.
  • Step S305 etching the third metal protective layer 206 to the first metal protective layer through the photoresist pattern layer to form a channel.
  • the array substrate can be etched by wet etching. Spraying an etchant on the photoresist pattern layer, the etchant sequentially etching the third metal protective layer, the second metal conductive layer, and the spacer layer via the hollow region on the photoresist pattern layer (ie, a plurality of fourth metal protection layers) a layer and a third metal conductive layer), a second metal protective layer, a first metal conductive layer, and a first metal protective layer.
  • the channel is formed together in the above layer structure. It will be appreciated that the channel is used for electron transfer.
  • the etching solution used in the wet etching may include H 2 O 2 , a metal chelating agent or an organic acid.
  • the process of forming the trench further includes removing the photoresist pattern layer. More specifically, the photoresist pattern layer can be removed by a wet etching method.
  • the method for fabricating the array substrate of the third embodiment of the present application by forming a plurality of metal conductive layers on the base substrate, and protecting the outer surface of the metal conductive layer by the metal protective layer, by increasing the number of layers of the metal conductive layer, Thereby, the thickness of the single-layer metal conductive layer is reduced, thereby reducing the depth of the recess formed on the sidewall of the metal conductive layer during the etching process, reducing the quality abnormality in the subsequent process, and improving the product yield of the array substrate.

Abstract

一种阵列基板及其制造方法，其中，方法包括如下步骤：提供一衬底基板（201），在衬底基板（201）上依次形成第一金属保护层（202）、第一金属导电层（203）和第二金属保护层（204）；在第二金属保护层（204）上方层叠设置第二金属导电层（205）；在第二金属导电层（205）表面覆盖第三金属保护层（206）；在第三金属保护层（206）表面覆盖光阻图案层（207）；透过光阻图案层（207）由第三金属保护层（206）蚀刻至第一金属保护层（202），以形成沟道（210）。通过在衬底基板上形成多层金属导电层，并且金属导电层外表面通过金属保护层进行保护，通过增加金属导电层的层数，从而减小单层金属导电层的厚度，进而减小蚀刻过程中在金属导电层侧壁上形成的凹陷的深度，降低后续工序中的品质异常，提升阵列基板的产品良率。

Description

阵列基板及其制造方法 技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板及其制造方法。
背景技术
阵列基板的制造过程中，通常需要对源漏极层进行湿法蚀刻以形成沟道。湿法蚀刻过程中除了药液化学腐蚀，往往还伴随着电化学腐蚀(Galvanic Corrosion)。
请参阅图1。目前，阵列基板中通常采用钼(Mo)-铝(Al)-钼(Mo)结构作为阵列基板的源漏极层10(如图1a所示)。当第一钼层11被蚀刻穿透后，第一钼层11侧面与铝层12的上表面之间会形成电场(如图1b所示)，从而产生电化学腐蚀现象，导致第一钼层11的蚀刻速率下降，同时铝层12的蚀刻速率上升。蚀刻完成后在铝层12的侧面上会形成产生较大的凹陷14(如图1c所示)，后续膜层结构无法完全覆盖所述凹陷14内表面中，造成阵列基板的品质异常。
申请内容
本申请的目的在于提供一种阵列基板及其制造方法，可以减小制造过程中在金属导电层上形成的凹陷，提升阵列基板品质。
为实现上述目的，本申请提供如下技术方案：
本申请提供一种阵列基板的制造方法，包括如下步骤：
提供一衬底基板，在所述衬底基板上依次形成第一金属保护层、第一金属导电层和第二金属保护层；
在所述第二金属保护层上方层叠设置第二金属导电层；
在所述第二金属导电层表面覆盖第三金属保护层；
在所述第三金属保护层表面覆盖光阻图案层；
透过所述光阻图案层由所述第三金属保护层蚀刻至所述第一金属保护层，以形成沟道。
本申请还提供一种阵列基板，包括衬底基板及依次层叠于所述衬底基板的 第一金属保护层、第一金属导电层、第二金属保护层，及层叠设置于所述第二金属保护层上方的第二金属导电层、覆盖所述第二金属导电层表面的第三金属保护层，由所述第三金属保护层至所述第一金属保护层上形成有相互连通的通孔以形成沟道。
本申请实施例具有如下优点或有益效果：
本申请的阵列基板的制造方法中，通过在衬底基板上形成多层金属导电层，并且金属导电层外表面通过金属保护层进行保护，通过增加金属导电层的层数，从而减小单层金属导电层的厚度，进而减小蚀刻过程中在金属导电层侧壁上形成的凹陷的深度，降低后续工序中的品质异常，提升阵列基板的产品良率。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术阵列基板制造过程示意图。
图2是本申请第一种实施方式阵列基板制造方法流程示意图。
图3-图7是本申请第一种实施方式阵列基板制造方法过程示意图。
图8是本申请第二种实施方式阵列基板制造方法流程示意图。
图9-图11是本申请第二种实施方式阵列基板制造方法过程示意图。
图12是本申请第三种实施方式阵列基板制造方法流程示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请以下实施例中所采用的序数限定词，第一、第二等仅是为了清楚地说明本申请中相似的特征的区别性的用语，不代表相应的特征的排列顺序或者 使用顺序。
请参阅图2，图2为本申请第一种实施方式的阵列基板的制造方法流程示意图。本申请的阵列基板的制造方法主要包括如下步骤：
步骤S101：提供一衬底基板，在所述衬底基板上依次形成第一金属保护层、第一金属导电层和第二金属保护层。
具体的，请结合参阅图3。可以在衬底基板201上采用溅射或热蒸发的方法依次形成第一金属保护层202和第一金属导电层203和第二金属保护层204。所述第一金属保护层202和所述第二金属保护层204的作用在于防止所述第一金属导电层203中的金属扩散到衬底基板201上的其他层结构中，以免降低阵列基板的性能。可以理解的是，所述第一金属导电层203的金属活动性大于所述第一金属导电层203及所述第二金属保护层204的金属活动性。所述第一金属保护层202和所述第二金属保护层204的材料可以相同也可以不相同。本申请一种可能的实现方式中，所述第一金属保护层202和所述第二金属保护层204的材料可以皆为钼(Mo)，所述第一金属导电层203的材料可以为铝(Al)。可以理解的是，本申请的其他实施方式中，所述第一金属保护层202、所述第二金属保护层204、所述第一金属导电层203不限于为上述金属材料。
步骤S102：在所述第二金属保护层204上方层叠设置第二金属导电层205。
具体的，请结合参阅图4。可以采用溅射或热蒸发的方法在所述第二金属保护层204上方沉积第二金属导电层205。所述第二金属导电层205覆盖于所述第二金属保护层204上方。所述第二金属导电层205的材料可以与所述第一金属导电层203的材料相同。
可以理解的是，所述第一金属导电层203和第二金属导电层205的厚度越大，其进行蚀刻所需的时间越长。蚀刻过程中在第二金属导电层205及第二金属导电层205侧壁上形成的凹陷也就越大。所述优选的，所述第一金属导电层203和所述第二金属导电层205的厚度皆小于3000A。进一步优选的，所述第一金属导电层203及所述第二金属导电层205的厚度介于1000A～3000A之间。所述这样设置的目的在于，避免后续的蚀刻过程中在第一金属导电层203及第二金属导电层205的侧壁上形成较大的凹陷。
步骤S103：在所述第二金属导电层205表面覆盖第三金属保护层206。
具体的，请结合参阅图5。所述第三金属保护层206可以与所述第一金属保护层202和所述第二金属保护层204的材料相同。也就是说，所述第二金属导电层205介于所述第二金属保护层204与所述第三金属保护层206之间。第二金属保护层204与所述第三金属保护层206共同防止所述第三金属导电层向阵列基板的其他层结构扩散。可以理解的是，本申请的表面为各层结构之远离所述衬底基板201的面。
步骤S104：在所述第三金属保护层206表面覆盖光阻图案层。
具体的，请结合参阅图6。可以在所述第三金属保护层206上涂覆光刻胶，然后通过掩膜版蚀刻工艺形成所述光阻图案层207。可以理解的是，所述光阻图案层207上包括图案区和镂空区208。
步骤S105：透过所述光阻图案层207由所述第三金属保护层206蚀刻至所述第一金属保护层202，以形成沟道210。
具体的，请结合参阅图7。可以采用湿法蚀刻对阵列基板进行蚀刻。在所述光阻图案层207上喷淋蚀刻液，蚀刻液经由所述光阻图案层207上的镂空区依次蚀刻第三金属保护层206、第二金属导电层205、第二金属保护层204、第一金属导电层203和第一金属保护层202。以在上述的层结构上共同形成沟道。可以理解的是，该沟道用于电子迁移。
可以理解的是，所述镂空区208的面积越大，其形成沟道210过程中的蚀刻时间越长。因此，为了保证在第一金属导电层203/第二金属导电层205上形成的凹陷较小，应当减小大镂空区域对应的第一金属导电层203/第二金属导电层205的厚度。也就是说，所述光阻图案层207镂空区208的面积越大，所述第一金属导电层203及所述第二金属导电层205的厚度越小。
进一步具体的，对于阵列基本中间区域对应的光阻图案层207镂空区208的面积大于其***区域上对应的光阻图案层207镂空区208的面积。也就是说，在***线路区域，刻蚀过程中***线路区域，湿法蚀刻后的凹陷较大。因此，也可以减小***区域中单层金属导电层的厚度一减小凹陷带来的不良影响。
进一步具体的，所述湿法蚀刻采用的蚀刻液可以包括H2O2、金属螯合剂或有机酸。
可以理解的是，在形成所述沟道还包括去除所述光阻图案层207的过程。进一步具体的，可以通过湿法蚀刻的方法去除所述光阻图案层207，从而形成 如图7所示的阵列基板。
本申请第一种实施方式的阵列基板的制造方法中，通过在衬底基板上形成两层金属导电层，并且金属导电层外表面通过金属保护层进行保护，通过增加金属导电层的层数，从而减小单层金属导电层的厚度，进而减小蚀刻过程中在金属导电层侧壁上形成的凹陷的深度，降低后续工序中的品质异常，提升阵列基板的产品良率。
请参阅图8，图8为本申请第二种实施方式的阵列基板的制造方法流程示意图。本申请的阵列基板的制造方法主要包括如下步骤：
步骤S201：提供一衬底基板，在所述衬底基板上依次形成第一金属保护层、第一金属导电层和第二金属保护层。
步骤S202：在所述第二金属保护层上方层叠设置第二金属导电层。
具体的，步骤S202包括：
步骤S2021：在所述第二金属保护层表面覆盖第三金属导电层。
步骤S2022：在所述第三金属导电层表面覆盖第四金属保护层。
步骤S2023：在所述第四金属导电层表面覆盖所述第二金属导电层。
请结合参阅图9。也就是说，所述第一金属保护层202、所述第一金属导电层203、所述第二金属保护层204、所述第三金属导电层211、所述第四金属保护层212和所述第二金属导电层205依次层叠设置于所述衬底基板201上。所述第二金属保护层204与所述第二金属导电层205之间层叠设置有第三金属导电层211和第四金属保护层212。
步骤S203：在所述第二金属导电层205表面覆盖第三金属保护层206。
具体的，所述第三金属保护层206可以与所述第一金属保护层202和所述第二金属保护层204、所述第四金属保护层212的材料相同。所述第一金属导电层203、所述第二金属导电层205和所述第三金属导电层211的材料可以相同。
步骤S204：在所述第三金属保护层206表面覆盖光阻图案层。
具体的，请结合参阅图10。可以在所述第三金属保护层206上涂覆光刻胶，然后通过掩膜版蚀刻工艺形成所述光阻图案层207。可以理解的是，所述光阻图案层上包括图案区和镂空区208。
步骤S205：透过所述光阻图案层由所述第三金属保护层206蚀刻至所述第一金属保护层202，以形成沟道。
具体的，请结合参阅图11。可以采用湿法蚀刻对阵列基板进行蚀刻。在所述光阻图案层上喷淋蚀刻液，蚀刻液经由所述光阻图案层上的镂空区依次蚀刻第三金属保护层206、第二金属导电层205、第四金属保护层212、第三金属导电层211、第二金属保护层204、第一金属导电层203和第一金属保护层202。以在上述的层结构上共同形成沟道210。可以理解的是，该沟道210用于电子迁移。
进一步具体的，所述湿法蚀刻采用的蚀刻液可以包括H2O2、金属螯合剂或有机酸。
可以理解的是，在形成所述沟道还包括去除所述光阻图案层207的过程。进一步具体的，可以通过湿法蚀刻的方法去除所述光阻图案层，从而形成如图11所示的阵列基板。
本申请第一种实施方式的阵列基板的制造方法中，通过在衬底基板上形成三层金属导电层，并且金属导电层外表面通过金属保护层进行保护，通过增加金属导电层的层数，从而减小单层金属导电层的厚度，进而减小蚀刻过程中在金属导电层侧壁上形成的凹陷的深度，降低后续工序中的品质异常，提升阵列基板的产品良率。
请参阅图12，图12为本申请第三种实施方式的阵列基板的制造方法流程示意图。本申请的阵列基板的制造方法主要包括如下步骤：
步骤S301：提供一衬底基板，在所述衬底基板上依次形成第一金属保护层、第一金属导电层和第二金属保护层。
步骤S302：在所述第二金属保护层上方层叠设置第二金属导电层。
具体的，包括：
步骤S3021：在所述第二金属保护层表面覆盖间隔层，其中，所述间隔层包括多个间隔设置的第三金属导电层和第四金属保护层，位于最下方的所述第三金属导电层覆盖于所述第二金属保护层上方。
可以理解的是，所述第三金属导电层的数量和所述第四金属保护层的数量相同。所述第三金属导电层及所述第四金属保护层212的数量可以为1、2、3、4、6……。可以理解的是，为了不增加阵列基板的总体厚度，所述第三金属导 电层及所述第四金属保护层的数量越多，其自个的厚度也就越小，相应的在各个金属导电层上形成的凹陷也就越小。
步骤S3022：在最上方的所述第四金属保护层表面覆盖所述第二金属导电层。
步骤S303：在所述第二金属导电层表面覆盖第三金属保护层。
具体的，所述第三金属保护层可以与所述第一金属保护层和所述第二金属保护层、所述第四金属保护层的材料相同。所述第一金属导电层、所述第二金属导电层和所述第三金属导电层的材料可以相同。
步骤S304：在所述第三金属保护层表面覆盖光阻图案层。
具体的，可以在所述第三金属保护层上涂覆光刻胶，然后通过掩膜版蚀刻工艺形成所述光阻图案层。可以理解的是，所述光阻图案层上包括图案区和镂空区。
步骤S305：透过所述光阻图案层由所述第三金属保护层206蚀刻至所述第一金属保护层，以形成沟道。
具体的，可以采用湿法蚀刻对阵列基板进行蚀刻。在所述光阻图案层上喷淋蚀刻液，蚀刻液经由所述光阻图案层上的镂空区依次蚀刻第三金属保护层、第二金属导电层、间隔层(即多个第四金属保护层和第三金属导电层)、第二金属保护层、第一金属导电层和第一金属保护层。以在上述的层结构上共同形成沟道。可以理解的是，该沟道用于电子迁移。
进一步具体的，所述湿法蚀刻采用的蚀刻液可以包括H2O2、金属螯合剂或有机酸。
可以理解的是，在形成所述沟道还包括去除所述光阻图案层的过程。进一步具体的，可以通过湿法蚀刻的方法去除所述光阻图案层。
本申请第三种实施方式的阵列基板的制造方法中，通过在衬底基板上形成多层金属导电层，并且金属导电层外表面通过金属保护层进行保护，通过增加金属导电层的层数，从而减小单层金属导电层的厚度，进而减小蚀刻过程中在金属导电层侧壁上形成的凹陷的深度，降低后续工序中的品质异常，提升阵列基板的产品良率。
以上对本申请实施例进行了详细介绍，本文中应用了具体个例对本申请的 原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的一般技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (16)

  1. 一种阵列基板的制造方法，其特征在于，包括如下步骤：
    提供一衬底基板，在所述衬底基板上依次形成第一金属保护层、第一金属导电层和第二金属保护层；
    在所述第二金属保护层上方层叠设置第二金属导电层；
    在所述第二金属导电层表面覆盖第三金属保护层；
    在所述第三金属保护层表面覆盖光阻图案层；
    透过所述光阻图案层由所述第三金属保护层蚀刻至所述第一金属保护层，以形成沟道。
  2. 如权利要求1所述的阵列基板的制造方法，其特征在于，所述在所述第二金属保护层上方层叠设置第二金属导电层包括：在所述第二金属保护层表面形成所述第二金属导电层，所述第二金属导电层覆盖于所述第二金属保护层。
  3. 如权利要求1所述的阵列基板的制造方法，其特征在于，所述在所述第二金属保护层上方层叠设置第二金属导电层包括：
    在所述第二金属保护层表面覆盖第三金属导电层；
    在所述第三金属导电层表面覆盖第四金属保护层；
    在所述第四金属导电层表面覆盖所述第二金属导电层。
  4. 如权利要求1所述的阵列基板的制造方法，其特征在于，所述在所述第二金属保护层上方层叠设置第二金属导电层包括：
    在所述第二金属保护层表面覆盖间隔层，其中，所述间隔层包括多个间隔设置的第三金属导电层和第四金属保护层，位于最下方的所述第三金属导电层连接并覆盖于所述第二金属保护层上方；
    在最上方的所述第四金属保护层表面覆盖所述第二金属导电层。
  5. 如权利要求1所述的阵列基板的制造方法，其特征在于，所述第一金属导电层及所述第二金属导电层的厚度小于或等于3000A。
  6. 如权利要求1所述的阵列基板的制造方法，其特征在于，形成所述沟道后，所述方法还包括通过湿法蚀刻去除所述光阻图案层。
  7. 如权利要求1所述的阵列基板的制造方法，其特征在于，所述光阻图 案层镂空区的面积越大，所述第一金属导电层及所述第二金属导电层的厚度越小。
  8. 如权利要求1所述的阵列基板的制造方法，其特征在于，透过所述光阻图案层由所述第三金属保护层采用湿法蚀刻至所述第一金属保护层，以形成沟道。
  9. 如权利要求8所述的阵列基板的制造方法，其特征在于，所述湿法蚀刻采用的蚀刻液包括H2O2、金属螯合剂或有机酸。
  10. 一种阵列基板，其特征在于，包括衬底基板及依次层叠于所述衬底基板的第一金属保护层、第一金属导电层、第二金属保护层，及层叠设置于所述第二金属保护层上方的第二金属导电层、覆盖所述第二金属导电层表面的第三金属保护层，由所述第三金属保护层至所述第一金属保护层上形成有相互连通的通孔以形成沟道。
  11. 如权利要求10所述的阵列基板，其特征在于，还包括第三金属导电层和所述第四金属保护层，所述第三金属导电层覆盖于所述第二金属保护层表面，所述第四金属保护层介于所述第三金属导电层与所述第二金属导电层之间。
  12. 如权利要求10所述的阵列基板，其特征在于，还包括多个间隔设置的第三金属导电层和第四金属保护层，位于最下方的所述第三金属导电层覆盖于所述第二金属保护层表面，位于在最上方的所述第四金属保护层表面覆盖所述第二金属导电层。
  13. 如权利要求10所述的阵列基板，其特征在于，所述第一金属导电层及所述第二金属导电层的材料相同。
  14. 如权利要求13所述的阵列基板，其特征在于，所述第一金属导电层及所述第二金属导电层的材料为铝。
  15. 如权利要求10所述的阵列基板，其特征在于，所述第一金属保护层、所述第二金属保护层及所述第三金属保护层材料相同。
  16. 如权利要求15所述的阵列基板，其特征在于，所述第一金属保护层、所述第二金属保护层及所述第三金属保护层材料为钼。
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