WO2018209599A1 - Substrat de réseau et son procédé de fabrication - Google Patents

Substrat de réseau et son procédé de fabrication Download PDF

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Publication number
WO2018209599A1
WO2018209599A1 PCT/CN2017/084720 CN2017084720W WO2018209599A1 WO 2018209599 A1 WO2018209599 A1 WO 2018209599A1 CN 2017084720 W CN2017084720 W CN 2017084720W WO 2018209599 A1 WO2018209599 A1 WO 2018209599A1
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WO
WIPO (PCT)
Prior art keywords
metal
layer
protective layer
conductive layer
metal conductive
Prior art date
Application number
PCT/CN2017/084720
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English (en)
Chinese (zh)
Inventor
钱俊
叶江波
肖禄
Original Assignee
深圳市柔宇科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市柔宇科技有限公司 filed Critical 深圳市柔宇科技有限公司
Priority to CN201780004625.7A priority Critical patent/CN108701695A/zh
Priority to PCT/CN2017/084720 priority patent/WO2018209599A1/fr
Publication of WO2018209599A1 publication Critical patent/WO2018209599A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs

Definitions

  • the present application relates to the field of display technologies, and in particular, to an array substrate and a method of fabricating the same.
  • a molybdenum (Mo)-aluminum (Al)-molybdenum (Mo) structure is generally used in the array substrate as the source and drain layer 10 of the array substrate (as shown in FIG. 1a).
  • an electric field is formed between the side surface of the first molybdenum layer 11 and the upper surface of the aluminum layer 12 (as shown in FIG. 1b), thereby causing electrochemical corrosion, resulting in the first molybdenum layer.
  • the etching rate of 11 is lowered while the etching rate of the aluminum layer 12 is increased.
  • a large recess 14 is formed on the side of the aluminum layer 12 (as shown in FIG. 1c), and the subsequent film structure cannot completely cover the inner surface of the recess 14, resulting in abnormal quality of the array substrate.
  • the purpose of the present application is to provide an array substrate and a manufacturing method thereof, which can reduce the depression formed on the metal conductive layer during the manufacturing process and improve the quality of the array substrate.
  • the application provides a method for manufacturing an array substrate, comprising the following steps:
  • the third metal protective layer is etched through the photoresist pattern layer to the first metal protective layer to form a channel.
  • the present application also provides an array substrate including a substrate substrate and sequentially stacked on the substrate substrate a first metal protective layer, a first metal conductive layer, a second metal protective layer, and a second metal conductive layer stacked over the second metal protective layer and a third metal covering the surface of the second metal conductive layer
  • the protective layer is formed with through holes communicating with each other from the third metal protective layer to the first metal protective layer to form a channel.
  • the method for fabricating the array substrate of the present application by forming a plurality of metal conductive layers on the base substrate, and protecting the outer surface of the metal conductive layer by a metal protective layer, by increasing the number of layers of the metal conductive layer, the single layer is reduced.
  • the thickness of the metal conductive layer further reduces the depth of the recess formed on the sidewall of the metal conductive layer during the etching process, reduces the quality abnormality in the subsequent process, and improves the product yield of the array substrate.
  • FIG. 1 is a schematic view showing a manufacturing process of a prior art array substrate.
  • FIG. 2 is a schematic flow chart of a method for fabricating an array substrate according to a first embodiment of the present application.
  • 3 to 7 are schematic views showing the process of manufacturing the array substrate according to the first embodiment of the present application.
  • FIG. 8 is a schematic flow chart of a method for fabricating an array substrate according to a second embodiment of the present application.
  • FIG. 9 to FIG. 11 are schematic diagrams showing the process of manufacturing the array substrate according to the second embodiment of the present application.
  • FIG. 12 is a schematic flow chart of a method for fabricating an array substrate according to a third embodiment of the present application.
  • FIG. 2 is a schematic flow chart of a method for manufacturing an array substrate according to a first embodiment of the present application.
  • the manufacturing method of the array substrate of the present application mainly includes the following steps:
  • Step S101 providing a base substrate on which a first metal protective layer, a first metal conductive layer and a second metal protective layer are sequentially formed.
  • the first metal protective layer 202 and the first metal conductive layer 203 and the second metal protective layer 204 may be sequentially formed on the base substrate 201 by sputtering or thermal evaporation.
  • the functions of the first metal protection layer 202 and the second metal protection layer 204 are to prevent the metal in the first metal conductive layer 203 from diffusing into other layer structures on the substrate substrate 201, so as not to reduce the array substrate. performance. It can be understood that the metal mobility of the first metal conductive layer 203 is greater than the metal mobility of the first metal conductive layer 203 and the second metal protective layer 204.
  • the materials of the first metal protective layer 202 and the second metal protective layer 204 may be the same or different.
  • the materials of the first metal protection layer 202 and the second metal protection layer 204 may both be molybdenum (Mo), and the material of the first metal conductive layer 203 may be aluminum. (Al). It is to be understood that, in other embodiments of the present application, the first metal protection layer 202, the second metal protection layer 204, and the first metal conductive layer 203 are not limited to the above metal materials.
  • Step S102 Laying a second metal conductive layer 205 over the second metal protection layer 204.
  • a second metal conductive layer 205 may be deposited over the second metal cap layer 204 by sputtering or thermal evaporation.
  • the second metal conductive layer 205 covers the second metal protection layer 204.
  • the material of the second metal conductive layer 205 may be the same as the material of the first metal conductive layer 203.
  • the depression formed on the sidewalls of the second metal conductive layer 205 and the second metal conductive layer 205 during etching is also greater.
  • the thickness of the first metal conductive layer 203 and the second metal conductive layer 205 are both less than 3000A.
  • the first metal conductive layer 203 and the second metal conductive layer 205 have a thickness of between 1000A and 3000A. The purpose of the arrangement is to prevent large depressions from being formed on the sidewalls of the first metal conductive layer 203 and the second metal conductive layer 205 during the subsequent etching process.
  • Step S103 covering the surface of the second metal conductive layer 205 with the third metal protective layer 206.
  • the third metal protective layer 206 may be the same material as the first metal protective layer 202 and the second metal protective layer 204. That is, the second metal conductive layer 205 is interposed between the second metal protective layer 204 and the third metal protective layer 206. The second metal protective layer 204 and the third metal protective layer 206 together prevent diffusion of the third metal conductive layer to other layer structures of the array substrate. It can be understood that the surface of the present application is a face of each layer structure away from the base substrate 201.
  • Step S104 covering the surface of the third metal protective layer 206 with a photoresist pattern layer.
  • a photoresist may be coated on the third metal protective layer 206, and then the photoresist pattern layer 207 may be formed by a mask etching process. It can be understood that the photoresist pattern layer 207 includes a pattern region and a hollow region 208.
  • Step S105 etching the third metal protective layer 206 to the first metal protective layer 202 through the photoresist pattern layer 207 to form the channel 210.
  • the array substrate can be etched using wet etching.
  • An etchant is sprayed on the photoresist pattern layer 207, and the etchant sequentially etches the third metal protective layer 206, the second metal conductive layer 205, and the second metal protective layer 204 via the hollow regions on the photoresist pattern layer 207.
  • the channel is formed together in the above layer structure. It will be appreciated that the channel is used for electron transfer.
  • the thickness of the first metal conductive layer 203 / the second metal conductive layer 205 corresponding to the large hollow region should be reduced. That is, the larger the area of the photoresist pattern layer 207 hollowed out region 208, the smaller the thickness of the first metal conductive layer 203 and the second metal conductive layer 205.
  • the area of the photoresist pattern layer 207 corresponding to the substantially intermediate region of the array is larger than the area of the corresponding photoresist pattern layer 207 hollow region 208 on the peripheral region. That is to say, in the peripheral line region, the peripheral line region during the etching process has a large recess after the wet etching. Therefore, it is also possible to reduce the thickness of the single-layer metal conductive layer in the peripheral region, and to reduce the adverse effects caused by the depression.
  • the etching solution used in the wet etching may include H 2 O 2 , a metal chelating agent or an organic acid.
  • the process of forming the trench further includes removing the photoresist pattern layer 207. Further specifically, the photoresist pattern layer 207 may be removed by a wet etching method to form The array substrate shown in FIG.
  • the method for fabricating an array substrate according to the first embodiment of the present application by forming two metal conductive layers on the base substrate, and protecting the outer surface of the metal conductive layer by a metal protective layer, by increasing the number of layers of the metal conductive layer, Thereby, the thickness of the single-layer metal conductive layer is reduced, thereby reducing the depth of the recess formed on the sidewall of the metal conductive layer during the etching process, reducing the quality abnormality in the subsequent process, and improving the product yield of the array substrate.
  • FIG. 8 is a schematic flow chart of a method for manufacturing an array substrate according to a second embodiment of the present application.
  • the manufacturing method of the array substrate of the present application mainly includes the following steps:
  • Step S201 providing a base substrate on which a first metal protective layer, a first metal conductive layer and a second metal protective layer are sequentially formed.
  • Step S202 laminating a second metal conductive layer over the second metal protection layer.
  • step S202 includes:
  • Step S2021 covering the surface of the second metal protective layer with the third metal conductive layer.
  • Step S2022 covering the surface of the third metal conductive layer with a fourth metal protective layer.
  • Step S2023 covering the surface of the fourth metal conductive layer with the second metal conductive layer.
  • the first metal protective layer 202, the first metal conductive layer 203, the second metal protective layer 204, the third metal conductive layer 211, the fourth metal protective layer 212, and the The second metal conductive layer 205 is sequentially stacked on the base substrate 201.
  • a third metal conductive layer 211 and a fourth metal protective layer 212 are stacked between the second metal protective layer 204 and the second metal conductive layer 205.
  • Step S203 covering the surface of the second metal conductive layer 205 with the third metal protective layer 206.
  • the third metal protection layer 206 may be the same material as the first metal protection layer 202 and the second metal protection layer 204 and the fourth metal protection layer 212.
  • the materials of the first metal conductive layer 203, the second metal conductive layer 205, and the third metal conductive layer 211 may be the same.
  • Step S204 covering the surface of the third metal protection layer 206 with a photoresist pattern layer.
  • a photoresist may be coated on the third metal protective layer 206, and then the photoresist pattern layer 207 may be formed by a mask etching process. It can be understood that the photoresist pattern layer includes a pattern region and a hollow region 208.
  • Step S205 etching the third metal protective layer 206 to the first metal protective layer 202 through the photoresist pattern layer to form a channel.
  • the array substrate can be etched using wet etching. Spraying an etchant on the photoresist pattern layer, and etching the third metal protective layer 206, the second metal conductive layer 205, the fourth metal protective layer 212, and the etchant sequentially through the hollow regions on the photoresist pattern layer.
  • the channel 210 is formed in common on the above layer structure. It will be appreciated that the channel 210 is used for electron transfer.
  • the etching solution used in the wet etching may include H 2 O 2 , a metal chelating agent or an organic acid.
  • the process of forming the trench further includes removing the photoresist pattern layer 207. More specifically, the photoresist pattern layer may be removed by a wet etching method to form an array substrate as shown in FIG.
  • the method for fabricating an array substrate according to the first embodiment of the present application by forming a three-layer metal conductive layer on the base substrate, and protecting the outer surface of the metal conductive layer by a metal protective layer, by increasing the number of layers of the metal conductive layer, Thereby, the thickness of the single-layer metal conductive layer is reduced, thereby reducing the depth of the recess formed on the sidewall of the metal conductive layer during the etching process, reducing the quality abnormality in the subsequent process, and improving the product yield of the array substrate.
  • FIG. 12 is a schematic flow chart of a method for manufacturing an array substrate according to a third embodiment of the present application.
  • the manufacturing method of the array substrate of the present application mainly includes the following steps:
  • Step S301 providing a substrate on which a first metal protective layer, a first metal conductive layer and a second metal protective layer are sequentially formed.
  • Step S302 Laying a second metal conductive layer on top of the second metal protective layer.
  • Step S3021 covering the surface of the second metal protective layer with a spacer layer, wherein the spacer layer comprises a plurality of spaced apart third metal conductive layers and a fourth metal protective layer, and the third metal conductive layer located at the bottom A layer covers the second metal protective layer.
  • the number of the third metal conductive layers is the same as the number of the fourth metal protective layers.
  • the number of the third metal conductive layer and the fourth metal protective layer 212 may be 1, 2, 3, 4, 6, . It can be understood that the third metal guide is not increased in order to increase the overall thickness of the array substrate. The more the number of the electric layer and the fourth metal protective layer, the smaller the thickness of the self-contained layer, and the smaller the depression formed on each of the metal conductive layers.
  • Step S3022 covering the second metal conductive layer on the surface of the fourth metal protective layer at the top.
  • Step S303 covering a surface of the second metal conductive layer with a third metal protective layer.
  • the third metal protective layer may be the same material as the first metal protective layer and the second metal protective layer and the fourth metal protective layer.
  • the materials of the first metal conductive layer, the second metal conductive layer, and the third metal conductive layer may be the same.
  • Step S304 covering the surface of the third metal protective layer with a photoresist pattern layer.
  • a photoresist may be coated on the third metal protective layer, and then the photoresist pattern layer is formed by a mask etching process. It can be understood that the photoresist pattern layer includes a pattern area and a hollow area.
  • Step S305 etching the third metal protective layer 206 to the first metal protective layer through the photoresist pattern layer to form a channel.
  • the array substrate can be etched by wet etching. Spraying an etchant on the photoresist pattern layer, the etchant sequentially etching the third metal protective layer, the second metal conductive layer, and the spacer layer via the hollow region on the photoresist pattern layer (ie, a plurality of fourth metal protection layers) a layer and a third metal conductive layer), a second metal protective layer, a first metal conductive layer, and a first metal protective layer.
  • the channel is formed together in the above layer structure. It will be appreciated that the channel is used for electron transfer.
  • the etching solution used in the wet etching may include H 2 O 2 , a metal chelating agent or an organic acid.
  • the process of forming the trench further includes removing the photoresist pattern layer. More specifically, the photoresist pattern layer can be removed by a wet etching method.
  • the method for fabricating the array substrate of the third embodiment of the present application by forming a plurality of metal conductive layers on the base substrate, and protecting the outer surface of the metal conductive layer by the metal protective layer, by increasing the number of layers of the metal conductive layer, Thereby, the thickness of the single-layer metal conductive layer is reduced, thereby reducing the depth of the recess formed on the sidewall of the metal conductive layer during the etching process, reducing the quality abnormality in the subsequent process, and improving the product yield of the array substrate.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • ing And Chemical Polishing (AREA)
  • Rolling Contact Bearings (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

L'invention concerne un substrat de réseau et son procédé de fabrication, le procédé comprenant les étapes suivantes consistant à : fournir un substrat (201), et former une première couche de protection de métal (202), une première couche conductrice métallique (203) et une deuxième couche de protection de métal (204) sur le substrat (201) dans cet ordre; empiler une seconde couche conductrice métallique (205) sur la deuxième couche de protection de métal (204); couvrir une troisième couche de protection de métal (206) sur une surface de la deuxième couche conductrice métallique (205); couvrir une couche de résine photosensible à motifs (207) sur une surface de la troisième couche de protection de métal (206); et graver depuis la troisième couche de protection de métal (206) jusqu'à la première couche de protection de métal (202) à travers la couche de résine photosensible à motifs (207) pour former un canal (210). La formation de plusieurs couches conductrices métalliques sur le substrat, la protection des surfaces externes des couches conductrices métalliques par des couches de protection de métal, et l'augmentation du nombre de couches conductrices métalliques, permet de réduire l'épaisseur d'une unique couche conductrice métallique en conséquence, ce qui permet de réduire la profondeur d'un évidement formé sur les parois latérales des couches conductrices métalliques lors du processus de gravure, de telle sorte que des problèmes de qualité dans des processus ultérieurs sont réduits, et par conséquent le rendement de produit du substrat de réseau est amélioré.
PCT/CN2017/084720 2017-05-17 2017-05-17 Substrat de réseau et son procédé de fabrication WO2018209599A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201780004625.7A CN108701695A (zh) 2017-05-17 2017-05-17 阵列基板及其制造方法
PCT/CN2017/084720 WO2018209599A1 (fr) 2017-05-17 2017-05-17 Substrat de réseau et son procédé de fabrication

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2017/084720 WO2018209599A1 (fr) 2017-05-17 2017-05-17 Substrat de réseau et son procédé de fabrication

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WO2018209599A1 true WO2018209599A1 (fr) 2018-11-22

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Citations (3)

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CN102912350A (zh) * 2012-07-24 2013-02-06 友达光电股份有限公司 蚀刻液及形成图案化多层金属层的方法
CN105742167A (zh) * 2014-12-08 2016-07-06 天津恒电空间电源有限公司 一种能够与玻璃牢固结合的多层金属电极的制备方法

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JP4142084B2 (ja) * 2006-10-16 2008-08-27 三菱電機株式会社 半導体光素子の製造方法
CN101685229B (zh) * 2008-09-25 2012-02-29 北京京东方光电科技有限公司 液晶显示器阵列基板的制造方法
JP2010212336A (ja) * 2009-03-09 2010-09-24 Fujifilm Corp 光電変換素子とその製造方法、及び太陽電池
KR101766488B1 (ko) * 2011-12-15 2017-08-09 동우 화인켐 주식회사 금속 배선 형성을 위한 식각액 조성물
CN103560113B (zh) * 2013-11-15 2017-02-01 北京京东方光电科技有限公司 一种阵列结构及其制作方法、阵列基板和显示装置

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Publication number Priority date Publication date Assignee Title
CN1501474A (zh) * 2002-11-15 2004-06-02 Nec液晶技术株式会社 用于改善腐蚀性和耐热性的包含多层金属膜叠层的互连
CN102912350A (zh) * 2012-07-24 2013-02-06 友达光电股份有限公司 蚀刻液及形成图案化多层金属层的方法
CN105742167A (zh) * 2014-12-08 2016-07-06 天津恒电空间电源有限公司 一种能够与玻璃牢固结合的多层金属电极的制备方法

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