WO2018188300A1 - 阵列基板栅极驱动电路及其驱动方法和显示装置 - Google Patents

阵列基板栅极驱动电路及其驱动方法和显示装置 Download PDF

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Publication number
WO2018188300A1
WO2018188300A1 PCT/CN2017/106921 CN2017106921W WO2018188300A1 WO 2018188300 A1 WO2018188300 A1 WO 2018188300A1 CN 2017106921 W CN2017106921 W CN 2017106921W WO 2018188300 A1 WO2018188300 A1 WO 2018188300A1
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Prior art keywords
shift register
output
reset
terminal
array substrate
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PCT/CN2017/106921
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English (en)
French (fr)
Inventor
白雅杰
许卓
张元波
方琰
邓鸣
唐子杰
金在光
Original Assignee
京东方科技集团股份有限公司
重庆京东方光电科技有限公司
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Priority to US15/774,442 priority Critical patent/US10916178B2/en
Publication of WO2018188300A1 publication Critical patent/WO2018188300A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present disclosure relates to an array substrate gate driving circuit, a driving method thereof, and a display device.
  • the Gate Driver on Array (GOA) technology integrates the gate drive circuit into the display panel through a thin film transistor process to reduce the cost of the gate drive circuit in the panel. Since the gate drive circuit bonding is not required, the GOA technology can also increase the MDL process capacity and realize the narrow bezel design of the display panel.
  • a GOA circuit typically includes a plurality of cascaded shift registers.
  • a Total Reset function may be added for the GOA circuit, that is, during the blanking period between the two frames (ie, Starting from the completion of the reset of the pull-up node and the output terminal of the shift register of the last stage in each shift register group in the GOA circuit, to the first-stage shift register reception in each shift register group
  • the full reset signal provided by the separately set clock control circuit (T-CON) is used for all the shift registers of the GOA circuit.
  • the pull-up node and/or the output are simultaneously reset or initialized.
  • the shift register in the GOA circuit may still be interfered by external factors before receiving the input signal after the full reset, and the later the connection position, the possibility of interference The greater the sex.
  • the STV signal can be used as the full reset signal TRST, and A certain time period between two frames (eg, blanking period) is simultaneously transmitted to each shift register in the GOA circuit of the television product.
  • TRST full reset signal
  • a certain time period between two frames eg, blanking period
  • such an implementation significantly increases the load on the STV signal.
  • the STV signal of notebook computers and other products has a limited pulse width. If the full reset function is implemented in the same manner as the TV product, the frame of the product such as a notebook computer will be significantly increased.
  • the approach is to have a separately provided clock control circuit provide a separate full reset signal for a certain period of time between two frames (eg, during blanking).
  • the separately provided clock control circuit needs to output one or two control signals more, and it is necessary to control the transmission timing of the control signals, resulting in very complicated timing control of the signals.
  • the bezel will be increased to varying degrees (depending on the size of the additional transistor), which is not conducive to the narrow bezel design of the display panel.
  • An aspect of the present disclosure relates to an array substrate gate driving circuit including at least one shift register group, each shift register group including a plurality of shift registers cascaded together, the plurality of shift registers including a shift register, a second shift register connected after the first shift register, and a third shift register connected after the second shift register, wherein the third shift register is provided with An initialization terminal, and the initialization terminal is connected to an output of the first shift register.
  • an input of the third shift register can be coupled to an output of the second shift register, and an input of the second shift register can be coupled to the first shift The output of the bit register.
  • a unidirectional conduction element can be provided between the first shift register and the third shift register.
  • An input end of the unidirectional conduction element may serve as an initialization end of the third shift register, and an output end of the unidirectional conduction element may be connected to a reset end of the third shift register.
  • the unidirectional conduction element may include: a first transistor, a source thereof, and The gates are connected together and serve as an input to the unidirectional conduction element, the drain of which serves as the output of the unidirectional conduction element.
  • the full reset terminal can be used as the initialization terminal.
  • the third shift register may include: an initialization sub-circuit that receives an initialization signal via an initialization terminal of the third shift register, and the third shift according to the received initialization signal The potential of the pull-up node in the bit register is reset.
  • the initialization sub-circuit in the third shift register may comprise a first transistor.
  • a source and a gate of the first transistor may be connected together and connected to an initialization terminal of the third shift register, and a drain of the first transistor is connected to a reset terminal of the third shift register .
  • a gate of the first transistor may be connected to an initialization terminal of the third shift register, a source of the first transistor is connected to a pull-up node of the third shift register, and the first The potential of the drain of one transistor is set to the reset potential.
  • the initialization sub-circuit in the third shift register may further include a second transistor.
  • the gate and the source of the second transistor may be connected to the drain of the first transistor and the output of the third shift register, respectively, and the potential of the drain of the second transistor is set to a reset potential .
  • the gate and the source of the second transistor may be respectively connected to the initialization terminal and the output terminal of the third shift register, and the potential of the drain of the second transistor is set to a reset potential.
  • the third shift register may further include: an input sub-circuit that receives an input signal via an input of the third shift register, and controls the upper portion according to the received input signal Pull the potential of the node.
  • the third shift register may further include: an output sub-circuit that receives a clock signal via a clock signal end of the third shift register, and controls the The output of the third shift register outputs the received clock signal.
  • the third shift register may further include: a reset sub-circuit that receives a reset signal via a reset terminal of the third shift register, and the pull-up according to the received reset signal The potential of the node and the output of the third shift register is reset.
  • the number of the at least one shift register set can be set to be half the number of external clock signals received by the array substrate gate drive circuit.
  • Another aspect of the present disclosure relates to a display device including any of the above array substrate grids Pole drive circuit.
  • Yet another aspect of the present disclosure is directed to a driving method of an array substrate gate driving circuit for driving any one of the above array substrate gate driving circuits, wherein, for each first shift register, the method includes: inputting an input signal Providing an input to the first shift register to cause a potential of the pull-up node in the first shift register to become an operating potential; after providing the input signal to the first shift register, The first shift register outputs a gate drive signal at its output, and the output gate drive signal is provided as an initialization signal to the initialization terminal of the third shift register to the third shift register.
  • a potential of the internal pull-up node is reset; and after the first shift register outputs the gate drive signal, the gate drive signal output by the second shift register is supplied to the first shift register
  • the reset terminal resets the potential of the pull-up node in the first shift register and the potential of the output of the first shift register.
  • the shift register for each shift register of at least the third stage in each shift register group, can be used by the connection before starting the operation.
  • the gate drive signal output by the other shift register before the shift register of the shift register is used as an initialization signal, and the pull-up node and/or the shift inside the shift register before starting operation
  • the potential at the output of the internal register is reset or initialized.
  • the array substrate gate driving circuit according to the present disclosure can achieve at least substantially the same technical effect as the method of performing full reset between frames in a step-by-step initialization manner within one frame, and does not increase the STV signal.
  • the load does not need to be separately set to the clock control circuit, the timing control of the signal is simple, the circuit cost is low, and it is universal to various products such as a television set and a notebook computer.
  • FIG. 1 illustrates an exemplary connection manner of a shift register in an array substrate gate drive circuit in accordance with an embodiment of the present disclosure.
  • FIG. 2 illustrates an exemplary structure of a shift register that can be used for an array substrate gate drive circuit in accordance with an embodiment of the present disclosure.
  • FIG. 3 illustrates another alternative that can be used in an array substrate gate drive circuit in accordance with an embodiment of the present disclosure.
  • FIG. 4 illustrates an exemplary operational timing of a shift register in an array substrate gate drive circuit in accordance with an embodiment of the present disclosure.
  • FIG. 5 illustrates another exemplary connection manner of a shift register in an array substrate gate drive circuit in accordance with an embodiment of the present disclosure.
  • FIG. 6 illustrates another exemplary connection manner of a shift register in an array substrate gate drive circuit in accordance with an embodiment of the present disclosure.
  • FIG. 7 illustrates an exemplary structure of a shift register provided with an initialization terminal according to an embodiment of the present disclosure.
  • FIG. 8 illustrates an exemplary structure of a shift register provided with an initialization end according to an embodiment of the present disclosure.
  • FIG. 9 illustrates an exemplary structure of a shift register provided with an initialization terminal according to an embodiment of the present disclosure.
  • FIG. 10 illustrates an exemplary structure of a shift register provided with an initialization end according to an embodiment of the present disclosure.
  • FIG. 11 illustrates an exemplary structure of a shift register provided with an initialization end according to an embodiment of the present disclosure.
  • FIG. 12 illustrates an exemplary structure of a shift register provided with an initialization end according to an embodiment of the present disclosure.
  • FIG. 13 illustrates an exemplary structure of a shift register provided with an initialization end according to an embodiment of the present disclosure.
  • FIG. 14 illustrates an exemplary method for driving a shift register in an array substrate gate drive circuit in accordance with an embodiment of the present disclosure.
  • the array substrate gate driving circuit shown in FIG. 1 includes at least one shift register group, each The shift register set includes a plurality of shift registers.
  • each shift register group the input of the shift register at the first stage receives the STV signal, and the inputs of the other stages of shift registers located after the first stage are respectively connected to their respective previous stages.
  • the output of the shift register receives the gate drive signal of the shift register output of the previous stage as an input signal, thereby cascading a plurality of shift registers in each shift register group.
  • SRi-j denotes a shift register which is cascaded in the jth stage in the i-th shift register group, wherein the shift register SRi-j is located in the shift register SRi-(j) In the upper stage of +1), the shift register SRi-(j+1) is located in the next stage of the shift register SRi-j. Accordingly, OUTPUTi-j represents the gate drive signal output by the shift register SRi-j.
  • the first shift register group includes a plurality of shift registers SR1-1, SR1-2, SR1-3, SR1-4, etc., wherein the shift register SR1- located in the first stage
  • the input terminal INPUT of 1 receives the STV signal; the input terminal INPUT of the shift register SR1-2 located at the second stage is connected to the output terminal OUTPUT of the shift register SR1-1 to receive the gate drive of the output of the shift register SR1-1.
  • the signal OUTPUT1-1 is used as an input signal; the input terminal INPUT of the shift register SR1-3 located in the third stage is connected to the output terminal OUTPUT of the shift register SR1-2 to receive the gate drive signal output from the shift register SR1-2.
  • OUTPUT1-2 is used as an input signal; the input terminal INPUT of the shift register SR1-4 located in the fourth stage is connected to the output terminal OUTPUT of the shift register SR1-3 to receive the gate drive signal OUTPUT1 output from the shift register SR1-3. -3 as an input signal; and so on, thereby cascading a plurality of shift registers such as SR1-1, SR1-2, SR1-3, SR1-4 included in the first shift register group.
  • Each shift register SRi-j is also provided with a clock signal terminal CLK for receiving a clock signal from a corresponding clock signal line (for example, CLK1 to CLK6 shown in FIG. 1) and a reset terminal RESET for receiving a reset signal.
  • the reset terminal RESET of each shift register SRi-j is connected to the output terminal OUTPUT of the shift register SRi-(j+1) cascaded in the next stage to be output using the shift register SRi-(j+1)
  • the gate drive signal OUTPUTi-(j+1) is used as its reset signal. For example, in FIG.
  • the reset terminal RESET of the shift register SR1-1 is connected to the output terminal OUTPUT of the shift register SR1-2 cascaded at its next stage, and the gate outputted by the shift register SR1-2 is used.
  • the pole drive signal OUTPUT1-2 acts as its reset signal.
  • the reset terminal RESET of the shift register SR3-2 is connected to the output terminal OUTPUT of the shift register SR3-3 cascaded at its next stage, and uses the gate drive signal OUTPUT3 outputted by the shift register SR3-3. -3 as its reset signal.
  • each shift register can use a gate drive signal output by any one or more shift registers connected after the shift register as a reset signal.
  • the shift register SR1-1 may use a gate drive signal output by any one or more of the shift registers SR1-2, SR1-3, SR1-4, SR1-5 (not shown) and the like.
  • the shift register SR1-1 may be reset a plurality of times after outputting the gate drive signal OUTPUT1-1, or may be, for example, a clock signal and/or an internal logic control It is only reset once or several times under the control of the circuit.
  • each shift register may also provide its output gate drive signal to the reset terminal of any one or more shift registers connected before the shift register as the one Or a reset signal of multiple shift registers.
  • the output terminal OUTPUT of the shift register SR2-4 can be connected to the reset terminal RESET of any one or more of the shift registers SR2-1, SR2-2, and SR2-3, and the shift register SR2-4
  • the output gate drive signal OUTPUT2-4 is used as a reset signal of any one or more of the shift registers SR2-1, SR2-2, and SR2-3.
  • each shift register SRi-j may supply its output gate drive signal OUTPUTi-j to the reset terminal of any one or more shift registers connected after the shift register SRi-(j+1) RESET, as an initialization signal for initialization of the one or more shift registers before starting operation.
  • the gate drive signal OUTPUTi-j outputted by each shift register SRi-j is also supplied to the reset terminal RESET of the shift register SRi-(j+2).
  • the output terminal OUTPUT of the shift register SR1-1 is also connected to the reset terminal RESET of the shift register SR1-3.
  • the reset terminal RESET of the shift register SRi-(j+2) for example, the shift register SR1-3
  • the output terminal of the shift register SRi-j for example, the shift register SR1-1
  • OUTPUT is connected to the output terminal OUTPUT of the shift register SRi-(j+3) (for example, shift register SR1-4), and the gate drive signal OUTPUTi-(j+ is output in the shift register SRi-(j+3).
  • the shift register SRi-j has completed the output of the gate signal, and the output terminal OUTPUT of the shift register SRi-j should be maintained at the reset potential state at this time.
  • the shift register SRi can be -j output OUTPUT and shift register
  • a one-way switch SWi-(j+2) is provided between the reset ends of SRi-(j+2), wherein the input of the one-way switch SWi-(j+2) is connected to the shift register SRi-j
  • the output terminal OUTPUT has its output connected to the reset terminal RESET of the shift register SRi-(j+2), thereby ensuring that the signal is always unidirectionally transferred from the output terminal OUTPUT of the shift register SRi-j to the shift register SRi-
  • the reset terminal RESET of (j+2) prevents the signal from being transmitted in the opposite direction.
  • a one-way switch SW1-3 may be provided between the output of the shift register SR1-1 and the reset terminal of SR1-3, at the output of the shift register SR3-2 and SR3-
  • a one-way switch SW3-4 is provided between the reset ends of 4.
  • the input terminal of the one-way switch SWi-(j+2) can be regarded as The initialization terminal of the shift register SRi-(j+2), and the gate drive signal OUTPUTi-j provided by the shift register SRi-j can be regarded as the shift register SRi-(j+2) before starting work Initialization signal for initialization.
  • the one-way switch can be implemented using a transistor (such as the one-way switch SW1-3 in FIG. 1).
  • the control terminal and the first terminal of the transistor can be connected together and used as an input of a one-way switch, and the second end of the transistor can be used as an output of a one-way switch.
  • the one-way switch can be implemented with a diode, wherein, for example, the input of the diode is used as the input of a one-way switch, and the output of the diode is used as the output of a one-way switch .
  • the one-way switch can employ any other components and/or circuits suitable for the integrated circuit and having a single-conduction capability.
  • each shift register SRi-j in the array substrate gate driving circuit shown in FIG. 1 may have any suitable circuit structure as needed, and each shift register SRi-j may adopt the same or different circuit as needed. Method to realize.
  • FIG. 2 illustrates an exemplary structure of a shift register that can be used for an array substrate gate drive circuit in accordance with an embodiment of the present disclosure.
  • the shift register shown in FIG. 2 includes an input circuit, an output circuit, and a reset circuit.
  • the input circuit comprises a switching element SW1, wherein the control terminal of the switching element SW1 is connected to the first terminal and serves as the input terminal INPUT of the shift register, and its second terminal is connected to the pull-up node PU in the shift register.
  • the output circuit includes a switching element SW2 and a capacitor C, wherein the control terminal of the switching element SW2 and one end of the capacitor C are connected together to the pull-up node PU, and the first end of the switching element SW2 is connected to the clock signal terminal CLK of the shift register, The second end of the switching element SW2 and the other end of the capacitor C are connected to the output terminal OUTPUT of the shift register.
  • the reset circuit includes a switching element SW3 and a switching element SW4, wherein the switching element SW3 and the switching element SW4 The control terminals are connected together and connected to the reset terminal RESET of the shift register, the first end of the switching element SW3 is connected to the pull-up node PU, and the first end of the switching element SW4 is connected to the output terminal OUTPUT of the shift register, the switch The potential of the second end of the element SW3 and the switching element SW4 is set to the reset potential.
  • the switching elements in the shift register can be any type of transistor, field effect transistor, etc., which is not limited herein.
  • the shift register shown in FIG. 2 starts to operate when an input signal is received via the input terminal INPUT, and the switching element SW1 in the input circuit is turned on, and the pull-up node PU
  • the potential becomes an operating potential (eg, a high level) such that the capacitance C in the output circuit is charged.
  • the switching element SW2 in the output circuit is turned on, thereby outputting the gate driving signal at the output terminal OUTPUT, and the pull-up node PU is bootstrapping due to the capacitance C. It remains at the working potential.
  • the switching elements SW3 and SW4 in the reset circuit are turned on. Since the second ends of the switching elements SW3 and SW4 are set to the reset potential (for example, the low level), the potentials of the pull-up node PU and the output terminal OUTPUT are reset to the reset potential. Then, in the absence of external interference, the potentials of the pull-up node PU and the output terminal OUTPUT are held at the reset potential until the shift register receives the next input signal, thereby avoiding the multi-output causing abnormal display of the picture.
  • the reset potential for example, the low level
  • FIG. 3 illustrates an exemplary structure of another shift register that can be used in an array substrate gate drive circuit in accordance with an embodiment of the present disclosure.
  • the control terminal of the switching element SW4 is not directly connected to the reset terminal RESET of the shift register, but the switching elements SW5 and SW6 are added inside the shift register.
  • the switching element SW3 When the shift register receives the reset signal at its reset terminal RESET, the switching element SW3 is turned on, so that the potential of the pull-up node PU becomes the reset potential, and the switching element SW6 is turned off. Since the switching element SW5 is in an on state, the potential of the pull-down node PD at the first end of the switching element SW6 becomes an operating potential at this time. When the potential of the pull-down node PD becomes the operating potential, the switching element SW4 is turned on, so that the potential of the output terminal OUTPUT of the shift register becomes the reset potential.
  • the shift register in the array substrate gate drive circuit according to the embodiment of the present disclosure shown in FIG. 1 may employ other circuits. structure.
  • the basic functions and basic principles of the various shift registers are the same.
  • CLK1-1-1 and CLK1-1-3 represent clock signals supplied to the shift registers SR1-1 and SR1-3 via the clock signal line CLK1 in FIG. 1
  • CLK4-1-2 and CLK4- 1-4 denotes clock signals supplied to the shift registers SR1-2 and SR1-4 via the clock signal line CLK4 in FIG. 1
  • RESET1-3 denotes the potential of the reset terminal RESET of the shift register SR1-3
  • PU1-3 denotes The potential of the pull-up node PU inside the shift register SR1-3.
  • the timing relationship of the clock signals provided via the clock signal lines CLK1 and CLK4 in FIG. 1 shown in FIG. 4 is merely exemplary.
  • the shift register SR1-1 receives the clock signal CLK1-1-1 (ie, the potential of CLK1-1-1 is an operating potential, for example, a high level).
  • the gate drive signal OUTPUT1-1 is output.
  • the output gate drive signal OUTPUT1-1 will be supplied to the input terminal INPUT of the shift register SR1-2 and the reset terminal RESET of the shift register SR1-3, respectively, so that the potential RESET1 of the reset terminal RESET of the shift register SR1-3 is set. -3 becomes the working potential. Referring to FIG. 2 or FIG.
  • the reset circuit inside the shift register SR1-3 operates, so that the potential PU1-3 of the pull-up node PU inside the shift register SR1-3 and the output terminal of the shift register SR1-3
  • the OUTPUT potential of OUTPUT is the reset potential, thus completing the initialization before starting the operation.
  • the shift register SR1-2 outputs the gate drive signal OUTPUT1-2 and supplies it to the input terminal INPUT of the shift register SR1-3.
  • the shift register SR1-3 in conjunction with FIG. 2 or FIG. 3, has its potential PU1-3 of the pull-up node PU becoming the operating potential, and the capacitor C in the output circuit starts to be charged.
  • the shift register SR1-3 receives the clock signal CLK1-1-3, the potential PU1-3 of the pull-up node PU inside the shift register SR1-3 is maintained at the operating potential due to the bootstrap action of the capacitor C, The output circuit is caused to start operating (i.e., the switching element SW2 in the output circuit is turned on), thereby outputting the gate driving signal OUTPUT1-3 at the output terminal OUTPUT.
  • the output gate drive signal OUTPUT1-3 is simultaneously supplied to the shift register SR1-4 of the next stage as an input signal of the shift register SR1-4.
  • the shift register SR1-3 is at the reset end after outputting the gate drive signal OUTPUT1-3 RESET receives the gate drive signal OUTPUT1-4 output from the shift register SR1-4 so that the potential RESET1-3 of its reset terminal RESET becomes the operating potential again.
  • the reset circuit inside the shift register SR1-3 operates again, so that the potential PU1-3 of the pull-up node PU inside the shift register SR1-3 and the potential OUTPUT1-3 of the output terminal OUTPUT of the shift register SR1-3 Both are reset potentials, thereby completing the reset after the output gate drive signal OUTPUT1-3.
  • the reset terminal RSEET receives the gate drive signal OUTPUTi-j from the shift register SRi-j as its initialization signal to perform the potential of its internal pull-up node PU and/or its output terminal OUTPUT before starting operation. initialization.
  • the array substrate gate driving circuit according to the embodiment of the present disclosure does not increase the load of the STV signal, and does not need to separately set the clock control circuit, the timing control of the signal is simple, the circuit cost is low, and the television, the notebook computer, and the like are The products are universal.
  • the reset is performed immediately after the pole drive signal.
  • the manner in which the initialization signals are provided to the shift registers of each stage shown in FIG. 1 is merely exemplary.
  • the gate drive signal OUTPUTi-j output from the shift register SRi-j may be supplied to the reset terminal RESET of any one or more shift registers connected after the shift register SRi-(j+1), as needed.
  • the output terminal OUTPUT of the shift register SR1-1 may be connected to the reset terminal of the shift register SR1-4 via, for example, the one-way switch SW1-4, or the output terminal OUTPUT of the shift register SR1-1 may be, for example.
  • the output terminal OUTPUT is connected to the reset terminals of the shift registers SR1-3 and SR1-5, for example, via the one-way switch SW1-3 and SW1-5, respectively. If the condition allows (for example, the gate drive signal OUTPUT1-1 output by SR1-1 has a sufficient pulse width), the output terminal OUTPUT of the shift register SR1-1 can be connected to the first via a plurality of one-way switches, respectively.
  • three shift register groups and six clock signal lines CLK1 to CLK6 are shown in FIG. 1, the present disclosure does not limit the number of shift register groups and clock signal lines.
  • one shift register group and two clock signal lines may be provided, or two shift register groups and four clock signal lines may be provided.
  • the relationship between the number of shift register groups and the number of clock signal lines can be set to 1:2. According to the current experimental results, the performance achieved by using three shift register groups and six clock signal lines is relatively good.
  • any one of the shift register in the array substrate gate drive circuit according to the present disclosure may employ any suitable circuit structure.
  • the exemplary shift register shown in FIG. 2 or FIG. 3 and any variations based on the exemplary shift register shown in FIG. 2 or FIG. 3 can be applied to the array substrate gate according to the present disclosure.
  • the drive circuit In the drive circuit.
  • FIG. 5 illustrates another exemplary connection manner of a shift register in an array substrate gate drive circuit in accordance with an embodiment of the present disclosure.
  • the shift register itself supports the full reset function (correspondingly, the full reset terminal TRST and the full reset circuit are provided), as shown in FIG. 5, at the output of the shift register SRi-j and SRi-(j+ 2) between the reset terminals, it is not necessary to set a separate one-way switch SWi-(j+2), but directly use the full reset terminal TRST of the shift register SRi-(j+2) as the initialization end, and Connect it to the output OUTPUT of the shift register SRi-j.
  • a shift register provided with a dedicated initialization terminal may also be employed in the array substrate gate drive circuit according to the present disclosure.
  • FIG. 6 illustrates another exemplary connection manner of a shift register in an array substrate gate drive circuit in accordance with an embodiment of the present disclosure.
  • the shift register SRi-(j+2) is provided with an initialization terminal, and the initialization terminal of the shift register SRi-(j+2) is directly connected to the shift The output OUTPUT of the register SRi-j.
  • the exemplary shift register shown in FIG. 7 is added to the shift register shown in FIG.
  • the initialization circuit may include a switching element SW5, wherein the control terminal and the first terminal of the switching element SW5 are connected together and connected to the initialization terminal INIT of the shift register, the second terminal of the switching element SW5 and the switching element SW3 in the reset circuit It is connected to the control terminal of the switching element SW4 and is connected to the reset terminal RESET of the shift register.
  • the switching element SW5 in the initialization circuit is turned on, so that the switching element SW3 and the switching element SW4 in the reset circuit are turned on, thereby causing the potential of the pull-up node PU and the potential of the output terminal OUTPUT become the reset potential.
  • the shift register is initialized.
  • the exemplary shift register shown in FIG. 8 adds an initialization terminal INIT and an initialization circuit to the shift register shown in FIG.
  • the initialization circuit may include a switching element SW7, wherein the control terminal and the first terminal of the switching element SW7 are connected together and connected to the initialization terminal INIT of the shift register, the second terminal of the switching element SW7 and the switching element SW3 in the reset circuit The control terminals are connected together and connected to the reset terminal RESET of the shift register.
  • the switching element SW7 in the initialization circuit is turned on, so that the potential of the reset terminal RESET of the shift register becomes the potential of the initialization signal. This is equivalent to receiving a reset signal at the reset terminal RESET of the shift register. Therefore, when the initialization signal is received via the initialization terminal INIT, the potential of the pull-up node PU of the shift register and the potential of the output terminal OUTPUT become the reset potential, whereby the shift register completes initialization.
  • the exemplary shift register shown in FIG. 7 or FIG. 8 is equivalent to treating the one-way switch SWi-(j+2) and the shift register SRi-(j+2) in FIG. 1 as a whole, wherein The input terminal of the one-way switch SWi-(j+2) corresponds to the initialization terminal INIT of the shift register SRi-(j+2).
  • FIG. 9 illustrates a variation of a shift register that is further provided with a reverse clock signal terminal CLKB (a clock signal received via CLKB, for example, may be via a clock signal, in accordance with an embodiment of the present disclosure)
  • CLKB a reverse clock signal received via CLKB
  • the clock signal received by the terminal CLK is opposite in phase, and further includes switching elements SW8 to SW13.
  • the basic functions and operating principles of such a shift register are the same as those of the exemplary shift register shown in FIG. 7 or FIG. 8, and thus will not be described herein.
  • FIG. 10 illustrates an exemplary structure of a shift register provided with an initialization terminal and an initialization circuit, according to an embodiment of the present disclosure.
  • the initialization circuit further includes a switching element SW8 whose control terminal is connected to the initialization terminal, the first end of which is connected to the output terminal OUTPUT of the shift register, and the potential of the second terminal is set to reset. Potential REF RESET .
  • the switching element SW8 may not be provided.
  • FIG. 11 shows a variation of the shift register shown in FIG. 10, wherein the shift register further includes switching elements SW9 to SW11.
  • FIG. 11 its basic function and operation principle are the same as those of the exemplary shift register shown in FIG. 10, and thus will not be described herein.
  • FIG. 12 illustrates an exemplary structure of a shift register provided with an initialization terminal and an initialization circuit, according to another embodiment of the present disclosure.
  • the first end of the switching element SW7 in the initialization circuit is connected to the pull-up node PU, the control terminal thereof is connected to the initialization terminal INIT, and the potential of the second terminal thereof is set to the reset potential REF RESET .
  • the shift register receives the initialization signal via the initialization terminal INIT
  • the potential of the pull-up node PU can be directly initialized via the switching element SW7 in the initialization circuit.
  • the initialization circuit may further include a switching element SW8, the first end of which is connected to the output terminal OUTPUT, the control end of which is connected to the initialization terminal INIT, and the potential of the second end thereof is set to the reset potential REF RESET for receiving the initialization signal.
  • the potential of the output terminal OUTPUT is initialized.
  • the switching element SW8 may not be provided.
  • FIG. 13 shows a variation of the shift register shown in FIG. 12, wherein the shift register further includes switching elements SW9 to SW11.
  • the structure of the exemplary shift register shown in FIG. 13 is more complicated, and its basic function and operation principle are the same as those of the exemplary shift register shown in FIG. 12, and thus will not be described herein.
  • shift registers that can be used for the array substrate gate drive circuit in accordance with embodiments of the present disclosure are given above.
  • the shift register that can be used for the array substrate gate drive circuit according to an embodiment of the present disclosure is not limited thereto.
  • the shift register SRi-j in the array substrate gate drive circuit according to an embodiment of the present disclosure may employ a shift register having any suitable circuit structure, and each shift register SRi-j may be employed as needed The same or different circuit implementations. For example, in one embodiment, even if the shift register is provided with a full reset terminal TRST or an initialization terminal INIT, it may be employed, for example, as shown in the figure, regardless of the full reset terminal TRST or the initialization terminal INIT.
  • various types of transistors, field effect transistors, and the like can be used as the switching elements in the above various shift registers, which are not limited in the present disclosure.
  • FIG. 14 shows a flow chart of a method for driving an array substrate gate drive circuit in accordance with an embodiment of the present disclosure.
  • step S1 an input signal is supplied to an input terminal of the shift register SRi-j to make the shift register
  • the potential of the pull-up node in SRi-j becomes the operating potential; then, in step S2, the gate drive signal OUTPUTi-j is outputted at the output of the shift register SRi-j, and the output gate drive signal is output OUTPUTi-j is supplied to the input terminal of the shift register SRi-(j+1) and the initialization terminal of the shift register SRi-(j+2) to the pull-up node in the shift register SRi-(j+2)
  • the potential is reset; then, in step S3, the reset terminal of the shift register SRi-j receives the gate drive signal OUTPUTi-(j+1) output by the shift register SRi-(j+1) to The potential of the pull-up node in the shift register SRi-j and the potential of the output terminal of the shift register
  • the array substrate gate drive circuit adds a full reset function to fully reset all shift registers in the array substrate gate drive circuit between two frames.
  • the array substrate gate driving circuit according to the present disclosure has low implementation cost, simple signal control, and is advantageous for a narrow bezel of an actual display panel, and thus can be applied to panels and/or display devices of various sizes, and can be used for large-sized splicing screens.
  • Various fields such as in-vehicle display devices, and various manufacturing processes such as a-Si, Oxide, LTPS, and HTPS. Accordingly, embodiments of the present disclosure provide a display device including any of the array substrate gate drive circuits described in the foregoing.

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Abstract

一种阵列基板栅极驱动电路及其驱动方法和显示装置。该阵列基板栅极驱动电路包含至少一个移位寄存器组，每个移位寄存器组包含级联在一起的多个移位寄存器，所述多个移位寄存器包含第一移位寄存器、连接在所述第一移位寄存器之后的第二移位寄存器以及连接在所述第二移位寄存器之后的第三移位寄存器，其中，所述第三移位寄存器设置有初始化端，并且所述初始化端连接到所述第一移位寄存器的输出端。

Description

阵列基板栅极驱动电路及其驱动方法和显示装置
相关申请的交叉引用
本申请要求2017年4月12日提交的申请号为201710237590.3且发明名称为“阵列基板栅极驱动电路及其驱动方法和显示装置”的中国专利申请的优先权，通过引用将其全部内容并入于此。
技术领域
本公开涉及阵列基板栅极驱动电路及其驱动方法和显示装置。
背景技术
阵列基板栅极驱动(Gate Driver on Array，GOA)技术将栅极驱动电路通过薄膜晶体管工艺集成在显示面板内部，以便降低面板中的栅极驱动电路的成本。由于不需要进行栅极驱动电路搭接(Bonding)，GOA技术还能够提高MDL工艺产能，并且能够实现显示面板的窄边框设计。
GOA电路通常包含级联的多个移位寄存器。为了防止当前帧的画面的异常显示影响到下一帧的画面，同时为了防止开机黑屏，可以针对GOA电路增加全复位(Total Reset)功能，即：在两帧之间的消隐期间(即，从GOA电路中的每个移位寄存器组中的最后一级的移位寄存器的上拉节点和输出端的复位都已完成开始、到该每个移位寄存器组中的第一级移位寄存器接收到新一帧的帧起始信号STV之前的某个时间段)内，使用由单独设置的时钟控制电路(T-CON)所提供的全复位信号，针对该GOA电路的所有移位寄存器中的上拉节点和/或输出端同时进行复位或者初始化。
由于全复位信号只能在两帧之间提供，所以GOA电路中的移位寄存器在经过全复位之后仍有可能在接收输入信号之前受到外界因素干扰，并且连接位置越靠后，受到干扰的可能性就越大。
另外，为了使GOA电路具备全复位功能，需要设置单独的时钟控制电路，或者使用STV信号作为全复位信号。对于电视机产品和笔记本计算机等不同的产品，全复位功能的实现方式不同，并且不存在具有普适性的电路设计。
例如，对于电视机产品，可以使用STV信号充当全复位信号TRST，并 在两帧之间的某个时间段(例如，消隐期间)同时发送给电视机产品的GOA电路中的每个移位寄存器。然而，这样的实现方式显著地增加了STV信号的负载。同时，仍然需要单独设置时钟控制电路，以控制发送用于全复位的STV信号的时机。
与电视机产品不同，笔记本计算机等产品的STV信号的脉宽有限。如果采用与电视机产品相同的方式来实现全复位功能，则将显著地增大笔记本计算机等产品的边框。因此，针对笔记本计算机等产品，所采用的方式是使单独设置的时钟控制电路在两帧之间的某个时间段(例如，消隐期间)提供单独的全复位信号。然而，在使用这样的实现方式的情况下，单独设置的时钟控制电路需要多输出一个或两个控制信号，并且需要控制好控制信号的发送时机，导致信号的时序控制非常复杂。
另外，为了实现全复位功能，需要在GOA电路中的每个移位寄存器中增加至少两个额外的晶体管(分别针对上拉节点和输出端的电位的初始化)。因此，会在不同的程度上增大边框(取决于额外增加的晶体管的大小)，不利于实现显示面板的窄边框设计。
发明内容
本公开的一方面涉及一种阵列基板栅极驱动电路，包含至少一个移位寄存器组，每个移位寄存器组包含级联在一起的多个移位寄存器，所述多个移位寄存器包含第一移位寄存器、连接在所述第一移位寄存器之后的第二移位寄存器以及连接在所述第二移位寄存器之后的第三移位寄存器，其中，所述第三移位寄存器设置有初始化端，并且所述初始化端连接到所述第一移位寄存器的输出端。
在一个实施例中，可以将所述第三移位寄存器的输入端连接到所述第二移位寄存器的输出端，并且将所述第二移位寄存器的输入端连接到所述第一移位寄存器的输出端。
在一个实施例中，可以在所述第一移位寄存器与所述第三移位寄存器之间设置单向导通元件。所述单向导通元件的输入端可以作为所述第三移位寄存器的初始化端，并且可以将所述单向导通元件的输出端连接到所述第三移位寄存器的复位端。
在一个实施例中，所述单向导通元件可以包含：第一晶体管，其源极和 栅极连接在一起并作为所述单向导通元件的输入端，其漏极作为所述单向导通元件的输出端。
在一个实施例中，在所述第三移位寄存器设置有全复位端的情况下，可以使用所述全复位端作为所述初始化端。在一个实施例中，所述第三移位寄存器可以包含：初始化子电路，其经由所述第三移位寄存器的初始化端接收初始化信号，并且根据所接收的初始化信号，对所述第三移位寄存器内的上拉节点的电位进行复位。
在一个实施例中，所述第三移位寄存器中的初始化子电路可以包含第一晶体管。可以将该第一晶体管的源极与栅极连接在一起并且连接到所述第三移位寄存器的初始化端，并且将该第一晶体管的漏极连接到所述第三移位寄存器的复位端。也可以将该第一晶体管的栅极连接到所述第三移位寄存器的初始化端，将该第一晶体管的源极连接到所述第三移位寄存器的上拉节点，并且将所述第一晶体管的漏极的电位设置为复位电位。
在一个实施例中，所述第三移位寄存器中的初始化子电路还可以包含第二晶体管。可以将该第二晶体管的栅极和源极分别与所述第一晶体管的漏极和所述第三移位寄存器的输出端相连，并将该第二晶体管的漏极的电位设置为复位电位。也可以将该第二晶体管的栅极和源极分别与所述第三移位寄存器的初始化端和输出端相连，并将该第二晶体管的漏极的电位设置为复位电位。
在一个实施例中，所述第三移位寄存器还可以包含：输入子电路，其经由所述第三移位寄存器的输入端接收的输入信号，并且根据所接收的输入信号，控制所述上拉节点的电位。
在一个实施例中，所述第三移位寄存器还可以包含：输出子电路，其经由所述第三移位寄存器的时钟信号端接收时钟信号，并且根据所述上拉节点的电位，控制在所述第三移位寄存器的输出端的输出所接收的时钟信号。
在一个实施例中，所述第三移位寄存器还可以包含：复位子电路，其经由所述第三移位寄存器的复位端接收复位信号，并且根据所接收的复位信号，对所述上拉节点和所述第三移位寄存器的输出端的电位进行复位。
在一个实施例中，可以将所述至少一个移位寄存器组的数量设置为所述阵列基板栅极驱动电路所接收的外部时钟信号的数量的一半。
本公开的另一方面涉及一种显示装置，其包含上述任何一种阵列基板栅 极驱动电路。
本公开的又一方面涉及阵列基板栅极驱动电路的驱动方法，用于驱动上述任何一种阵列基板栅极驱动电路，其中，对于每个第一移位寄存器，所述方法包含：将输入信号提供到所述第一移位寄存器的输入端，使所述第一移位寄存器内的上拉节点的电位成为工作电位；在对所述第一移位寄存器提供所述输入信号之后，使所述第一移位寄存器在其输出端输出栅极驱动信号，同时将所输出的栅极驱动信号作为初始化信号提供到所述第三移位寄存器的初始化端，以对所述第三移位寄存器内的上拉节点的电位进行复位；以及在所述第一移位寄存器输出栅极驱动信号之后，将由所述第二移位寄存器所输出的栅极驱动信号提供到所述第一移位寄存器的复位端，对所述第一移位寄存器内的上拉节点的电位和所述第一移位寄存器的输出端的电位进行复位。
在本公开的阵列基板栅极驱动电路中，对于每个移位寄存器组中的至少第三级以后的每个移位寄存器来说，该移位寄存器能够在开始工作之前，使用由连接在该移位寄存器的前一级移位寄存器之前的另一个移位寄存器所输出的栅极驱动信号作为初始化信号，并且在开始工作之前，对该移位寄存器内部的上拉节点和/或该移位寄存器内部的输出端的电位进行复位或者初始化。从整体上看，根据本公开的阵列基板栅极驱动电路能够在一帧内以逐级初始化的方式实现与采用在帧间进行全复位的方式至少基本相同的技术效果，而且并没有增加STV信号负载，也不需要单独设置时钟控制电路，信号的时序控制简单，电路成本低，并且对电视机、笔记本计算机等各种产品具有普适性。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1示出根据本公开的实施例的阵列基板栅极驱动电路中的移位寄存器的示例性的连接方式。
图2示出可用于根据本公开的实施例的阵列基板栅极驱动电路的移位寄存器的示例性结构。
图3示出可用于根据本公开的实施例的阵列基板栅极驱动电路的另一种 移位寄存器的示例性结构。
图4示出根据本公开的实施例的阵列基板栅极驱动电路中的移位寄存器的示例性的工作时序。
图5示出根据本公开的实施例的阵列基板栅极驱动电路中的移位寄存器的另一种示例性的连接方式。
图6示出根据本公开的实施例的阵列基板栅极驱动电路中的移位寄存器的另一种示例性的连接方式。
图7示出根据本公开的实施例的设置有初始化端的移位寄存器的示例性结构。
图8示出根据本公开的实施例的设置有初始化端的移位寄存器的示例性结构。
图9示出根据本公开的实施例的设置有初始化端的移位寄存器的示例性结构。
图10示出根据本公开的实施例的设置有初始化端的移位寄存器的示例性结构。
图11示出根据本公开的实施例的设置有初始化端的移位寄存器的示例性结构。
图12示出根据本公开的实施例的设置有初始化端的移位寄存器的示例性结构。
图13示出根据本公开的实施例的设置有初始化端的移位寄存器的示例性结构。
图14示出用于驱动根据本公开的实施例的阵列基板栅极驱动电路中的移位寄存器的示例性方法。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
图1所示的阵列基板栅极驱动电路中包含至少一个移位寄存器组，每个 移位寄存器组包括多个移位寄存器。在每个移位寄存器组中，位于第一级的移位寄存器的输入端接收STV信号，并且位于第一级之后的其他各级移位寄存器的输入端分别连接到位于其各自前一级的移位寄存器的输出端，以接收其前一级的移位寄存器输出的栅极驱动信号作为输入信号，由此将每个移位寄存器组中的多个移位寄存器级联在一起。为了便于描述，在本文中，“SRi-j”表示第i个移位寄存器组中被级联在第j级的移位寄存器，其中，移位寄存器SRi-j位于移位寄存器SRi-(j+1)的上一级，移位寄存器SRi-(j+1)位于移位寄存器SRi-j的下一级。相应地，OUTPUTi-j表示由移位寄存器SRi-j输出的栅极驱动信号。
例如，如图1所示，第一个移位寄存器组包含多个移位寄存器SR1-1、SR1-2、SR1-3、SR1-4等，其中，位于第一级的移位寄存器SR1-1的输入端INPUT接收STV信号；位于第二级的移位寄存器SR1-2的输入端INPUT连接到移位寄存器SR1-1的输出端OUTPUT，以接收移位寄存器SR1-1输出的栅极驱动信号OUTPUT1-1作为输入信号；位于第三级的移位寄存器SR1-3的输入端INPUT连接到移位寄存器SR1-2的输出端OUTPUT，以接收移位寄存器SR1-2输出的栅极驱动信号OUTPUT1-2作为输入信号；位于第四级的移位寄存器SR1-4的输入端INPUT连接到移位寄存器SR1-3的输出端OUTPUT，以接收移位寄存器SR1-3输出的栅极驱动信号OUTPUT1-3作为输入信号；以此类推，从而将第一个移位寄存器组中包含的SR1-1、SR1-2、SR1-3、SR1-4等多个移位寄存器级联在一起。
每个移位寄存器SRi-j还设置有用于从相应的时钟信号线(例如图1中所示的CLK1至CLK6)接收时钟信号的时钟信号端CLK和用于接收复位信号的复位端RESET。每个移位寄存器SRi-j的复位端RESET连接到级联在下一级的移位寄存器SRi-(j+1)的输出端OUTPUT，以使用由移位寄存器SRi-(j+1)输出的栅极驱动信号OUTPUTi-(j+1)作为其复位信号。例如，在图1中，移位寄存器SR1-1的复位端RESET连接到级联在其下一级的移位寄存器SR1-2的输出端OUTPUT，并使用由移位寄存器SR1-2输出的栅极驱动信号OUTPUT1-2作为其复位信号。再例如，移位寄存器SR3-2的复位端RESET连接到级联在其下一级的移位寄存器SR3-3的输出端OUTPUT，并使用由移位寄存器SR3-3输出的栅极驱动信号OUTPUT3-3作为其复位信号。
应当了解，图1所示的向各级移位寄存器提供复位信号的方式仅是示例 性的。在一些实施例中，每个移位寄存器可以使用由连接在该移位寄存器之后的任何一个或多个移位寄存器所输出的栅极驱动信号作为复位信号。例如，移位寄存器SR1-1可以使用由移位寄存器SR1-2、SR1-3、SR1-4、SR1-5(未示出)等之中的任何一个或多个所输出的栅极驱动信号OUTPUT1-2、OUTPUT1-3、OUTPUT1-4、OUTPUT1-5(未示出)等之中的任何一个或多个作为复位信号，其中，在使用由连接在后的多个移位寄存器所输出的多个栅极驱动信号作为复位信号的情况下，移位寄存器SR1-1可以在输出栅极驱动信号OUTPUT1-1之后被多次复位，也可以例如在时钟信号和/或内部所设置的逻辑控制电路的控制下仅复位一次或者若干次。
另外，在一些实施例中，每个移位寄存器也可以将其所输出的栅极驱动信号提供给连接在该移位寄存器之前的任何一个或者多个移位寄存器的复位端，作为所述一个或多个移位寄存器的复位信号。例如，可以将移位寄存器SR2-4的输出端OUTPUT连接到移位寄存器SR2-1、SR2-2和SR2-3中的任何一个或多个的复位端RESET，并将移位寄存器SR2-4所输出的栅极驱动信号OUTPUT2-4用作移位寄存器SR2-1、SR2-2和SR2-3中的任何一个或多个的复位信号。
另外，每个移位寄存器SRi-j可以将其所输出的栅极驱动信号OUTPUTi-j提供给连接在移位寄存器SRi-(j+1)之后的任何一个或多个移位寄存器的复位端RESET，作为所述一个或多个移位寄存器在开始工作之前用于进行初始化的初始化信号。例如，每个移位寄存器SRi-j所输出的栅极驱动信号OUTPUTi-j还提供给移位寄存器SRi-(j+2)的复位端RESET。例如，在图1所示的阵列基板栅极驱动电路中，移位寄存器SR1-1的输出端OUTPUT还连接到移位寄存器SR1-3的复位端RESET。
如图1所示，移位寄存器SRi-(j+2)(例如，移位寄存器SR1-3)的复位端RESET与移位寄存器SRi-j(例如，移位寄存器SR1-1)的输出端OUTPUT和移位寄存器SRi-(j+3)(例如，移位寄存器SR1-4)的输出端OUTPUT相连，而在移位寄存器SRi-(j+3)输出栅极驱动信号OUTPUTi-(j+3)时，移位寄存器SRi-j已经完成了栅极信号的输出，并且移位寄存器SRi-j的输出端OUTPUT在此时应当保持为复位电位状态。因此，为了防止移位寄存器SRi-(j+3)所输出的栅极驱动信号OUTPUTi-(j+3)可能对移位寄存器SRi-j的输出端OUTPUT产生不利影响，可以在移位寄存器SRi-j的输出端OUTPUT与移位寄存器 SRi-(j+2)的复位端之间设置单向导通开关SWi-(j+2)，其中，单向导通开关SWi-(j+2)的输入端连接到移位寄存器SRi-j的输出端OUTPUT，其输出端连接到移位寄存器SRi-(j+2)的复位端RESET，从而确保信号总是从移位寄存器SRi-j的输出端OUTPUT单向地传递给移位寄存器SRi-(j+2)的复位端RESET，从而避免信号在相反方向上的传递。例如，如图1所示，可以在移位寄存器SR1-1的输出端和SR1-3的复位端之间设置单向导通开关SW1-3，在移位寄存器SR3-2的输出端和SR3-4的复位端之间设置单向导通开关SW3-4。
此时，如果将单向导通开关SWi-(j+2)视为移位寄存器SRi-(j+2)的一部分，则可以将单向导通开关SWi-(j+2)的输入端视为移位寄存器SRi-(j+2)的初始化端，并且可以将移位寄存器SRi-j所提供的栅极驱动信号OUTPUTi-j视为移位寄存器SRi-(j+2)在开始工作之前用于进行初始化的初始化信号。
在一个实施例中，单向导通开关可以采用晶体管(例如图1中的单向导通开关SW1-3)来实现。在这样的情况下，例如，可以将晶体管的控制端和第一端连接到一起并用作单向导通开关的输入端，并且将晶体管的第二端用作单向导通开关的输出端。在另一个实施例中，单向导通开关可以采用二极管来实现，其中，例如将二极管的输入端用作单向导通开关的输入端，并且将二极管的输出端用作单向导通开关的输出端。在其他实施例中，单向导通开关可以采用适用于集成电路并具有单向导通能力的其他任何元件和/或电路。
应当了解，图1所示的阵列基板栅极驱动电路中的移位寄存器SRi-j可以根据需要而具有任何适当的电路结构，并且各个移位寄存器SRi-j可以根据需要采用相同或不同的电路实现方式。
图2示出可用于根据本公开的实施例的阵列基板栅极驱动电路的移位寄存器的示例性结构。图2所示的移位寄存器包含输入电路、输出电路和复位电路。输入电路包含开关元件SW1，其中，开关元件SW1的控制端与第一端相连并作为移位寄存器的输入端INPUT，并且其第二端连接到该移位寄存器内的上拉节点PU。输出电路包含开关元件SW2和电容器C，其中，开关元件SW2的控制端和电容器C的一端一起连接到上拉节点PU，开关元件SW2的第一端连接到该移位寄存器的时钟信号端CLK，开关元件SW2的第二端和电容器C的另一端连接到该移位寄存器的输出端OUTPUT。复位电路包含开关元件SW3和开关元件SW4，其中，开关元件SW3和开关元件SW4的 控制端连接到一起并连接到该移位寄存器的复位端RESET，开关元件SW3的第一端连接到上拉节点PU，开关元件SW4的第一端连接到该移位寄存器的输出端OUTPUT，开关元件SW3和开关元件SW4的第二端的电位被设置为复位电位。移位寄存器中的开关元件可以为任意类型的晶体管、场效应管等，本文对此不作限制。
在单独考虑一个移位寄存器的工作过程的情况下，图2所示的移位寄存器当经由输入端INPUT接收到输入信号时开始工作，输入电路中的开关元件SW1导通，上拉节点PU的电位成为工作电位(例如，高电平)，使得对输出电路中的电容C进行充电。然后，当经由时钟信号端CLK接收到时钟信号时，输出电路中的开关元件SW2导通，从而在输出端OUTPUT输出栅极驱动信号，并且上拉节点PU由于电容C的自举作用(bootstrapping)而保持为工作电位。然后，当经由复位端RESET接收复位信号时，复位电路中的开关元件SW3和SW4导通。由于开关元件SW3和SW4的第二端被设置为复位电位(例如，低电平)，因而上拉节点PU和输出端OUTPUT的电位被复位成复位电位。然后，在没有外部干扰的情况下，上拉节点PU和输出端OUTPUT的电位被保持为复位电位，直至该移位寄存器接收到下一个输入信号为止，由此避免多输出引起画面的异常显示。
图3示出可用于根据本公开的实施例的阵列基板栅极驱动电路的另一种移位寄存器的示例性结构。在图3所示的示例性的移位寄存器中，没有将开关元件SW4的控制端直接连接到移位寄存器的复位端RESET，而是在移位寄存器内部增设了开关元件SW5和SW6。当移位寄存器在其复位端RESET接收到复位信号时，开关元件SW3导通，使得上拉节点PU的电位成为复位电位，进而使开关元件SW6截止。由于开关元件SW5处于导通状态，所以位于开关元件SW6的第一端处的下拉节点PD的电位在此时成为工作电位。当下拉节点PD的电位成为工作电位时，开关元件SW4导通，使得移位寄存器的输出端OUTPUT的电位成为复位电位。
应当了解，除了图2和图3所示的移位寄存器的示例性结构之外，图1所示的根据本公开的实施例的阵列基板栅极驱动电路中的移位寄存器还可以采用其他电路结构。然而，各种移位寄存器的基本功能和基本原理均是相同的。
图4示出图1所示的阵列基板栅极驱动电路中的移位寄存器SR1-3的工 作时序，其中，CLK1-1-1和CLK1-1-3表示经由图1中的时钟信号线CLK1提供给移位寄存器SR1-1和SR1-3的时钟信号，CLK4-1-2和CLK4-1-4表示经由图1中的时钟信号线CLK4提供给移位寄存器SR1-2和SR1-4的时钟信号，RESET1-3表示移位寄存器SR1-3的复位端RESET的电位，PU1-3表示移位寄存器SR1-3内部的上拉节点PU的电位。需要说明的是，图4所示的经由图1中的时钟信号线CLK1和CLK4所提供的时钟信号的时序关系仅是示例性的。
如图4所示，移位寄存器SR1-1在接收到STV信号之后，当接收到时钟信号CLK1-1-1(即，CLK1-1-1的电位为工作电位，例如高电平)时，输出栅极驱动信号OUTPUT1-1。所输出的栅极驱动信号OUTPUT1-1将分别提供给移位寄存器SR1-2的输入端INPUT和移位寄存器SR1-3的复位端RESET，使得移位寄存器SR1-3的复位端RESET的电位RESET1-3成为工作电位。结合图2或图3，此时，移位寄存器SR1-3内部的复位电路工作，使得移位寄存器SR1-3内部的上拉节点PU的电位PU1-3以及移位寄存器SR1-3的输出端OUTPUT的电位OUTPUT1-3均为复位电位，从而完成开始工作前的初始化。
接着，移位寄存器SR1-2输出栅极驱动信号OUTPUT1-2，并提供给移位寄存器SR1-3的输入端INPUT。移位寄存器SR1-3在接收到输入信号之后，结合图2或图3，其内部的上拉节点PU的电位PU1-3成为工作电位，并且输出电路中的电容C开始充电。然而，由于此时未接收到时钟信号CLK1-1-3(CLK1-1-3当前未处于工作电位)，所以移位寄存器SR1-3内部的输出电路中的开关元件SW2未导通，因而在移位寄存器SR1-3的输出端OUTPUT没有栅极驱动信号OUTPUT1-3输出(即，此时的OUTPUT1-3的电位仍为复位电位)。
然后，当移位寄存器SR1-3接收到时钟信号CLK1-1-3时，移位寄存器SR1-3内部的上拉节点PU的电位PU1-3由于电容器C的自举作用而保持为工作电位，使得输出电路开始工作(即，输出电路中的开关元件SW2导通)，从而在输出端OUTPUT输出栅极驱动信号OUTPUT1-3。所输出的栅极驱动信号OUTPUT1-3同时被提供给下一级的移位寄存器SR1-4作为移位寄存器SR1-4的输入信号。
移位寄存器SR1-3在输出栅极驱动信号OUTPUT1-3之后，在其复位端 RESET接收到移位寄存器SR1-4输出的栅极驱动信号OUTPUT1-4，使得其复位端RESET的电位RESET1-3再次成为工作电位。此时，移位寄存器SR1-3内部的复位电路再次工作，使得移位寄存器SR1-3内部的上拉节点PU的电位PU1-3以及移位寄存器SR1-3的输出端OUTPUT的电位OUTPUT1-3均为复位电位，从而完成在输出栅极驱动信号OUTPUT1-3之后的复位。
对于图1中的任何移位寄存器SRi-j(j>＝3)，其工作过程与图4所示的移位寄存器SR1-3的工作过程相似，在本文中不再赘述。
在如图1所示的阵列基板栅极驱动电路中，任何移位寄存器SRi-(j+2)(j>＝1)均能够在开始工作之前(即，接收到输入信号之前)，在其复位端RSEET接收到来自移位寄存器SRi-j的栅极驱动信号OUTPUTi-j，作为其初始化信号，以便在开始工作之前，对其内部的上拉节点PU和/或其输出端OUTPUT的电位进行初始化。
从整体上来看，如图1所示的阵列基板栅极驱动电路能够在一帧内对所有的移位寄存器SRi-(j+2)(j>＝1)逐级地进行初始化，并且不需要为阵列基板栅极驱动电路增设全复位功能以在两帧之间对阵列基板栅极驱动电路中的所有移位寄存器进行全复位。而且，根据本公开实施例的阵列基板栅极驱动电路并没有增加STV信号的负载，也不需要单独设置时钟控制电路，信号的时序控制简单，电路成本低，并且对电视机、笔记本计算机等各种产品具有普适性。
在采用图1所示的连接方式的情况下，每个移位寄存器SRi-(j+2)(j>＝1)能够恰好在开始工作之前接收到初始化信号并进行初始化，并且能够在输出栅极驱动信号之后立即进行复位。由此，能够有效地避免移位寄存器在开始工作之前由于过早地被初始化而可能受到外界噪声干扰的情况，从而更加有效地抑制噪声积累，并进一步提高GOA电路的输出信号的准确性和稳定性。
图1所示的向各级移位寄存器提供初始化信号的方式仅是示例性。根据需要，可以将移位寄存器SRi-j所输出的栅极驱动信号OUTPUTi-j提供给连接在移位寄存器SRi-(j+1)之后的任何一个或多个移位寄存器的复位端RESET。例如，可以将移位寄存器SR1-1的输出端OUTPUT例如经由单向导通开关SW1-4连接到移位寄存器SR1-4的复位端，或者也可以将移位寄存器SR1-1的输出端OUTPUT例如分别经由单向导通开关SW1-3和SW1-4连接到移位寄存器SR1-3和SR1-4的复位端，或者也可以将移位寄存器SR1-1的 输出端OUTPUT例如分别经由单向导通开关SW1-3和SW1-5连接到移位寄存器SR1-3和SR1-5的复位端。如果条件允许(例如，SR1-1所输出的栅极驱动信号OUTPUT1-1具有足够的脉宽)，甚至可以将移位寄存器SR1-1的输出端OUTPUT分别经由多个单向导通开关连接到第一个移位寄存器组中除了移位寄存器SR1-2之外的所有移位寄存器SR1-j(j≥3)的复位端RESET。
另外，虽然在图1中示出3个移位寄存器组和6个时钟信号线CLK1至CLK6，但是本公开并不限制移位寄存器组和时钟信号线的数量。例如，也可以设置1个移位寄存器组和2个时钟信号线，或者设置2个移位寄存器组和4个时钟信号线。一般来说，可以将移位寄存器组的数量和时钟信号线的数量之间的关系设置为1:2。根据当前的实验结果，采用3个移位寄存器组和6个时钟信号线在性能方面所取得的效果相对较好。
如前文所述，在根据本公开的阵列基板栅极驱动电路中的任何一个移位寄存器可以采用任何适当的电路结构。例如，图2或图3所示的示例性的移位寄存器以及在图2或图3所示的示例性的移位寄存器的基础上的任何变型均可以应用于根据本公开的阵列基板栅极驱动电路中。
图5示出根据本公开的实施例的阵列基板栅极驱动电路中的移位寄存器的另一种示例性的连接方式。在移位寄存器本身支持全复位功能(相应地，设置有全复位端TRST和全复位电路)的情况下，如图5所示，在移位寄存器SRi-j的输出端和SRi-(j+2)的复位端之间，可以不必设置单独的单向导通开关SWi-(j+2)，而是直接将移位寄存器SRi-(j+2)的全复位端TRST用作初始化端，并将其连接到移位寄存器SRi-j的输出端OUTPUT。
另外，在根据本公开的阵列基板栅极驱动电路中也可以采用设置有专门的初始化端的移位寄存器。
图6示出根据本公开的实施例的阵列基板栅极驱动电路中的移位寄存器的另一种示例性的连接方式。在该实施例中，阵列基板栅极驱动电路中的移位寄存器SRi-(j+2)(j>＝1)还设置有专用的初始化端。如图6所示，在该阵列基板栅极驱动电路中，移位寄存器SRi-(j+2)设置有初始化端，并且移位寄存器SRi-(j+2)的初始化端直接连接到移位寄存器SRi-j的输出端OUTPUT。
图7至图13分别示出根据本公开的实施例的设置有初始化端的移位寄存器的示例性结构。
图7所示的示例性的移位寄存器在图2所示的移位寄存器的基础上增加 了初始化端INIT和初始化电路。初始化电路可以包含开关元件SW5，其中，开关元件SW5的控制端和第一端连接到一起，并连接到移位寄存器的初始化端INIT，开关元件SW5的第二端与复位电路中的开关元件SW3和开关元件SW4的控制端连接到一起，并连接到移位寄存器的复位端RESET。当经由初始化端INIT接收到初始化信号时，初始化电路中的开关元件SW5导通，使得复位电路中的开关元件SW3和开关元件SW4导通，从而使上拉节点PU的电位和输出端OUTPUT的电位成为复位电位。由此，该移位寄存器完成初始化。
图8所示的示例性的移位寄存器在图3所示的移位寄存器的基础上增加了初始化端INIT和初始化电路。初始化电路可以包含开关元件SW7，其中，开关元件SW7的控制端和第一端连接到一起，并连接到移位寄存器的初始化端INIT，开关元件SW7的第二端与复位电路中的开关元件SW3的控制端连接到一起，并连接到移位寄存器的复位端RESET。当经由初始化端INIT接收到初始化信号时，初始化电路中的开关元件SW7导通，使得移位寄存器的复位端RESET的电位成为初始化信号的电位。这相当于在移位寄存器的复位端RESET接收到复位信号。因此，当经由初始化端INIT接收到初始化信号时，移位寄存器的上拉节点PU的电位和输出端OUTPUT的电位成为复位电位，由此该移位寄存器完成初始化。
图7或图8所示的示例性的移位寄存器相当于将图1中的单向导通开关SWi-(j+2)和移位寄存器SRi-(j+2)视为一个整体，其中，单向导通开关SWi-(j+2)的输入端相当于移位寄存器SRi-(j+2)的初始化端INIT。
以类似的方式，可以设计出其他移位寄存器。例如，图9示出根据本公开的实施例的移位寄存器的一种变型，其中，该移位寄存器还设置有反向时钟信号端CLKB(经由CLKB所接收的时钟信号例如可以与经由时钟信号端CLK所接收的时钟信号相位相反)，并且还包含开关元件SW8至SW13。然而，这样的移位寄存器的基本功能和工作原理与图7或图8所示的示例性的移位寄存器是相同的，因此在本文中不再赘述。
图10示出根据本公开的实施例的设置有初始化端和初始化电路的移位寄存器的示例性结构。在图10所示的移位寄存器中，初始化电路还包含开关元件SW8，其控制端连接到初始化端，其第一端连接到移位寄存器的输出端OUTPUT，其第二端的电位被置为复位电位REFRESET。这样，当移位寄存器 经由初始化端INIT接收到初始化信号时，还能够通过开关元件SW8对输出端OUTPUT的电位进行复位。相对于图8所示的电路结构，图10所示的移位寄存器中的初始化电路对输出端OUTPUT的初始化能力更强。当然，在考虑窄边框的情况下，也可以不设置开关元件SW8。
以与图10类似的方式，能够设计出其他移位寄存器。例如，图11示出了图10所示的移位寄存器的一种变型，其中，该移位寄存器还包含开关元件SW9至SW11。然而，关于图11所示的示例性的移位寄存器，其基本功能和工作原理与图10所示的示例性的移位寄存器是相同的，因此在本文中不再赘述。
图12示出根据本公开的另一个实施例的设置有初始化端和初始化电路的的移位寄存器的示例性结构。在图12中，初始化电路中的开关元件SW7的第一端连接到上拉节点PU，其控制端连接到初始化端INIT，其第二端的电位被设置为复位电位REFRESET。这样，当移位寄存器经由初始化端INIT接收到初始化信号时，能够经由初始化电路中的开关元件SW7直接对上拉节点PU的电位进行初始化。另外，初始化电路中还可以包含开关元件SW8，其第一端连接到输出端OUTPUT，其控制端连接到初始化端INIT，其第二端的电位被设置为复位电位REFRESET，以便在接收到初始化信号时对输出端OUTPUT的电位进行初始化。当然，在考虑窄边框的情况下，也可以不设置开关元件SW8。
以与图12类似的方式，能够设计出其他移位寄存器。例如，图13示出了图12所示的移位寄存器的一种变型，其中，该移位寄存器还包含开关元件SW9至SW11。然而，关于图13所示的示例性的移位寄存器的结构更加复杂，其基本功能和工作原理与图12所示的示例性的移位寄存器是相同的，因此在本文中不再赘述。
以上仅给出了可用于根据本公开的实施例的阵列基板栅极驱动电路的移位寄存器的若干示例。可用于根据本公开的实施例的阵列基板栅极驱动电路的移位寄存器并不限于此。如前文所述，根据本公开的实施例的阵列基板栅极驱动电路中的移位寄存器SRi-j可以采用具有任何适当电路结构的移位寄存器，并且各个移位寄存器SRi-j可以根据需要采用相同或不同的电路实现方式。例如，在一个实施例中，即使移位寄存器设置有全复位端TRST或者初始化端INIT，也可以不管全复位端TRST或者初始化端INIT而采用例如如图 1所示的阵列基板栅极驱动电路的连接方式。
另外，上述的各种移位寄存器中的开关元件可以根据需要采用各种类型的晶体管、场效应管等，本公开对此不作限制。
图14示出用于驱动根据本公开的实施例的阵列基板栅极驱动电路的方法的流程图。
如图14所示，针对阵列基板栅极驱动电路中的每个移位寄存器SRi-j，在步骤S1中，将输入信号提供到该移位寄存器SRi-j的输入端，使该移位寄存器SRi-j内的上拉节点的电位成为工作电位；然后，在步骤S2中，在该移位寄存器SRi-j的输出端输出栅极驱动信号OUTPUTi-j，并将所输出的栅极驱动信号OUTPUTi-j提供到移位寄存器SRi-(j+1)的输入端和移位寄存器SRi-(j+2)的初始化端，以对移位寄存器SRi-(j+2)内的上拉节点的电位进行复位；然后，在步骤S3中，该移位寄存器SRi-j的复位端接收由移位寄存器SRi-(j+1)所输出的栅极驱动信号OUTPUTi-(j+1)，以对该移位寄存器SRi-j内的上拉节点的电位和移位寄存器SRi-j的输出端的电位进行复位。由此，该方法能够驱动根据本公开的阵列基板栅极驱动电路在一帧内对所有的移位寄存器SRi-(j+2)(j>＝1)逐级地进行初始化，从而不需要为阵列基板栅极驱动电路增设全复位功能以在两帧之间对阵列基板栅极驱动电路中的所有移位寄存器进行全复位。
根据本公开的阵列基板栅极驱动电路的实现成本低、信号控制简单并且有利于实际显示面板的窄边框，因此能够适用于各种尺寸的面板和/或显示装置，并可用于大尺寸拼接屏、车载显示装置等各种领域，而且还可以适用于a-Si、Oxide、LTPS、HTPS等各种制造工艺。相应地，本公开的实施例提供包含在前文中所述的任何一种阵列基板栅极驱动电路的显示装置。
应当理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式。然而，本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神的情况下，可以做出各种变型和改进，这些变型和改进也在本公开的范围内。

Claims (16)

  1. 一种阵列基板栅极驱动电路，包含至少一个移位寄存器组，每个移位寄存器组包含级联在一起的多个移位寄存器，所述多个移位寄存器包含第一移位寄存器、连接在所述第一移位寄存器之后的第二移位寄存器以及连接在所述第二移位寄存器之后的第三移位寄存器，其中，所述第三移位寄存器设置有初始化端，并且所述初始化端连接到所述第一移位寄存器的输出端。
  2. 根据权利要求1所述的阵列基板栅极驱动电路，其中，在所述第一移位寄存器与所述第三移位寄存器之间设置有单向导通元件，其中，所述单向导通元件的输入端作为所述第三移位寄存器的初始化端，并且所述单向导通元件的输出端连接到所述第三移位寄存器的复位端。
  3. 根据权利要求2所述的阵列基板栅极驱动电路，其中，所述单向导通元件包含：
    第一晶体管，其源极和栅极连接在一起并作为所述单向导通元件的输入端，其漏极作为所述单向导通元件的输出端。
  4. 根据权利要求1所述的阵列基板栅极驱动电路，其中，在所述第三移位寄存器设置有全复位端的情况下，使用所述全复位端作为所述初始化端。
  5. 根据权利要求1所述的阵列基板栅极驱动电路，其中，所述第三移位寄存器包含：
    初始化子电路，其经由所述第三移位寄存器的初始化端接收初始化信号，并且根据所接收的初始化信号，对所述第三移位寄存器内的上拉节点的电位进行复位。
  6. 根据权利要求5所述的阵列基板栅极驱动电路，其中，所述初始化子电路包含：
    第一晶体管，其源极与栅极连接在一起并且连接到所述第三移位寄存器的初始化端，其漏极连接到所述第三移位寄存器的复位端。
  7. 根据权利要求5所述的阵列基板栅极驱动电路，其中，所述初始化子电路包含：
    第一晶体管，其栅极连接到所述第三移位寄存器的初始化端，其源极连接到所述上拉节点，其漏极的电位被设置为复位电位。
  8. 根据权利要求6或7所述的阵列基板栅极驱动电路，其中，所述初始 化子电路还包含：
    第二晶体管，其栅极与所述第一晶体管的漏极相连，其源极与所述第三移位寄存器的输出端相连，其漏极的电位被设置为复位电位。
  9. 根据权利要求6或7所述的阵列基板栅极驱动电路，其中，所述初始化子电路还包含：
    第二晶体管，其栅极与所述第三移位寄存器的初始化端相连，其源极与所述第三移位寄存器的输出端相连，其漏极的电位被设置为复位电位。
  10. 根据权利要求5所述的阵列基板栅极驱动电路，其中，所述第三移位寄存器包含：
    输入子电路，其经由所述第三移位寄存器的输入端接收输入信号，并且根据所接收的输入信号，控制所述上拉节点的电位。
  11. 根据权利要求10所述的阵列基板栅极驱动电路，其中，所述第三移位寄存器包含：
    输出子电路，其经由所述第三移位寄存器的时钟信号端接收时钟信号，并且根据所述上拉节点的电位，控制在所述第三移位寄存器的输出端输出所接收的时钟信号。
  12. 根据权利要求11所述的阵列基板栅极驱动电路，其中，所述第三移位寄存器包含：
    复位子电路，其经由所述第三移位寄存器的复位端接收复位信号，并且根据所接收的复位信号，对所述上拉节点和所述第三移位寄存器的输出端的电位进行复位。
  13. 根据权利要求1所述的阵列基板栅极驱动电路，其中，所述第二移位寄存器的输入端连接到所述第一移位寄存器的输出端，并且所述第三移位寄存器的输入端连接到所述第二移位寄存器的输出端。
  14. 根据权利要求1所述的阵列基板栅极驱动电路，其中，所述至少一个移位寄存器组的数量为所述阵列基板栅极驱动电路所接收的外部时钟信号的数量的一半。
  15. 一种显示装置，包含根据1至14中的任一项所述的阵列基板栅极驱动电路。
  16. 一种用于驱动根据权利要求1至14中的任一项所述的阵列基板栅极驱动电路的方法，其中，对于每个第一移位寄存器，所述方法包含：
    将输入信号提供到所述第一移位寄存器的输入端，使所述第一移位寄存器内的上拉节点的电位成为工作电位；
    在对所述第一移位寄存器提供所述输入信号之后，使所述第一移位寄存器在其输出端输出栅极驱动信号，同时将所输出的栅极驱动信号作为初始化信号提供到所述第三移位寄存器的初始化端，以对所述第三移位寄存器内的上拉节点的电位进行复位；以及
    在所述第一移位寄存器输出栅极驱动信号之后，将由所述第二移位寄存器所输出的栅极驱动信号提供到所述第一移位寄存器的复位端，对所述第一移位寄存器内的上拉节点的电位和所述第一移位寄存器的输出端的电位进行复位。
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